1 ; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s 2 ; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s 3 4 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 5 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 6 declare void @llvm.amdgcn.s.barrier() #2 7 8 ; The required pointer calculations for the alloca'd actually requires 9 ; an add and won't be folded into the addressing, which fails with a 10 ; 64-bit pointer add. This should work since private pointers should 11 ; be 32-bits. 12 13 ; SI-LABEL: {{^}}test_private_array_ptr_calc: 14 15 ; FIXME: We end up with zero argument for ADD, because 16 ; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index 17 ; with the appropriate offset. We should fold this into the store. 18 19 ; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 0, v{{[0-9]+}} 20 ; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 21 ; SI-ALLOCA: s_barrier 22 ; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 23 ; 24 ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this 25 ; alloca to a vector. It currently fails because it does not know how 26 ; to interpret: 27 ; getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b 28 29 ; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64 30 ; SI-PROMOTE: ds_write_b32 [[PTRREG]] 31 define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 { 32 %alloca = alloca [16 x i32], align 16 33 %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); 34 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) 35 %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid 36 %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid 37 %a = load i32, i32 addrspace(1)* %a_ptr 38 %b = load i32, i32 addrspace(1)* %b_ptr 39 %result = add i32 %a, %b 40 %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b 41 store i32 %result, i32* %alloca_ptr, align 4 42 ; Dummy call 43 call void @llvm.amdgcn.s.barrier() 44 %reload = load i32, i32* %alloca_ptr, align 4 45 %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid 46 store i32 %reload, i32 addrspace(1)* %out_ptr, align 4 47 ret void 48 } 49 50 attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="1" } 51 attributes #1 = { nounwind readnone } 52 attributes #2 = { nounwind convergent } 53
