1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ;CHECK-LABEL: {{^}}image_load_v4i32: 5 ;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm 6 ;CHECK: s_waitcnt vmcnt(0) 7 define amdgpu_ps <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) { 8 main_body: 9 %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 10 ret <4 x float> %tex 11 } 12 13 ;CHECK-LABEL: {{^}}image_load_v2i32: 14 ;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm 15 ;CHECK: s_waitcnt vmcnt(0) 16 define amdgpu_ps <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) { 17 main_body: 18 %tex = call <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 19 ret <4 x float> %tex 20 } 21 22 ;CHECK-LABEL: {{^}}image_load_i32: 23 ;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm 24 ;CHECK: s_waitcnt vmcnt(0) 25 define amdgpu_ps <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) { 26 main_body: 27 %tex = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 28 ret <4 x float> %tex 29 } 30 31 ;CHECK-LABEL: {{^}}image_load_mip: 32 ;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm 33 ;CHECK: s_waitcnt vmcnt(0) 34 define amdgpu_ps <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) { 35 main_body: 36 %tex = call <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 37 ret <4 x float> %tex 38 } 39 40 ;CHECK-LABEL: {{^}}image_load_1: 41 ;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm 42 ;CHECK: s_waitcnt vmcnt(0) 43 define amdgpu_ps float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) { 44 main_body: 45 %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 46 %elt = extractelement <4 x float> %tex, i32 0 47 ; Only first component used, test that dmask etc. is changed accordingly 48 ret float %elt 49 } 50 51 ;CHECK-LABEL: {{^}}image_store_v4i32: 52 ;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm 53 define amdgpu_ps void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) { 54 main_body: 55 call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 56 ret void 57 } 58 59 ;CHECK-LABEL: {{^}}image_store_v2i32: 60 ;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm 61 define amdgpu_ps void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) { 62 main_body: 63 call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 64 ret void 65 } 66 67 ;CHECK-LABEL: {{^}}image_store_i32: 68 ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm 69 define amdgpu_ps void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) { 70 main_body: 71 call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 72 ret void 73 } 74 75 ;CHECK-LABEL: {{^}}image_store_mip: 76 ;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm 77 define amdgpu_ps void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) { 78 main_body: 79 call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) 80 ret void 81 } 82 83 ; Ideally, the register allocator would avoid the wait here 84 ; 85 ;CHECK-LABEL: {{^}}image_store_wait: 86 ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm 87 ;CHECK: s_waitcnt vmcnt(0) expcnt(0) 88 ;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm 89 ;CHECK: s_waitcnt vmcnt(0) 90 ;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm 91 define amdgpu_ps void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) { 92 main_body: 93 call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0) 94 %data = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %4, <8 x i32> %1, i32 15, i1 0, i1 0, i1 0, i1 0) 95 call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %4, <8 x i32> %2, i32 15, i1 0, i1 0, i1 0, i1 0) 96 ret void 97 } 98 99 declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0 100 declare void @llvm.amdgcn.image.store.v2i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 101 declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 102 declare void @llvm.amdgcn.image.store.mip.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 103 104 declare <4 x float> @llvm.amdgcn.image.load.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1 105 declare <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 106 declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 107 declare <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 108 109 attributes #0 = { nounwind } 110 attributes #1 = { nounwind readonly } 111
