1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s 3 4 ;GCN-LABEL: {{^}}v_interp: 5 ;GCN-NOT: s_wqm 6 ;GCN: s_mov_b32 m0, s{{[0-9]+}} 7 ;GCN: v_interp_p1_f32 8 ;GCN: v_interp_p2_f32 9 define amdgpu_ps void @v_interp(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) { 10 main_body: 11 %i = extractelement <2 x i32> %4, i32 0 12 %j = extractelement <2 x i32> %4, i32 1 13 %p0_0 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 0, i32 0, i32 %3) 14 %p1_0 = call float @llvm.amdgcn.interp.p2(float %p0_0, i32 %j, i32 0, i32 0, i32 %3) 15 %p0_1 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 1, i32 0, i32 %3) 16 %p1_1 = call float @llvm.amdgcn.interp.p2(float %p0_1, i32 %j, i32 1, i32 0, i32 %3) 17 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %p0_0, float %p0_0, float %p1_1, float %p1_1) 18 ret void 19 } 20 21 ; Function Attrs: nounwind readnone 22 declare float @llvm.amdgcn.interp.p1(i32, i32, i32, i32) #0 23 24 ; Function Attrs: nounwind readnone 25 declare float @llvm.amdgcn.interp.p2(float, i32, i32, i32, i32) #0 26 27 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 28 29 attributes #0 = { nounwind readnone } 30
