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      1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s
      2 
      3 ; CHECK-LABEL: {{^}}test1:
      4 ; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec
      5 ;
      6 ; Note: We could generate better code here if we recognized earlier that
      7 ; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,
      8 ; the expectation is that the intrinsic will be used in non-trivial shaders,
      9 ; so such an optimization doesn't seem worth the effort.
     10 define amdgpu_ps float @test1() {
     11   %live = call i1 @llvm.amdgcn.ps.live()
     12   %live.32 = zext i1 %live to i32
     13   %r = bitcast i32 %live.32 to float
     14   ret float %r
     15 }
     16 
     17 ; CHECK-LABEL: {{^}}test2:
     18 ; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
     19 ; CHECK-DAG: s_wqm_b64 exec, exec
     20 ; CHECK-DAG: v_cndmask_b32_e64 [[VAR:v[0-9]+]], 0, 1, [[LIVE]]
     21 ; CHECK: image_sample v0, [[VAR]],
     22 define amdgpu_ps float @test2() {
     23   %live = call i1 @llvm.amdgcn.ps.live()
     24   %live.32 = zext i1 %live to i32
     25 
     26   %t = call <4 x float> @llvm.SI.image.sample.i32(i32 %live.32, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
     27 
     28   %r = extractelement <4 x float> %t, i32 0
     29   ret float %r
     30 }
     31 
     32 ; CHECK-LABEL: {{^}}test3:
     33 ; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
     34 ; CHECK-DAG: s_wqm_b64 exec, exec
     35 ; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
     36 ; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
     37 ; CHECK: ; %dead
     38 define amdgpu_ps float @test3(i32 %in) {
     39 entry:
     40   %live = call i1 @llvm.amdgcn.ps.live()
     41   br i1 %live, label %end, label %dead
     42 
     43 dead:
     44   %tc.dead = mul i32 %in, 2
     45   br label %end
     46 
     47 end:
     48   %tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
     49   %t = call <4 x float> @llvm.SI.image.sample.i32(i32 %tc, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
     50 
     51   %r = extractelement <4 x float> %t, i32 0
     52   ret float %r
     53 }
     54 
     55 declare i1 @llvm.amdgcn.ps.live() #0
     56 
     57 declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
     58 
     59 attributes #0 = { nounwind readnone }
     60