1 ; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null < %s 3 4 ; The register coalescer introduces a verifier error which later 5 ; results in a crash during scheduling. 6 7 declare i32 @llvm.amdgcn.workitem.id.x() #0 8 9 define void @reg_coalescer_breaks_dead(<2 x i32> addrspace(1)* nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3) #1 { 10 bb: 11 %id.x = call i32 @llvm.amdgcn.workitem.id.x() 12 %cmp0 = icmp eq i32 %id.x, 0 13 br i1 %cmp0, label %bb3, label %bb4 14 15 bb3: ; preds = %bb 16 %tmp = ashr exact i32 undef, 8 17 br label %bb6 18 19 bb4: ; preds = %bb6, %bb 20 %tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ] 21 br i1 undef, label %bb15, label %bb16 22 23 bb6: ; preds = %bb6, %bb3 24 %tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ] 25 %tmp8 = add nsw i32 0, %arg1 26 %tmp9 = add nsw i32 %tmp8, 0 27 %tmp10 = sext i32 %tmp9 to i64 28 %tmp11 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg, i64 %tmp10 29 %tmp12 = load <2 x i32>, <2 x i32> addrspace(1)* %tmp11, align 8 30 %tmp13 = add <2 x i32> %tmp12, %tmp7 31 %tmp14 = icmp slt i32 undef, %arg2 32 br i1 %tmp14, label %bb6, label %bb4 33 34 bb15: ; preds = %bb4 35 store <2 x i32> %tmp5, <2 x i32> addrspace(3)* undef, align 8 36 br label %bb16 37 38 bb16: ; preds = %bb15, %bb4 39 unreachable 40 } 41 42 attributes #0 = { nounwind readnone } 43 attributes #1 = { nounwind } 44
