1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4 ; This should end with an no-op sequence of exec mask manipulations 5 ; Mask should be in original state after executed unreachable block 6 7 ; GCN-LABEL: {{^}}main: 8 ; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]] 9 10 ; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc 11 ; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]] 12 ; GCN-NEXT: ; mask branch [[UNREACHABLE_BB:BB[0-9]+_[0-9]+]] 13 14 ; GCN: [[RET_BB]]: 15 ; GCN-NEXT: s_branch [[FINAL_BB:BB[0-9]+_[0-9]+]] 16 17 ; GCN-NEXT: [[UNREACHABLE_BB]]: 18 ; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]] 19 ; GCN-NEXT: [[FINAL_BB]]: 20 ; GCN-NEXT: .Lfunc_end0 21 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 { 22 main_body: 23 %p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) 24 %p87 = fmul float undef, %p83 25 %p88 = fadd float %p87, undef 26 %p93 = fadd float %p88, undef 27 %p97 = fmul float %p93, undef 28 %p102 = fsub float %p97, undef 29 %p104 = fmul float %p102, undef 30 %p106 = fadd float 0.000000e+00, %p104 31 %p108 = fadd float undef, %p106 32 br i1 undef, label %ENDIF69, label %ELSE 33 34 ELSE: ; preds = %main_body 35 %p124 = fmul float %p108, %p108 36 %p125 = fsub float %p124, undef 37 %p126 = fcmp olt float %p125, 0.000000e+00 38 br i1 %p126, label %ENDIF69, label %ELSE41 39 40 ELSE41: ; preds = %ELSE 41 unreachable 42 43 ENDIF69: ; preds = %ELSE, %main_body 44 ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef 45 } 46 47 ; Function Attrs: nounwind readnone 48 declare float @llvm.SI.load.const(<16 x i8>, i32) #1 49 50 ; Function Attrs: nounwind readnone 51 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 52 53 ; Function Attrs: nounwind readnone 54 declare float @llvm.fabs.f32(float) #1 55 56 ; Function Attrs: nounwind readnone 57 declare float @llvm.sqrt.f32(float) #1 58 59 ; Function Attrs: nounwind readnone 60 declare float @llvm.floor.f32(float) #1 61 62 attributes #0 = { "InitialPSInputAddr"="36983" } 63 attributes #1 = { nounwind readnone } 64
