1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s 2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ; This test checks that no VGPR to SGPR copies are created by the register 5 ; allocator. 6 7 8 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 9 10 11 ; CHECK-LABEL: {{^}}phi1: 12 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 13 ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] 14 define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 15 main_body: 16 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 17 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 18 %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) 19 %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) 20 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) 21 %tmp24 = fptosi float %tmp22 to i32 22 %tmp25 = icmp ne i32 %tmp24, 0 23 br i1 %tmp25, label %ENDIF, label %ELSE 24 25 ELSE: ; preds = %main_body 26 %tmp26 = fsub float -0.000000e+00, %tmp21 27 br label %ENDIF 28 29 ENDIF: ; preds = %ELSE, %main_body 30 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] 31 %tmp27 = fadd float %temp.0, %tmp23 32 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00) 33 ret void 34 } 35 36 ; Make sure this program doesn't crash 37 ; CHECK-LABEL: {{^}}phi2: 38 define amdgpu_ps void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 39 main_body: 40 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 41 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 42 %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) 43 %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) 44 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 36) 45 %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 40) 46 %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 48) 47 %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 52) 48 %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 56) 49 %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 64) 50 %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 68) 51 %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 72) 52 %tmp31 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 76) 53 %tmp32 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 80) 54 %tmp33 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 84) 55 %tmp34 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 88) 56 %tmp35 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 92) 57 %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 58 %tmp37 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp36, !tbaa !0 59 %tmp38 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0 60 %tmp39 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp38, !tbaa !0 61 %tmp40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5) 62 %tmp41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5) 63 %tmp42 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg3, <2 x i32> %arg5) 64 %tmp43 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg3, <2 x i32> %arg5) 65 %tmp44 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg3, <2 x i32> %arg5) 66 %tmp45 = bitcast float %tmp40 to i32 67 %tmp46 = bitcast float %tmp41 to i32 68 %tmp47 = insertelement <2 x i32> undef, i32 %tmp45, i32 0 69 %tmp48 = insertelement <2 x i32> %tmp47, i32 %tmp46, i32 1 70 %tmp39.bc = bitcast <16 x i8> %tmp39 to <4 x i32> 71 %tmp49 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp48, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 72 %tmp50 = extractelement <4 x float> %tmp49, i32 2 73 %tmp51 = call float @fabs(float %tmp50) 74 %tmp52 = fmul float %tmp42, %tmp42 75 %tmp53 = fmul float %tmp43, %tmp43 76 %tmp54 = fadd float %tmp53, %tmp52 77 %tmp55 = fmul float %tmp44, %tmp44 78 %tmp56 = fadd float %tmp54, %tmp55 79 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56) 80 %tmp58 = fmul float %tmp42, %tmp57 81 %tmp59 = fmul float %tmp43, %tmp57 82 %tmp60 = fmul float %tmp44, %tmp57 83 %tmp61 = fmul float %tmp58, %tmp22 84 %tmp62 = fmul float %tmp59, %tmp23 85 %tmp63 = fadd float %tmp62, %tmp61 86 %tmp64 = fmul float %tmp60, %tmp24 87 %tmp65 = fadd float %tmp63, %tmp64 88 %tmp66 = fsub float -0.000000e+00, %tmp25 89 %tmp67 = fmul float %tmp65, %tmp51 90 %tmp68 = fadd float %tmp67, %tmp66 91 %tmp69 = fmul float %tmp26, %tmp68 92 %tmp70 = fmul float %tmp27, %tmp68 93 %tmp71 = call float @fabs(float %tmp69) 94 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71 95 %tmp73 = sext i1 %tmp72 to i32 96 %tmp74 = bitcast i32 %tmp73 to float 97 %tmp75 = bitcast float %tmp74 to i32 98 %tmp76 = icmp ne i32 %tmp75, 0 99 br i1 %tmp76, label %IF, label %ENDIF 100 101 IF: ; preds = %main_body 102 %tmp77 = fsub float -0.000000e+00, %tmp69 103 %tmp78 = call float @llvm.exp2.f32(float %tmp77) 104 %tmp79 = fsub float -0.000000e+00, %tmp78 105 %tmp80 = fadd float 1.000000e+00, %tmp79 106 %tmp81 = fdiv float 1.000000e+00, %tmp69 107 %tmp82 = fmul float %tmp80, %tmp81 108 %tmp83 = fmul float %tmp31, %tmp82 109 br label %ENDIF 110 111 ENDIF: ; preds = %IF, %main_body 112 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ] 113 %tmp84 = call float @fabs(float %tmp70) 114 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84 115 %tmp86 = sext i1 %tmp85 to i32 116 %tmp87 = bitcast i32 %tmp86 to float 117 %tmp88 = bitcast float %tmp87 to i32 118 %tmp89 = icmp ne i32 %tmp88, 0 119 br i1 %tmp89, label %IF25, label %ENDIF24 120 121 IF25: ; preds = %ENDIF 122 %tmp90 = fsub float -0.000000e+00, %tmp70 123 %tmp91 = call float @llvm.exp2.f32(float %tmp90) 124 %tmp92 = fsub float -0.000000e+00, %tmp91 125 %tmp93 = fadd float 1.000000e+00, %tmp92 126 %tmp94 = fdiv float 1.000000e+00, %tmp70 127 %tmp95 = fmul float %tmp93, %tmp94 128 %tmp96 = fmul float %tmp35, %tmp95 129 br label %ENDIF24 130 131 ENDIF24: ; preds = %IF25, %ENDIF 132 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ] 133 %tmp97 = fmul float %tmp28, %temp4.0 134 %tmp98 = fmul float %tmp29, %temp4.0 135 %tmp99 = fmul float %tmp30, %temp4.0 136 %tmp100 = fmul float %tmp32, %temp8.0 137 %tmp101 = fadd float %tmp100, %tmp97 138 %tmp102 = fmul float %tmp33, %temp8.0 139 %tmp103 = fadd float %tmp102, %tmp98 140 %tmp104 = fmul float %tmp34, %temp8.0 141 %tmp105 = fadd float %tmp104, %tmp99 142 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21) 143 %tmp107 = fsub float -0.000000e+00, %tmp101 144 %tmp108 = fmul float %tmp107, %tmp106 145 %tmp109 = fsub float -0.000000e+00, %tmp103 146 %tmp110 = fmul float %tmp109, %tmp106 147 %tmp111 = fsub float -0.000000e+00, %tmp105 148 %tmp112 = fmul float %tmp111, %tmp106 149 %tmp113 = call i32 @llvm.SI.packf16(float %tmp108, float %tmp110) 150 %tmp114 = bitcast i32 %tmp113 to float 151 %tmp115 = call i32 @llvm.SI.packf16(float %tmp112, float 1.000000e+00) 152 %tmp116 = bitcast i32 %tmp115 to float 153 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp114, float %tmp116, float %tmp114, float %tmp116) 154 ret void 155 } 156 157 ; We just want ot make sure the program doesn't crash 158 ; CHECK-LABEL: {{^}}loop: 159 define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 160 main_body: 161 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 162 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 163 %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) 164 %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 4) 165 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 8) 166 %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 12) 167 %tmp25 = fptosi float %tmp24 to i32 168 %tmp26 = bitcast i32 %tmp25 to float 169 %tmp27 = bitcast float %tmp26 to i32 170 br label %LOOP 171 172 LOOP: ; preds = %ENDIF, %main_body 173 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ] 174 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ] 175 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ] 176 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ] 177 %tmp28 = bitcast float %temp8.0 to i32 178 %tmp29 = icmp sge i32 %tmp28, %tmp27 179 %tmp30 = sext i1 %tmp29 to i32 180 %tmp31 = bitcast i32 %tmp30 to float 181 %tmp32 = bitcast float %tmp31 to i32 182 %tmp33 = icmp ne i32 %tmp32, 0 183 br i1 %tmp33, label %IF, label %ENDIF 184 185 IF: ; preds = %LOOP 186 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00) 187 ret void 188 189 ENDIF: ; preds = %LOOP 190 %tmp34 = bitcast float %temp8.0 to i32 191 %tmp35 = add i32 %tmp34, 1 192 %tmp36 = bitcast i32 %tmp35 to float 193 br label %LOOP 194 } 195 196 ; Function Attrs: nounwind readnone 197 declare float @llvm.SI.load.const(<16 x i8>, i32) #1 198 199 ; Function Attrs: readonly 200 declare float @fabs(float) #2 201 202 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 203 204 ; Function Attrs: nounwind readnone 205 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 206 207 ; Function Attrs: nounwind readnone 208 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <8 x i32>, <16 x i8>, i32) #1 209 210 ; Function Attrs: readnone 211 declare float @llvm.amdgcn.rsq.f32(float) #1 212 213 declare float @llvm.exp2.f32(float) #1 214 215 ; Function Attrs: nounwind readnone 216 declare float @llvm.pow.f32(float, float) #1 217 218 ; Function Attrs: nounwind readnone 219 declare i32 @llvm.SI.packf16(float, float) #1 220 221 ; This checks for a bug in the FixSGPRCopies pass where VReg96 222 ; registers were being identified as an SGPR regclass which was causing 223 ; an assertion failure. 224 225 ; CHECK-LABEL: {{^}}sample_v3: 226 ; CHECK: image_sample 227 ; CHECK: image_sample 228 ; CHECK: exp 229 ; CHECK: s_endpgm 230 define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 231 entry: 232 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 233 %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 234 %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 16) 235 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 236 %tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0 237 %tmp25 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0 238 %tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0 239 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 240 %tmp26.bc = bitcast <16 x i8> %tmp26 to <4 x i32> 241 br i1 %tmp27, label %if, label %else 242 243 if: ; preds = %entry 244 %val.if = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> zeroinitializer, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 245 %val.if.0 = extractelement <4 x float> %val.if, i32 0 246 %val.if.1 = extractelement <4 x float> %val.if, i32 1 247 %val.if.2 = extractelement <4 x float> %val.if, i32 2 248 br label %endif 249 250 else: ; preds = %entry 251 %val.else = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1, i32 0>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 252 %val.else.0 = extractelement <4 x float> %val.else, i32 0 253 %val.else.1 = extractelement <4 x float> %val.else, i32 1 254 %val.else.2 = extractelement <4 x float> %val.else, i32 2 255 br label %endif 256 257 endif: ; preds = %else, %if 258 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ] 259 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ] 260 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ] 261 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.000000e+00) 262 ret void 263 } 264 265 ; CHECK-LABEL: {{^}}copy1: 266 ; CHECK: buffer_load_dword 267 ; CHECK: v_add 268 ; CHECK: s_endpgm 269 define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { 270 entry: 271 %tmp = load float, float addrspace(1)* %in0 272 %tmp1 = fcmp oeq float %tmp, 0.000000e+00 273 br i1 %tmp1, label %if0, label %endif 274 275 if0: ; preds = %entry 276 %tmp2 = bitcast float %tmp to i32 277 %tmp3 = fcmp olt float %tmp, 0.000000e+00 278 br i1 %tmp3, label %if1, label %endif 279 280 if1: ; preds = %if0 281 %tmp4 = add i32 %tmp2, 1 282 br label %endif 283 284 endif: ; preds = %if1, %if0, %entry 285 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ] 286 %tmp6 = bitcast i32 %tmp5 to float 287 store float %tmp6, float addrspace(1)* %out 288 ret void 289 } 290 291 ; This test is just checking that we don't crash / assertion fail. 292 ; CHECK-LABEL: {{^}}copy2: 293 ; CHECK: s_endpgm 294 define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 295 entry: 296 br label %LOOP68 297 298 LOOP68: ; preds = %ENDIF69, %entry 299 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] 300 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] 301 %g = icmp eq i32 0, %t 302 %l = bitcast float %temp4.7 to i32 303 br i1 %g, label %IF70, label %ENDIF69 304 305 IF70: ; preds = %LOOP68 306 %q = icmp ne i32 %l, 13 307 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 308 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) 309 ret void 310 311 ENDIF69: ; preds = %LOOP68 312 %u = add i32 %l, %t 313 %v = bitcast i32 %u to float 314 %x = add i32 %t, -1 315 br label %LOOP68 316 } 317 318 ; This test checks that image_sample resource descriptors aren't loaded into 319 ; vgprs. The verifier will fail if this happens. 320 ; CHECK-LABEL:{{^}}sample_rsrc: 321 ; CHECK: image_sample 322 ; CHECK: image_sample 323 ; CHECK: s_endpgm 324 define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 325 bb: 326 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0 327 %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !2 328 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16) 329 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0 330 %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !2 331 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0 332 %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !2 333 %tmp29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg7) 334 %tmp30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg7) 335 %tmp31 = bitcast float %tmp23 to i32 336 %tmp36 = icmp ne i32 %tmp31, 0 337 br i1 %tmp36, label %bb38, label %bb80 338 339 bb38: ; preds = %bb 340 %tmp52 = bitcast float %tmp29 to i32 341 %tmp53 = bitcast float %tmp30 to i32 342 %tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0 343 %tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1 344 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32> 345 %tmp58 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp55, <8 x i32> %tmp56, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 346 br label %bb71 347 348 bb80: ; preds = %bb 349 %tmp81 = bitcast float %tmp29 to i32 350 %tmp82 = bitcast float %tmp30 to i32 351 %tmp82.2 = add i32 %tmp82, 1 352 %tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0 353 %tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1 354 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32> 355 %tmp87 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 356 br label %bb71 357 358 bb71: ; preds = %bb80, %bb38 359 %tmp72 = phi <4 x float> [ %tmp58, %bb38 ], [ %tmp87, %bb80 ] 360 %tmp88 = extractelement <4 x float> %tmp72, i32 0 361 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp88, float %tmp88, float %tmp88, float %tmp88) 362 ret void 363 } 364 365 ; Check the the resource descriptor is stored in an sgpr. 366 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: 367 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 368 define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { 369 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 370 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid 371 %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 372 %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 373 %tmp10 = extractelement <4 x float> %tmp9, i32 0 374 %tmp12 = call i32 @llvm.SI.packf16(float undef, float %tmp10) 375 %tmp13 = bitcast i32 %tmp12 to float 376 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) 377 ret void 378 } 379 380 ; Check the the sampler is stored in an sgpr. 381 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: 382 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 383 define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 { 384 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 385 %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid 386 %tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0 387 %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 388 %tmp10 = extractelement <4 x float> %tmp9, i32 0 389 %tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef) 390 %tmp13 = bitcast i32 %tmp12 to float 391 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) 392 ret void 393 } 394 395 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 396 397 attributes #0 = { nounwind } 398 attributes #1 = { nounwind readnone } 399 attributes #2 = { nounwind readonly } 400 401 !0 = !{!1, !1, i64 0, i32 1} 402 !1 = !{!"const", null} 403 !2 = !{!1, !1, i64 0} 404
