1 ; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so 2 ; we need to disable this when the si scheduler is being used. 3 ; The only way the subtarget knows that the si machine scheduler is being used 4 ; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend 5 ; won't know what scheduler we are using. 6 ; RUN: llc -march=amdgcn -mcpu=SI --misched=si -mattr=si-scheduler < %s | FileCheck %s 7 8 ; The test checks the "si" machine scheduler pass works correctly. 9 10 ; CHECK-LABEL: {{^}}main: 11 ; CHECK: s_wqm 12 ; CHECK: s_load_dwordx4 13 ; CHECK: s_load_dwordx8 14 ; CHECK: s_waitcnt lgkmcnt(0) 15 ; CHECK: image_sample 16 ; CHECK: s_waitcnt vmcnt(0) 17 ; CHECK: exp 18 ; CHECK: s_endpgm 19 define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 20 main_body: 21 %tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)* 22 %tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0 23 %tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)* 24 %tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0 25 %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11) 26 %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11) 27 %tmp27 = bitcast float %tmp25 to i32 28 %tmp28 = bitcast float %tmp26 to i32 29 %tmp29 = insertelement <2 x i32> undef, i32 %tmp27, i32 0 30 %tmp30 = insertelement <2 x i32> %tmp29, i32 %tmp28, i32 1 31 %tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32> 32 %tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32> 33 %tmp31 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp30, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 34 %tmp32 = extractelement <4 x float> %tmp31, i32 0 35 %tmp33 = extractelement <4 x float> %tmp31, i32 1 36 %tmp34 = extractelement <4 x float> %tmp31, i32 2 37 %tmp35 = extractelement <4 x float> %tmp31, i32 3 38 %tmp36 = call i32 @llvm.SI.packf16(float %tmp32, float %tmp33) 39 %tmp37 = bitcast i32 %tmp36 to float 40 %tmp38 = call i32 @llvm.SI.packf16(float %tmp34, float %tmp35) 41 %tmp39 = bitcast i32 %tmp38 to float 42 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp37, float %tmp39, float %tmp37, float %tmp39) 43 ret void 44 } 45 46 ; Function Attrs: nounwind readnone 47 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 48 49 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 50 51 52 ; Function Attrs: nounwind readnone 53 declare i32 @llvm.SI.packf16(float, float) #1 54 55 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 56 57 attributes #1 = { nounwind readnone } 58 59 !0 = !{!1, !1, i64 0, i32 1} 60 !1 = !{!"const", null} 61
