1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 3 declare i32 @llvm.amdgcn.workitem.id.x() readnone 4 5 ; This is broken because the low half of the 64-bit add remains on the 6 ; SALU, but the upper half does not. The addc expects the carry bit 7 ; set in vcc, which is undefined since the low scalar half add sets 8 ; scc instead. 9 10 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_0: 11 ; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0x18f, v{{[0-9]+}} 12 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 13 define void @imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %s.val) { 14 %v.val = load volatile i32, i32 addrspace(1)* %in 15 %vec.0 = insertelement <2 x i32> undef, i32 %s.val, i32 0 16 %vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1 17 %bc = bitcast <2 x i32> %vec.1 to i64 18 %add = add i64 %bc, 399 19 store i64 %add, i64 addrspace(1)* %out, align 8 20 ret void 21 } 22 23 ; FUNC-LABEL: {{^}}s_imp_def_vcc_split_i64_add_0: 24 ; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x18f 25 ; SI: s_addc_u32 {{s[0-9]+}}, 0xf423f, 0 26 define void @s_imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 %val) { 27 %vec.0 = insertelement <2 x i32> undef, i32 %val, i32 0 28 %vec.1 = insertelement <2 x i32> %vec.0, i32 999999, i32 1 29 %bc = bitcast <2 x i32> %vec.1 to i64 30 %add = add i64 %bc, 399 31 store i64 %add, i64 addrspace(1)* %out, align 8 32 ret void 33 } 34 35 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_1: 36 ; SI: v_add_i32 37 ; SI: v_addc_u32 38 define void @imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { 39 %v.val = load volatile i32, i32 addrspace(1)* %in 40 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 41 %vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1 42 %bc = bitcast <2 x i32> %vec.1 to i64 43 %add = add i64 %bc, %val1 44 store i64 %add, i64 addrspace(1)* %out, align 8 45 ret void 46 } 47 48 ; FUNC-LABEL: {{^}}s_imp_def_vcc_split_i64_add_1: 49 ; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 50 ; SI: s_addc_u32 {{s[0-9]+}}, 0x1869f, {{s[0-9]+}} 51 define void @s_imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64 %val1) { 52 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 53 %vec.1 = insertelement <2 x i32> %vec.0, i32 99999, i32 1 54 %bc = bitcast <2 x i32> %vec.1 to i64 55 %add = add i64 %bc, %val1 56 store i64 %add, i64 addrspace(1)* %out, align 8 57 ret void 58 } 59 60 ; Doesn't use constants 61 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_2: 62 ; SI: v_add_i32_e32 {{v[0-9]+}}, vcc, {{s[0-9]+}}, {{v[0-9]+}} 63 ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc 64 define void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { 65 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone 66 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 67 %load = load i32, i32 addrspace(1)* %gep 68 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 69 %vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1 70 %bc = bitcast <2 x i32> %vec.1 to i64 71 %add = add i64 %bc, %val1 72 store i64 %add, i64 addrspace(1)* %out, align 8 73 ret void 74 } 75
