1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 3 ; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. 4 ; Make sure that when we split an smrd instruction in order to move it to 5 ; the VALU, we are also moving its users to the VALU. 6 ; CHECK-LABEL: {{^}}split_smrd_add_worklist: 7 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 8 9 define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { 10 bb: 11 %tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 96) 12 %tmp1 = bitcast float %tmp to i32 13 br i1 undef, label %bb2, label %bb3 14 15 bb2: ; preds = %bb 16 unreachable 17 18 bb3: ; preds = %bb 19 %tmp4 = bitcast float %tmp to i32 20 %tmp5 = add i32 %tmp4, 4 21 %tmp6 = sext i32 %tmp5 to i64 22 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i64 0, i64 %tmp6 23 %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 24 %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 25 %tmp10 = extractelement <4 x float> %tmp9, i32 0 26 %tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef) 27 %tmp13 = bitcast i32 %tmp12 to float 28 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %tmp13, float undef, float undef) 29 ret void 30 } 31 32 ; Function Attrs: nounwind readnone 33 declare float @llvm.SI.load.const(<16 x i8>, i32) #1 34 35 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 36 37 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 38 39 declare i32 @llvm.SI.packf16(float, float) #1 40 41 attributes #0 = { nounwind } 42 attributes #1 = { nounwind readnone } 43 44 !0 = !{!1, !1, i64 0, i32 1} 45 !1 = !{!"const", null} 46 !2 = !{!1, !1, i64 0} 47
