1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that 4 ; is compiles without errors. 5 ; CHECK: valign 6 ; CHECK: vshuff 7 8 target triple = "hexagon" 9 10 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0 11 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0 12 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 13 14 define void @fred() #1 { 15 entry: 16 %t0 = bitcast <64 x i16> zeroinitializer to <32 x i32> 17 %t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2) 18 %t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2) 19 %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2) 20 store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128 21 store <32 x i32> %t3, <32 x i32>* undef, align 128 22 unreachable 23 } 24 25 26 attributes #0 = { nounwind readnone } 27 attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } 28
