1 ; RUN: llc -march=hexagon -hexagon-extract=0 < %s | FileCheck %s 2 ; Check that we generate fused logical and with shift instruction. 3 ; Disable "extract" generation, since it may eliminate the and/lsr. 4 5 ; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) 6 7 define i32 @main(i16* %a, i16* %b) nounwind { 8 entry: 9 %0 = load i16, i16* %a, align 2 10 %conv1 = sext i16 %0 to i32 11 %shr1 = ashr i32 %conv1, 3 12 %and1 = and i32 %shr1, 15 13 %conv2 = trunc i32 %and1 to i16 14 store i16 %conv2, i16* %b, align 2 15 ret i32 0 16 } 17 18
