1 ; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s 2 3 ; Test that we generate a .cur 4 5 ; CHECK: v{{[0-9]*}}.cur{{ *}} 6 ; CHECK: v{{[0-9]*}}.cur{{ *}} 7 8 define void @conv3x3_i(i8* noalias nocapture readonly %iptr0, i32 %shift, i32 %width) #0 { 9 entry: 10 br i1 undef, label %for.body.lr.ph, label %for.end 11 12 for.body.lr.ph: 13 br label %for.body 14 15 for.body: 16 %iptr0.pn = phi i8* [ %iptr0, %for.body.lr.ph ], [ %iptr0.addr.0121, %for.body ] 17 %j.0115 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ] 18 %sline000.0114 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ %1, %for.body ] 19 %sline100.0113 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ zeroinitializer, %for.body ] 20 %iptr0.addr.0121 = getelementptr inbounds i8, i8* %iptr0.pn, i32 64 21 %0 = bitcast i8* %iptr0.addr.0121 to <16 x i32>* 22 %1 = load <16 x i32>, <16 x i32>* %0, align 64, !tbaa !1 23 %2 = load <16 x i32>, <16 x i32>* null, align 64, !tbaa !1 24 %3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %1, <16 x i32> %sline000.0114, i32 4) 25 %4 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %sline100.0113, i32 4) 26 %5 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %2, <16 x i32> zeroinitializer, i32 4) 27 %6 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %3, <16 x i32> %sline000.0114) 28 %7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %5, <16 x i32> zeroinitializer) 29 %8 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %6, i32 0, i32 0) 30 %9 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %8, <32 x i32> zeroinitializer, i32 undef, i32 0) 31 %10 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %9, <32 x i32> undef, i32 undef, i32 0) 32 %11 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %10) 33 %12 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %11, <16 x i32> undef, i32 %shift) 34 %13 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %12) 35 store <16 x i32> %13, <16 x i32>* undef, align 64, !tbaa !1 36 %14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %7, i32 undef, i32 1) 37 %15 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %14) 38 %16 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %15, <16 x i32> undef, i32 %shift) 39 %17 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %16, <16 x i32> undef) 40 store <16 x i32> %17, <16 x i32>* undef, align 64, !tbaa !1 41 %add = add nsw i32 %j.0115, 64 42 %cmp = icmp slt i32 %add, %width 43 br i1 %cmp, label %for.body, label %for.end 44 45 for.end: 46 ret void 47 } 48 49 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 50 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 51 declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1 52 declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1 53 declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1 54 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 55 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 56 57 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } 58 attributes #1 = { nounwind readnone } 59 60 !1 = !{!2, !2, i64 0} 61 !2 = !{!"omnipotent char", !3, i64 0} 62 !3 = !{!"Simple C/C++ TBAA"} 63
