1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \ 2 ; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32 3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \ 4 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \ 6 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \ 8 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \ 10 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \ 12 ; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32 13 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \ 14 ; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6 15 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ 16 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 17 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ 18 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ 20 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ 22 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ 24 ; RUN: FileCheck %s -check-prefixes=ALL,64R6 25 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ 26 ; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 27 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ 28 ; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 29 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \ 30 ; RUN: FileCheck %s -check-prefix=64R6 31 32 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { 33 entry: 34 ; ALL-LABEL: mul_i1: 35 36 ; M2: mult $4, $5 37 ; M2: mflo $[[T0:[0-9]+]] 38 ; M2: sll $[[T0]], $[[T0]], 31 39 ; M2: sra $2, $[[T0]], 31 40 41 ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5 42 ; 32R1-R5: sll $[[T0]], $[[T0]], 31 43 ; 32R1-R5: sra $2, $[[T0]], 31 44 45 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 46 ; 32R6: sll $[[T0]], $[[T0]], 31 47 ; 32R6: sra $2, $[[T0]], 31 48 49 ; M4: mult $4, $5 50 ; M4: mflo $[[T0:[0-9]+]] 51 ; M4: sll $[[T0]], $[[T0]], 31 52 ; M4: sra $2, $[[T0]], 31 53 54 ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5 55 ; 64R1-R5: sll $[[T0]], $[[T0]], 31 56 ; 64R1-R5: sra $2, $[[T0]], 31 57 58 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 59 ; 64R6: sll $[[T0]], $[[T0]], 31 60 ; 64R6: sra $2, $[[T0]], 31 61 62 ; MM32: mul $[[T0:[0-9]+]], $4, $5 63 ; MM32: sll $[[T0]], $[[T0]], 31 64 ; MM32: sra $2, $[[T0]], 31 65 66 %r = mul i1 %a, %b 67 ret i1 %r 68 } 69 70 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) { 71 entry: 72 ; ALL-LABEL: mul_i8: 73 74 ; M2: mult $4, $5 75 ; M2: mflo $[[T0:[0-9]+]] 76 ; M2: sll $[[T0]], $[[T0]], 24 77 ; M2: sra $2, $[[T0]], 24 78 79 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 80 ; 32R1: sll $[[T0]], $[[T0]], 24 81 ; 32R1: sra $2, $[[T0]], 24 82 83 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 84 ; 32R2-R5: seb $2, $[[T0]] 85 86 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 87 ; 32R6: seb $2, $[[T0]] 88 89 ; M4: mult $4, $5 90 ; M4: mflo $[[T0:[0-9]+]] 91 ; M4: sll $[[T0]], $[[T0]], 24 92 ; M4: sra $2, $[[T0]], 24 93 94 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 95 ; 64R1: sll $[[T0]], $[[T0]], 24 96 ; 64R1: sra $2, $[[T0]], 24 97 98 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 99 ; 64R2: seb $2, $[[T0]] 100 101 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 102 ; 64R6: seb $2, $[[T0]] 103 104 ; MM32: mul $[[T0:[0-9]+]], $4, $5 105 ; MM32: seb $2, $[[T0]] 106 107 %r = mul i8 %a, %b 108 ret i8 %r 109 } 110 111 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) { 112 entry: 113 ; ALL-LABEL: mul_i16: 114 115 ; M2: mult $4, $5 116 ; M2: mflo $[[T0:[0-9]+]] 117 ; M2: sll $[[T0]], $[[T0]], 16 118 ; M2: sra $2, $[[T0]], 16 119 120 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 121 ; 32R1: sll $[[T0]], $[[T0]], 16 122 ; 32R1: sra $2, $[[T0]], 16 123 124 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 125 ; 32R2-R5: seh $2, $[[T0]] 126 127 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 128 ; 32R6: seh $2, $[[T0]] 129 130 ; M4: mult $4, $5 131 ; M4: mflo $[[T0:[0-9]+]] 132 ; M4: sll $[[T0]], $[[T0]], 16 133 ; M4: sra $2, $[[T0]], 16 134 135 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 136 ; 64R1: sll $[[T0]], $[[T0]], 16 137 ; 64R1: sra $2, $[[T0]], 16 138 139 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 140 ; 64R2: seh $2, $[[T0]] 141 142 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 143 ; 64R6: seh $2, $[[T0]] 144 145 ; MM32: mul $[[T0:[0-9]+]], $4, $5 146 ; MM32: seh $2, $[[T0]] 147 148 %r = mul i16 %a, %b 149 ret i16 %r 150 } 151 152 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) { 153 entry: 154 ; ALL-LABEL: mul_i32: 155 156 ; M2: mult $4, $5 157 ; M2: mflo $2 158 159 ; 32R1-R5: mul $2, $4, $5 160 ; 32R6: mul $2, $4, $5 161 162 ; 64R1-R5: mul $2, $4, $5 163 ; 64R6: mul $2, $4, $5 164 165 ; MM32: mul $2, $4, $5 166 167 %r = mul i32 %a, %b 168 ret i32 %r 169 } 170 171 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) { 172 entry: 173 ; ALL-LABEL: mul_i64: 174 175 ; M2: mult $4, $7 176 ; M2: mflo $[[T0:[0-9]+]] 177 ; M2: mult $5, $6 178 ; M2: mflo $[[T1:[0-9]+]] 179 ; M2: multu $5, $7 180 ; M2: mflo $3 181 ; M2: mfhi $4 182 ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]] 183 ; M2: addu $2, $[[T2]], $[[T0]] 184 185 ; 32R1-R5: multu $5, $7 186 ; 32R1-R5: mflo $3 187 ; 32R1-R5: mfhi $[[T0:[0-9]+]] 188 ; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7 189 ; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6 190 ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] 191 ; 32R1-R5: addu $2, $[[T0]], $[[T1]] 192 193 ; 32R6-DAG: mul $3, $5, $7 194 ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7 195 ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6 196 ; 32R6: muhu $[[T2:[0-9]+]], $5, $7 197 ; 32R6: addu $[[T1]], $[[T2]], $[[T1]] 198 ; 32R6: addu $2, $[[T1]], $[[T0]] 199 200 ; M4: dmult $4, $5 201 ; M4: mflo $2 202 203 ; 64R1-R5: dmult $4, $5 204 ; 64R1-R5: mflo $2 205 206 ; 64R6: dmul $2, $4, $5 207 208 ; MM32R3: multu $[[T0:[0-9]+]], $7 209 ; MM32R3: mflo $[[T1:[0-9]+]] 210 ; MM32R3: mfhi $[[T2:[0-9]+]] 211 ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 212 ; MM32R3: mul $[[T0]], $[[T0]], $6 213 ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]] 214 ; MM32R3: addu16 $2, $[[T2]], $[[T3]] 215 216 ; MM32R6: mul $[[T0:[0-9]+]], $5, $7 217 ; MM32R6: mul $[[T1:[0-9]+]], $4, $7 218 ; MM32R6: mul $[[T2:[0-9]+]], $5, $6 219 ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7 220 ; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]] 221 ; MM32R6: addu16 $2, $[[T2]], $[[T1]] 222 223 %r = mul i64 %a, %b 224 ret i64 %r 225 } 226 227 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { 228 entry: 229 ; ALL-LABEL: mul_i128: 230 231 ; GP32: lw $25, %call16(__multi3)($gp) 232 233 ; GP64-NOT-R6: dmult $4, $7 234 ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] 235 ; GP64-NOT-R6: dmult $5, $6 236 ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] 237 ; GP64-NOT-R6: dmultu $5, $7 238 ; GP64-NOT-R6: mflo $3 239 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] 240 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] 241 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] 242 243 ; 64R6-DAG: dmul $3, $5, $7 244 ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 245 ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 246 ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 247 ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] 248 ; 64R6: daddu $2, $[[T1]], $[[T0]] 249 250 ; MM32: lw $25, %call16(__multi3)($2) 251 252 %r = mul i128 %a, %b 253 ret i128 %r 254 } 255
