1 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ 2 ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s 3 ; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ 4 ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s 5 6 @a = global i32 10, align 4 7 @b = global i32 0, align 4 8 @c = global i32 10, align 4 9 @d = global i32 0, align 4 10 11 define i32 @shift_left() nounwind { 12 entry: 13 %0 = load i32, i32* @a, align 4 14 %shl = shl i32 %0, 4 15 store i32 %shl, i32* @b, align 4 16 17 %1 = load i32, i32* @c, align 4 18 %shl1 = shl i32 %1, 10 19 store i32 %shl1, i32* @d, align 4 20 21 ret i32 0 22 } 23 24 ; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} 25 ; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} 26 27 @i = global i32 10654, align 4 28 @j = global i32 0, align 4 29 @m = global i32 10, align 4 30 @n = global i32 0, align 4 31 32 define i32 @shift_right() nounwind { 33 entry: 34 %0 = load i32, i32* @i, align 4 35 %shr = lshr i32 %0, 4 36 store i32 %shr, i32* @j, align 4 37 38 %1 = load i32, i32* @m, align 4 39 %shr1 = lshr i32 %1, 10 40 store i32 %shr1, i32* @n, align 4 41 42 ret i32 0 43 } 44 45 ; CHECK: srl16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} 46 ; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} 47
