1 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s 2 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s 3 4 ; Function Attrs: nounwind 5 define zeroext i8 @_Z6testcff(float %arg) { 6 entry: 7 %arg.addr = alloca float, align 4 8 store float %arg, float* %arg.addr, align 4 9 %0 = load float, float* %arg.addr, align 4 10 %conv = fptoui float %0 to i8 11 ret i8 %conv 12 ; CHECK-LABEL: @_Z6testcff 13 ; CHECK: xscvdpsxws [[CONVREG01:[0-9]+]], 1 14 ; CHECK: mfvsrwz 3, [[CONVREG01]] 15 } 16 17 ; Function Attrs: nounwind 18 define float @_Z6testfcc(i8 zeroext %arg) { 19 entry: 20 %arg.addr = alloca i8, align 1 21 store i8 %arg, i8* %arg.addr, align 1 22 %0 = load i8, i8* %arg.addr, align 1 23 %conv = uitofp i8 %0 to float 24 ret float %conv 25 ; CHECK-LABEL: @_Z6testfcc 26 ; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3 27 ; CHECK: xscvuxdsp 1, [[MOVEREG01]] 28 } 29 30 ; Function Attrs: nounwind 31 define zeroext i8 @_Z6testcdd(double %arg) { 32 entry: 33 %arg.addr = alloca double, align 8 34 store double %arg, double* %arg.addr, align 8 35 %0 = load double, double* %arg.addr, align 8 36 %conv = fptoui double %0 to i8 37 ret i8 %conv 38 ; CHECK-LABEL: @_Z6testcdd 39 ; CHECK: xscvdpsxws [[CONVREG02:[0-9]+]], 1 40 ; CHECK: mfvsrwz 3, [[CONVREG02]] 41 } 42 43 ; Function Attrs: nounwind 44 define double @_Z6testdcc(i8 zeroext %arg) { 45 entry: 46 %arg.addr = alloca i8, align 1 47 store i8 %arg, i8* %arg.addr, align 1 48 %0 = load i8, i8* %arg.addr, align 1 49 %conv = uitofp i8 %0 to double 50 ret double %conv 51 ; CHECK-LABEL: @_Z6testdcc 52 ; CHECK: mtvsrwz [[MOVEREG02:[0-9]+]], 3 53 ; CHECK: xscvuxddp 1, [[MOVEREG02]] 54 } 55 56 ; Function Attrs: nounwind 57 define zeroext i8 @_Z7testucff(float %arg) { 58 entry: 59 %arg.addr = alloca float, align 4 60 store float %arg, float* %arg.addr, align 4 61 %0 = load float, float* %arg.addr, align 4 62 %conv = fptoui float %0 to i8 63 ret i8 %conv 64 ; CHECK-LABEL: @_Z7testucff 65 ; CHECK: xscvdpsxws [[CONVREG03:[0-9]+]], 1 66 ; CHECK: mfvsrwz 3, [[CONVREG03]] 67 } 68 69 ; Function Attrs: nounwind 70 define float @_Z7testfuch(i8 zeroext %arg) { 71 entry: 72 %arg.addr = alloca i8, align 1 73 store i8 %arg, i8* %arg.addr, align 1 74 %0 = load i8, i8* %arg.addr, align 1 75 %conv = uitofp i8 %0 to float 76 ret float %conv 77 ; CHECK-LABEL: @_Z7testfuch 78 ; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3 79 ; CHECK: xscvuxdsp 1, [[MOVEREG03]] 80 } 81 82 ; Function Attrs: nounwind 83 define zeroext i8 @_Z7testucdd(double %arg) { 84 entry: 85 %arg.addr = alloca double, align 8 86 store double %arg, double* %arg.addr, align 8 87 %0 = load double, double* %arg.addr, align 8 88 %conv = fptoui double %0 to i8 89 ret i8 %conv 90 ; CHECK-LABEL: @_Z7testucdd 91 ; CHECK: xscvdpsxws [[CONVREG04:[0-9]+]], 1 92 ; CHECK: mfvsrwz 3, [[CONVREG04]] 93 } 94 95 ; Function Attrs: nounwind 96 define double @_Z7testduch(i8 zeroext %arg) { 97 entry: 98 %arg.addr = alloca i8, align 1 99 store i8 %arg, i8* %arg.addr, align 1 100 %0 = load i8, i8* %arg.addr, align 1 101 %conv = uitofp i8 %0 to double 102 ret double %conv 103 ; CHECK-LABEL: @_Z7testduch 104 ; CHECK: mtvsrwz [[MOVEREG04:[0-9]+]], 3 105 ; CHECK: xscvuxddp 1, [[MOVEREG04]] 106 } 107 108 ; Function Attrs: nounwind 109 define signext i16 @_Z6testsff(float %arg) { 110 entry: 111 %arg.addr = alloca float, align 4 112 store float %arg, float* %arg.addr, align 4 113 %0 = load float, float* %arg.addr, align 4 114 %conv = fptosi float %0 to i16 115 ret i16 %conv 116 ; CHECK-LABEL: @_Z6testsff 117 ; CHECK: xscvdpsxws [[CONVREG05:[0-9]+]], 1 118 ; CHECK: mfvsrwz 3, [[CONVREG05]] 119 } 120 121 ; Function Attrs: nounwind 122 define float @_Z6testfss(i16 signext %arg) { 123 entry: 124 %arg.addr = alloca i16, align 2 125 store i16 %arg, i16* %arg.addr, align 2 126 %0 = load i16, i16* %arg.addr, align 2 127 %conv = sitofp i16 %0 to float 128 ret float %conv 129 ; CHECK-LABEL: @_Z6testfss 130 ; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3 131 ; CHECK: xscvsxdsp 1, [[MOVEREG05]] 132 } 133 134 ; Function Attrs: nounwind 135 define signext i16 @_Z6testsdd(double %arg) { 136 entry: 137 %arg.addr = alloca double, align 8 138 store double %arg, double* %arg.addr, align 8 139 %0 = load double, double* %arg.addr, align 8 140 %conv = fptosi double %0 to i16 141 ret i16 %conv 142 ; CHECK-LABEL: @_Z6testsdd 143 ; CHECK: xscvdpsxws [[CONVREG06:[0-9]+]], 1 144 ; CHECK: mfvsrwz 3, [[CONVREG06]] 145 } 146 147 ; Function Attrs: nounwind 148 define double @_Z6testdss(i16 signext %arg) { 149 entry: 150 %arg.addr = alloca i16, align 2 151 store i16 %arg, i16* %arg.addr, align 2 152 %0 = load i16, i16* %arg.addr, align 2 153 %conv = sitofp i16 %0 to double 154 ret double %conv 155 ; CHECK-LABEL: @_Z6testdss 156 ; CHECK: mtvsrwa [[MOVEREG06:[0-9]+]], 3 157 ; CHECK: xscvsxddp 1, [[MOVEREG06]] 158 } 159 160 ; Function Attrs: nounwind 161 define zeroext i16 @_Z7testusff(float %arg) { 162 entry: 163 %arg.addr = alloca float, align 4 164 store float %arg, float* %arg.addr, align 4 165 %0 = load float, float* %arg.addr, align 4 166 %conv = fptoui float %0 to i16 167 ret i16 %conv 168 ; CHECK-LABEL: @_Z7testusff 169 ; CHECK: xscvdpsxws [[CONVREG07:[0-9]+]], 1 170 ; CHECK: mfvsrwz 3, [[CONVREG07]] 171 } 172 173 ; Function Attrs: nounwind 174 define float @_Z7testfust(i16 zeroext %arg) { 175 entry: 176 %arg.addr = alloca i16, align 2 177 store i16 %arg, i16* %arg.addr, align 2 178 %0 = load i16, i16* %arg.addr, align 2 179 %conv = uitofp i16 %0 to float 180 ret float %conv 181 ; CHECK-LABEL: @_Z7testfust 182 ; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3 183 ; CHECK: xscvuxdsp 1, [[MOVEREG07]] 184 } 185 186 ; Function Attrs: nounwind 187 define zeroext i16 @_Z7testusdd(double %arg) { 188 entry: 189 %arg.addr = alloca double, align 8 190 store double %arg, double* %arg.addr, align 8 191 %0 = load double, double* %arg.addr, align 8 192 %conv = fptoui double %0 to i16 193 ret i16 %conv 194 ; CHECK-LABEL: @_Z7testusdd 195 ; CHECK: xscvdpsxws [[CONVREG08:[0-9]+]], 1 196 ; CHECK: mfvsrwz 3, [[CONVREG08]] 197 } 198 199 ; Function Attrs: nounwind 200 define double @_Z7testdust(i16 zeroext %arg) { 201 entry: 202 %arg.addr = alloca i16, align 2 203 store i16 %arg, i16* %arg.addr, align 2 204 %0 = load i16, i16* %arg.addr, align 2 205 %conv = uitofp i16 %0 to double 206 ret double %conv 207 ; CHECK-LABEL: @_Z7testdust 208 ; CHECK: mtvsrwz [[MOVEREG08:[0-9]+]], 3 209 ; CHECK: xscvuxddp 1, [[MOVEREG08]] 210 } 211 212 ; Function Attrs: nounwind 213 define signext i32 @_Z6testiff(float %arg) { 214 entry: 215 %arg.addr = alloca float, align 4 216 store float %arg, float* %arg.addr, align 4 217 %0 = load float, float* %arg.addr, align 4 218 %conv = fptosi float %0 to i32 219 ret i32 %conv 220 ; CHECK-LABEL: @_Z6testiff 221 ; CHECK: xscvdpsxws [[CONVREG09:[0-9]+]], 1 222 ; CHECK: mfvsrwz 3, [[CONVREG09]] 223 } 224 225 ; Function Attrs: nounwind 226 define float @_Z6testfii(i32 signext %arg) { 227 entry: 228 %arg.addr = alloca i32, align 4 229 store i32 %arg, i32* %arg.addr, align 4 230 %0 = load i32, i32* %arg.addr, align 4 231 %conv = sitofp i32 %0 to float 232 ret float %conv 233 ; CHECK-LABEL: @_Z6testfii 234 ; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3 235 ; CHECK: xscvsxdsp 1, [[MOVEREG09]] 236 } 237 238 ; Function Attrs: nounwind 239 define signext i32 @_Z6testidd(double %arg) { 240 entry: 241 %arg.addr = alloca double, align 8 242 store double %arg, double* %arg.addr, align 8 243 %0 = load double, double* %arg.addr, align 8 244 %conv = fptosi double %0 to i32 245 ret i32 %conv 246 ; CHECK-LABEL: @_Z6testidd 247 ; CHECK: xscvdpsxws [[CONVREG10:[0-9]+]], 1 248 ; CHECK: mfvsrwz 3, [[CONVREG10]] 249 } 250 251 ; Function Attrs: nounwind 252 define double @_Z6testdii(i32 signext %arg) { 253 entry: 254 %arg.addr = alloca i32, align 4 255 store i32 %arg, i32* %arg.addr, align 4 256 %0 = load i32, i32* %arg.addr, align 4 257 %conv = sitofp i32 %0 to double 258 ret double %conv 259 ; CHECK-LABEL: @_Z6testdii 260 ; CHECK: mtvsrwa [[MOVEREG10:[0-9]+]], 3 261 ; CHECK: xscvsxddp 1, [[MOVEREG10]] 262 } 263 264 ; Function Attrs: nounwind 265 define zeroext i32 @_Z7testuiff(float %arg) { 266 entry: 267 %arg.addr = alloca float, align 4 268 store float %arg, float* %arg.addr, align 4 269 %0 = load float, float* %arg.addr, align 4 270 %conv = fptoui float %0 to i32 271 ret i32 %conv 272 ; CHECK-LABEL: @_Z7testuiff 273 ; CHECK: xscvdpuxws [[CONVREG11:[0-9]+]], 1 274 ; CHECK: mfvsrwz 3, [[CONVREG11]] 275 } 276 277 ; Function Attrs: nounwind 278 define float @_Z7testfuij(i32 zeroext %arg) { 279 entry: 280 %arg.addr = alloca i32, align 4 281 store i32 %arg, i32* %arg.addr, align 4 282 %0 = load i32, i32* %arg.addr, align 4 283 %conv = uitofp i32 %0 to float 284 ret float %conv 285 ; CHECK-LABEL: @_Z7testfuij 286 ; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3 287 ; CHECK: xscvuxdsp 1, [[MOVEREG11]] 288 } 289 290 ; Function Attrs: nounwind 291 define zeroext i32 @_Z7testuidd(double %arg) { 292 entry: 293 %arg.addr = alloca double, align 8 294 store double %arg, double* %arg.addr, align 8 295 %0 = load double, double* %arg.addr, align 8 296 %conv = fptoui double %0 to i32 297 ret i32 %conv 298 ; CHECK-LABEL: @_Z7testuidd 299 ; CHECK: xscvdpuxws [[CONVREG12:[0-9]+]], 1 300 ; CHECK: mfvsrwz 3, [[CONVREG12]] 301 } 302 303 ; Function Attrs: nounwind 304 define double @_Z7testduij(i32 zeroext %arg) { 305 entry: 306 %arg.addr = alloca i32, align 4 307 store i32 %arg, i32* %arg.addr, align 4 308 %0 = load i32, i32* %arg.addr, align 4 309 %conv = uitofp i32 %0 to double 310 ret double %conv 311 ; CHECK-LABEL: @_Z7testduij 312 ; CHECK: mtvsrwz [[MOVEREG12:[0-9]+]], 3 313 ; CHECK: xscvuxddp 1, [[MOVEREG12]] 314 } 315 316 ; Function Attrs: nounwind 317 define i64 @_Z7testllff(float %arg) { 318 entry: 319 %arg.addr = alloca float, align 4 320 store float %arg, float* %arg.addr, align 4 321 %0 = load float, float* %arg.addr, align 4 322 %conv = fptosi float %0 to i64 323 ret i64 %conv 324 ; CHECK-LABEL: @_Z7testllff 325 ; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1 326 ; CHECK: mfvsrd 3, [[CONVREG13]] 327 } 328 329 ; Function Attrs: nounwind 330 define float @_Z7testfllx(i64 %arg) { 331 entry: 332 %arg.addr = alloca i64, align 8 333 store i64 %arg, i64* %arg.addr, align 8 334 %0 = load i64, i64* %arg.addr, align 8 335 %conv = sitofp i64 %0 to float 336 ret float %conv 337 ; CHECK-LABEL:@_Z7testfllx 338 ; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3 339 ; CHECK: xscvsxdsp 1, [[MOVEREG13]] 340 } 341 342 ; Function Attrs: nounwind 343 define i64 @_Z7testlldd(double %arg) { 344 entry: 345 %arg.addr = alloca double, align 8 346 store double %arg, double* %arg.addr, align 8 347 %0 = load double, double* %arg.addr, align 8 348 %conv = fptosi double %0 to i64 349 ret i64 %conv 350 ; CHECK-LABEL: @_Z7testlldd 351 ; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1 352 ; CHECK: mfvsrd 3, [[CONVREG14]] 353 } 354 355 ; Function Attrs: nounwind 356 define double @_Z7testdllx(i64 %arg) { 357 entry: 358 %arg.addr = alloca i64, align 8 359 store i64 %arg, i64* %arg.addr, align 8 360 %0 = load i64, i64* %arg.addr, align 8 361 %conv = sitofp i64 %0 to double 362 ret double %conv 363 ; CHECK-LABEL: @_Z7testdllx 364 ; CHECK: mtvsrd [[MOVEREG14:[0-9]+]], 3 365 ; CHECK: xscvsxddp 1, [[MOVEREG14]] 366 } 367 368 ; Function Attrs: nounwind 369 define i64 @_Z8testullff(float %arg) { 370 entry: 371 %arg.addr = alloca float, align 4 372 store float %arg, float* %arg.addr, align 4 373 %0 = load float, float* %arg.addr, align 4 374 %conv = fptoui float %0 to i64 375 ret i64 %conv 376 ; CHECK-LABEL: @_Z8testullff 377 ; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1 378 ; CHECK: mfvsrd 3, [[CONVREG15]] 379 } 380 381 ; Function Attrs: nounwind 382 define float @_Z8testfully(i64 %arg) { 383 entry: 384 %arg.addr = alloca i64, align 8 385 store i64 %arg, i64* %arg.addr, align 8 386 %0 = load i64, i64* %arg.addr, align 8 387 %conv = uitofp i64 %0 to float 388 ret float %conv 389 ; CHECK-LABEL: @_Z8testfully 390 ; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3 391 ; CHECK: xscvuxdsp 1, [[MOVEREG15]] 392 } 393 394 ; Function Attrs: nounwind 395 define i64 @_Z8testulldd(double %arg) { 396 entry: 397 %arg.addr = alloca double, align 8 398 store double %arg, double* %arg.addr, align 8 399 %0 = load double, double* %arg.addr, align 8 400 %conv = fptoui double %0 to i64 401 ret i64 %conv 402 ; CHECK-LABEL: @_Z8testulldd 403 ; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1 404 ; CHECK: mfvsrd 3, [[CONVREG16]] 405 } 406 407 ; Function Attrs: nounwind 408 define double @_Z8testdully(i64 %arg) { 409 entry: 410 %arg.addr = alloca i64, align 8 411 store i64 %arg, i64* %arg.addr, align 8 412 %0 = load i64, i64* %arg.addr, align 8 413 %conv = uitofp i64 %0 to double 414 ret double %conv 415 ; CHECK-LABEL: @_Z8testdully 416 ; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3 417 ; CHECK: xscvuxddp 1, [[MOVEREG16]] 418 } 419
