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      1 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
      2 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s
      3 ; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-32 %s
      4 ; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-32-PIC %s
      5 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
      6 target triple = "powerpc64-unknown-linux-gnu"
      7 
      8 %struct.s = type { i32, i32 }
      9 
     10 declare void @bar(i32*)
     11 
     12 @barbaz = external global i32
     13 
     14 define void @goo(%struct.s* byval nocapture readonly %a) {
     15 entry:
     16   %x = alloca [2 x i32], align 32
     17   %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
     18   %0 = load i32, i32* %a1, align 4
     19   %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
     20   store i32 %0, i32* %arrayidx, align 32
     21   %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
     22   %1 = load i32, i32* %b, align 4
     23   %2 = load i32, i32* @barbaz, align 4
     24   %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
     25   store i32 %2, i32* %arrayidx2, align 4
     26   call void @bar(i32* %arrayidx)
     27   ret void
     28 }
     29 
     30 ; CHECK-LABEL: @goo
     31 
     32 ; CHECK-DAG: mflr {{[0-9]+}}
     33 ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
     34 ; CHECK-DAG: std 30, -16(1)
     35 ; CHECK-DAG: mr 30, 1
     36 ; CHECK-DAG: std 0, 16(1)
     37 ; CHECK-DAG: subfic 0, [[REG]], -160
     38 ; CHECK: stdux 1, 1, 0
     39 
     40 ; CHECK: .cfi_def_cfa_register r30
     41 ; CHECK: .cfi_offset r30, -16
     42 ; CHECK: .cfi_offset lr, 16
     43 
     44 ; CHECK: std 3, 48(30)
     45 
     46 ; CHECK: ld 1, 0(1)
     47 ; CHECK-DAG: ld [[SR:[0-9]+]], 16(1)
     48 ; CHECK-DAG: ld 30, -16(1)
     49 ; CHECK-DAG: mtlr [[SR]]
     50 ; CHECK: blr
     51 
     52 ; CHECK-FP-LABEL: @goo
     53 
     54 ; CHECK-FP-DAG: mflr {{[0-9]+}}
     55 ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
     56 ; CHECK-FP-DAG: std 31, -8(1)
     57 ; CHECK-FP-DAG: std 30, -16(1)
     58 ; CHECK-FP-DAG: mr 30, 1
     59 ; CHECK-FP-DAG: std 0, 16(1)
     60 ; CHECK-FP-DAG: subfic 0, [[REG]], -160
     61 ; CHECK-FP: stdux 1, 1, 0
     62 
     63 ; CHECK-FP: .cfi_def_cfa_register r30
     64 ; CHECK-FP: .cfi_offset r31, -8
     65 ; CHECK-FP: .cfi_offset r30, -16
     66 ; CHECK-FP: .cfi_offset lr, 16
     67 
     68 ; CHECK-FP: mr 31, 1
     69 
     70 ; CHECK-FP: std 3, 48(30)
     71 
     72 ; CHECK-FP: ld 1, 0(1)
     73 ; CHECK-FP-DAG: ld [[SR:[0-9]+]], 16(1)
     74 ; CHECK-FP-DAG: ld 31, -8(1)
     75 ; CHECK-FP-DAG: ld 30, -16(1)
     76 ; CHECK-FP-DAG: mtlr [[SR]]
     77 ; CHECK-FP: blr
     78 
     79 ; CHECK-32-LABEL: @goo
     80 ; CHECK-32-DAG: mflr {{[0-9]+}}
     81 ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
     82 ; CHECK-32-DAG: stw 30, -8(1)
     83 ; CHECK-32-DAG: mr 30, 1
     84 ; CHECK-32-DAG: stw 0, 4(1)
     85 ; CHECK-32-DAG: subfic 0, [[REG]], -64
     86 ; CHECK-32: stwux 1, 1, 0
     87 
     88 ; CHECK-32-PIC-LABEL: @goo
     89 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
     90 ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
     91 ; CHECK-32-PIC-DAG: stw 29, -12(1)
     92 ; CHECK-32-PIC-DAG: mr 29, 1
     93 ; CHECK-32-PIC-DAG: stw 0, 4(1)
     94 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
     95 ; CHECK-32-PIC: stwux 1, 1, 0
     96 
     97 ; The large-frame-size case.
     98 define void @hoo(%struct.s* byval nocapture readonly %a) {
     99 entry:
    100   %x = alloca [200000 x i32], align 32
    101   %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
    102   %0 = load i32, i32* %a1, align 4
    103   %arrayidx = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 0
    104   store i32 %0, i32* %arrayidx, align 32
    105   %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
    106   %1 = load i32, i32* %b, align 4
    107   %arrayidx2 = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 1
    108   store i32 %1, i32* %arrayidx2, align 4
    109   call void @bar(i32* %arrayidx)
    110   ret void
    111 }
    112 
    113 ; CHECK-LABEL: @hoo
    114 
    115 ; CHECK-DAG: lis [[REG1:[0-9]+]], -13
    116 ; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59
    117 ; CHECK-DAG: mflr {{[0-9]+}}
    118 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
    119 ; CHECK-DAG: std 30, -16(1)
    120 ; CHECK-DAG: mr 30, 1
    121 ; CHECK-DAG: std 0, 16(1)
    122 ; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
    123 ; CHECK: stdux 1, 1, 0
    124 
    125 ; CHECK: .cfi_def_cfa_register r30
    126 
    127 ; CHECK: blr
    128 
    129 ; CHECK-32-LABEL: @hoo
    130 
    131 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
    132 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
    133 ; CHECK-32-DAG: mflr {{[0-9]+}}
    134 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
    135 ; CHECK-32-DAG: stw 30, -8(1)
    136 ; CHECK-32-DAG: mr 30, 1
    137 ; CHECK-32-DAG: stw 0, 4(1)
    138 ; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
    139 ; CHECK-32: stwux 1, 1, 0
    140 
    141 ; CHECK-32: blr
    142 
    143 ; CHECK-32-PIC-LABEL: @hoo
    144 
    145 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
    146 ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
    147 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
    148 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
    149 ; CHECK-32-PIC-DAG: stw 29, -12(1)
    150 ; CHECK-32-PIC-DAG: mr 29, 1
    151 ; CHECK-32-PIC-DAG: stw 0, 4(1)
    152 ; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
    153 ; CHECK-32: stwux 1, 1, 0
    154 
    155 ; CHECK-32: blr
    156 
    157 ; Make sure that the FP save area is still allocated correctly relative to
    158 ; where r30 is saved.
    159 define void @loo(%struct.s* byval nocapture readonly %a) {
    160 entry:
    161   %x = alloca [2 x i32], align 32
    162   %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
    163   %0 = load i32, i32* %a1, align 4
    164   %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
    165   store i32 %0, i32* %arrayidx, align 32
    166   %b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
    167   %1 = load i32, i32* %b, align 4
    168   %arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
    169   store i32 %1, i32* %arrayidx2, align 4
    170   call void @bar(i32* %arrayidx)
    171   call void asm sideeffect "", "~{f30}"() nounwind
    172   ret void
    173 }
    174 
    175 ; CHECK-LABEL: @loo
    176 
    177 ; CHECK-DAG: mflr {{[0-9]+}}
    178 ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
    179 ; CHECK-DAG: std 30, -32(1)
    180 ; CHECK-DAG: mr 30, 1
    181 ; CHECK-DAG: std 0, 16(1)
    182 ; CHECK-DAG: subfic 0, [[REG]], -192
    183 ; CHECK: stdux 1, 1, 0
    184 
    185 ; CHECK: .cfi_def_cfa_register r30
    186 
    187 ; CHECK: stfd 30, -16(30)
    188 
    189 ; CHECK: blr
    190 
    191 ; CHECK-FP-LABEL: @loo
    192 
    193 ; CHECK-FP-DAG: mflr {{[0-9]+}}
    194 ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
    195 ; CHECK-FP-DAG: std 31, -24(1)
    196 ; CHECK-FP-DAG: std 30, -32(1)
    197 ; CHECK-FP-DAG: mr 30, 1
    198 ; CHECK-FP-DAG: std 0, 16(1)
    199 ; CHECK-FP-DAG: subfic 0, [[REG]], -192
    200 ; CHECK-FP: stdux 1, 1, 0
    201 
    202 ; CHECK-FP: .cfi_def_cfa_register r30
    203 
    204 ; CHECK-FP: stfd 30, -16(30)
    205 
    206 ; CHECK-FP: blr
    207