1 ; Check VMX 64-bit integer operations 2 ; 3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 5 6 define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind { 7 %result = add <2 x i64> %x, %y 8 ret <2 x i64> %result 9 ; CHECK: vaddudm 2, 2, 3 10 } 11 12 define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind { 13 %result = add <2 x i64> %x, <i64 1, i64 1> 14 ret <2 x i64> %result 15 ; CHECK: vaddudm 2, 2, 3 16 } 17 18 define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind { 19 %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0 20 %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1 21 %result = add <2 x i64> %x, %tmpvec2 22 ret <2 x i64> %result 23 ; CHECK: vaddudm 2, 2, 3 24 ; FIXME: This is currently generating the following instruction sequence 25 ; 26 ; std 5, -8(1) 27 ; std 5, -16(1) 28 ; addi 3, 1, -16 29 ; ori 2, 2, 0 30 ; lxvd2x 35, 0, 3 31 ; vaddudm 2, 2, 3 32 ; blr 33 ; 34 ; This will almost certainly cause a load-hit-store hazard. 35 ; Since val is a value parameter, it should not need to be 36 ; saved onto the stack at all (unless we're using this to set 37 ; up the vector register). Instead, it would be better to splat 38 ; the value into a vector register. 39 } 40 41 define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind { 42 %result = sub <2 x i64> %x, %y 43 ret <2 x i64> %result 44 ; CHECK: vsubudm 2, 2, 3 45 } 46 47 define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind { 48 %result = sub <2 x i64> %x, <i64 -1, i64 -1> 49 ret <2 x i64> %result 50 ; CHECK: vsubudm 2, 2, 3 51 } 52 53 define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind { 54 %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0 55 %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1 56 %result = sub <2 x i64> %x, %tmpvec2 57 ret <2 x i64> %result 58 ; CHECK: vsubudm 2, 2, 3 59 } 60 61 62 63
