1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2 ; This test makes sure that these instructions are properly eliminated. 3 ; 4 ; RUN: opt < %s -instcombine -S | FileCheck %s 5 6 define i32 @test1(i32 %A) { 7 ; CHECK-LABEL: @test1( 8 ; CHECK-NEXT: ret i32 %A 9 ; 10 %B = shl i32 %A, 0 ; <i32> [#uses=1] 11 ret i32 %B 12 } 13 14 define i32 @test2(i8 %A) { 15 ; CHECK-LABEL: @test2( 16 ; CHECK-NEXT: ret i32 0 17 ; 18 %shift.upgrd.1 = zext i8 %A to i32 ; <i32> [#uses=1] 19 %B = shl i32 0, %shift.upgrd.1 ; <i32> [#uses=1] 20 ret i32 %B 21 } 22 23 define i32 @test3(i32 %A) { 24 ; CHECK-LABEL: @test3( 25 ; CHECK-NEXT: ret i32 %A 26 ; 27 %B = ashr i32 %A, 0 ; <i32> [#uses=1] 28 ret i32 %B 29 } 30 31 define i32 @test4(i8 %A) { 32 ; CHECK-LABEL: @test4( 33 ; CHECK-NEXT: ret i32 0 34 ; 35 %shift.upgrd.2 = zext i8 %A to i32 ; <i32> [#uses=1] 36 %B = ashr i32 0, %shift.upgrd.2 ; <i32> [#uses=1] 37 ret i32 %B 38 } 39 40 41 define i32 @test5(i32 %A) { 42 ; CHECK-LABEL: @test5( 43 ; CHECK-NEXT: ret i32 undef 44 ; 45 %B = lshr i32 %A, 32 ;; shift all bits out 46 ret i32 %B 47 } 48 49 define <4 x i32> @test5_splat_vector(<4 x i32> %A) { 50 ; CHECK-LABEL: @test5_splat_vector( 51 ; CHECK-NEXT: ret <4 x i32> undef 52 ; 53 %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 54 ret <4 x i32> %B 55 } 56 57 define <4 x i32> @test5_zero_vector(<4 x i32> %A) { 58 ; CHECK-LABEL: @test5_zero_vector( 59 ; CHECK-NEXT: ret <4 x i32> %A 60 ; 61 %B = lshr <4 x i32> %A, zeroinitializer 62 ret <4 x i32> %B 63 } 64 65 define <4 x i32> @test5_non_splat_vector(<4 x i32> %A) { 66 ; CHECK-LABEL: @test5_non_splat_vector( 67 ; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 68 ; CHECK-NEXT: ret <4 x i32> [[B]] 69 ; 70 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 71 ret <4 x i32> %B 72 } 73 74 define i32 @test5a(i32 %A) { 75 ; CHECK-LABEL: @test5a( 76 ; CHECK-NEXT: ret i32 undef 77 ; 78 %B = shl i32 %A, 32 ;; shift all bits out 79 ret i32 %B 80 } 81 82 define <4 x i32> @test5a_splat_vector(<4 x i32> %A) { 83 ; CHECK-LABEL: @test5a_splat_vector( 84 ; CHECK-NEXT: ret <4 x i32> undef 85 ; 86 %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 87 ret <4 x i32> %B 88 } 89 90 define <4 x i32> @test5a_non_splat_vector(<4 x i32> %A) { 91 ; CHECK-LABEL: @test5a_non_splat_vector( 92 ; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 93 ; CHECK-NEXT: ret <4 x i32> [[B]] 94 ; 95 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 96 ret <4 x i32> %B 97 } 98 99 define i32 @test5b() { 100 ; CHECK-LABEL: @test5b( 101 ; CHECK-NEXT: ret i32 0 102 ; 103 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 104 ret i32 %B 105 } 106 107 define i32 @test5b2(i32 %A) { 108 ; CHECK-LABEL: @test5b2( 109 ; CHECK-NEXT: ret i32 0 110 ; 111 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 112 ret i32 %B 113 } 114 115 define i32 @test6(i32 %A) { 116 ; CHECK-LABEL: @test6( 117 ; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 118 ; CHECK-NEXT: ret i32 [[C]] 119 ; 120 %B = shl i32 %A, 1 ;; convert to an mul instruction 121 %C = mul i32 %B, 3 122 ret i32 %C 123 } 124 125 define i32 @test6a(i32 %A) { 126 ; CHECK-LABEL: @test6a( 127 ; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 128 ; CHECK-NEXT: ret i32 [[C]] 129 ; 130 %B = mul i32 %A, 3 131 %C = shl i32 %B, 1 ;; convert to an mul instruction 132 ret i32 %C 133 } 134 135 define i32 @test7(i8 %A) { 136 ; CHECK-LABEL: @test7( 137 ; CHECK-NEXT: ret i32 -1 138 ; 139 %shift.upgrd.3 = zext i8 %A to i32 140 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1 141 ret i32 %B 142 } 143 144 ;; (A << 5) << 3 === A << 8 == 0 145 define i8 @test8(i8 %A) { 146 ; CHECK-LABEL: @test8( 147 ; CHECK-NEXT: ret i8 0 148 ; 149 %B = shl i8 %A, 5 ; <i8> [#uses=1] 150 %C = shl i8 %B, 3 ; <i8> [#uses=1] 151 ret i8 %C 152 } 153 154 ;; (A << 7) >> 7 === A & 1 155 define i8 @test9(i8 %A) { 156 ; CHECK-LABEL: @test9( 157 ; CHECK-NEXT: [[B:%.*]] = and i8 %A, 1 158 ; CHECK-NEXT: ret i8 [[B]] 159 ; 160 %B = shl i8 %A, 7 ; <i8> [#uses=1] 161 %C = lshr i8 %B, 7 ; <i8> [#uses=1] 162 ret i8 %C 163 } 164 165 ;; This transformation is deferred to DAGCombine: 166 ;; (A >> 7) << 7 === A & 128 167 ;; The shl may be valuable to scalar evolution. 168 define i8 @test10(i8 %A) { 169 ; CHECK-LABEL: @test10( 170 ; CHECK-NEXT: [[B:%.*]] = and i8 %A, -128 171 ; CHECK-NEXT: ret i8 [[B]] 172 ; 173 %B = lshr i8 %A, 7 ; <i8> [#uses=1] 174 %C = shl i8 %B, 7 ; <i8> [#uses=1] 175 ret i8 %C 176 } 177 178 ;; Allow the simplification when the lshr shift is exact. 179 define i8 @test10a(i8 %A) { 180 ; CHECK-LABEL: @test10a( 181 ; CHECK-NEXT: ret i8 %A 182 ; 183 %B = lshr exact i8 %A, 7 184 %C = shl i8 %B, 7 185 ret i8 %C 186 } 187 188 ;; This transformation is deferred to DAGCombine: 189 ;; (A >> 3) << 4 === (A & 0x1F) << 1 190 ;; The shl may be valuable to scalar evolution. 191 define i8 @test11(i8 %A) { 192 ; CHECK-LABEL: @test11( 193 ; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 194 ; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 3 195 ; CHECK-NEXT: [[C:%.*]] = shl i8 [[B]], 4 196 ; CHECK-NEXT: ret i8 [[C]] 197 ; 198 %a = mul i8 %A, 3 ; <i8> [#uses=1] 199 %B = lshr i8 %a, 3 ; <i8> [#uses=1] 200 %C = shl i8 %B, 4 ; <i8> [#uses=1] 201 ret i8 %C 202 } 203 204 ;; Allow the simplification in InstCombine when the lshr shift is exact. 205 define i8 @test11a(i8 %A) { 206 ; CHECK-LABEL: @test11a( 207 ; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 208 ; CHECK-NEXT: ret i8 [[C]] 209 ; 210 %a = mul i8 %A, 3 211 %B = lshr exact i8 %a, 3 212 %C = shl i8 %B, 4 213 ret i8 %C 214 } 215 216 ;; This is deferred to DAGCombine unless %B is single-use. 217 ;; (A >> 8) << 8 === A & -256 218 define i32 @test12(i32 %A) { 219 ; CHECK-LABEL: @test12( 220 ; CHECK-NEXT: [[B1:%.*]] = and i32 %A, -256 221 ; CHECK-NEXT: ret i32 [[B1]] 222 ; 223 %B = ashr i32 %A, 8 ; <i32> [#uses=1] 224 %C = shl i32 %B, 8 ; <i32> [#uses=1] 225 ret i32 %C 226 } 227 228 ;; This transformation is deferred to DAGCombine: 229 ;; (A >> 3) << 4 === (A & -8) * 2 230 ;; The shl may be valuable to scalar evolution. 231 define i8 @test13(i8 %A) { 232 ; CHECK-LABEL: @test13( 233 ; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 234 ; CHECK-NEXT: [[B1:%.*]] = lshr i8 [[A]], 3 235 ; CHECK-NEXT: [[C:%.*]] = shl i8 [[B1]], 4 236 ; CHECK-NEXT: ret i8 [[C]] 237 ; 238 %a = mul i8 %A, 3 ; <i8> [#uses=1] 239 %B = ashr i8 %a, 3 ; <i8> [#uses=1] 240 %C = shl i8 %B, 4 ; <i8> [#uses=1] 241 ret i8 %C 242 } 243 244 define i8 @test13a(i8 %A) { 245 ; CHECK-LABEL: @test13a( 246 ; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 247 ; CHECK-NEXT: ret i8 [[C]] 248 ; 249 %a = mul i8 %A, 3 250 %B = ashr exact i8 %a, 3 251 %C = shl i8 %B, 4 252 ret i8 %C 253 } 254 255 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 256 define i32 @test14(i32 %A) { 257 ; CHECK-LABEL: @test14( 258 ; CHECK-NEXT: [[B:%.*]] = and i32 %A, -19760 259 ; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744 260 ; CHECK-NEXT: ret i32 [[C]] 261 ; 262 %B = lshr i32 %A, 4 ; <i32> [#uses=1] 263 %C = or i32 %B, 1234 ; <i32> [#uses=1] 264 %D = shl i32 %C, 4 ; <i32> [#uses=1] 265 ret i32 %D 266 } 267 268 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 269 define i32 @test14a(i32 %A) { 270 ; CHECK-LABEL: @test14a( 271 ; CHECK-NEXT: [[C:%.*]] = and i32 %A, 77 272 ; CHECK-NEXT: ret i32 [[C]] 273 ; 274 %B = shl i32 %A, 4 ; <i32> [#uses=1] 275 %C = and i32 %B, 1234 ; <i32> [#uses=1] 276 %D = lshr i32 %C, 4 ; <i32> [#uses=1] 277 ret i32 %D 278 } 279 280 define i32 @test15(i1 %C) { 281 ; CHECK-LABEL: @test15( 282 ; CHECK-NEXT: [[A:%.*]] = select i1 %C, i32 12, i32 4 283 ; CHECK-NEXT: ret i32 [[A]] 284 ; 285 %A = select i1 %C, i32 3, i32 1 ; <i32> [#uses=1] 286 %V = shl i32 %A, 2 ; <i32> [#uses=1] 287 ret i32 %V 288 } 289 290 define i32 @test15a(i1 %C) { 291 ; CHECK-LABEL: @test15a( 292 ; CHECK-NEXT: [[V:%.*]] = select i1 %C, i32 512, i32 128 293 ; CHECK-NEXT: ret i32 [[V]] 294 ; 295 %A = select i1 %C, i8 3, i8 1 ; <i8> [#uses=1] 296 %shift.upgrd.4 = zext i8 %A to i32 ; <i32> [#uses=1] 297 %V = shl i32 64, %shift.upgrd.4 ; <i32> [#uses=1] 298 ret i32 %V 299 } 300 301 define i1 @test16(i32 %X) { 302 ; CHECK-LABEL: @test16( 303 ; CHECK-NEXT: [[TMP_6:%.*]] = and i32 %X, 16 304 ; CHECK-NEXT: [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0 305 ; CHECK-NEXT: ret i1 [[TMP_7]] 306 ; 307 %tmp.3 = ashr i32 %X, 4 308 %tmp.6 = and i32 %tmp.3, 1 309 %tmp.7 = icmp ne i32 %tmp.6, 0 310 ret i1 %tmp.7 311 } 312 313 define i1 @test17(i32 %A) { 314 ; CHECK-LABEL: @test17( 315 ; CHECK-NEXT: [[B_MASK:%.*]] = and i32 %A, -8 316 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872 317 ; CHECK-NEXT: ret i1 [[C]] 318 ; 319 %B = lshr i32 %A, 3 ; <i32> [#uses=1] 320 %C = icmp eq i32 %B, 1234 ; <i1> [#uses=1] 321 ret i1 %C 322 } 323 324 325 define i1 @test18(i8 %A) { 326 ; CHECK-LABEL: @test18( 327 ; CHECK-NEXT: ret i1 false 328 ; 329 %B = lshr i8 %A, 7 ; <i8> [#uses=1] 330 ;; false 331 %C = icmp eq i8 %B, 123 ; <i1> [#uses=1] 332 ret i1 %C 333 } 334 335 define i1 @test19(i32 %A) { 336 ; CHECK-LABEL: @test19( 337 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 %A, 4 338 ; CHECK-NEXT: ret i1 [[C]] 339 ; 340 %B = ashr i32 %A, 2 ; <i32> [#uses=1] 341 ;; (X & -4) == 0 342 %C = icmp eq i32 %B, 0 ; <i1> [#uses=1] 343 ret i1 %C 344 } 345 346 347 define i1 @test19a(i32 %A) { 348 ; CHECK-LABEL: @test19a( 349 ; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %A, -5 350 ; CHECK-NEXT: ret i1 [[C]] 351 ; 352 %B = ashr i32 %A, 2 ; <i32> [#uses=1] 353 ;; X >u ~4 354 %C = icmp eq i32 %B, -1 ; <i1> [#uses=1] 355 ret i1 %C 356 } 357 358 define i1 @test20(i8 %A) { 359 ; CHECK-LABEL: @test20( 360 ; CHECK-NEXT: ret i1 false 361 ; 362 %B = ashr i8 %A, 7 ; <i8> [#uses=1] 363 ;; false 364 %C = icmp eq i8 %B, 123 ; <i1> [#uses=1] 365 ret i1 %C 366 } 367 368 define i1 @test21(i8 %A) { 369 ; CHECK-LABEL: @test21( 370 ; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 371 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8 372 ; CHECK-NEXT: ret i1 [[C]] 373 ; 374 %B = shl i8 %A, 4 ; <i8> [#uses=1] 375 %C = icmp eq i8 %B, -128 ; <i1> [#uses=1] 376 ret i1 %C 377 } 378 379 define i1 @test22(i8 %A) { 380 ; CHECK-LABEL: @test22( 381 ; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 382 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0 383 ; CHECK-NEXT: ret i1 [[C]] 384 ; 385 %B = shl i8 %A, 4 ; <i8> [#uses=1] 386 %C = icmp eq i8 %B, 0 ; <i1> [#uses=1] 387 ret i1 %C 388 } 389 390 define i8 @test23(i32 %A) { 391 ; CHECK-LABEL: @test23( 392 ; CHECK-NEXT: [[D:%.*]] = trunc i32 %A to i8 393 ; CHECK-NEXT: ret i8 [[D]] 394 ; 395 ;; casts not needed 396 %B = shl i32 %A, 24 ; <i32> [#uses=1] 397 %C = ashr i32 %B, 24 ; <i32> [#uses=1] 398 %D = trunc i32 %C to i8 ; <i8> [#uses=1] 399 ret i8 %D 400 } 401 402 define i8 @test24(i8 %X) { 403 ; CHECK-LABEL: @test24( 404 ; CHECK-NEXT: [[Z:%.*]] = and i8 %X, 3 405 ; CHECK-NEXT: ret i8 [[Z]] 406 ; 407 %Y = and i8 %X, -5 ; <i8> [#uses=1] 408 %Z = shl i8 %Y, 5 ; <i8> [#uses=1] 409 %Q = ashr i8 %Z, 5 ; <i8> [#uses=1] 410 ret i8 %Q 411 } 412 413 define i32 @test25(i32 %tmp.2, i32 %AA) { 414 ; CHECK-LABEL: @test25( 415 ; CHECK-NEXT: [[TMP_3:%.*]] = and i32 %tmp.2, -131072 416 ; CHECK-NEXT: [[X2:%.*]] = add i32 [[TMP_3]], %AA 417 ; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X2]], -131072 418 ; CHECK-NEXT: ret i32 [[TMP_6]] 419 ; 420 %x = lshr i32 %AA, 17 ; <i32> [#uses=1] 421 %tmp.3 = lshr i32 %tmp.2, 17 ; <i32> [#uses=1] 422 %tmp.5 = add i32 %tmp.3, %x ; <i32> [#uses=1] 423 %tmp.6 = shl i32 %tmp.5, 17 ; <i32> [#uses=1] 424 ret i32 %tmp.6 425 } 426 427 define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) { 428 ; CHECK-LABEL: @test25_vector( 429 ; CHECK-NEXT: [[TMP_3:%.*]] = lshr <2 x i32> %tmp.2, <i32 17, i32 17> 430 ; CHECK-NEXT: [[TMP_51:%.*]] = shl <2 x i32> [[TMP_3]], <i32 17, i32 17> 431 ; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_51]], %AA 432 ; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072> 433 ; CHECK-NEXT: ret <2 x i32> [[TMP_6]] 434 ; 435 %x = lshr <2 x i32> %AA, <i32 17, i32 17> 436 %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> 437 %tmp.5 = add <2 x i32> %tmp.3, %x 438 %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17> 439 ret <2 x i32> %tmp.6 440 } 441 442 ;; handle casts between shifts. 443 define i32 @test26(i32 %A) { 444 ; CHECK-LABEL: @test26( 445 ; CHECK-NEXT: [[B:%.*]] = and i32 %A, -2 446 ; CHECK-NEXT: ret i32 [[B]] 447 ; 448 %B = lshr i32 %A, 1 ; <i32> [#uses=1] 449 %C = bitcast i32 %B to i32 ; <i32> [#uses=1] 450 %D = shl i32 %C, 1 ; <i32> [#uses=1] 451 ret i32 %D 452 } 453 454 455 define i1 @test27(i32 %x) nounwind { 456 ; CHECK-LABEL: @test27( 457 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 8 458 ; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 459 ; CHECK-NEXT: ret i1 [[Z]] 460 ; 461 %y = lshr i32 %x, 3 462 %z = trunc i32 %y to i1 463 ret i1 %z 464 } 465 466 define i8 @test28(i8 %x) { 467 ; CHECK-LABEL: @test28( 468 ; CHECK-NEXT: entry: 469 ; CHECK-NEXT: [[COND1:%.*]] = icmp slt i8 %x, 0 470 ; CHECK-NEXT: br i1 [[COND1]], label %bb1, label %bb2 471 ; CHECK: bb1: 472 ; CHECK-NEXT: ret i8 0 473 ; CHECK: bb2: 474 ; CHECK-NEXT: ret i8 1 475 ; 476 entry: 477 %tmp1 = lshr i8 %x, 7 478 %cond1 = icmp ne i8 %tmp1, 0 479 br i1 %cond1, label %bb1, label %bb2 480 481 bb1: 482 ret i8 0 483 484 bb2: 485 ret i8 1 486 } 487 488 define i8 @test28a(i8 %x, i8 %y) { 489 ; CHECK-LABEL: @test28a( 490 ; CHECK-NEXT: entry: 491 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 %x, 7 492 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0 493 ; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1 494 ; CHECK: bb1: 495 ; CHECK-NEXT: ret i8 [[TMP1]] 496 ; CHECK: bb2: 497 ; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], %y 498 ; CHECK-NEXT: ret i8 [[TMP2]] 499 ; 500 entry: 501 ; This shouldn't be transformed. 502 %tmp1 = lshr i8 %x, 7 503 %cond1 = icmp ne i8 %tmp1, 0 504 br i1 %cond1, label %bb1, label %bb2 505 bb1: 506 ret i8 %tmp1 507 bb2: 508 %tmp2 = add i8 %tmp1, %y 509 ret i8 %tmp2 510 } 511 512 513 define i32 @test29(i64 %d18) { 514 ; CHECK-LABEL: @test29( 515 ; CHECK-NEXT: entry: 516 ; CHECK-NEXT: [[TMP916:%.*]] = lshr i64 %d18, 63 517 ; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32 518 ; CHECK-NEXT: ret i32 [[TMP10]] 519 ; 520 entry: 521 %tmp916 = lshr i64 %d18, 32 522 %tmp917 = trunc i64 %tmp916 to i32 523 %tmp10 = lshr i32 %tmp917, 31 524 ret i32 %tmp10 525 } 526 527 528 define i32 @test30(i32 %A, i32 %B, i32 %C) { 529 ; CHECK-LABEL: @test30( 530 ; CHECK-NEXT: [[X1:%.*]] = and i32 %A, %B 531 ; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], %C 532 ; CHECK-NEXT: ret i32 [[Z]] 533 ; 534 %X = shl i32 %A, %C 535 %Y = shl i32 %B, %C 536 %Z = and i32 %X, %Y 537 ret i32 %Z 538 } 539 540 define i32 @test31(i32 %A, i32 %B, i32 %C) { 541 ; CHECK-LABEL: @test31( 542 ; CHECK-NEXT: [[X1:%.*]] = or i32 %A, %B 543 ; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], %C 544 ; CHECK-NEXT: ret i32 [[Z]] 545 ; 546 %X = lshr i32 %A, %C 547 %Y = lshr i32 %B, %C 548 %Z = or i32 %X, %Y 549 ret i32 %Z 550 } 551 552 define i32 @test32(i32 %A, i32 %B, i32 %C) { 553 ; CHECK-LABEL: @test32( 554 ; CHECK-NEXT: [[X1:%.*]] = xor i32 %A, %B 555 ; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], %C 556 ; CHECK-NEXT: ret i32 [[Z]] 557 ; 558 %X = ashr i32 %A, %C 559 %Y = ashr i32 %B, %C 560 %Z = xor i32 %X, %Y 561 ret i32 %Z 562 } 563 564 define i1 @test33(i32 %X) { 565 ; CHECK-LABEL: @test33( 566 ; CHECK-NEXT: [[TMP1_MASK:%.*]] = and i32 %X, 16777216 567 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0 568 ; CHECK-NEXT: ret i1 [[TMP2]] 569 ; 570 %tmp1 = shl i32 %X, 7 571 %tmp2 = icmp slt i32 %tmp1, 0 572 ret i1 %tmp2 573 } 574 575 define i1 @test34(i32 %X) { 576 ; CHECK-LABEL: @test34( 577 ; CHECK-NEXT: ret i1 false 578 ; 579 %tmp1 = lshr i32 %X, 7 580 %tmp2 = icmp slt i32 %tmp1, 0 581 ret i1 %tmp2 582 } 583 584 define i1 @test35(i32 %X) { 585 ; CHECK-LABEL: @test35( 586 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 %X, 0 587 ; CHECK-NEXT: ret i1 [[TMP2]] 588 ; 589 %tmp1 = ashr i32 %X, 7 590 %tmp2 = icmp slt i32 %tmp1, 0 591 ret i1 %tmp2 592 } 593 594 define i128 @test36(i128 %A, i128 %B) { 595 ; CHECK-LABEL: @test36( 596 ; CHECK-NEXT: entry: 597 ; CHECK-NEXT: [[TMP231:%.*]] = or i128 %B, %A 598 ; CHECK-NEXT: [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615 599 ; CHECK-NEXT: ret i128 [[INS]] 600 ; 601 entry: 602 %tmp27 = shl i128 %A, 64 603 %tmp23 = shl i128 %B, 64 604 %ins = or i128 %tmp23, %tmp27 605 %tmp45 = lshr i128 %ins, 64 606 ret i128 %tmp45 607 608 } 609 610 define i64 @test37(i128 %A, i32 %B) { 611 ; CHECK-LABEL: @test37( 612 ; CHECK-NEXT: entry: 613 ; CHECK-NEXT: [[TMP22:%.*]] = zext i32 %B to i128 614 ; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32 615 ; CHECK-NEXT: [[INS:%.*]] = or i128 [[TMP23]], %A 616 ; CHECK-NEXT: [[TMP46:%.*]] = trunc i128 [[INS]] to i64 617 ; CHECK-NEXT: ret i64 [[TMP46]] 618 ; 619 entry: 620 %tmp27 = shl i128 %A, 64 621 %tmp22 = zext i32 %B to i128 622 %tmp23 = shl i128 %tmp22, 96 623 %ins = or i128 %tmp23, %tmp27 624 %tmp45 = lshr i128 %ins, 64 625 %tmp46 = trunc i128 %tmp45 to i64 626 ret i64 %tmp46 627 628 } 629 630 define i32 @test38(i32 %x) nounwind readnone { 631 ; CHECK-LABEL: @test38( 632 ; CHECK-NEXT: [[REM1:%.*]] = and i32 %x, 31 633 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] 634 ; CHECK-NEXT: ret i32 [[SHL]] 635 ; 636 %rem = srem i32 %x, 32 637 %shl = shl i32 1, %rem 638 ret i32 %shl 639 } 640 641 ; <rdar://problem/8756731> 642 define i8 @test39(i32 %a0) { 643 ; CHECK-LABEL: @test39( 644 ; CHECK-NEXT: entry: 645 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 %a0 to i8 646 ; CHECK-NEXT: [[TMP5:%.*]] = shl i8 [[TMP4]], 5 647 ; CHECK-NEXT: [[TMP49:%.*]] = shl i8 [[TMP4]], 6 648 ; CHECK-NEXT: [[TMP50:%.*]] = and i8 [[TMP49]], 64 649 ; CHECK-NEXT: [[TMP51:%.*]] = xor i8 [[TMP50]], [[TMP5]] 650 ; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[TMP4]], 2 651 ; CHECK-NEXT: [[TMP54:%.*]] = and i8 [[TMP0]], 16 652 ; CHECK-NEXT: [[TMP551:%.*]] = or i8 [[TMP54]], [[TMP51]] 653 ; CHECK-NEXT: ret i8 [[TMP551]] 654 ; 655 entry: 656 %tmp4 = trunc i32 %a0 to i8 657 %tmp5 = shl i8 %tmp4, 5 658 %tmp48 = and i8 %tmp5, 32 659 %tmp49 = lshr i8 %tmp48, 5 660 %tmp50 = mul i8 %tmp49, 64 661 %tmp51 = xor i8 %tmp50, %tmp5 662 %tmp52 = and i8 %tmp51, -128 663 %tmp53 = lshr i8 %tmp52, 7 664 %tmp54 = mul i8 %tmp53, 16 665 %tmp55 = xor i8 %tmp54, %tmp51 666 ret i8 %tmp55 667 } 668 669 ; PR9809 670 define i32 @test40(i32 %a, i32 %b) nounwind { 671 ; CHECK-LABEL: @test40( 672 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 2 673 ; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, [[TMP1]] 674 ; CHECK-NEXT: ret i32 [[DIV]] 675 ; 676 %shl1 = shl i32 1, %b 677 %shl2 = shl i32 %shl1, 2 678 %div = udiv i32 %a, %shl2 679 ret i32 %div 680 } 681 682 define i32 @test41(i32 %a, i32 %b) nounwind { 683 ; CHECK-LABEL: @test41( 684 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, %b 685 ; CHECK-NEXT: ret i32 [[TMP1]] 686 ; 687 %1 = shl i32 1, %b 688 %2 = shl i32 %1, 3 689 ret i32 %2 690 } 691 692 define i32 @test42(i32 %a, i32 %b) nounwind { 693 ; CHECK-LABEL: @test42( 694 ; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, %b 695 ; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]] 696 ; CHECK-NEXT: ret i32 [[DIV2]] 697 ; 698 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero 699 %div2 = udiv i32 %a, %div 700 ret i32 %div2 701 } 702 703 define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) { 704 ; CHECK-LABEL: @test42vec( 705 ; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b 706 ; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]] 707 ; CHECK-NEXT: ret <2 x i32> [[DIV2]] 708 ; 709 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero 710 %div2 = udiv <2 x i32> %a, %div 711 ret <2 x i32> %div2 712 } 713 714 define i32 @test43(i32 %a, i32 %b) nounwind { 715 ; CHECK-LABEL: @test43( 716 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 12 717 ; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]] 718 ; CHECK-NEXT: ret i32 [[DIV2]] 719 ; 720 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero 721 %div2 = udiv i32 %a, %div 722 ret i32 %div2 723 } 724 725 define i32 @test44(i32 %a) nounwind { 726 ; CHECK-LABEL: @test44( 727 ; CHECK-NEXT: [[Y:%.*]] = shl i32 %a, 5 728 ; CHECK-NEXT: ret i32 [[Y]] 729 ; 730 %y = shl nuw i32 %a, 1 731 %z = shl i32 %y, 4 732 ret i32 %z 733 } 734 735 define i32 @test45(i32 %a) nounwind { 736 ; CHECK-LABEL: @test45( 737 ; CHECK-NEXT: [[Y:%.*]] = lshr i32 %a, 5 738 ; CHECK-NEXT: ret i32 [[Y]] 739 ; 740 %y = lshr exact i32 %a, 1 741 %z = lshr i32 %y, 4 742 ret i32 %z 743 } 744 745 define i32 @test46(i32 %a) { 746 ; CHECK-LABEL: @test46( 747 ; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 %a, 2 748 ; CHECK-NEXT: ret i32 [[Z]] 749 ; 750 %y = ashr exact i32 %a, 3 751 %z = shl i32 %y, 1 752 ret i32 %z 753 } 754 755 define i32 @test47(i32 %a) { 756 ; CHECK-LABEL: @test47( 757 ; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %a, 2 758 ; CHECK-NEXT: ret i32 [[Z]] 759 ; 760 %y = lshr exact i32 %a, 3 761 %z = shl i32 %y, 1 762 ret i32 %z 763 } 764 765 define i32 @test48(i32 %x) { 766 ; CHECK-LABEL: @test48( 767 ; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 768 ; CHECK-NEXT: ret i32 [[B]] 769 ; 770 %A = lshr exact i32 %x, 1 771 %B = shl i32 %A, 3 772 ret i32 %B 773 } 774 775 define i32 @test49(i32 %x) { 776 ; CHECK-LABEL: @test49( 777 ; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 778 ; CHECK-NEXT: ret i32 [[B]] 779 ; 780 %A = ashr exact i32 %x, 1 781 %B = shl i32 %A, 3 782 ret i32 %B 783 } 784 785 define i32 @test50(i32 %x) { 786 ; CHECK-LABEL: @test50( 787 ; CHECK-NEXT: [[B:%.*]] = ashr i32 %x, 2 788 ; CHECK-NEXT: ret i32 [[B]] 789 ; 790 %A = shl nsw i32 %x, 1 791 %B = ashr i32 %A, 3 792 ret i32 %B 793 } 794 795 define i32 @test51(i32 %x) { 796 ; CHECK-LABEL: @test51( 797 ; CHECK-NEXT: [[B:%.*]] = lshr i32 %x, 2 798 ; CHECK-NEXT: ret i32 [[B]] 799 ; 800 %A = shl nuw i32 %x, 1 801 %B = lshr i32 %A, 3 802 ret i32 %B 803 } 804 805 define i32 @test52(i32 %x) { 806 ; CHECK-LABEL: @test52( 807 ; CHECK-NEXT: [[B:%.*]] = shl nsw i32 %x, 2 808 ; CHECK-NEXT: ret i32 [[B]] 809 ; 810 %A = shl nsw i32 %x, 3 811 %B = ashr i32 %A, 1 812 ret i32 %B 813 } 814 815 define i32 @test53(i32 %x) { 816 ; CHECK-LABEL: @test53( 817 ; CHECK-NEXT: [[B:%.*]] = shl nuw i32 %x, 2 818 ; CHECK-NEXT: ret i32 [[B]] 819 ; 820 %A = shl nuw i32 %x, 3 821 %B = lshr i32 %A, 1 822 ret i32 %B 823 } 824 825 define i32 @test54(i32 %x) { 826 ; CHECK-LABEL: @test54( 827 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 828 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16 829 ; CHECK-NEXT: ret i32 [[AND]] 830 ; 831 %shr2 = lshr i32 %x, 1 832 %shl = shl i32 %shr2, 4 833 %and = and i32 %shl, 16 834 ret i32 %and 835 } 836 837 838 define i32 @test55(i32 %x) { 839 ; CHECK-LABEL: @test55( 840 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 841 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8 842 ; CHECK-NEXT: ret i32 [[OR]] 843 ; 844 %shr2 = lshr i32 %x, 1 845 %shl = shl i32 %shr2, 4 846 %or = or i32 %shl, 8 847 ret i32 %or 848 } 849 850 define i32 @test56(i32 %x) { 851 ; CHECK-LABEL: @test56( 852 ; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 %x, 1 853 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR2]], 4 854 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 855 ; CHECK-NEXT: ret i32 [[OR]] 856 ; 857 %shr2 = lshr i32 %x, 1 858 %shl = shl i32 %shr2, 4 859 %or = or i32 %shl, 7 860 ret i32 %or 861 } 862 863 864 define i32 @test57(i32 %x) { 865 ; CHECK-LABEL: @test57( 866 ; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 %x, 1 867 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR1]], 4 868 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 869 ; CHECK-NEXT: ret i32 [[OR]] 870 ; 871 %shr = ashr i32 %x, 1 872 %shl = shl i32 %shr, 4 873 %or = or i32 %shl, 7 874 ret i32 %or 875 } 876 877 878 define i32 @test58(i32 %x) { 879 ; CHECK-LABEL: @test58( 880 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 %x, 3 881 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1 882 ; CHECK-NEXT: ret i32 [[OR]] 883 ; 884 %shr = ashr i32 %x, 4 885 %shl = shl i32 %shr, 1 886 %or = or i32 %shl, 1 887 ret i32 %or 888 } 889 890 891 define i32 @test59(i32 %x) { 892 ; CHECK-LABEL: @test59( 893 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 %x, 4 894 ; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SHR]], 1 895 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2 896 ; CHECK-NEXT: ret i32 [[OR]] 897 ; 898 %shr = ashr i32 %x, 4 899 %shl = shl i32 %shr, 1 900 %or = or i32 %shl, 2 901 ret i32 %or 902 } 903 904 ; propagate "exact" trait 905 define i32 @test60(i32 %x) { 906 ; CHECK-LABEL: @test60( 907 ; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 %x, 3 908 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1 909 ; CHECK-NEXT: ret i32 [[OR]] 910 ; 911 %shr = ashr exact i32 %x, 4 912 %shl = shl i32 %shr, 1 913 %or = or i32 %shl, 1 914 ret i32 %or 915 } 916 917 ; PR17026 918 define void @test61(i128 %arg) { 919 ; CHECK-LABEL: @test61( 920 ; CHECK-NEXT: bb: 921 ; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 922 ; CHECK: bb1: 923 ; CHECK-NEXT: br label %bb2 924 ; CHECK: bb2: 925 ; CHECK-NEXT: br i1 undef, label %bb3, label %bb7 926 ; CHECK: bb3: 927 ; CHECK-NEXT: br label %bb8 928 ; CHECK: bb7: 929 ; CHECK-NEXT: br i1 undef, label %bb8, label %bb2 930 ; CHECK: bb8: 931 ; CHECK-NEXT: br i1 undef, label %bb11, label %bb12 932 ; CHECK: bb11: 933 ; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 934 ; CHECK: bb12: 935 ; CHECK-NEXT: ret void 936 ; 937 bb: 938 br i1 undef, label %bb1, label %bb12 939 940 bb1: ; preds = %bb11, %bb 941 br label %bb2 942 943 bb2: ; preds = %bb7, %bb1 944 br i1 undef, label %bb3, label %bb7 945 946 bb3: ; preds = %bb2 947 %tmp = lshr i128 %arg, 36893488147419103232 948 %tmp4 = shl i128 %tmp, 0 949 %tmp5 = or i128 %tmp4, undef 950 %tmp6 = trunc i128 %tmp5 to i16 951 br label %bb8 952 953 bb7: ; preds = %bb2 954 br i1 undef, label %bb8, label %bb2 955 956 bb8: ; preds = %bb7, %bb3 957 %tmp9 = phi i16 [ %tmp6, %bb3 ], [ undef, %bb7 ] 958 %tmp10 = icmp eq i16 %tmp9, 0 959 br i1 %tmp10, label %bb11, label %bb12 960 961 bb11: ; preds = %bb8 962 br i1 undef, label %bb1, label %bb12 963 964 bb12: ; preds = %bb11, %bb8, %bb 965 ret void 966 } 967 968 define i32 @test62(i32 %a) { 969 ; CHECK-LABEL: @test62( 970 ; CHECK-NEXT: ret i32 undef 971 ; 972 %b = ashr i32 %a, 32 ; shift all bits out 973 ret i32 %b 974 } 975 976 define <4 x i32> @test62_splat_vector(<4 x i32> %a) { 977 ; CHECK-LABEL: @test62_splat_vector( 978 ; CHECK-NEXT: ret <4 x i32> undef 979 ; 980 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out 981 ret <4 x i32> %b 982 } 983 984 define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) { 985 ; CHECK-LABEL: @test62_non_splat_vector( 986 ; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> 987 ; CHECK-NEXT: ret <4 x i32> [[B]] 988 ; 989 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out 990 ret <4 x i32> %b 991 } 992 993 define <2 x i65> @test_63(<2 x i64> %t) { 994 ; CHECK-LABEL: @test_63( 995 ; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65> 996 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33> 997 ; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], <i65 33, i65 33> 998 ; CHECK-NEXT: ret <2 x i65> [[B]] 999 ; 1000 %a = zext <2 x i64> %t to <2 x i65> 1001 %sext = shl <2 x i65> %a, <i65 33, i65 33> 1002 %b = ashr <2 x i65> %sext, <i65 33, i65 33> 1003 ret <2 x i65> %b 1004 } 1005
