1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2 ; RUN: opt < %s -instsimplify -S | FileCheck %s 3 4 ; If any bits of the shift amount are known to make it exceed or equal 5 ; the number of bits in the type, the shift causes undefined behavior. 6 7 define i32 @shl_amount_is_known_bogus(i32 %a, i32 %b) { 8 ; CHECK-LABEL: @shl_amount_is_known_bogus( 9 ; CHECK-NEXT: ret i32 undef 10 ; 11 %or = or i32 %b, 32 12 %shl = shl i32 %a, %or 13 ret i32 %shl 14 } 15 16 ; Check some weird types and the other shift ops. 17 18 define i31 @lshr_amount_is_known_bogus(i31 %a, i31 %b) { 19 ; CHECK-LABEL: @lshr_amount_is_known_bogus( 20 ; CHECK-NEXT: ret i31 undef 21 ; 22 %or = or i31 %b, 31 23 %shr = lshr i31 %a, %or 24 ret i31 %shr 25 } 26 27 define i33 @ashr_amount_is_known_bogus(i33 %a, i33 %b) { 28 ; CHECK-LABEL: @ashr_amount_is_known_bogus( 29 ; CHECK-NEXT: ret i33 undef 30 ; 31 %or = or i33 %b, 33 32 %shr = ashr i33 %a, %or 33 ret i33 %shr 34 } 35 36 37 ; If all valid bits of the shift amount are known 0, there's no shift. 38 ; It doesn't matter if high bits are set because that would be undefined. 39 ; Therefore, the only possible valid result of these shifts is %a. 40 41 define i16 @ashr_amount_is_zero(i16 %a, i16 %b) { 42 ; CHECK-LABEL: @ashr_amount_is_zero( 43 ; CHECK-NEXT: ret i16 %a 44 ; 45 %and = and i16 %b, 65520 ; 0xfff0 46 %shr = ashr i16 %a, %and 47 ret i16 %shr 48 } 49 50 define i300 @lshr_amount_is_zero(i300 %a, i300 %b) { 51 ; CHECK-LABEL: @lshr_amount_is_zero( 52 ; CHECK-NEXT: ret i300 %a 53 ; 54 %and = and i300 %b, 2048 55 %shr = lshr i300 %a, %and 56 ret i300 %shr 57 } 58 59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) { 60 ; CHECK-LABEL: @shl_amount_is_zero( 61 ; CHECK-NEXT: ret i9 %a 62 ; 63 %and = and i9 %b, 496 ; 0x1f0 64 %shl = shl i9 %a, %and 65 ret i9 %shl 66 } 67 68 69 ; Verify that we've calculated the log2 boundary of valid bits correctly for a weird type. 70 71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) { 72 ; CHECK-LABEL: @shl_amount_is_not_known_zero( 73 ; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8 74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]] 75 ; CHECK-NEXT: ret i9 [[SHL]] 76 ; 77 %and = and i9 %b, 504 ; 0x1f8 78 %shl = shl i9 %a, %and 79 ret i9 %shl 80 } 81 82 83 ; For vectors, we need all scalar elements to meet the requirements to optimize. 84 85 define <2 x i32> @ashr_vector_bogus(<2 x i32> %a, <2 x i32> %b) { 86 ; CHECK-LABEL: @ashr_vector_bogus( 87 ; CHECK-NEXT: ret <2 x i32> undef 88 ; 89 %or = or <2 x i32> %b, <i32 32, i32 32> 90 %shr = ashr <2 x i32> %a, %or 91 ret <2 x i32> %shr 92 } 93 94 ; FIXME: This is undef, but computeKnownBits doesn't handle the union. 95 define <2 x i32> @shl_vector_bogus(<2 x i32> %a, <2 x i32> %b) { 96 ; CHECK-LABEL: @shl_vector_bogus( 97 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> %b, <i32 32, i32 64> 98 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]] 99 ; CHECK-NEXT: ret <2 x i32> [[SHL]] 100 ; 101 %or = or <2 x i32> %b, <i32 32, i32 64> 102 %shl = shl <2 x i32> %a, %or 103 ret <2 x i32> %shl 104 } 105 106 define <2 x i32> @lshr_vector_zero(<2 x i32> %a, <2 x i32> %b) { 107 ; CHECK-LABEL: @lshr_vector_zero( 108 ; CHECK-NEXT: ret <2 x i32> %a 109 ; 110 %and = and <2 x i32> %b, <i32 64, i32 256> 111 %shr = lshr <2 x i32> %a, %and 112 ret <2 x i32> %shr 113 } 114 115 ; Make sure that weird vector types work too. 116 define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) { 117 ; CHECK-LABEL: @shl_vector_zero( 118 ; CHECK-NEXT: ret <2 x i15> %a 119 ; 120 %and = and <2 x i15> %b, <i15 1024, i15 1024> 121 %shl = shl <2 x i15> %a, %and 122 ret <2 x i15> %shl 123 } 124 125 define <2 x i32> @shl_vector_for_real(<2 x i32> %a, <2 x i32> %b) { 126 ; CHECK-LABEL: @shl_vector_for_real( 127 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %b, <i32 3, i32 3> 128 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]] 129 ; CHECK-NEXT: ret <2 x i32> [[SHL]] 130 ; 131 %and = and <2 x i32> %b, <i32 3, i32 3> ; a necessary mask op 132 %shl = shl <2 x i32> %a, %and 133 ret <2 x i32> %shl 134 } 135 136 137 ; We calculate the valid bits of the shift using log2, and log2 of 1 (the type width) is 0. 138 ; That should be ok. Either the shift amount is 0 or invalid (1), so we can always return %a. 139 140 define i1 @shl_i1(i1 %a, i1 %b) { 141 ; CHECK-LABEL: @shl_i1( 142 ; CHECK-NEXT: ret i1 %a 143 ; 144 %shl = shl i1 %a, %b 145 ret i1 %shl 146 } 147 148
