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      1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
      2 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
      3 
      4 define i32 @test1(i32 %x) nounwind {
      5 ; CHECK-LABEL: @test1(
      6 ; CHECK-NEXT:  a:
      7 ; CHECK-NEXT:    [[I:%.*]] = shl i32 %x, 1
      8 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
      9 ; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0
     10 ; CHECK-NEXT:    ret i32 [[DOT]]
     11 ;
     12   %i = shl i32 %x, 1
     13   switch i32 %i, label %a [
     14   i32 21, label %b
     15   i32 24, label %c
     16   ]
     17 
     18 a:
     19   ret i32 0
     20 b:
     21   ret i32 3
     22 c:
     23   ret i32 5
     24 }
     25 
     26 
     27 define i32 @test2(i32 %x) nounwind {
     28 ; CHECK-LABEL: @test2(
     29 ; CHECK-NEXT:  a:
     30 ; CHECK-NEXT:    ret i32 0
     31 ;
     32   %i = shl i32 %x, 1
     33   switch i32 %i, label %a [
     34   i32 21, label %b
     35   i32 23, label %c
     36   ]
     37 
     38 a:
     39   ret i32 0
     40 b:
     41   ret i32 3
     42 c:
     43   ret i32 5
     44 }
     45 
     46 ; We're sign extending an 8-bit value.
     47 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
     48 
     49 define i1 @repeated_signbits(i8 %condition) {
     50 ; CHECK-LABEL: @repeated_signbits(
     51 ; CHECK:         switch i32
     52 ; CHECK-DAG:     i32 -128, label %a
     53 ; CHECK-DAG:     i32 -1, label %a
     54 ; CHECK-DAG:     i32  0, label %a
     55 ; CHECK-DAG:     i32  127, label %a
     56 ; CHECK-NEXT:    ]
     57 ;
     58 entry:
     59   %sext = sext i8 %condition to i32
     60   switch i32 %sext, label %default [
     61   i32 -2147483648, label %a
     62   i32 -129, label %a
     63   i32 -128, label %a
     64   i32 -1, label %a
     65   i32  0, label %a
     66   i32  127, label %a
     67   i32  128, label %a
     68   i32  2147483647, label %a
     69   ]
     70 
     71 a:
     72   ret i1 1
     73 
     74 default:
     75   ret i1 0
     76 }
     77 
     78