1 /* 2 * Copyright 2016 Red Hat. 3 * Copyright 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright 2015 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 25 * IN THE SOFTWARE. 26 */ 27 28 #include "util/mesa-sha1.h" 29 #include "util/u_atomic.h" 30 #include "radv_debug.h" 31 #include "radv_private.h" 32 #include "radv_shader.h" 33 #include "nir/nir.h" 34 #include "nir/nir_builder.h" 35 #include "spirv/nir_spirv.h" 36 37 #include <llvm-c/Core.h> 38 #include <llvm-c/TargetMachine.h> 39 40 #include "sid.h" 41 #include "gfx9d.h" 42 #include "ac_binary.h" 43 #include "ac_llvm_util.h" 44 #include "ac_nir_to_llvm.h" 45 #include "vk_format.h" 46 #include "util/debug.h" 47 #include "ac_exp_param.h" 48 49 #include "util/string_buffer.h" 50 51 static const struct nir_shader_compiler_options nir_options = { 52 .vertex_id_zero_based = true, 53 .lower_scmp = true, 54 .lower_flrp32 = true, 55 .lower_flrp64 = true, 56 .lower_fsat = true, 57 .lower_fdiv = true, 58 .lower_sub = true, 59 .lower_pack_snorm_2x16 = true, 60 .lower_pack_snorm_4x8 = true, 61 .lower_pack_unorm_2x16 = true, 62 .lower_pack_unorm_4x8 = true, 63 .lower_unpack_snorm_2x16 = true, 64 .lower_unpack_snorm_4x8 = true, 65 .lower_unpack_unorm_2x16 = true, 66 .lower_unpack_unorm_4x8 = true, 67 .lower_extract_byte = true, 68 .lower_extract_word = true, 69 .lower_ffma = true, 70 .max_unroll_iterations = 32 71 }; 72 73 VkResult radv_CreateShaderModule( 74 VkDevice _device, 75 const VkShaderModuleCreateInfo* pCreateInfo, 76 const VkAllocationCallbacks* pAllocator, 77 VkShaderModule* pShaderModule) 78 { 79 RADV_FROM_HANDLE(radv_device, device, _device); 80 struct radv_shader_module *module; 81 82 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO); 83 assert(pCreateInfo->flags == 0); 84 85 module = vk_alloc2(&device->alloc, pAllocator, 86 sizeof(*module) + pCreateInfo->codeSize, 8, 87 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 88 if (module == NULL) 89 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); 90 91 module->nir = NULL; 92 module->size = pCreateInfo->codeSize; 93 memcpy(module->data, pCreateInfo->pCode, module->size); 94 95 _mesa_sha1_compute(module->data, module->size, module->sha1); 96 97 *pShaderModule = radv_shader_module_to_handle(module); 98 99 return VK_SUCCESS; 100 } 101 102 void radv_DestroyShaderModule( 103 VkDevice _device, 104 VkShaderModule _module, 105 const VkAllocationCallbacks* pAllocator) 106 { 107 RADV_FROM_HANDLE(radv_device, device, _device); 108 RADV_FROM_HANDLE(radv_shader_module, module, _module); 109 110 if (!module) 111 return; 112 113 vk_free2(&device->alloc, pAllocator, module); 114 } 115 116 bool 117 radv_lower_indirect_derefs(struct nir_shader *nir, 118 struct radv_physical_device *device) 119 { 120 /* While it would be nice not to have this flag, we are constrained 121 * by the reality that LLVM 5.0 doesn't have working VGPR indexing 122 * on GFX9. 123 */ 124 bool llvm_has_working_vgpr_indexing = 125 device->rad_info.chip_class <= VI; 126 127 /* TODO: Indirect indexing of GS inputs is unimplemented. 128 * 129 * TCS and TES load inputs directly from LDS or offchip memory, so 130 * indirect indexing is trivial. 131 */ 132 nir_variable_mode indirect_mask = 0; 133 if (nir->info.stage == MESA_SHADER_GEOMETRY || 134 (nir->info.stage != MESA_SHADER_TESS_CTRL && 135 nir->info.stage != MESA_SHADER_TESS_EVAL && 136 !llvm_has_working_vgpr_indexing)) { 137 indirect_mask |= nir_var_shader_in; 138 } 139 if (!llvm_has_working_vgpr_indexing && 140 nir->info.stage != MESA_SHADER_TESS_CTRL) 141 indirect_mask |= nir_var_shader_out; 142 143 /* TODO: We shouldn't need to do this, however LLVM isn't currently 144 * smart enough to handle indirects without causing excess spilling 145 * causing the gpu to hang. 146 * 147 * See the following thread for more details of the problem: 148 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html 149 */ 150 indirect_mask |= nir_var_local; 151 152 return nir_lower_indirect_derefs(nir, indirect_mask); 153 } 154 155 void 156 radv_optimize_nir(struct nir_shader *shader) 157 { 158 bool progress; 159 160 do { 161 progress = false; 162 163 NIR_PASS_V(shader, nir_lower_vars_to_ssa); 164 NIR_PASS_V(shader, nir_lower_64bit_pack); 165 NIR_PASS_V(shader, nir_lower_alu_to_scalar); 166 NIR_PASS_V(shader, nir_lower_phis_to_scalar); 167 168 NIR_PASS(progress, shader, nir_copy_prop); 169 NIR_PASS(progress, shader, nir_opt_remove_phis); 170 NIR_PASS(progress, shader, nir_opt_dce); 171 if (nir_opt_trivial_continues(shader)) { 172 progress = true; 173 NIR_PASS(progress, shader, nir_copy_prop); 174 NIR_PASS(progress, shader, nir_opt_remove_phis); 175 NIR_PASS(progress, shader, nir_opt_dce); 176 } 177 NIR_PASS(progress, shader, nir_opt_if); 178 NIR_PASS(progress, shader, nir_opt_dead_cf); 179 NIR_PASS(progress, shader, nir_opt_cse); 180 NIR_PASS(progress, shader, nir_opt_peephole_select, 8); 181 NIR_PASS(progress, shader, nir_opt_algebraic); 182 NIR_PASS(progress, shader, nir_opt_constant_folding); 183 NIR_PASS(progress, shader, nir_opt_undef); 184 NIR_PASS(progress, shader, nir_opt_conditional_discard); 185 if (shader->options->max_unroll_iterations) { 186 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0); 187 } 188 } while (progress); 189 } 190 191 nir_shader * 192 radv_shader_compile_to_nir(struct radv_device *device, 193 struct radv_shader_module *module, 194 const char *entrypoint_name, 195 gl_shader_stage stage, 196 const VkSpecializationInfo *spec_info) 197 { 198 if (strcmp(entrypoint_name, "main") != 0) { 199 radv_finishme("Multiple shaders per module not really supported"); 200 } 201 202 nir_shader *nir; 203 nir_function *entry_point; 204 if (module->nir) { 205 /* Some things such as our meta clear/blit code will give us a NIR 206 * shader directly. In that case, we just ignore the SPIR-V entirely 207 * and just use the NIR shader */ 208 nir = module->nir; 209 nir->options = &nir_options; 210 nir_validate_shader(nir); 211 212 assert(exec_list_length(&nir->functions) == 1); 213 struct exec_node *node = exec_list_get_head(&nir->functions); 214 entry_point = exec_node_data(nir_function, node, node); 215 } else { 216 uint32_t *spirv = (uint32_t *) module->data; 217 assert(module->size % 4 == 0); 218 219 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV) 220 radv_print_spirv(spirv, module->size, stderr); 221 222 uint32_t num_spec_entries = 0; 223 struct nir_spirv_specialization *spec_entries = NULL; 224 if (spec_info && spec_info->mapEntryCount > 0) { 225 num_spec_entries = spec_info->mapEntryCount; 226 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries)); 227 for (uint32_t i = 0; i < num_spec_entries; i++) { 228 VkSpecializationMapEntry entry = spec_info->pMapEntries[i]; 229 const void *data = spec_info->pData + entry.offset; 230 assert(data + entry.size <= spec_info->pData + spec_info->dataSize); 231 232 spec_entries[i].id = spec_info->pMapEntries[i].constantID; 233 if (spec_info->dataSize == 8) 234 spec_entries[i].data64 = *(const uint64_t *)data; 235 else 236 spec_entries[i].data32 = *(const uint32_t *)data; 237 } 238 } 239 const struct spirv_to_nir_options spirv_options = { 240 .caps = { 241 .draw_parameters = true, 242 .float64 = true, 243 .image_read_without_format = true, 244 .image_write_without_format = true, 245 .tessellation = true, 246 .int64 = true, 247 .multiview = true, 248 .variable_pointers = true, 249 }, 250 }; 251 entry_point = spirv_to_nir(spirv, module->size / 4, 252 spec_entries, num_spec_entries, 253 stage, entrypoint_name, 254 &spirv_options, &nir_options); 255 nir = entry_point->shader; 256 assert(nir->info.stage == stage); 257 nir_validate_shader(nir); 258 259 free(spec_entries); 260 261 /* We have to lower away local constant initializers right before we 262 * inline functions. That way they get properly initialized at the top 263 * of the function and not at the top of its caller. 264 */ 265 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local); 266 NIR_PASS_V(nir, nir_lower_returns); 267 NIR_PASS_V(nir, nir_inline_functions); 268 269 /* Pick off the single entrypoint that we want */ 270 foreach_list_typed_safe(nir_function, func, node, &nir->functions) { 271 if (func != entry_point) 272 exec_node_remove(&func->node); 273 } 274 assert(exec_list_length(&nir->functions) == 1); 275 entry_point->name = ralloc_strdup(entry_point, "main"); 276 277 NIR_PASS_V(nir, nir_remove_dead_variables, 278 nir_var_shader_in | nir_var_shader_out | nir_var_system_value); 279 280 /* Now that we've deleted all but the main function, we can go ahead and 281 * lower the rest of the constant initializers. 282 */ 283 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); 284 NIR_PASS_V(nir, nir_lower_system_values); 285 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); 286 } 287 288 /* Vulkan uses the separate-shader linking model */ 289 nir->info.separate_shader = true; 290 291 nir_shader_gather_info(nir, entry_point->impl); 292 293 static const nir_lower_tex_options tex_options = { 294 .lower_txp = ~0, 295 }; 296 297 nir_lower_tex(nir, &tex_options); 298 299 nir_lower_vars_to_ssa(nir); 300 nir_lower_var_copies(nir); 301 nir_lower_global_vars_to_local(nir); 302 nir_remove_dead_variables(nir, nir_var_local); 303 radv_lower_indirect_derefs(nir, device->physical_device); 304 radv_optimize_nir(nir); 305 306 return nir; 307 } 308 309 void * 310 radv_alloc_shader_memory(struct radv_device *device, 311 struct radv_shader_variant *shader) 312 { 313 mtx_lock(&device->shader_slab_mutex); 314 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) { 315 uint64_t offset = 0; 316 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) { 317 if (s->bo_offset - offset >= shader->code_size) { 318 shader->bo = slab->bo; 319 shader->bo_offset = offset; 320 list_addtail(&shader->slab_list, &s->slab_list); 321 mtx_unlock(&device->shader_slab_mutex); 322 return slab->ptr + offset; 323 } 324 offset = align_u64(s->bo_offset + s->code_size, 256); 325 } 326 if (slab->size - offset >= shader->code_size) { 327 shader->bo = slab->bo; 328 shader->bo_offset = offset; 329 list_addtail(&shader->slab_list, &slab->shaders); 330 mtx_unlock(&device->shader_slab_mutex); 331 return slab->ptr + offset; 332 } 333 } 334 335 mtx_unlock(&device->shader_slab_mutex); 336 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab)); 337 338 slab->size = 256 * 1024; 339 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, 340 RADEON_DOMAIN_VRAM, 341 RADEON_FLAG_NO_INTERPROCESS_SHARING | 342 device->physical_device->cpdma_prefetch_writes_memory ? 343 0 : RADEON_FLAG_READ_ONLY); 344 slab->ptr = (char*)device->ws->buffer_map(slab->bo); 345 list_inithead(&slab->shaders); 346 347 mtx_lock(&device->shader_slab_mutex); 348 list_add(&slab->slabs, &device->shader_slabs); 349 350 shader->bo = slab->bo; 351 shader->bo_offset = 0; 352 list_add(&shader->slab_list, &slab->shaders); 353 mtx_unlock(&device->shader_slab_mutex); 354 return slab->ptr; 355 } 356 357 void 358 radv_destroy_shader_slabs(struct radv_device *device) 359 { 360 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) { 361 device->ws->buffer_destroy(slab->bo); 362 free(slab); 363 } 364 mtx_destroy(&device->shader_slab_mutex); 365 } 366 367 static void 368 radv_fill_shader_variant(struct radv_device *device, 369 struct radv_shader_variant *variant, 370 struct ac_shader_binary *binary, 371 gl_shader_stage stage) 372 { 373 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; 374 unsigned vgpr_comp_cnt = 0; 375 376 if (scratch_enabled && !device->llvm_supports_spill) 377 radv_finishme("shader scratch support only available with LLVM 4.0"); 378 379 variant->code_size = binary->code_size; 380 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | 381 S_00B12C_SCRATCH_EN(scratch_enabled); 382 383 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | 384 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | 385 S_00B848_DX10_CLAMP(1) | 386 S_00B848_FLOAT_MODE(variant->config.float_mode); 387 388 switch (stage) { 389 case MESA_SHADER_TESS_EVAL: 390 vgpr_comp_cnt = 3; 391 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); 392 break; 393 case MESA_SHADER_TESS_CTRL: 394 if (device->physical_device->rad_info.chip_class >= GFX9) 395 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; 396 else 397 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); 398 break; 399 case MESA_SHADER_VERTEX: 400 case MESA_SHADER_GEOMETRY: 401 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; 402 break; 403 case MESA_SHADER_FRAGMENT: 404 break; 405 case MESA_SHADER_COMPUTE: { 406 struct ac_shader_info *info = &variant->info.info; 407 variant->rsrc2 |= 408 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | 409 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | 410 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) | 411 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 : 412 info->cs.uses_thread_id[1] ? 1 : 0) | 413 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) | 414 S_00B84C_LDS_SIZE(variant->config.lds_size); 415 break; 416 } 417 default: 418 unreachable("unsupported shader type"); 419 break; 420 } 421 422 if (device->physical_device->rad_info.chip_class >= GFX9 && 423 stage == MESA_SHADER_GEOMETRY) { 424 struct ac_shader_info *info = &variant->info.info; 425 unsigned es_type = variant->info.gs.es_type; 426 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; 427 428 if (es_type == MESA_SHADER_VERTEX) { 429 es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; 430 } else if (es_type == MESA_SHADER_TESS_EVAL) { 431 es_vgpr_comp_cnt = 3; 432 } else { 433 unreachable("invalid shader ES type"); 434 } 435 436 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and 437 * VGPR[0:4] are always loaded. 438 */ 439 if (info->uses_invocation_id) 440 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ 441 else if (info->uses_prim_id) 442 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ 443 else if (variant->info.gs.vertices_in >= 3) 444 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ 445 else 446 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ 447 448 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); 449 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | 450 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); 451 } else if (device->physical_device->rad_info.chip_class >= GFX9 && 452 stage == MESA_SHADER_TESS_CTRL) 453 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); 454 else 455 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); 456 457 void *ptr = radv_alloc_shader_memory(device, variant); 458 memcpy(ptr, binary->code, binary->code_size); 459 } 460 461 static struct radv_shader_variant * 462 shader_variant_create(struct radv_device *device, 463 struct radv_shader_module *module, 464 struct nir_shader * const *shaders, 465 int shader_count, 466 gl_shader_stage stage, 467 struct ac_nir_compiler_options *options, 468 bool gs_copy_shader, 469 void **code_out, 470 unsigned *code_size_out) 471 { 472 enum radeon_family chip_family = device->physical_device->rad_info.family; 473 bool dump_shaders = radv_can_dump_shader(device, module); 474 enum ac_target_machine_options tm_options = 0; 475 struct radv_shader_variant *variant; 476 struct ac_shader_binary binary; 477 LLVMTargetMachineRef tm; 478 479 variant = calloc(1, sizeof(struct radv_shader_variant)); 480 if (!variant) 481 return NULL; 482 483 options->family = chip_family; 484 options->chip_class = device->physical_device->rad_info.chip_class; 485 options->dump_preoptir = radv_can_dump_shader(device, module) && 486 device->instance->debug_flags & RADV_DEBUG_PREOPTIR; 487 488 if (options->supports_spill) 489 tm_options |= AC_TM_SUPPORTS_SPILL; 490 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) 491 tm_options |= AC_TM_SISCHED; 492 tm = ac_create_target_machine(chip_family, tm_options); 493 494 if (gs_copy_shader) { 495 assert(shader_count == 1); 496 ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config, 497 &variant->info, options, dump_shaders); 498 } else { 499 ac_compile_nir_shader(tm, &binary, &variant->config, 500 &variant->info, shaders, shader_count, options, 501 dump_shaders); 502 } 503 504 LLVMDisposeTargetMachine(tm); 505 506 radv_fill_shader_variant(device, variant, &binary, stage); 507 508 if (code_out) { 509 *code_out = binary.code; 510 *code_size_out = binary.code_size; 511 } else 512 free(binary.code); 513 free(binary.config); 514 free(binary.rodata); 515 free(binary.global_symbol_offsets); 516 free(binary.relocs); 517 variant->ref_count = 1; 518 519 if (device->keep_shader_info) { 520 variant->disasm_string = binary.disasm_string; 521 if (!gs_copy_shader && !module->nir) { 522 variant->nir = *shaders; 523 variant->spirv = (uint32_t *)module->data; 524 variant->spirv_size = module->size; 525 } 526 } else { 527 free(binary.disasm_string); 528 } 529 530 return variant; 531 } 532 533 struct radv_shader_variant * 534 radv_shader_variant_create(struct radv_device *device, 535 struct radv_shader_module *module, 536 struct nir_shader *const *shaders, 537 int shader_count, 538 struct radv_pipeline_layout *layout, 539 const struct ac_shader_variant_key *key, 540 void **code_out, 541 unsigned *code_size_out) 542 { 543 struct ac_nir_compiler_options options = {0}; 544 545 options.layout = layout; 546 if (key) 547 options.key = *key; 548 549 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH); 550 options.supports_spill = device->llvm_supports_spill; 551 552 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, 553 &options, false, code_out, code_size_out); 554 } 555 556 struct radv_shader_variant * 557 radv_create_gs_copy_shader(struct radv_device *device, 558 struct nir_shader *shader, 559 void **code_out, 560 unsigned *code_size_out, 561 bool multiview) 562 { 563 struct ac_nir_compiler_options options = {0}; 564 565 options.key.has_multiview_view_index = multiview; 566 567 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX, 568 &options, true, code_out, code_size_out); 569 } 570 571 void 572 radv_shader_variant_destroy(struct radv_device *device, 573 struct radv_shader_variant *variant) 574 { 575 if (!p_atomic_dec_zero(&variant->ref_count)) 576 return; 577 578 mtx_lock(&device->shader_slab_mutex); 579 list_del(&variant->slab_list); 580 mtx_unlock(&device->shader_slab_mutex); 581 582 ralloc_free(variant->nir); 583 free(variant->disasm_string); 584 free(variant); 585 } 586 587 const char * 588 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage) 589 { 590 switch (stage) { 591 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS"; 592 case MESA_SHADER_GEOMETRY: return "Geometry Shader"; 593 case MESA_SHADER_FRAGMENT: return "Pixel Shader"; 594 case MESA_SHADER_COMPUTE: return "Compute Shader"; 595 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader"; 596 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS"; 597 default: 598 return "Unknown shader"; 599 }; 600 } 601 602 static uint32_t 603 get_total_sgprs(struct radv_device *device) 604 { 605 if (device->physical_device->rad_info.chip_class >= VI) 606 return 800; 607 else 608 return 512; 609 } 610 611 static void 612 generate_shader_stats(struct radv_device *device, 613 struct radv_shader_variant *variant, 614 gl_shader_stage stage, 615 struct _mesa_string_buffer *buf) 616 { 617 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; 618 struct ac_shader_config *conf; 619 unsigned max_simd_waves; 620 unsigned lds_per_wave = 0; 621 622 switch (device->physical_device->rad_info.family) { 623 /* These always have 8 waves: */ 624 case CHIP_POLARIS10: 625 case CHIP_POLARIS11: 626 case CHIP_POLARIS12: 627 max_simd_waves = 8; 628 break; 629 default: 630 max_simd_waves = 10; 631 } 632 633 conf = &variant->config; 634 635 if (stage == MESA_SHADER_FRAGMENT) { 636 lds_per_wave = conf->lds_size * lds_increment + 637 align(variant->info.fs.num_interp * 48, 638 lds_increment); 639 } 640 641 if (conf->num_sgprs) 642 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs); 643 644 if (conf->num_vgprs) 645 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs); 646 647 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD 648 * that PS can use. 649 */ 650 if (lds_per_wave) 651 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave); 652 653 if (stage == MESA_SHADER_FRAGMENT) { 654 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n" 655 "SPI_PS_INPUT_ADDR = 0x%04x\n" 656 "SPI_PS_INPUT_ENA = 0x%04x\n", 657 conf->spi_ps_input_addr, conf->spi_ps_input_ena); 658 } 659 660 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n" 661 "SGPRS: %d\n" 662 "VGPRS: %d\n" 663 "Spilled SGPRs: %d\n" 664 "Spilled VGPRs: %d\n" 665 "Code Size: %d bytes\n" 666 "LDS: %d blocks\n" 667 "Scratch: %d bytes per wave\n" 668 "Max Waves: %d\n" 669 "********************\n\n\n", 670 conf->num_sgprs, conf->num_vgprs, 671 conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size, 672 conf->lds_size, conf->scratch_bytes_per_wave, 673 max_simd_waves); 674 } 675 676 void 677 radv_shader_dump_stats(struct radv_device *device, 678 struct radv_shader_variant *variant, 679 gl_shader_stage stage, 680 FILE *file) 681 { 682 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256); 683 684 generate_shader_stats(device, variant, stage, buf); 685 686 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage)); 687 fprintf(file, "%s", buf->buf); 688 689 _mesa_string_buffer_destroy(buf); 690 } 691 692 VkResult 693 radv_GetShaderInfoAMD(VkDevice _device, 694 VkPipeline _pipeline, 695 VkShaderStageFlagBits shaderStage, 696 VkShaderInfoTypeAMD infoType, 697 size_t* pInfoSize, 698 void* pInfo) 699 { 700 RADV_FROM_HANDLE(radv_device, device, _device); 701 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); 702 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage); 703 struct radv_shader_variant *variant = pipeline->shaders[stage]; 704 struct _mesa_string_buffer *buf; 705 VkResult result = VK_SUCCESS; 706 707 /* Spec doesn't indicate what to do if the stage is invalid, so just 708 * return no info for this. */ 709 if (!variant) 710 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT); 711 712 switch (infoType) { 713 case VK_SHADER_INFO_TYPE_STATISTICS_AMD: 714 if (!pInfo) { 715 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD); 716 } else { 717 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; 718 struct ac_shader_config *conf = &variant->config; 719 720 VkShaderStatisticsInfoAMD statistics = {}; 721 statistics.shaderStageMask = shaderStage; 722 statistics.numPhysicalVgprs = 256; 723 statistics.numPhysicalSgprs = get_total_sgprs(device); 724 statistics.numAvailableSgprs = statistics.numPhysicalSgprs; 725 726 if (stage == MESA_SHADER_COMPUTE) { 727 unsigned *local_size = variant->nir->info.cs.local_size; 728 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2]; 729 730 statistics.numAvailableVgprs = statistics.numPhysicalVgprs / 731 ceil(workgroup_size / statistics.numPhysicalVgprs); 732 733 statistics.computeWorkGroupSize[0] = local_size[0]; 734 statistics.computeWorkGroupSize[1] = local_size[1]; 735 statistics.computeWorkGroupSize[2] = local_size[2]; 736 } else { 737 statistics.numAvailableVgprs = statistics.numPhysicalVgprs; 738 } 739 740 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs; 741 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs; 742 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768; 743 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier; 744 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave; 745 746 size_t size = *pInfoSize; 747 *pInfoSize = sizeof(statistics); 748 749 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize)); 750 751 if (size < *pInfoSize) 752 result = VK_INCOMPLETE; 753 } 754 755 break; 756 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD: 757 buf = _mesa_string_buffer_create(NULL, 1024); 758 759 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage)); 760 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string); 761 generate_shader_stats(device, variant, stage, buf); 762 763 /* Need to include the null terminator. */ 764 size_t length = buf->length + 1; 765 766 if (!pInfo) { 767 *pInfoSize = length; 768 } else { 769 size_t size = *pInfoSize; 770 *pInfoSize = length; 771 772 memcpy(pInfo, buf->buf, MIN2(size, length)); 773 774 if (size < length) 775 result = VK_INCOMPLETE; 776 } 777 778 _mesa_string_buffer_destroy(buf); 779 break; 780 default: 781 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */ 782 result = VK_ERROR_FEATURE_NOT_PRESENT; 783 break; 784 } 785 786 return result; 787 } 788
