1 /* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj (at) gmail.com> 25 * Christian Gmeiner <christian.gmeiner (at) gmail.com> 26 */ 27 28 #include "etnaviv_screen.h" 29 30 #include "hw/common.xml.h" 31 32 #include "etnaviv_compiler.h" 33 #include "etnaviv_context.h" 34 #include "etnaviv_debug.h" 35 #include "etnaviv_fence.h" 36 #include "etnaviv_format.h" 37 #include "etnaviv_query.h" 38 #include "etnaviv_resource.h" 39 #include "etnaviv_translate.h" 40 41 #include "util/os_time.h" 42 #include "util/u_math.h" 43 #include "util/u_memory.h" 44 #include "util/u_string.h" 45 46 #include "state_tracker/drm_driver.h" 47 48 #include <drm_fourcc.h> 49 50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor)) 51 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) 52 53 static const struct debug_named_value debug_options[] = { 54 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, 55 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, 56 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"}, 57 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"}, 58 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"}, 59 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"}, 60 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"}, 61 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"}, 62 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"}, 63 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"}, 64 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"}, 65 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"}, 66 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"}, 67 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, 68 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, 69 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, 70 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, 71 DEBUG_NAMED_VALUE_END 72 }; 73 74 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0) 75 int etna_mesa_debug = 0; 76 77 static void 78 etna_screen_destroy(struct pipe_screen *pscreen) 79 { 80 struct etna_screen *screen = etna_screen(pscreen); 81 82 if (screen->pipe) 83 etna_pipe_del(screen->pipe); 84 85 if (screen->gpu) 86 etna_gpu_del(screen->gpu); 87 88 if (screen->ro) 89 FREE(screen->ro); 90 91 if (screen->dev) 92 etna_device_del(screen->dev); 93 94 FREE(screen); 95 } 96 97 static const char * 98 etna_screen_get_name(struct pipe_screen *pscreen) 99 { 100 struct etna_screen *priv = etna_screen(pscreen); 101 static char buffer[128]; 102 103 util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model, 104 priv->revision); 105 106 return buffer; 107 } 108 109 static const char * 110 etna_screen_get_vendor(struct pipe_screen *pscreen) 111 { 112 return "etnaviv"; 113 } 114 115 static const char * 116 etna_screen_get_device_vendor(struct pipe_screen *pscreen) 117 { 118 return "Vivante"; 119 } 120 121 static int 122 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 123 { 124 struct etna_screen *screen = etna_screen(pscreen); 125 126 switch (param) { 127 /* Supported features (boolean caps). */ 128 case PIPE_CAP_ANISOTROPIC_FILTER: 129 case PIPE_CAP_POINT_SPRITE: 130 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 131 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 132 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 133 case PIPE_CAP_SM3: 134 case PIPE_CAP_TEXTURE_BARRIER: 135 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 136 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 137 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 138 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 139 case PIPE_CAP_TGSI_TEXCOORD: 140 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 141 return 1; 142 case PIPE_CAP_NATIVE_FENCE_FD: 143 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; 144 145 /* Memory */ 146 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 147 return 256; 148 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 149 return 4; /* XXX could easily be supported */ 150 case PIPE_CAP_GLSL_FEATURE_LEVEL: 151 return 120; 152 153 case PIPE_CAP_NPOT_TEXTURES: 154 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, 155 NON_POWER_OF_TWO); */ 156 157 case PIPE_CAP_TEXTURE_SWIZZLE: 158 case PIPE_CAP_PRIMITIVE_RESTART: 159 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 160 161 case PIPE_CAP_ENDIANNESS: 162 return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature 163 ENDIANNESS_CONFIG) */ 164 165 /* Unsupported features. */ 166 case PIPE_CAP_SEAMLESS_CUBE_MAP: 167 case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */ 168 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */ 169 case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */ 170 case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */ 171 case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */ 172 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */ 173 case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */ 174 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */ 175 case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */ 176 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */ 177 case PIPE_CAP_INDEP_BLEND_ENABLE: 178 case PIPE_CAP_INDEP_BLEND_FUNC: 179 case PIPE_CAP_DEPTH_CLIP_DISABLE: 180 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 181 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 182 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 183 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */ 184 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 185 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 186 case PIPE_CAP_USER_VERTEX_BUFFERS: 187 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 188 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 189 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 190 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */ 191 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 192 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 193 case PIPE_CAP_TEXTURE_GATHER_SM5: 194 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 195 case PIPE_CAP_FAKE_SW_MSAA: 196 case PIPE_CAP_TEXTURE_QUERY_LOD: 197 case PIPE_CAP_SAMPLE_SHADING: 198 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 199 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 200 case PIPE_CAP_DRAW_INDIRECT: 201 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 202 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 203 case PIPE_CAP_SAMPLER_VIEW_TARGET: 204 case PIPE_CAP_CLIP_HALFZ: 205 case PIPE_CAP_VERTEXID_NOBASE: 206 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 207 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 208 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 209 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 210 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 211 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 212 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 213 case PIPE_CAP_DEPTH_BOUNDS_TEST: 214 case PIPE_CAP_TGSI_TXQS: 215 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 216 case PIPE_CAP_SHAREABLE_SHADERS: 217 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 218 case PIPE_CAP_CLEAR_TEXTURE: 219 case PIPE_CAP_DRAW_PARAMETERS: 220 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 221 case PIPE_CAP_MULTI_DRAW_INDIRECT: 222 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 223 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 224 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 225 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 226 case PIPE_CAP_INVALIDATE_BUFFER: 227 case PIPE_CAP_GENERATE_MIPMAP: 228 case PIPE_CAP_STRING_MARKER: 229 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 230 case PIPE_CAP_QUERY_BUFFER_OBJECT: 231 case PIPE_CAP_QUERY_MEMORY_INFO: 232 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 233 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 234 case PIPE_CAP_CULL_DISTANCE: 235 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 236 case PIPE_CAP_TGSI_VOTE: 237 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 238 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 239 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 240 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 241 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 242 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 243 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 244 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 245 case PIPE_CAP_TGSI_FS_FBFETCH: 246 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 247 case PIPE_CAP_DOUBLES: 248 case PIPE_CAP_INT64: 249 case PIPE_CAP_INT64_DIVMOD: 250 case PIPE_CAP_TGSI_TEX_TXF_LZ: 251 case PIPE_CAP_TGSI_CLOCK: 252 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 253 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 254 case PIPE_CAP_TGSI_BALLOT: 255 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 256 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 257 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 258 case PIPE_CAP_POST_DEPTH_COVERAGE: 259 case PIPE_CAP_BINDLESS_TEXTURE: 260 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 261 case PIPE_CAP_QUERY_SO_OVERFLOW: 262 case PIPE_CAP_MEMOBJ: 263 case PIPE_CAP_LOAD_CONSTBUF: 264 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 265 case PIPE_CAP_TILE_RASTER_ORDER: 266 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 267 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 268 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 269 return 0; 270 271 /* Stream output. */ 272 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 273 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 274 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 275 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 276 return 0; 277 278 /* Geometry shader output, unsupported. */ 279 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 280 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 281 case PIPE_CAP_MAX_VERTEX_STREAMS: 282 return 0; 283 284 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 285 return 128; 286 287 /* Texturing. */ 288 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 289 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 290 { 291 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); 292 assert(log2_max_tex_size > 0); 293 return log2_max_tex_size; 294 } 295 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */ 296 return 5; 297 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 298 return 0; 299 case PIPE_CAP_CUBE_MAP_ARRAY: 300 return 0; 301 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 302 case PIPE_CAP_MIN_TEXEL_OFFSET: 303 return -8; 304 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 305 case PIPE_CAP_MAX_TEXEL_OFFSET: 306 return 7; 307 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 308 return 0; 309 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 310 return 65536; 311 312 /* Render targets. */ 313 case PIPE_CAP_MAX_RENDER_TARGETS: 314 return 1; 315 316 /* Viewports and scissors. */ 317 case PIPE_CAP_MAX_VIEWPORTS: 318 return 1; 319 320 /* Timer queries. */ 321 case PIPE_CAP_QUERY_TIME_ELAPSED: 322 return 0; 323 case PIPE_CAP_OCCLUSION_QUERY: 324 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 325 case PIPE_CAP_QUERY_TIMESTAMP: 326 return 1; 327 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 328 return 0; 329 330 /* Preferences */ 331 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 332 return 0; 333 334 case PIPE_CAP_PCI_GROUP: 335 case PIPE_CAP_PCI_BUS: 336 case PIPE_CAP_PCI_DEVICE: 337 case PIPE_CAP_PCI_FUNCTION: 338 return 0; 339 case PIPE_CAP_VENDOR_ID: 340 case PIPE_CAP_DEVICE_ID: 341 return 0xFFFFFFFF; 342 case PIPE_CAP_ACCELERATED: 343 return 1; 344 case PIPE_CAP_VIDEO_MEMORY: 345 return 0; 346 case PIPE_CAP_UMA: 347 return 1; 348 } 349 350 debug_printf("unknown param %d", param); 351 return 0; 352 } 353 354 static float 355 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 356 { 357 struct etna_screen *screen = etna_screen(pscreen); 358 359 switch (param) { 360 case PIPE_CAPF_MAX_LINE_WIDTH: 361 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 362 case PIPE_CAPF_MAX_POINT_WIDTH: 363 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 364 return 8192.0f; 365 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 366 return 16.0f; 367 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 368 return util_last_bit(screen->specs.max_texture_size); 369 case PIPE_CAPF_GUARD_BAND_LEFT: 370 case PIPE_CAPF_GUARD_BAND_TOP: 371 case PIPE_CAPF_GUARD_BAND_RIGHT: 372 case PIPE_CAPF_GUARD_BAND_BOTTOM: 373 return 0.0f; 374 } 375 376 debug_printf("unknown paramf %d", param); 377 return 0; 378 } 379 380 static int 381 etna_screen_get_shader_param(struct pipe_screen *pscreen, 382 enum pipe_shader_type shader, 383 enum pipe_shader_cap param) 384 { 385 struct etna_screen *screen = etna_screen(pscreen); 386 387 switch (shader) { 388 case PIPE_SHADER_FRAGMENT: 389 case PIPE_SHADER_VERTEX: 390 break; 391 case PIPE_SHADER_COMPUTE: 392 case PIPE_SHADER_GEOMETRY: 393 case PIPE_SHADER_TESS_CTRL: 394 case PIPE_SHADER_TESS_EVAL: 395 return 0; 396 default: 397 DBG("unknown shader type %d", shader); 398 return 0; 399 } 400 401 switch (param) { 402 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 403 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 404 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 405 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 406 return ETNA_MAX_TOKENS; 407 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 408 return ETNA_MAX_DEPTH; /* XXX */ 409 case PIPE_SHADER_CAP_MAX_INPUTS: 410 /* Maximum number of inputs for the vertex shader is the number 411 * of vertex elements - each element defines one vertex shader 412 * input register. For the fragment shader, this is the number 413 * of varyings. */ 414 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings 415 : screen->specs.vertex_max_elements; 416 case PIPE_SHADER_CAP_MAX_OUTPUTS: 417 return 16; /* see VIVS_VS_OUTPUT */ 418 case PIPE_SHADER_CAP_MAX_TEMPS: 419 return 64; /* Max native temporaries. */ 420 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 421 return 1; 422 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 423 return 1; 424 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 425 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 426 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 427 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 428 return 1; 429 case PIPE_SHADER_CAP_SUBROUTINES: 430 return 0; 431 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 432 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 433 case PIPE_SHADER_CAP_INTEGERS: 434 case PIPE_SHADER_CAP_INT64_ATOMICS: 435 case PIPE_SHADER_CAP_FP16: 436 return 0; 437 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 438 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 439 return shader == PIPE_SHADER_FRAGMENT 440 ? screen->specs.fragment_sampler_count 441 : screen->specs.vertex_sampler_count; 442 case PIPE_SHADER_CAP_PREFERRED_IR: 443 return PIPE_SHADER_IR_TGSI; 444 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 445 return 4096; 446 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 447 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 448 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 449 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 450 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 451 return false; 452 case PIPE_SHADER_CAP_SUPPORTED_IRS: 453 return 0; 454 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 455 return 32; 456 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 457 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 458 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 459 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 460 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 461 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 462 return 0; 463 } 464 465 debug_printf("unknown shader param %d", param); 466 return 0; 467 } 468 469 static uint64_t 470 etna_screen_get_timestamp(struct pipe_screen *pscreen) 471 { 472 return os_time_get_nano(); 473 } 474 475 static bool 476 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt, 477 enum pipe_format format) 478 { 479 bool supported = true; 480 481 if (fmt == TEXTURE_FORMAT_ETC1) 482 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); 483 484 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) 485 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); 486 487 if (util_format_is_srgb(format)) 488 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 489 490 if (fmt & EXT_FORMAT) { 491 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 492 493 /* ETC1 is checked above, as it has its own feature bit. ETC2 is 494 * supported with HALTI0, however that implementation is buggy in hardware. 495 * The blob driver does per-block patching to work around this. As this 496 * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000) 497 * only. 498 */ 499 if (util_format_is_etc(format)) 500 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); 501 } 502 503 if (fmt & ASTC_FORMAT) { 504 supported = screen->specs.tex_astc; 505 } 506 507 if (!supported) 508 return false; 509 510 if (texture_format_needs_swiz(format)) 511 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 512 513 return true; 514 } 515 516 static boolean 517 etna_screen_is_format_supported(struct pipe_screen *pscreen, 518 enum pipe_format format, 519 enum pipe_texture_target target, 520 unsigned sample_count, unsigned usage) 521 { 522 struct etna_screen *screen = etna_screen(pscreen); 523 unsigned allowed = 0; 524 525 if (target != PIPE_BUFFER && 526 target != PIPE_TEXTURE_1D && 527 target != PIPE_TEXTURE_2D && 528 target != PIPE_TEXTURE_3D && 529 target != PIPE_TEXTURE_CUBE && 530 target != PIPE_TEXTURE_RECT) 531 return FALSE; 532 533 if (usage & PIPE_BIND_RENDER_TARGET) { 534 /* if render target, must be RS-supported format */ 535 if (translate_rs_format(format) != ETNA_NO_MATCH) { 536 /* Validate MSAA; number of samples must be allowed, and render target 537 * must have MSAA'able format. */ 538 if (sample_count > 1) { 539 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && 540 translate_msaa_format(format) != ETNA_NO_MATCH) { 541 allowed |= PIPE_BIND_RENDER_TARGET; 542 } 543 } else { 544 allowed |= PIPE_BIND_RENDER_TARGET; 545 } 546 } 547 } 548 549 if (usage & PIPE_BIND_DEPTH_STENCIL) { 550 if (translate_depth_format(format) != ETNA_NO_MATCH) 551 allowed |= PIPE_BIND_DEPTH_STENCIL; 552 } 553 554 if (usage & PIPE_BIND_SAMPLER_VIEW) { 555 uint32_t fmt = translate_texture_format(format); 556 557 if (!gpu_supports_texure_format(screen, fmt, format)) 558 fmt = ETNA_NO_MATCH; 559 560 if (sample_count < 2 && fmt != ETNA_NO_MATCH) 561 allowed |= PIPE_BIND_SAMPLER_VIEW; 562 } 563 564 if (usage & PIPE_BIND_VERTEX_BUFFER) { 565 if (translate_vertex_format_type(format) != ETNA_NO_MATCH) 566 allowed |= PIPE_BIND_VERTEX_BUFFER; 567 } 568 569 if (usage & PIPE_BIND_INDEX_BUFFER) { 570 /* must be supported index format */ 571 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT || 572 (format == PIPE_FORMAT_I32_UINT && 573 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { 574 allowed |= PIPE_BIND_INDEX_BUFFER; 575 } 576 } 577 578 /* Always allowed */ 579 allowed |= 580 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); 581 582 if (usage != allowed) { 583 DBG("not supported: format=%s, target=%d, sample_count=%d, " 584 "usage=%x, allowed=%x", 585 util_format_name(format), target, sample_count, usage, allowed); 586 } 587 588 return usage == allowed; 589 } 590 591 const uint64_t supported_modifiers[] = { 592 DRM_FORMAT_MOD_LINEAR, 593 DRM_FORMAT_MOD_VIVANTE_TILED, 594 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED, 595 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED, 596 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED, 597 }; 598 599 static void 600 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 601 enum pipe_format format, int max, 602 uint64_t *modifiers, 603 unsigned int *external_only, int *count) 604 { 605 struct etna_screen *screen = etna_screen(pscreen); 606 int i, num_modifiers = 0; 607 608 if (max > ARRAY_SIZE(supported_modifiers)) 609 max = ARRAY_SIZE(supported_modifiers); 610 611 if (!max) { 612 modifiers = NULL; 613 max = ARRAY_SIZE(supported_modifiers); 614 } 615 616 for (i = 0; num_modifiers < max; i++) { 617 /* don't advertise split tiled formats on single pipe/buffer GPUs */ 618 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) && 619 i >= 3) 620 break; 621 622 if (modifiers) 623 modifiers[num_modifiers] = supported_modifiers[i]; 624 if (external_only) 625 external_only[num_modifiers] = 0; 626 num_modifiers++; 627 } 628 629 *count = num_modifiers; 630 } 631 632 static boolean 633 etna_get_specs(struct etna_screen *screen) 634 { 635 uint64_t val; 636 uint32_t instruction_count; 637 638 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { 639 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); 640 goto fail; 641 } 642 instruction_count = val; 643 644 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, 645 &val)) { 646 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); 647 goto fail; 648 } 649 screen->specs.vertex_output_buffer_size = val; 650 651 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { 652 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); 653 goto fail; 654 } 655 screen->specs.vertex_cache_size = val; 656 657 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { 658 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); 659 goto fail; 660 } 661 screen->specs.shader_core_count = val; 662 663 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { 664 DBG("could not get ETNA_GPU_STREAM_COUNT"); 665 goto fail; 666 } 667 screen->specs.stream_count = val; 668 669 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { 670 DBG("could not get ETNA_GPU_REGISTER_MAX"); 671 goto fail; 672 } 673 screen->specs.max_registers = val; 674 675 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { 676 DBG("could not get ETNA_GPU_PIXEL_PIPES"); 677 goto fail; 678 } 679 screen->specs.pixel_pipes = val; 680 681 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { 682 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); 683 goto fail; 684 } 685 if (val == 0) { 686 fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); 687 val = 168; 688 } 689 screen->specs.num_constants = val; 690 691 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific 692 * description of the differences. */ 693 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) 694 screen->specs.halti = 5; /* New GC7000/GC8x00 */ 695 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) 696 screen->specs.halti = 4; /* Old GC7000/GC7400 */ 697 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) 698 screen->specs.halti = 3; /* None? */ 699 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) 700 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ 701 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) 702 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ 703 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) 704 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ 705 else 706 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ 707 if (screen->specs.halti >= 0) 708 DBG("etnaviv: GPU arch: HALTI%d\n", screen->specs.halti); 709 else 710 DBG("etnaviv: GPU arch: pre-HALTI\n"); 711 712 screen->specs.can_supertile = 713 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); 714 screen->specs.bits_per_tile = 715 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; 716 screen->specs.ts_clear_value = 717 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 718 : 0x11111111; 719 720 /* vertex and fragment samplers live in one address space */ 721 screen->specs.vertex_sampler_offset = 8; 722 screen->specs.fragment_sampler_count = 8; 723 screen->specs.vertex_sampler_count = 4; 724 screen->specs.vs_need_z_div = 725 screen->model < 0x1000 && screen->model != 0x880; 726 screen->specs.has_sin_cos_sqrt = 727 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 728 screen->specs.has_sign_floor_ceil = 729 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); 730 screen->specs.has_shader_range_registers = 731 screen->model >= 0x1000 || screen->model == 0x880; 732 screen->specs.npot_tex_any_wrap = 733 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); 734 screen->specs.has_new_transcendentals = 735 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); 736 screen->specs.has_halti2_instructions = 737 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 738 739 if (screen->specs.halti >= 5) { 740 /* GC7000 - this core must load shaders from memory. */ 741 screen->specs.vs_offset = 0; 742 screen->specs.ps_offset = 0; 743 screen->specs.max_instructions = 0; /* Do not program shaders manually */ 744 screen->specs.has_icache = true; 745 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { 746 /* GC3000 - this core is capable of loading shaders from 747 * memory. It can also run shaders from registers, as a fallback, but 748 * "max_instructions" does not have the correct value. It has place for 749 * 2*256 instructions just like GC2000, but the offsets are slightly 750 * different. 751 */ 752 screen->specs.vs_offset = 0xC000; 753 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses 754 * this mirror for writing PS instructions, probably safest to do the 755 * same. 756 */ 757 screen->specs.ps_offset = 0x8000 + 0x1000; 758 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ 759 screen->specs.has_icache = true; 760 } else { 761 if (instruction_count > 256) { /* unified instruction memory? */ 762 screen->specs.vs_offset = 0xC000; 763 screen->specs.ps_offset = 0xD000; /* like vivante driver */ 764 screen->specs.max_instructions = 256; 765 } else { 766 screen->specs.vs_offset = 0x4000; 767 screen->specs.ps_offset = 0x6000; 768 screen->specs.max_instructions = instruction_count / 2; 769 } 770 screen->specs.has_icache = false; 771 } 772 773 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { 774 screen->specs.max_varyings = 12; 775 screen->specs.vertex_max_elements = 16; 776 } else { 777 screen->specs.max_varyings = 8; 778 /* Etna_viv documentation seems confused over the correct value 779 * here so choose the lower to be safe: HALTI0 says 16 i.s.o. 780 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ 781 screen->specs.vertex_max_elements = 10; 782 } 783 784 /* Etna_viv documentation does not indicate where varyings above 8 are 785 * stored. Moreover, if we are passed more than 8 varyings, we will 786 * walk off the end of some arrays. Limit the maximum number of varyings. */ 787 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) 788 screen->specs.max_varyings = ETNA_NUM_VARYINGS; 789 790 /* from QueryShaderCaps in kernel driver */ 791 if (screen->model < chipModel_GC4000) { 792 screen->specs.max_vs_uniforms = 168; 793 screen->specs.max_ps_uniforms = 64; 794 } else { 795 screen->specs.max_vs_uniforms = 256; 796 screen->specs.max_ps_uniforms = 256; 797 } 798 799 if (screen->specs.halti >= 5) { 800 screen->specs.has_unified_uniforms = true; 801 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); 802 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); 803 } else if (screen->specs.halti >= 1) { 804 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess 805 */ 806 screen->specs.has_unified_uniforms = true; 807 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); 808 /* hardcode PS uniforms to start after end of VS uniforms - 809 * for more flexibility this offset could be variable based on the 810 * shader. 811 */ 812 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); 813 } else { 814 screen->specs.has_unified_uniforms = false; 815 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); 816 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); 817 } 818 819 screen->specs.max_texture_size = 820 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; 821 screen->specs.max_rendertarget_size = 822 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; 823 824 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); 825 if (screen->specs.single_buffer) 826 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes); 827 828 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); 829 830 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); 831 832 return true; 833 834 fail: 835 return false; 836 } 837 838 struct etna_bo * 839 etna_screen_bo_from_handle(struct pipe_screen *pscreen, 840 struct winsys_handle *whandle, unsigned *out_stride) 841 { 842 struct etna_screen *screen = etna_screen(pscreen); 843 struct etna_bo *bo; 844 845 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 846 bo = etna_bo_from_name(screen->dev, whandle->handle); 847 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { 848 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle); 849 } else { 850 DBG("Attempt to import unsupported handle type %d", whandle->type); 851 return NULL; 852 } 853 854 if (!bo) { 855 DBG("ref name 0x%08x failed", whandle->handle); 856 return NULL; 857 } 858 859 *out_stride = whandle->stride; 860 861 return bo; 862 } 863 864 struct pipe_screen * 865 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, 866 struct renderonly *ro) 867 { 868 struct etna_screen *screen = CALLOC_STRUCT(etna_screen); 869 struct pipe_screen *pscreen; 870 drmVersionPtr version; 871 uint64_t val; 872 873 if (!screen) 874 return NULL; 875 876 pscreen = &screen->base; 877 screen->dev = dev; 878 screen->gpu = gpu; 879 screen->ro = renderonly_dup(ro); 880 screen->refcnt = 1; 881 882 if (!screen->ro) { 883 DBG("could not create renderonly object"); 884 goto fail; 885 } 886 887 version = drmGetVersion(screen->ro->gpu_fd); 888 screen->drm_version = ETNA_DRM_VERSION(version->version_major, 889 version->version_minor); 890 drmFreeVersion(version); 891 892 etna_mesa_debug = debug_get_option_etna_mesa_debug(); 893 894 /* Disable autodisable for correct rendering with TS */ 895 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; 896 897 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); 898 if (!screen->pipe) { 899 DBG("could not create 3d pipe"); 900 goto fail; 901 } 902 903 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { 904 DBG("could not get ETNA_GPU_MODEL"); 905 goto fail; 906 } 907 screen->model = val; 908 909 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { 910 DBG("could not get ETNA_GPU_REVISION"); 911 goto fail; 912 } 913 screen->revision = val; 914 915 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { 916 DBG("could not get ETNA_GPU_FEATURES_0"); 917 goto fail; 918 } 919 screen->features[0] = val; 920 921 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { 922 DBG("could not get ETNA_GPU_FEATURES_1"); 923 goto fail; 924 } 925 screen->features[1] = val; 926 927 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { 928 DBG("could not get ETNA_GPU_FEATURES_2"); 929 goto fail; 930 } 931 screen->features[2] = val; 932 933 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { 934 DBG("could not get ETNA_GPU_FEATURES_3"); 935 goto fail; 936 } 937 screen->features[3] = val; 938 939 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { 940 DBG("could not get ETNA_GPU_FEATURES_4"); 941 goto fail; 942 } 943 screen->features[4] = val; 944 945 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { 946 DBG("could not get ETNA_GPU_FEATURES_5"); 947 goto fail; 948 } 949 screen->features[5] = val; 950 951 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { 952 DBG("could not get ETNA_GPU_FEATURES_6"); 953 goto fail; 954 } 955 screen->features[6] = val; 956 957 if (!etna_get_specs(screen)) 958 goto fail; 959 960 /* apply debug options that disable individual features */ 961 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) 962 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; 963 if (DBG_ENABLED(ETNA_DBG_NO_TS)) 964 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 965 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) 966 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; 967 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) 968 screen->specs.can_supertile = 0; 969 970 pscreen->destroy = etna_screen_destroy; 971 pscreen->get_param = etna_screen_get_param; 972 pscreen->get_paramf = etna_screen_get_paramf; 973 pscreen->get_shader_param = etna_screen_get_shader_param; 974 975 pscreen->get_name = etna_screen_get_name; 976 pscreen->get_vendor = etna_screen_get_vendor; 977 pscreen->get_device_vendor = etna_screen_get_device_vendor; 978 979 pscreen->get_timestamp = etna_screen_get_timestamp; 980 pscreen->context_create = etna_context_create; 981 pscreen->is_format_supported = etna_screen_is_format_supported; 982 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; 983 984 etna_fence_screen_init(pscreen); 985 etna_query_screen_init(pscreen); 986 etna_resource_screen_init(pscreen); 987 988 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); 989 990 return pscreen; 991 992 fail: 993 etna_screen_destroy(pscreen); 994 return NULL; 995 } 996
