1 { 0, "PC(L)" }, 2 { 4, "PC(U)" }, 3 { 8, "SR(L)" }, 4 { 12, "SR(U)" }, 5 { 16, "syscall no.(L)" }, 6 { 20, "syscall_no.(U)" }, 7 { 24, "R0(L)" }, 8 { 28, "R0(U)" }, 9 { 32, "R1(L)" }, 10 { 36, "R1(U)" }, 11 { 40, "R2(L)" }, 12 { 44, "R2(U)" }, 13 { 48, "R3(L)" }, 14 { 52, "R3(U)" }, 15 { 56, "R4(L)" }, 16 { 60, "R4(U)" }, 17 { 64, "R5(L)" }, 18 { 68, "R5(U)" }, 19 { 72, "R6(L)" }, 20 { 76, "R6(U)" }, 21 { 80, "R7(L)" }, 22 { 84, "R7(U)" }, 23 { 88, "R8(L)" }, 24 { 92, "R8(U)" }, 25 { 96, "R9(L)" }, 26 { 100, "R9(U)" }, 27 { 104, "R10(L)" }, 28 { 108, "R10(U)" }, 29 { 112, "R11(L)" }, 30 { 116, "R11(U)" }, 31 { 120, "R12(L)" }, 32 { 124, "R12(U)" }, 33 { 128, "R13(L)" }, 34 { 132, "R13(U)" }, 35 { 136, "R14(L)" }, 36 { 140, "R14(U)" }, 37 { 144, "R15(L)" }, 38 { 148, "R15(U)" }, 39 { 152, "R16(L)" }, 40 { 156, "R16(U)" }, 41 { 160, "R17(L)" }, 42 { 164, "R17(U)" }, 43 { 168, "R18(L)" }, 44 { 172, "R18(U)" }, 45 { 176, "R19(L)" }, 46 { 180, "R19(U)" }, 47 { 184, "R20(L)" }, 48 { 188, "R20(U)" }, 49 { 192, "R21(L)" }, 50 { 196, "R21(U)" }, 51 { 200, "R22(L)" }, 52 { 204, "R22(U)" }, 53 { 208, "R23(L)" }, 54 { 212, "R23(U)" }, 55 { 216, "R24(L)" }, 56 { 220, "R24(U)" }, 57 { 224, "R25(L)" }, 58 { 228, "R25(U)" }, 59 { 232, "R26(L)" }, 60 { 236, "R26(U)" }, 61 { 240, "R27(L)" }, 62 { 244, "R27(U)" }, 63 { 248, "R28(L)" }, 64 { 252, "R28(U)" }, 65 { 256, "R29(L)" }, 66 { 260, "R29(U)" }, 67 { 264, "R30(L)" }, 68 { 268, "R30(U)" }, 69 { 272, "R31(L)" }, 70 { 276, "R31(U)" }, 71 { 280, "R32(L)" }, 72 { 284, "R32(U)" }, 73 { 288, "R33(L)" }, 74 { 292, "R33(U)" }, 75 { 296, "R34(L)" }, 76 { 300, "R34(U)" }, 77 { 304, "R35(L)" }, 78 { 308, "R35(U)" }, 79 { 312, "R36(L)" }, 80 { 316, "R36(U)" }, 81 { 320, "R37(L)" }, 82 { 324, "R37(U)" }, 83 { 328, "R38(L)" }, 84 { 332, "R38(U)" }, 85 { 336, "R39(L)" }, 86 { 340, "R39(U)" }, 87 { 344, "R40(L)" }, 88 { 348, "R40(U)" }, 89 { 352, "R41(L)" }, 90 { 356, "R41(U)" }, 91 { 360, "R42(L)" }, 92 { 364, "R42(U)" }, 93 { 368, "R43(L)" }, 94 { 372, "R43(U)" }, 95 { 376, "R44(L)" }, 96 { 380, "R44(U)" }, 97 { 384, "R45(L)" }, 98 { 388, "R45(U)" }, 99 { 392, "R46(L)" }, 100 { 396, "R46(U)" }, 101 { 400, "R47(L)" }, 102 { 404, "R47(U)" }, 103 { 408, "R48(L)" }, 104 { 412, "R48(U)" }, 105 { 416, "R49(L)" }, 106 { 420, "R49(U)" }, 107 { 424, "R50(L)" }, 108 { 428, "R50(U)" }, 109 { 432, "R51(L)" }, 110 { 436, "R51(U)" }, 111 { 440, "R52(L)" }, 112 { 444, "R52(U)" }, 113 { 448, "R53(L)" }, 114 { 452, "R53(U)" }, 115 { 456, "R54(L)" }, 116 { 460, "R54(U)" }, 117 { 464, "R55(L)" }, 118 { 468, "R55(U)" }, 119 { 472, "R56(L)" }, 120 { 476, "R56(U)" }, 121 { 480, "R57(L)" }, 122 { 484, "R57(U)" }, 123 { 488, "R58(L)" }, 124 { 492, "R58(U)" }, 125 { 496, "R59(L)" }, 126 { 500, "R59(U)" }, 127 { 504, "R60(L)" }, 128 { 508, "R60(U)" }, 129 { 512, "R61(L)" }, 130 { 516, "R61(U)" }, 131 { 520, "R62(L)" }, 132 { 524, "R62(U)" }, 133 { 528, "TR0(L)" }, 134 { 532, "TR0(U)" }, 135 { 536, "TR1(L)" }, 136 { 540, "TR1(U)" }, 137 { 544, "TR2(L)" }, 138 { 548, "TR2(U)" }, 139 { 552, "TR3(L)" }, 140 { 556, "TR3(U)" }, 141 { 560, "TR4(L)" }, 142 { 564, "TR4(U)" }, 143 { 568, "TR5(L)" }, 144 { 572, "TR5(U)" }, 145 { 576, "TR6(L)" }, 146 { 580, "TR6(U)" }, 147 { 584, "TR7(L)" }, 148 { 588, "TR7(U)" }, 149 /* Other fields in "struct user" */ 150 /* This entry is in case pt_regs contains dregs (depends on 151 the kernel build options). */ 152 XLAT_UOFF(regs), 153 XLAT_UOFF(fpu), 154 #include "../sh/userent0.h" 155
