1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target-independent interfaces which should be 11 // implemented by each target which is using a TableGen based code generator. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // Include all information about LLVM intrinsics. 16 include "llvm/Intrinsics.td" 17 18 //===----------------------------------------------------------------------===// 19 // Register file description - These classes are used to fill in the target 20 // description classes. 21 22 class RegisterClass; // Forward def 23 24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25 class SubRegIndex { 26 string Namespace = ""; 27 } 28 29 // RegAltNameIndex - The alternate name set to use for register operands of 30 // this register class when printing. 31 class RegAltNameIndex { 32 string Namespace = ""; 33 } 34 def NoRegAltName : RegAltNameIndex; 35 36 // Register - You should define one instance of this class for each register 37 // in the target machine. String n will become the "name" of the register. 38 class Register<string n, list<string> altNames = []> { 39 string Namespace = ""; 40 string AsmName = n; 41 list<string> AltNames = altNames; 42 43 // Aliases - A list of registers that this register overlaps with. A read or 44 // modification of this register can potentially read or modify the aliased 45 // registers. 46 list<Register> Aliases = []; 47 48 // SubRegs - A list of registers that are parts of this register. Note these 49 // are "immediate" sub-registers and the registers within the list do not 50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 51 // not [AX, AH, AL]. 52 list<Register> SubRegs = []; 53 54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 55 // to address it. Sub-sub-register indices are automatically inherited from 56 // SubRegs. 57 list<SubRegIndex> SubRegIndices = []; 58 59 // RegAltNameIndices - The alternate name indices which are valid for this 60 // register. 61 list<RegAltNameIndex> RegAltNameIndices = []; 62 63 // CompositeIndices - Specify subreg indices that don't correspond directly to 64 // a register in SubRegs and are not inherited. The following formats are 65 // supported: 66 // 67 // (a) Identity - Reg:a == Reg 68 // (a b) Alias - Reg:a == Reg:b 69 // (a b,c) Composite - Reg:a == (Reg:b):c 70 // 71 // This can be used to disambiguate a sub-sub-register that exists in more 72 // than one subregister and other weird stuff. 73 list<dag> CompositeIndices = []; 74 75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 76 // These values can be determined by locating the <target>.h file in the 77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 78 // order of these names correspond to the enumeration used by gcc. A value of 79 // -1 indicates that the gcc number is undefined and -2 that register number 80 // is invalid for this mode/flavour. 81 list<int> DwarfNumbers = []; 82 83 // CostPerUse - Additional cost of instructions using this register compared 84 // to other registers in its class. The register allocator will try to 85 // minimize the number of instructions using a register with a CostPerUse. 86 // This is used by the x86-64 and ARM Thumb targets where some registers 87 // require larger instruction encodings. 88 int CostPerUse = 0; 89 } 90 91 // RegisterWithSubRegs - This can be used to define instances of Register which 92 // need to specify sub-registers. 93 // List "subregs" specifies which registers are sub-registers to this one. This 94 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 95 // This allows the code generator to be careful not to put two values with 96 // overlapping live ranges into registers which alias. 97 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 98 let SubRegs = subregs; 99 } 100 101 // RegisterClass - Now that all of the registers are defined, and aliases 102 // between registers are defined, specify which registers belong to which 103 // register classes. This also defines the default allocation order of 104 // registers by register allocators. 105 // 106 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 107 dag regList, RegAltNameIndex idx = NoRegAltName> { 108 string Namespace = namespace; 109 110 // RegType - Specify the list ValueType of the registers in this register 111 // class. Note that all registers in a register class must have the same 112 // ValueTypes. This is a list because some targets permit storing different 113 // types in same register, for example vector values with 128-bit total size, 114 // but different count/size of items, like SSE on x86. 115 // 116 list<ValueType> RegTypes = regTypes; 117 118 // Size - Specify the spill size in bits of the registers. A default value of 119 // zero lets tablgen pick an appropriate size. 120 int Size = 0; 121 122 // Alignment - Specify the alignment required of the registers when they are 123 // stored or loaded to memory. 124 // 125 int Alignment = alignment; 126 127 // CopyCost - This value is used to specify the cost of copying a value 128 // between two registers in this register class. The default value is one 129 // meaning it takes a single instruction to perform the copying. A negative 130 // value means copying is extremely expensive or impossible. 131 int CopyCost = 1; 132 133 // MemberList - Specify which registers are in this class. If the 134 // allocation_order_* method are not specified, this also defines the order of 135 // allocation used by the register allocator. 136 // 137 dag MemberList = regList; 138 139 // AltNameIndex - The alternate register name to use when printing operands 140 // of this register class. Every register in the register class must have 141 // a valid alternate name for the given index. 142 RegAltNameIndex altNameIndex = idx; 143 144 // SubRegClasses - Specify the register class of subregisters as a list of 145 // dags: (RegClass SubRegIndex, SubRegindex, ...) 146 list<dag> SubRegClasses = []; 147 148 // isAllocatable - Specify that the register class can be used for virtual 149 // registers and register allocation. Some register classes are only used to 150 // model instruction operand constraints, and should have isAllocatable = 0. 151 bit isAllocatable = 1; 152 153 // AltOrders - List of alternative allocation orders. The default order is 154 // MemberList itself, and that is good enough for most targets since the 155 // register allocators automatically remove reserved registers and move 156 // callee-saved registers to the end. 157 list<dag> AltOrders = []; 158 159 // AltOrderSelect - The body of a function that selects the allocation order 160 // to use in a given machine function. The code will be inserted in a 161 // function like this: 162 // 163 // static inline unsigned f(const MachineFunction &MF) { ... } 164 // 165 // The function should return 0 to select the default order defined by 166 // MemberList, 1 to select the first AltOrders entry and so on. 167 code AltOrderSelect = [{}]; 168 } 169 170 // The memberList in a RegisterClass is a dag of set operations. TableGen 171 // evaluates these set operations and expand them into register lists. These 172 // are the most common operation, see test/TableGen/SetTheory.td for more 173 // examples of what is possible: 174 // 175 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 176 // register class, or a sub-expression. This is also the way to simply list 177 // registers. 178 // 179 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 180 // 181 // (and GPR, CSR) - Set intersection. All registers from the first set that are 182 // also in the second set. 183 // 184 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 185 // numbered registers. 186 // 187 // (shl GPR, 4) - Remove the first N elements. 188 // 189 // (trunc GPR, 4) - Truncate after the first N elements. 190 // 191 // (rotl GPR, 1) - Rotate N places to the left. 192 // 193 // (rotr GPR, 1) - Rotate N places to the right. 194 // 195 // (decimate GPR, 2) - Pick every N'th element, starting with the first. 196 // 197 // All of these operators work on ordered sets, not lists. That means 198 // duplicates are removed from sub-expressions. 199 200 // Set operators. The rest is defined in TargetSelectionDAG.td. 201 def sequence; 202 def decimate; 203 204 // RegisterTuples - Automatically generate super-registers by forming tuples of 205 // sub-registers. This is useful for modeling register sequence constraints 206 // with pseudo-registers that are larger than the architectural registers. 207 // 208 // The sub-register lists are zipped together: 209 // 210 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 211 // 212 // Generates the same registers as: 213 // 214 // let SubRegIndices = [sube, subo] in { 215 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 216 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 217 // } 218 // 219 // The generated pseudo-registers inherit super-classes and fields from their 220 // first sub-register. Most fields from the Register class are inferred, and 221 // the AsmName and Dwarf numbers are cleared. 222 // 223 // RegisterTuples instances can be used in other set operations to form 224 // register classes and so on. This is the only way of using the generated 225 // registers. 226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 227 // SubRegs - N lists of registers to be zipped up. Super-registers are 228 // synthesized from the first element of each SubRegs list, the second 229 // element and so on. 230 list<dag> SubRegs = Regs; 231 232 // SubRegIndices - N SubRegIndex instances. This provides the names of the 233 // sub-registers in the synthesized super-registers. 234 list<SubRegIndex> SubRegIndices = Indices; 235 236 // Compose sub-register indices like in a normal Register. 237 list<dag> CompositeIndices = []; 238 } 239 240 241 //===----------------------------------------------------------------------===// 242 // DwarfRegNum - This class provides a mapping of the llvm register enumeration 243 // to the register numbering used by gcc and gdb. These values are used by a 244 // debug information writer to describe where values may be located during 245 // execution. 246 class DwarfRegNum<list<int> Numbers> { 247 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 248 // These values can be determined by locating the <target>.h file in the 249 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 250 // order of these names correspond to the enumeration used by gcc. A value of 251 // -1 indicates that the gcc number is undefined and -2 that register number 252 // is invalid for this mode/flavour. 253 list<int> DwarfNumbers = Numbers; 254 } 255 256 // DwarfRegAlias - This class declares that a given register uses the same dwarf 257 // numbers as another one. This is useful for making it clear that the two 258 // registers do have the same number. It also lets us build a mapping 259 // from dwarf register number to llvm register. 260 class DwarfRegAlias<Register reg> { 261 Register DwarfAlias = reg; 262 } 263 264 //===----------------------------------------------------------------------===// 265 // Pull in the common support for scheduling 266 // 267 include "llvm/Target/TargetSchedule.td" 268 269 class Predicate; // Forward def 270 271 //===----------------------------------------------------------------------===// 272 // Instruction set description - These classes correspond to the C++ classes in 273 // the Target/TargetInstrInfo.h file. 274 // 275 class Instruction { 276 string Namespace = ""; 277 278 dag OutOperandList; // An dag containing the MI def operand list. 279 dag InOperandList; // An dag containing the MI use operand list. 280 string AsmString = ""; // The .s format to print the instruction with. 281 282 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 283 // otherwise, uninitialized. 284 list<dag> Pattern; 285 286 // The follow state will eventually be inferred automatically from the 287 // instruction pattern. 288 289 list<Register> Uses = []; // Default to using no non-operand registers 290 list<Register> Defs = []; // Default to modifying no non-operand registers 291 292 // Predicates - List of predicates which will be turned into isel matching 293 // code. 294 list<Predicate> Predicates = []; 295 296 // Size - Size of encoded instruction, or zero if the size cannot be determined 297 // from the opcode. 298 int Size = 0; 299 300 // DecoderNamespace - The "namespace" in which this instruction exists, on 301 // targets like ARM which multiple ISA namespaces exist. 302 string DecoderNamespace = ""; 303 304 // Code size, for instruction selection. 305 // FIXME: What does this actually mean? 306 int CodeSize = 0; 307 308 // Added complexity passed onto matching pattern. 309 int AddedComplexity = 0; 310 311 // These bits capture information about the high-level semantics of the 312 // instruction. 313 bit isReturn = 0; // Is this instruction a return instruction? 314 bit isBranch = 0; // Is this instruction a branch instruction? 315 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 316 bit isCompare = 0; // Is this instruction a comparison instruction? 317 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 318 bit isBitcast = 0; // Is this instruction a bitcast instruction? 319 bit isBarrier = 0; // Can control flow fall through this instruction? 320 bit isCall = 0; // Is this instruction a call instruction? 321 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 322 bit mayLoad = 0; // Is it possible for this inst to read memory? 323 bit mayStore = 0; // Is it possible for this inst to write memory? 324 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 325 bit isCommutable = 0; // Is this 3 operand instruction commutable? 326 bit isTerminator = 0; // Is this part of the terminator for a basic block? 327 bit isReMaterializable = 0; // Is this instruction re-materializable? 328 bit isPredicable = 0; // Is this instruction predicable? 329 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 330 bit usesCustomInserter = 0; // Pseudo instr needing special help. 331 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 332 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 333 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 334 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 335 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 336 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 337 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 338 // If so, won't have encoding information for 339 // the [MC]CodeEmitter stuff. 340 341 // Side effect flags - When set, the flags have these meanings: 342 // 343 // hasSideEffects - The instruction has side effects that are not 344 // captured by any operands of the instruction or other flags. 345 // 346 // neverHasSideEffects - Set on an instruction with no pattern if it has no 347 // side effects. 348 bit hasSideEffects = 0; 349 bit neverHasSideEffects = 0; 350 351 // Is this instruction a "real" instruction (with a distinct machine 352 // encoding), or is it a pseudo instruction used for codegen modeling 353 // purposes. 354 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 355 // instructions can (and often do) still have encoding information 356 // associated with them. Once we've migrated all of them over to true 357 // pseudo-instructions that are lowered to real instructions prior to 358 // the printer/emitter, we can remove this attribute and just use isPseudo. 359 bit isCodeGenOnly = 0; 360 361 // Is this instruction a pseudo instruction for use by the assembler parser. 362 bit isAsmParserOnly = 0; 363 364 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 365 366 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 367 368 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 369 /// be encoded into the output machineinstr. 370 string DisableEncoding = ""; 371 372 string PostEncoderMethod = ""; 373 string DecoderMethod = ""; 374 375 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 376 bits<64> TSFlags = 0; 377 378 ///@name Assembler Parser Support 379 ///@{ 380 381 string AsmMatchConverter = ""; 382 383 ///@} 384 } 385 386 /// PseudoInstExpansion - Expansion information for a pseudo-instruction. 387 /// Which instruction it expands to and how the operands map from the 388 /// pseudo. 389 class PseudoInstExpansion<dag Result> { 390 dag ResultInst = Result; // The instruction to generate. 391 bit isPseudo = 1; 392 } 393 394 /// Predicates - These are extra conditionals which are turned into instruction 395 /// selector matching code. Currently each predicate is just a string. 396 class Predicate<string cond> { 397 string CondString = cond; 398 399 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 400 /// matcher, this is true. Targets should set this by inheriting their 401 /// feature from the AssemblerPredicate class in addition to Predicate. 402 bit AssemblerMatcherPredicate = 0; 403 404 /// AssemblerCondString - Name of the subtarget feature being tested used 405 /// as alternative condition string used for assembler matcher. 406 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 407 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 408 /// It can also list multiple features separated by ",". 409 /// e.g. "ModeThumb,FeatureThumb2" is translated to 410 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 411 string AssemblerCondString = ""; 412 } 413 414 /// NoHonorSignDependentRounding - This predicate is true if support for 415 /// sign-dependent-rounding is not enabled. 416 def NoHonorSignDependentRounding 417 : Predicate<"!HonorSignDependentRoundingFPMath()">; 418 419 class Requires<list<Predicate> preds> { 420 list<Predicate> Predicates = preds; 421 } 422 423 /// ops definition - This is just a simple marker used to identify the operand 424 /// list for an instruction. outs and ins are identical both syntactically and 425 /// semanticallyr; they are used to define def operands and use operands to 426 /// improve readibility. This should be used like this: 427 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 428 def ops; 429 def outs; 430 def ins; 431 432 /// variable_ops definition - Mark this instruction as taking a variable number 433 /// of operands. 434 def variable_ops; 435 436 437 /// PointerLikeRegClass - Values that are designed to have pointer width are 438 /// derived from this. TableGen treats the register class as having a symbolic 439 /// type that it doesn't know, and resolves the actual regclass to use by using 440 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 441 class PointerLikeRegClass<int Kind> { 442 int RegClassKind = Kind; 443 } 444 445 446 /// ptr_rc definition - Mark this operand as being a pointer value whose 447 /// register class is resolved dynamically via a callback to TargetInstrInfo. 448 /// FIXME: We should probably change this to a class which contain a list of 449 /// flags. But currently we have but one flag. 450 def ptr_rc : PointerLikeRegClass<0>; 451 452 /// unknown definition - Mark this operand as being of unknown type, causing 453 /// it to be resolved by inference in the context it is used. 454 def unknown; 455 456 /// AsmOperandClass - Representation for the kinds of operands which the target 457 /// specific parser can create and the assembly matcher may need to distinguish. 458 /// 459 /// Operand classes are used to define the order in which instructions are 460 /// matched, to ensure that the instruction which gets matched for any 461 /// particular list of operands is deterministic. 462 /// 463 /// The target specific parser must be able to classify a parsed operand into a 464 /// unique class which does not partially overlap with any other classes. It can 465 /// match a subset of some other class, in which case the super class field 466 /// should be defined. 467 class AsmOperandClass { 468 /// The name to use for this class, which should be usable as an enum value. 469 string Name = ?; 470 471 /// The super classes of this operand. 472 list<AsmOperandClass> SuperClasses = []; 473 474 /// The name of the method on the target specific operand to call to test 475 /// whether the operand is an instance of this class. If not set, this will 476 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 477 /// signature should be: 478 /// bool isFoo() const; 479 string PredicateMethod = ?; 480 481 /// The name of the method on the target specific operand to call to add the 482 /// target specific operand to an MCInst. If not set, this will default to 483 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 484 /// signature should be: 485 /// void addFooOperands(MCInst &Inst, unsigned N) const; 486 string RenderMethod = ?; 487 488 /// The name of the method on the target specific operand to call to custom 489 /// handle the operand parsing. This is useful when the operands do not relate 490 /// to immediates or registers and are very instruction specific (as flags to 491 /// set in a processor register, coprocessor number, ...). 492 string ParserMethod = ?; 493 } 494 495 def ImmAsmOperand : AsmOperandClass { 496 let Name = "Imm"; 497 } 498 499 /// Operand Types - These provide the built-in operand types that may be used 500 /// by a target. Targets can optionally provide their own operand types as 501 /// needed, though this should not be needed for RISC targets. 502 class Operand<ValueType ty> { 503 ValueType Type = ty; 504 string PrintMethod = "printOperand"; 505 string EncoderMethod = ""; 506 string DecoderMethod = ""; 507 string AsmOperandLowerMethod = ?; 508 string OperandType = "OPERAND_UNKNOWN"; 509 dag MIOperandInfo = (ops); 510 511 // ParserMatchClass - The "match class" that operands of this type fit 512 // in. Match classes are used to define the order in which instructions are 513 // match, to ensure that which instructions gets matched is deterministic. 514 // 515 // The target specific parser must be able to classify an parsed operand into 516 // a unique class, which does not partially overlap with any other classes. It 517 // can match a subset of some other class, in which case the AsmOperandClass 518 // should declare the other operand as one of its super classes. 519 AsmOperandClass ParserMatchClass = ImmAsmOperand; 520 } 521 522 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> { 523 // RegClass - The register class of the operand. 524 RegisterClass RegClass = regclass; 525 // PrintMethod - The target method to call to print register operands of 526 // this type. The method normally will just use an alt-name index to look 527 // up the name to print. Default to the generic printOperand(). 528 string PrintMethod = pm; 529 // ParserMatchClass - The "match class" that operands of this type fit 530 // in. Match classes are used to define the order in which instructions are 531 // match, to ensure that which instructions gets matched is deterministic. 532 // 533 // The target specific parser must be able to classify an parsed operand into 534 // a unique class, which does not partially overlap with any other classes. It 535 // can match a subset of some other class, in which case the AsmOperandClass 536 // should declare the other operand as one of its super classes. 537 AsmOperandClass ParserMatchClass; 538 } 539 540 let OperandType = "OPERAND_IMMEDIATE" in { 541 def i1imm : Operand<i1>; 542 def i8imm : Operand<i8>; 543 def i16imm : Operand<i16>; 544 def i32imm : Operand<i32>; 545 def i64imm : Operand<i64>; 546 547 def f32imm : Operand<f32>; 548 def f64imm : Operand<f64>; 549 } 550 551 /// zero_reg definition - Special node to stand for the zero register. 552 /// 553 def zero_reg; 554 555 /// PredicateOperand - This can be used to define a predicate operand for an 556 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and 557 /// AlwaysVal specifies the value of this predicate when set to "always 558 /// execute". 559 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 560 : Operand<ty> { 561 let MIOperandInfo = OpTypes; 562 dag DefaultOps = AlwaysVal; 563 } 564 565 /// OptionalDefOperand - This is used to define a optional definition operand 566 /// for an instruction. DefaultOps is the register the operand represents if 567 /// none is supplied, e.g. zero_reg. 568 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 569 : Operand<ty> { 570 let MIOperandInfo = OpTypes; 571 dag DefaultOps = defaultops; 572 } 573 574 575 // InstrInfo - This class should only be instantiated once to provide parameters 576 // which are global to the target machine. 577 // 578 class InstrInfo { 579 // Target can specify its instructions in either big or little-endian formats. 580 // For instance, while both Sparc and PowerPC are big-endian platforms, the 581 // Sparc manual specifies its instructions in the format [31..0] (big), while 582 // PowerPC specifies them using the format [0..31] (little). 583 bit isLittleEndianEncoding = 0; 584 } 585 586 // Standard Pseudo Instructions. 587 // This list must match TargetOpcodes.h and CodeGenTarget.cpp. 588 // Only these instructions are allowed in the TargetOpcode namespace. 589 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 590 def PHI : Instruction { 591 let OutOperandList = (outs); 592 let InOperandList = (ins variable_ops); 593 let AsmString = "PHINODE"; 594 } 595 def INLINEASM : Instruction { 596 let OutOperandList = (outs); 597 let InOperandList = (ins variable_ops); 598 let AsmString = ""; 599 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 600 } 601 def PROLOG_LABEL : Instruction { 602 let OutOperandList = (outs); 603 let InOperandList = (ins i32imm:$id); 604 let AsmString = ""; 605 let hasCtrlDep = 1; 606 let isNotDuplicable = 1; 607 } 608 def EH_LABEL : Instruction { 609 let OutOperandList = (outs); 610 let InOperandList = (ins i32imm:$id); 611 let AsmString = ""; 612 let hasCtrlDep = 1; 613 let isNotDuplicable = 1; 614 } 615 def GC_LABEL : Instruction { 616 let OutOperandList = (outs); 617 let InOperandList = (ins i32imm:$id); 618 let AsmString = ""; 619 let hasCtrlDep = 1; 620 let isNotDuplicable = 1; 621 } 622 def KILL : Instruction { 623 let OutOperandList = (outs); 624 let InOperandList = (ins variable_ops); 625 let AsmString = ""; 626 let neverHasSideEffects = 1; 627 } 628 def EXTRACT_SUBREG : Instruction { 629 let OutOperandList = (outs unknown:$dst); 630 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 631 let AsmString = ""; 632 let neverHasSideEffects = 1; 633 } 634 def INSERT_SUBREG : Instruction { 635 let OutOperandList = (outs unknown:$dst); 636 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 637 let AsmString = ""; 638 let neverHasSideEffects = 1; 639 let Constraints = "$supersrc = $dst"; 640 } 641 def IMPLICIT_DEF : Instruction { 642 let OutOperandList = (outs unknown:$dst); 643 let InOperandList = (ins); 644 let AsmString = ""; 645 let neverHasSideEffects = 1; 646 let isReMaterializable = 1; 647 let isAsCheapAsAMove = 1; 648 } 649 def SUBREG_TO_REG : Instruction { 650 let OutOperandList = (outs unknown:$dst); 651 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 652 let AsmString = ""; 653 let neverHasSideEffects = 1; 654 } 655 def COPY_TO_REGCLASS : Instruction { 656 let OutOperandList = (outs unknown:$dst); 657 let InOperandList = (ins unknown:$src, i32imm:$regclass); 658 let AsmString = ""; 659 let neverHasSideEffects = 1; 660 let isAsCheapAsAMove = 1; 661 } 662 def DBG_VALUE : Instruction { 663 let OutOperandList = (outs); 664 let InOperandList = (ins variable_ops); 665 let AsmString = "DBG_VALUE"; 666 let neverHasSideEffects = 1; 667 } 668 def REG_SEQUENCE : Instruction { 669 let OutOperandList = (outs unknown:$dst); 670 let InOperandList = (ins variable_ops); 671 let AsmString = ""; 672 let neverHasSideEffects = 1; 673 let isAsCheapAsAMove = 1; 674 } 675 def COPY : Instruction { 676 let OutOperandList = (outs unknown:$dst); 677 let InOperandList = (ins unknown:$src); 678 let AsmString = ""; 679 let neverHasSideEffects = 1; 680 let isAsCheapAsAMove = 1; 681 } 682 } 683 684 //===----------------------------------------------------------------------===// 685 // AsmParser - This class can be implemented by targets that wish to implement 686 // .s file parsing. 687 // 688 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 689 // syntax on X86 for example). 690 // 691 class AsmParser { 692 // AsmParserClassName - This specifies the suffix to use for the asmparser 693 // class. Generated AsmParser classes are always prefixed with the target 694 // name. 695 string AsmParserClassName = "AsmParser"; 696 697 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 698 // function of the AsmParser class to call on every matched instruction. 699 // This can be used to perform target specific instruction post-processing. 700 string AsmParserInstCleanup = ""; 701 702 // Variant - AsmParsers can be of multiple different variants. Variants are 703 // used to support targets that need to parser multiple formats for the 704 // assembly language. 705 int Variant = 0; 706 707 // CommentDelimiter - If given, the delimiter string used to recognize 708 // comments which are hard coded in the .td assembler strings for individual 709 // instructions. 710 string CommentDelimiter = ""; 711 712 // RegisterPrefix - If given, the token prefix which indicates a register 713 // token. This is used by the matcher to automatically recognize hard coded 714 // register tokens as constrained registers, instead of tokens, for the 715 // purposes of matching. 716 string RegisterPrefix = ""; 717 } 718 def DefaultAsmParser : AsmParser; 719 720 /// AssemblerPredicate - This is a Predicate that can be used when the assembler 721 /// matches instructions and aliases. 722 class AssemblerPredicate<string cond> { 723 bit AssemblerMatcherPredicate = 1; 724 string AssemblerCondString = cond; 725 } 726 727 728 729 /// MnemonicAlias - This class allows targets to define assembler mnemonic 730 /// aliases. This should be used when all forms of one mnemonic are accepted 731 /// with a different mnemonic. For example, X86 allows: 732 /// sal %al, 1 -> shl %al, 1 733 /// sal %ax, %cl -> shl %ax, %cl 734 /// sal %eax, %cl -> shl %eax, %cl 735 /// etc. Though "sal" is accepted with many forms, all of them are directly 736 /// translated to a shl, so it can be handled with (in the case of X86, it 737 /// actually has one for each suffix as well): 738 /// def : MnemonicAlias<"sal", "shl">; 739 /// 740 /// Mnemonic aliases are mapped before any other translation in the match phase, 741 /// and do allow Requires predicates, e.g.: 742 /// 743 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 744 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 745 /// 746 class MnemonicAlias<string From, string To> { 747 string FromMnemonic = From; 748 string ToMnemonic = To; 749 750 // Predicates - Predicates that must be true for this remapping to happen. 751 list<Predicate> Predicates = []; 752 } 753 754 /// InstAlias - This defines an alternate assembly syntax that is allowed to 755 /// match an instruction that has a different (more canonical) assembly 756 /// representation. 757 class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 758 string AsmString = Asm; // The .s format to match the instruction with. 759 dag ResultInst = Result; // The MCInst to generate. 760 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 761 762 // Predicates - Predicates that must be true for this to match. 763 list<Predicate> Predicates = []; 764 } 765 766 //===----------------------------------------------------------------------===// 767 // AsmWriter - This class can be implemented by targets that need to customize 768 // the format of the .s file writer. 769 // 770 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 771 // on X86 for example). 772 // 773 class AsmWriter { 774 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 775 // class. Generated AsmWriter classes are always prefixed with the target 776 // name. 777 string AsmWriterClassName = "AsmPrinter"; 778 779 // Variant - AsmWriters can be of multiple different variants. Variants are 780 // used to support targets that need to emit assembly code in ways that are 781 // mostly the same for different targets, but have minor differences in 782 // syntax. If the asmstring contains {|} characters in them, this integer 783 // will specify which alternative to use. For example "{x|y|z}" with Variant 784 // == 1, will expand to "y". 785 int Variant = 0; 786 787 788 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 789 // layout, the asmwriter can actually generate output in this columns (in 790 // verbose-asm mode). These two values indicate the width of the first column 791 // (the "opcode" area) and the width to reserve for subsequent operands. When 792 // verbose asm mode is enabled, operands will be indented to respect this. 793 int FirstOperandColumn = -1; 794 795 // OperandSpacing - Space between operand columns. 796 int OperandSpacing = -1; 797 798 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 799 // generation of the printInstruction() method. For MC printers, it takes 800 // an MCInstr* operand, otherwise it takes a MachineInstr*. 801 bit isMCAsmWriter = 0; 802 } 803 def DefaultAsmWriter : AsmWriter; 804 805 806 //===----------------------------------------------------------------------===// 807 // Target - This class contains the "global" target information 808 // 809 class Target { 810 // InstructionSet - Instruction set description for this target. 811 InstrInfo InstructionSet; 812 813 // AssemblyParsers - The AsmParser instances available for this target. 814 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 815 816 // AssemblyWriters - The AsmWriter instances available for this target. 817 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 818 } 819 820 //===----------------------------------------------------------------------===// 821 // SubtargetFeature - A characteristic of the chip set. 822 // 823 class SubtargetFeature<string n, string a, string v, string d, 824 list<SubtargetFeature> i = []> { 825 // Name - Feature name. Used by command line (-mattr=) to determine the 826 // appropriate target chip. 827 // 828 string Name = n; 829 830 // Attribute - Attribute to be set by feature. 831 // 832 string Attribute = a; 833 834 // Value - Value the attribute to be set to by feature. 835 // 836 string Value = v; 837 838 // Desc - Feature description. Used by command line (-mattr=) to display help 839 // information. 840 // 841 string Desc = d; 842 843 // Implies - Features that this feature implies are present. If one of those 844 // features isn't set, then this one shouldn't be set either. 845 // 846 list<SubtargetFeature> Implies = i; 847 } 848 849 //===----------------------------------------------------------------------===// 850 // Processor chip sets - These values represent each of the chip sets supported 851 // by the scheduler. Each Processor definition requires corresponding 852 // instruction itineraries. 853 // 854 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 855 // Name - Chip set name. Used by command line (-mcpu=) to determine the 856 // appropriate target chip. 857 // 858 string Name = n; 859 860 // ProcItin - The scheduling information for the target processor. 861 // 862 ProcessorItineraries ProcItin = pi; 863 864 // Features - list of 865 list<SubtargetFeature> Features = f; 866 } 867 868 //===----------------------------------------------------------------------===// 869 // Pull in the common support for calling conventions. 870 // 871 include "llvm/Target/TargetCallingConv.td" 872 873 //===----------------------------------------------------------------------===// 874 // Pull in the common support for DAG isel generation. 875 // 876 include "llvm/Target/TargetSelectionDAG.td" 877