1 //===- AlphaSchedule.td - Alpha Scheduling Definitions -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //This is table 2-2 from the 21264 compiler writers guide 11 //modified some 12 13 //Pipelines 14 15 def L0 : FuncUnit; 16 def L1 : FuncUnit; 17 def FST0 : FuncUnit; 18 def FST1 : FuncUnit; 19 def U0 : FuncUnit; 20 def U1 : FuncUnit; 21 def FA : FuncUnit; 22 def FM : FuncUnit; 23 24 def s_ild : InstrItinClass; 25 def s_fld : InstrItinClass; 26 def s_ist : InstrItinClass; 27 def s_fst : InstrItinClass; 28 def s_lda : InstrItinClass; 29 def s_rpcc : InstrItinClass; 30 def s_rx : InstrItinClass; 31 def s_mxpr : InstrItinClass; 32 def s_icbr : InstrItinClass; 33 def s_ubr : InstrItinClass; 34 def s_jsr : InstrItinClass; 35 def s_iadd : InstrItinClass; 36 def s_ilog : InstrItinClass; 37 def s_ishf : InstrItinClass; 38 def s_cmov : InstrItinClass; 39 def s_imul : InstrItinClass; 40 def s_imisc : InstrItinClass; 41 def s_fbr : InstrItinClass; 42 def s_fadd : InstrItinClass; 43 def s_fmul : InstrItinClass; 44 def s_fcmov : InstrItinClass; 45 def s_fdivt : InstrItinClass; 46 def s_fdivs : InstrItinClass; 47 def s_fsqrts: InstrItinClass; 48 def s_fsqrtt: InstrItinClass; 49 def s_ftoi : InstrItinClass; 50 def s_itof : InstrItinClass; 51 def s_pseudo : InstrItinClass; 52 53 //Table 2-4 Instruction Class Latency in Cycles 54 //modified some 55 56 def Alpha21264Itineraries : ProcessorItineraries< 57 [L0, L1, FST0, FST1, U0, U1, FA, FM], [], [ 58 InstrItinData<s_ild , [InstrStage<3, [L0, L1]>]>, 59 InstrItinData<s_fld , [InstrStage<4, [L0, L1]>]>, 60 InstrItinData<s_ist , [InstrStage<0, [L0, L1]>]>, 61 InstrItinData<s_fst , [InstrStage<0, [FST0, FST1, L0, L1]>]>, 62 InstrItinData<s_lda , [InstrStage<1, [L0, L1, U0, U1]>]>, 63 InstrItinData<s_rpcc , [InstrStage<1, [L1]>]>, 64 InstrItinData<s_rx , [InstrStage<1, [L1]>]>, 65 InstrItinData<s_mxpr , [InstrStage<1, [L0, L1]>]>, 66 InstrItinData<s_icbr , [InstrStage<0, [U0, U1]>]>, 67 InstrItinData<s_ubr , [InstrStage<3, [U0, U1]>]>, 68 InstrItinData<s_jsr , [InstrStage<3, [L0]>]>, 69 InstrItinData<s_iadd , [InstrStage<1, [L0, U0, L1, U1]>]>, 70 InstrItinData<s_ilog , [InstrStage<1, [L0, U0, L1, U1]>]>, 71 InstrItinData<s_ishf , [InstrStage<1, [U0, U1]>]>, 72 InstrItinData<s_cmov , [InstrStage<1, [L0, U0, L1, U1]>]>, 73 InstrItinData<s_imul , [InstrStage<7, [U1]>]>, 74 InstrItinData<s_imisc , [InstrStage<3, [U0]>]>, 75 InstrItinData<s_fbr , [InstrStage<0, [FA]>]>, 76 InstrItinData<s_fadd , [InstrStage<6, [FA]>]>, 77 InstrItinData<s_fmul , [InstrStage<6, [FM]>]>, 78 InstrItinData<s_fcmov , [InstrStage<6, [FA]>]>, 79 InstrItinData<s_fdivs , [InstrStage<12, [FA]>]>, 80 InstrItinData<s_fdivt , [InstrStage<15, [FA]>]>, 81 InstrItinData<s_fsqrts , [InstrStage<18, [FA]>]>, 82 InstrItinData<s_fsqrtt , [InstrStage<33, [FA]>]>, 83 InstrItinData<s_ftoi , [InstrStage<3, [FST0, FST1, L0, L1]>]>, 84 InstrItinData<s_itof , [InstrStage<4, [L0, L1]>]> 85 ]>; 86
