1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Top-level implementation for the PowerPC target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPC.h" 15 #include "PPCTargetMachine.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/MC/MCStreamer.h" 18 #include "llvm/Target/TargetOptions.h" 19 #include "llvm/Support/FormattedStream.h" 20 #include "llvm/Support/TargetRegistry.h" 21 using namespace llvm; 22 23 extern "C" void LLVMInitializePowerPCTarget() { 24 // Register the targets 25 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); 26 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target); 27 } 28 29 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, 30 StringRef CPU, StringRef FS, 31 Reloc::Model RM, CodeModel::Model CM, 32 bool is64Bit) 33 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 34 Subtarget(TT, CPU, FS, is64Bit), 35 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), 36 FrameLowering(Subtarget), JITInfo(*this, is64Bit), 37 TLInfo(*this), TSInfo(*this), 38 InstrItins(Subtarget.getInstrItineraryData()) { 39 } 40 41 /// Override this for PowerPC. Tail merging happily breaks up instruction issue 42 /// groups, which typically degrades performance. 43 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } 44 45 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, 46 StringRef CPU, StringRef FS, 47 Reloc::Model RM, CodeModel::Model CM) 48 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) { 49 } 50 51 52 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, 53 StringRef CPU, StringRef FS, 54 Reloc::Model RM, CodeModel::Model CM) 55 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) { 56 } 57 58 59 //===----------------------------------------------------------------------===// 60 // Pass Pipeline Configuration 61 //===----------------------------------------------------------------------===// 62 63 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, 64 CodeGenOpt::Level OptLevel) { 65 // Install an instruction selector. 66 PM.add(createPPCISelDag(*this)); 67 return false; 68 } 69 70 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, 71 CodeGenOpt::Level OptLevel) { 72 // Must run branch selection immediately preceding the asm printer. 73 PM.add(createPPCBranchSelectionPass()); 74 return false; 75 } 76 77 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, 78 CodeGenOpt::Level OptLevel, 79 JITCodeEmitter &JCE) { 80 // FIXME: This should be moved to TargetJITInfo!! 81 if (Subtarget.isPPC64()) 82 // Temporary workaround for the inability of PPC64 JIT to handle jump 83 // tables. 84 DisableJumpTables = true; 85 86 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho 87 // writing? 88 Subtarget.SetJITMode(); 89 90 // Machine code emitter pass for PowerPC. 91 PM.add(createPPCJITCodeEmitterPass(*this, JCE)); 92 93 return false; 94 } 95
