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      1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
      2 |*                                                                            *|
      3 |* Register Bank Source Fragments                                             *|
      4 |*                                                                            *|
      5 |* Automatically generated file, do not edit!                                 *|
      6 |*                                                                            *|
      7 \*===----------------------------------------------------------------------===*/
      8 
      9 #ifdef GET_REGBANK_DECLARATIONS
     10 #undef GET_REGBANK_DECLARATIONS
     11 namespace llvm {
     12 namespace Mips {
     13 enum {
     14   GPRBRegBankID,
     15   NumRegisterBanks,
     16 };
     17 } // end namespace Mips
     18 } // end namespace llvm
     19 #endif // GET_REGBANK_DECLARATIONS
     20 
     21 #ifdef GET_TARGET_REGBANK_CLASS
     22 #undef GET_TARGET_REGBANK_CLASS
     23 private:
     24   static RegisterBank *RegBanks[];
     25 
     26 protected:
     27   MipsGenRegisterBankInfo();
     28 
     29 #endif // GET_TARGET_REGBANK_CLASS
     30 
     31 #ifdef GET_TARGET_REGBANK_IMPL
     32 #undef GET_TARGET_REGBANK_IMPL
     33 namespace llvm {
     34 namespace Mips {
     35 const uint32_t GPRBRegBankCoverageData[] = {
     36     // 0-31
     37     (1u << (Mips::GPR32RegClassID - 0)) |
     38     (1u << (Mips::GPR32NONZERORegClassID - 0)) |
     39     (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
     40     (1u << (Mips::CPU16RegsRegClassID - 0)) |
     41     (1u << (Mips::GPRMM16RegClassID - 0)) |
     42     (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
     43     (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
     44     (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
     45     (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
     46     (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
     47     (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
     48     0,
     49     // 32-63
     50     (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
     51     (1u << (Mips::CPUSPRegRegClassID - 32)) |
     52     (1u << (Mips::SP32RegClassID - 32)) |
     53     (1u << (Mips::CPURARegRegClassID - 32)) |
     54     (1u << (Mips::GP32RegClassID - 32)) |
     55     (1u << (Mips::GPR32ZERORegClassID - 32)) |
     56     0,
     57     // 64-95
     58     0,
     59 };
     60 
     61 RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 73);
     62 } // end namespace Mips
     63 
     64 RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
     65     &Mips::GPRBRegBank,
     66 };
     67 
     68 MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
     69     : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
     70   // Assert that RegBank indices match their ID's
     71 #ifndef NDEBUG
     72   unsigned Index = 0;
     73   for (const auto &RB : RegBanks)
     74     assert(Index++ == RB->getID() && "Index != ID");
     75 #endif // NDEBUG
     76 }
     77 } // end namespace llvm
     78 #endif // GET_TARGET_REGBANK_IMPL
     79