1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the ScheduleDAG class, which is a base class used by 11 // scheduling implementation classes. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ScheduleDAGSDNodes.h" 16 #include "InstrEmitter.h" 17 #include "SDNodeDbgValue.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/SmallSet.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/SelectionDAG.h" 26 #include "llvm/CodeGen/TargetInstrInfo.h" 27 #include "llvm/CodeGen/TargetLowering.h" 28 #include "llvm/CodeGen/TargetRegisterInfo.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include "llvm/Config/llvm-config.h" 31 #include "llvm/MC/MCInstrItineraries.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/raw_ostream.h" 35 using namespace llvm; 36 37 #define DEBUG_TYPE "pre-RA-sched" 38 39 STATISTIC(LoadsClustered, "Number of loads clustered together"); 40 41 // This allows the latency-based scheduler to notice high latency instructions 42 // without a target itinerary. The choice of number here has more to do with 43 // balancing scheduler heuristics than with the actual machine latency. 44 static cl::opt<int> HighLatencyCycles( 45 "sched-high-latency-cycles", cl::Hidden, cl::init(10), 46 cl::desc("Roughly estimate the number of cycles that 'long latency'" 47 "instructions take for targets with no itinerary")); 48 49 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr), 51 InstrItins(mf.getSubtarget().getInstrItineraryData()) {} 52 53 /// Run - perform scheduling. 54 /// 55 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) { 56 BB = bb; 57 DAG = dag; 58 59 // Clear the scheduler's SUnit DAG. 60 ScheduleDAG::clearDAG(); 61 Sequence.clear(); 62 63 // Invoke the target's selection of scheduler. 64 Schedule(); 65 } 66 67 /// NewSUnit - Creates a new SUnit and return a ptr to it. 68 /// 69 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) { 70 #ifndef NDEBUG 71 const SUnit *Addr = nullptr; 72 if (!SUnits.empty()) 73 Addr = &SUnits[0]; 74 #endif 75 SUnits.emplace_back(N, (unsigned)SUnits.size()); 76 assert((Addr == nullptr || Addr == &SUnits[0]) && 77 "SUnits std::vector reallocated on the fly!"); 78 SUnits.back().OrigNode = &SUnits.back(); 79 SUnit *SU = &SUnits.back(); 80 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 81 if (!N || 82 (N->isMachineOpcode() && 83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) 84 SU->SchedulingPref = Sched::None; 85 else 86 SU->SchedulingPref = TLI.getSchedulingPreference(N); 87 return SU; 88 } 89 90 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 91 SUnit *SU = newSUnit(Old->getNode()); 92 SU->OrigNode = Old->OrigNode; 93 SU->Latency = Old->Latency; 94 SU->isVRegCycle = Old->isVRegCycle; 95 SU->isCall = Old->isCall; 96 SU->isCallOp = Old->isCallOp; 97 SU->isTwoAddress = Old->isTwoAddress; 98 SU->isCommutable = Old->isCommutable; 99 SU->hasPhysRegDefs = Old->hasPhysRegDefs; 100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers; 101 SU->isScheduleHigh = Old->isScheduleHigh; 102 SU->isScheduleLow = Old->isScheduleLow; 103 SU->SchedulingPref = Old->SchedulingPref; 104 Old->isCloned = true; 105 return SU; 106 } 107 108 /// CheckForPhysRegDependency - Check if the dependency between def and use of 109 /// a specified operand is a physical register dependency. If so, returns the 110 /// register and the cost of copying the register. 111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 112 const TargetRegisterInfo *TRI, 113 const TargetInstrInfo *TII, 114 unsigned &PhysReg, int &Cost) { 115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 116 return; 117 118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 119 if (TargetRegisterInfo::isVirtualRegister(Reg)) 120 return; 121 122 unsigned ResNo = User->getOperand(2).getResNo(); 123 if (Def->getOpcode() == ISD::CopyFromReg && 124 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) { 125 PhysReg = Reg; 126 } else if (Def->isMachineOpcode()) { 127 const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 128 if (ResNo >= II.getNumDefs() && 129 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) 130 PhysReg = Reg; 131 } 132 133 if (PhysReg != 0) { 134 const TargetRegisterClass *RC = 135 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); 136 Cost = RC->getCopyCost(); 137 } 138 } 139 140 // Helper for AddGlue to clone node operands. 141 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, 142 SDValue ExtraOper = SDValue()) { 143 SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end()); 144 if (ExtraOper.getNode()) 145 Ops.push_back(ExtraOper); 146 147 SDVTList VTList = DAG->getVTList(VTs); 148 MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr; 149 MachineSDNode *MN = dyn_cast<MachineSDNode>(N); 150 151 // Store memory references. 152 if (MN) { 153 Begin = MN->memoperands_begin(); 154 End = MN->memoperands_end(); 155 } 156 157 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); 158 159 // Reset the memory references 160 if (MN) 161 MN->setMemRefs(Begin, End); 162 } 163 164 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { 165 SDNode *GlueDestNode = Glue.getNode(); 166 167 // Don't add glue from a node to itself. 168 if (GlueDestNode == N) return false; 169 170 // Don't add a glue operand to something that already uses glue. 171 if (GlueDestNode && 172 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) { 173 return false; 174 } 175 // Don't add glue to something that already has a glue value. 176 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false; 177 178 SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end()); 179 if (AddGlue) 180 VTs.push_back(MVT::Glue); 181 182 CloneNodeWithValues(N, DAG, VTs, Glue); 183 184 return true; 185 } 186 187 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the 188 // node even though simply shrinking the value list is sufficient. 189 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { 190 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue && 191 !N->hasAnyUseOfValue(N->getNumValues() - 1)) && 192 "expected an unused glue value"); 193 194 CloneNodeWithValues(N, DAG, 195 makeArrayRef(N->value_begin(), N->getNumValues() - 1)); 196 } 197 198 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them. 199 /// This function finds loads of the same base and different offsets. If the 200 /// offsets are not far apart (target specific), it add MVT::Glue inputs and 201 /// outputs to ensure they are scheduled together and in order. This 202 /// optimization may benefit some targets by improving cache locality. 203 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { 204 SDNode *Chain = nullptr; 205 unsigned NumOps = Node->getNumOperands(); 206 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 207 Chain = Node->getOperand(NumOps-1).getNode(); 208 if (!Chain) 209 return; 210 211 // Look for other loads of the same chain. Find loads that are loading from 212 // the same base pointer and different offsets. 213 SmallPtrSet<SDNode*, 16> Visited; 214 SmallVector<int64_t, 4> Offsets; 215 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. 216 bool Cluster = false; 217 SDNode *Base = Node; 218 // This algorithm requires a reasonably low use count before finding a match 219 // to avoid uselessly blowing up compile time in large blocks. 220 unsigned UseCount = 0; 221 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); 222 I != E && UseCount < 100; ++I, ++UseCount) { 223 SDNode *User = *I; 224 if (User == Node || !Visited.insert(User).second) 225 continue; 226 int64_t Offset1, Offset2; 227 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 228 Offset1 == Offset2) 229 // FIXME: Should be ok if they addresses are identical. But earlier 230 // optimizations really should have eliminated one of the loads. 231 continue; 232 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 233 Offsets.push_back(Offset1); 234 O2SMap.insert(std::make_pair(Offset2, User)); 235 Offsets.push_back(Offset2); 236 if (Offset2 < Offset1) 237 Base = User; 238 Cluster = true; 239 // Reset UseCount to allow more matches. 240 UseCount = 0; 241 } 242 243 if (!Cluster) 244 return; 245 246 // Sort them in increasing order. 247 llvm::sort(Offsets.begin(), Offsets.end()); 248 249 // Check if the loads are close enough. 250 SmallVector<SDNode*, 4> Loads; 251 unsigned NumLoads = 0; 252 int64_t BaseOff = Offsets[0]; 253 SDNode *BaseLoad = O2SMap[BaseOff]; 254 Loads.push_back(BaseLoad); 255 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) { 256 int64_t Offset = Offsets[i]; 257 SDNode *Load = O2SMap[Offset]; 258 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 259 break; // Stop right here. Ignore loads that are further away. 260 Loads.push_back(Load); 261 ++NumLoads; 262 } 263 264 if (NumLoads == 0) 265 return; 266 267 // Cluster loads by adding MVT::Glue outputs and inputs. This also 268 // ensure they are scheduled in order of increasing addresses. 269 SDNode *Lead = Loads[0]; 270 SDValue InGlue = SDValue(nullptr, 0); 271 if (AddGlue(Lead, InGlue, true, DAG)) 272 InGlue = SDValue(Lead, Lead->getNumValues() - 1); 273 for (unsigned I = 1, E = Loads.size(); I != E; ++I) { 274 bool OutGlue = I < E - 1; 275 SDNode *Load = Loads[I]; 276 277 // If AddGlue fails, we could leave an unsused glue value. This should not 278 // cause any 279 if (AddGlue(Load, InGlue, OutGlue, DAG)) { 280 if (OutGlue) 281 InGlue = SDValue(Load, Load->getNumValues() - 1); 282 283 ++LoadsClustered; 284 } 285 else if (!OutGlue && InGlue.getNode()) 286 RemoveUnusedGlue(InGlue.getNode(), DAG); 287 } 288 } 289 290 /// ClusterNodes - Cluster certain nodes which should be scheduled together. 291 /// 292 void ScheduleDAGSDNodes::ClusterNodes() { 293 for (SDNode &NI : DAG->allnodes()) { 294 SDNode *Node = &NI; 295 if (!Node || !Node->isMachineOpcode()) 296 continue; 297 298 unsigned Opc = Node->getMachineOpcode(); 299 const MCInstrDesc &MCID = TII->get(Opc); 300 if (MCID.mayLoad()) 301 // Cluster loads from "near" addresses into combined SUnits. 302 ClusterNeighboringLoads(Node); 303 } 304 } 305 306 void ScheduleDAGSDNodes::BuildSchedUnits() { 307 // During scheduling, the NodeId field of SDNode is used to map SDNodes 308 // to their associated SUnits by holding SUnits table indices. A value 309 // of -1 means the SDNode does not yet have an associated SUnit. 310 unsigned NumNodes = 0; 311 for (SDNode &NI : DAG->allnodes()) { 312 NI.setNodeId(-1); 313 ++NumNodes; 314 } 315 316 // Reserve entries in the vector for each of the SUnits we are creating. This 317 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 318 // invalidated. 319 // FIXME: Multiply by 2 because we may clone nodes during scheduling. 320 // This is a temporary workaround. 321 SUnits.reserve(NumNodes * 2); 322 323 // Add all nodes in depth first order. 324 SmallVector<SDNode*, 64> Worklist; 325 SmallPtrSet<SDNode*, 32> Visited; 326 Worklist.push_back(DAG->getRoot().getNode()); 327 Visited.insert(DAG->getRoot().getNode()); 328 329 SmallVector<SUnit*, 8> CallSUnits; 330 while (!Worklist.empty()) { 331 SDNode *NI = Worklist.pop_back_val(); 332 333 // Add all operands to the worklist unless they've already been added. 334 for (const SDValue &Op : NI->op_values()) 335 if (Visited.insert(Op.getNode()).second) 336 Worklist.push_back(Op.getNode()); 337 338 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 339 continue; 340 341 // If this node has already been processed, stop now. 342 if (NI->getNodeId() != -1) continue; 343 344 SUnit *NodeSUnit = newSUnit(NI); 345 346 // See if anything is glued to this node, if so, add them to glued 347 // nodes. Nodes can have at most one glue input and one glue output. Glue 348 // is required to be the last operand and result of a node. 349 350 // Scan up to find glued preds. 351 SDNode *N = NI; 352 while (N->getNumOperands() && 353 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) { 354 N = N->getOperand(N->getNumOperands()-1).getNode(); 355 assert(N->getNodeId() == -1 && "Node already inserted!"); 356 N->setNodeId(NodeSUnit->NodeNum); 357 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 358 NodeSUnit->isCall = true; 359 } 360 361 // Scan down to find any glued succs. 362 N = NI; 363 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) { 364 SDValue GlueVal(N, N->getNumValues()-1); 365 366 // There are either zero or one users of the Glue result. 367 bool HasGlueUse = false; 368 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 369 UI != E; ++UI) 370 if (GlueVal.isOperandOf(*UI)) { 371 HasGlueUse = true; 372 assert(N->getNodeId() == -1 && "Node already inserted!"); 373 N->setNodeId(NodeSUnit->NodeNum); 374 N = *UI; 375 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 376 NodeSUnit->isCall = true; 377 break; 378 } 379 if (!HasGlueUse) break; 380 } 381 382 if (NodeSUnit->isCall) 383 CallSUnits.push_back(NodeSUnit); 384 385 // Schedule zero-latency TokenFactor below any nodes that may increase the 386 // schedule height. Otherwise, ancestors of the TokenFactor may appear to 387 // have false stalls. 388 if (NI->getOpcode() == ISD::TokenFactor) 389 NodeSUnit->isScheduleLow = true; 390 391 // If there are glue operands involved, N is now the bottom-most node 392 // of the sequence of nodes that are glued together. 393 // Update the SUnit. 394 NodeSUnit->setNode(N); 395 assert(N->getNodeId() == -1 && "Node already inserted!"); 396 N->setNodeId(NodeSUnit->NodeNum); 397 398 // Compute NumRegDefsLeft. This must be done before AddSchedEdges. 399 InitNumRegDefsLeft(NodeSUnit); 400 401 // Assign the Latency field of NodeSUnit using target-provided information. 402 computeLatency(NodeSUnit); 403 } 404 405 // Find all call operands. 406 while (!CallSUnits.empty()) { 407 SUnit *SU = CallSUnits.pop_back_val(); 408 for (const SDNode *SUNode = SU->getNode(); SUNode; 409 SUNode = SUNode->getGluedNode()) { 410 if (SUNode->getOpcode() != ISD::CopyToReg) 411 continue; 412 SDNode *SrcN = SUNode->getOperand(2).getNode(); 413 if (isPassiveNode(SrcN)) continue; // Not scheduled. 414 SUnit *SrcSU = &SUnits[SrcN->getNodeId()]; 415 SrcSU->isCallOp = true; 416 } 417 } 418 } 419 420 void ScheduleDAGSDNodes::AddSchedEdges() { 421 const TargetSubtargetInfo &ST = MF.getSubtarget(); 422 423 // Check to see if the scheduler cares about latencies. 424 bool UnitLatencies = forceUnitLatencies(); 425 426 // Pass 2: add the preds, succs, etc. 427 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 428 SUnit *SU = &SUnits[su]; 429 SDNode *MainNode = SU->getNode(); 430 431 if (MainNode->isMachineOpcode()) { 432 unsigned Opc = MainNode->getMachineOpcode(); 433 const MCInstrDesc &MCID = TII->get(Opc); 434 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 435 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 436 SU->isTwoAddress = true; 437 break; 438 } 439 } 440 if (MCID.isCommutable()) 441 SU->isCommutable = true; 442 } 443 444 // Find all predecessors and successors of the group. 445 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) { 446 if (N->isMachineOpcode() && 447 TII->get(N->getMachineOpcode()).getImplicitDefs()) { 448 SU->hasPhysRegClobbers = true; 449 unsigned NumUsed = InstrEmitter::CountResults(N); 450 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1)) 451 --NumUsed; // Skip over unused values at the end. 452 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) 453 SU->hasPhysRegDefs = true; 454 } 455 456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 457 SDNode *OpN = N->getOperand(i).getNode(); 458 if (isPassiveNode(OpN)) continue; // Not scheduled. 459 SUnit *OpSU = &SUnits[OpN->getNodeId()]; 460 assert(OpSU && "Node has no SUnit!"); 461 if (OpSU == SU) continue; // In the same group. 462 463 EVT OpVT = N->getOperand(i).getValueType(); 464 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); 465 bool isChain = OpVT == MVT::Other; 466 467 unsigned PhysReg = 0; 468 int Cost = 1; 469 // Determine if this is a physical register dependency. 470 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 471 assert((PhysReg == 0 || !isChain) && 472 "Chain dependence via physreg data?"); 473 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 474 // emits a copy from the physical register to a virtual register unless 475 // it requires a cross class copy (cost < 0). That means we are only 476 // treating "expensive to copy" register dependency as physical register 477 // dependency. This may change in the future though. 478 if (Cost >= 0 && !StressSched) 479 PhysReg = 0; 480 481 // If this is a ctrl dep, latency is 1. 482 unsigned OpLatency = isChain ? 1 : OpSU->Latency; 483 // Special-case TokenFactor chains as zero-latency. 484 if(isChain && OpN->getOpcode() == ISD::TokenFactor) 485 OpLatency = 0; 486 487 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) 488 : SDep(OpSU, SDep::Data, PhysReg); 489 Dep.setLatency(OpLatency); 490 if (!isChain && !UnitLatencies) { 491 computeOperandLatency(OpN, N, i, Dep); 492 ST.adjustSchedDependency(OpSU, SU, Dep); 493 } 494 495 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { 496 // Multiple register uses are combined in the same SUnit. For example, 497 // we could have a set of glued nodes with all their defs consumed by 498 // another set of glued nodes. Register pressure tracking sees this as 499 // a single use, so to keep pressure balanced we reduce the defs. 500 // 501 // We can't tell (without more book-keeping) if this results from 502 // glued nodes or duplicate operands. As long as we don't reduce 503 // NumRegDefsLeft to zero, we handle the common cases well. 504 --OpSU->NumRegDefsLeft; 505 } 506 } 507 } 508 } 509 } 510 511 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we 512 /// are input. This SUnit graph is similar to the SelectionDAG, but 513 /// excludes nodes that aren't interesting to scheduling, and represents 514 /// glued together nodes with a single SUnit. 515 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) { 516 // Cluster certain nodes which should be scheduled together. 517 ClusterNodes(); 518 // Populate the SUnits array. 519 BuildSchedUnits(); 520 // Compute all the scheduling dependencies between nodes. 521 AddSchedEdges(); 522 } 523 524 // Initialize NumNodeDefs for the current Node's opcode. 525 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() { 526 // Check for phys reg copy. 527 if (!Node) 528 return; 529 530 if (!Node->isMachineOpcode()) { 531 if (Node->getOpcode() == ISD::CopyFromReg) 532 NodeNumDefs = 1; 533 else 534 NodeNumDefs = 0; 535 return; 536 } 537 unsigned POpc = Node->getMachineOpcode(); 538 if (POpc == TargetOpcode::IMPLICIT_DEF) { 539 // No register need be allocated for this. 540 NodeNumDefs = 0; 541 return; 542 } 543 if (POpc == TargetOpcode::PATCHPOINT && 544 Node->getValueType(0) == MVT::Other) { 545 // PATCHPOINT is defined to have one result, but it might really have none 546 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a 547 // real definition. 548 NodeNumDefs = 0; 549 return; 550 } 551 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); 552 // Some instructions define regs that are not represented in the selection DAG 553 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues. 554 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs); 555 DefIdx = 0; 556 } 557 558 // Construct a RegDefIter for this SUnit and find the first valid value. 559 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU, 560 const ScheduleDAGSDNodes *SD) 561 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 562 InitNodeNumDefs(); 563 Advance(); 564 } 565 566 // Advance to the next valid value defined by the SUnit. 567 void ScheduleDAGSDNodes::RegDefIter::Advance() { 568 for (;Node;) { // Visit all glued nodes. 569 for (;DefIdx < NodeNumDefs; ++DefIdx) { 570 if (!Node->hasAnyUseOfValue(DefIdx)) 571 continue; 572 ValueType = Node->getSimpleValueType(DefIdx); 573 ++DefIdx; 574 return; // Found a normal regdef. 575 } 576 Node = Node->getGluedNode(); 577 if (!Node) { 578 return; // No values left to visit. 579 } 580 InitNodeNumDefs(); 581 } 582 } 583 584 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) { 585 assert(SU->NumRegDefsLeft == 0 && "expect a new node"); 586 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) { 587 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected"); 588 ++SU->NumRegDefsLeft; 589 } 590 } 591 592 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) { 593 SDNode *N = SU->getNode(); 594 595 // TokenFactor operands are considered zero latency, and some schedulers 596 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero 597 // whenever node latency is nonzero. 598 if (N && N->getOpcode() == ISD::TokenFactor) { 599 SU->Latency = 0; 600 return; 601 } 602 603 // Check to see if the scheduler cares about latencies. 604 if (forceUnitLatencies()) { 605 SU->Latency = 1; 606 return; 607 } 608 609 if (!InstrItins || InstrItins->isEmpty()) { 610 if (N && N->isMachineOpcode() && 611 TII->isHighLatencyDef(N->getMachineOpcode())) 612 SU->Latency = HighLatencyCycles; 613 else 614 SU->Latency = 1; 615 return; 616 } 617 618 // Compute the latency for the node. We use the sum of the latencies for 619 // all nodes glued together into this SUnit. 620 SU->Latency = 0; 621 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) 622 if (N->isMachineOpcode()) 623 SU->Latency += TII->getInstrLatency(InstrItins, N); 624 } 625 626 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use, 627 unsigned OpIdx, SDep& dep) const{ 628 // Check to see if the scheduler cares about latencies. 629 if (forceUnitLatencies()) 630 return; 631 632 if (dep.getKind() != SDep::Data) 633 return; 634 635 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 636 if (Use->isMachineOpcode()) 637 // Adjust the use operand index by num of defs. 638 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); 639 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); 640 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && 641 !BB->succ_empty()) { 642 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); 643 if (TargetRegisterInfo::isVirtualRegister(Reg)) 644 // This copy is a liveout value. It is likely coalesced, so reduce the 645 // latency so not to penalize the def. 646 // FIXME: need target specific adjustment here? 647 Latency = (Latency > 1) ? Latency - 1 : 1; 648 } 649 if (Latency >= 0) 650 dep.setLatency(Latency); 651 } 652 653 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 654 // Cannot completely remove virtual function even in release mode. 655 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 656 if (!SU->getNode()) { 657 dbgs() << "PHYS REG COPY\n"; 658 return; 659 } 660 661 SU->getNode()->dump(DAG); 662 dbgs() << "\n"; 663 SmallVector<SDNode *, 4> GluedNodes; 664 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) 665 GluedNodes.push_back(N); 666 while (!GluedNodes.empty()) { 667 dbgs() << " "; 668 GluedNodes.back()->dump(DAG); 669 dbgs() << "\n"; 670 GluedNodes.pop_back(); 671 } 672 #endif 673 } 674 675 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 676 void ScheduleDAGSDNodes::dumpSchedule() const { 677 for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 678 if (SUnit *SU = Sequence[i]) 679 SU->dump(this); 680 else 681 dbgs() << "**** NOOP ****\n"; 682 } 683 } 684 #endif 685 686 #ifndef NDEBUG 687 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that 688 /// their state is consistent with the nodes listed in Sequence. 689 /// 690 void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) { 691 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp); 692 unsigned Noops = 0; 693 for (unsigned i = 0, e = Sequence.size(); i != e; ++i) 694 if (!Sequence[i]) 695 ++Noops; 696 assert(Sequence.size() - Noops == ScheduledNodes && 697 "The number of nodes scheduled doesn't match the expected number!"); 698 } 699 #endif // NDEBUG 700 701 /// ProcessSDDbgValues - Process SDDbgValues associated with this node. 702 static void 703 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, 704 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, 705 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) { 706 if (!N->getHasDebugValue()) 707 return; 708 709 // Opportunistically insert immediate dbg_value uses, i.e. those with the same 710 // source order number as N. 711 MachineBasicBlock *BB = Emitter.getBlock(); 712 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos(); 713 for (auto DV : DAG->GetDbgValues(N)) { 714 if (DV->isInvalidated()) 715 continue; 716 unsigned DVOrder = DV->getOrder(); 717 if (!Order || DVOrder == Order) { 718 MachineInstr *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap); 719 if (DbgMI) { 720 Orders.push_back({DVOrder, DbgMI}); 721 BB->insert(InsertPos, DbgMI); 722 } 723 DV->setIsInvalidated(); 724 } 725 } 726 } 727 728 // ProcessSourceNode - Process nodes with source order numbers. These are added 729 // to a vector which EmitSchedule uses to determine how to insert dbg_value 730 // instructions in the right order. 731 static void 732 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, 733 DenseMap<SDValue, unsigned> &VRBaseMap, 734 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, 735 SmallSet<unsigned, 8> &Seen) { 736 unsigned Order = N->getIROrder(); 737 if (!Order || !Seen.insert(Order).second) { 738 // Process any valid SDDbgValues even if node does not have any order 739 // assigned. 740 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); 741 return; 742 } 743 744 MachineBasicBlock *BB = Emitter.getBlock(); 745 auto IP = Emitter.getInsertPos(); 746 if (IP == BB->begin() || BB->back().isPHI() || 747 // Fast-isel may have inserted some instructions, in which case the 748 // BB->back().isPHI() test will not fire when we want it to. 749 std::prev(IP)->isPHI()) { 750 // Did not insert any instruction. 751 Orders.push_back({Order, (MachineInstr *)nullptr}); 752 return; 753 } 754 755 Orders.push_back({Order, &*std::prev(IP)}); 756 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); 757 } 758 759 void ScheduleDAGSDNodes:: 760 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap, 761 MachineBasicBlock::iterator InsertPos) { 762 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 763 I != E; ++I) { 764 if (I->isCtrl()) continue; // ignore chain preds 765 if (I->getSUnit()->CopyDstRC) { 766 // Copy to physical register. 767 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit()); 768 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late"); 769 // Find the destination physical register. 770 unsigned Reg = 0; 771 for (SUnit::const_succ_iterator II = SU->Succs.begin(), 772 EE = SU->Succs.end(); II != EE; ++II) { 773 if (II->isCtrl()) continue; // ignore chain preds 774 if (II->getReg()) { 775 Reg = II->getReg(); 776 break; 777 } 778 } 779 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg) 780 .addReg(VRI->second); 781 } else { 782 // Copy from physical register. 783 assert(I->getReg() && "Unknown physical register!"); 784 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC); 785 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; 786 (void)isNew; // Silence compiler warning. 787 assert(isNew && "Node emitted out of order - early"); 788 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase) 789 .addReg(I->getReg()); 790 } 791 break; 792 } 793 } 794 795 /// EmitSchedule - Emit the machine code in scheduled order. Return the new 796 /// InsertPos and MachineBasicBlock that contains this insertion 797 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does 798 /// not necessarily refer to returned BB. The emitter may split blocks. 799 MachineBasicBlock *ScheduleDAGSDNodes:: 800 EmitSchedule(MachineBasicBlock::iterator &InsertPos) { 801 InstrEmitter Emitter(BB, InsertPos); 802 DenseMap<SDValue, unsigned> VRBaseMap; 803 DenseMap<SUnit*, unsigned> CopyVRBaseMap; 804 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; 805 SmallSet<unsigned, 8> Seen; 806 bool HasDbg = DAG->hasDebugValues(); 807 808 // If this is the first BB, emit byval parameter dbg_value's. 809 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) { 810 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin(); 811 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd(); 812 for (; PDI != PDE; ++PDI) { 813 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap); 814 if (DbgMI) 815 BB->insert(InsertPos, DbgMI); 816 } 817 } 818 819 for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 820 SUnit *SU = Sequence[i]; 821 if (!SU) { 822 // Null SUnit* is a noop. 823 TII->insertNoop(*Emitter.getBlock(), InsertPos); 824 continue; 825 } 826 827 // For pre-regalloc scheduling, create instructions corresponding to the 828 // SDNode and any glued SDNodes and append them to the block. 829 if (!SU->getNode()) { 830 // Emit a copy. 831 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos); 832 continue; 833 } 834 835 SmallVector<SDNode *, 4> GluedNodes; 836 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) 837 GluedNodes.push_back(N); 838 while (!GluedNodes.empty()) { 839 SDNode *N = GluedNodes.back(); 840 Emitter.EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap); 841 // Remember the source order of the inserted instruction. 842 if (HasDbg) 843 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); 844 GluedNodes.pop_back(); 845 } 846 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, 847 VRBaseMap); 848 // Remember the source order of the inserted instruction. 849 if (HasDbg) 850 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, 851 Seen); 852 } 853 854 // Insert all the dbg_values which have not already been inserted in source 855 // order sequence. 856 if (HasDbg) { 857 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI(); 858 859 // Sort the source order instructions and use the order to insert debug 860 // values. Use stable_sort so that DBG_VALUEs are inserted in the same order 861 // regardless of the host's implementation fo std::sort. 862 std::stable_sort(Orders.begin(), Orders.end(), less_first()); 863 std::stable_sort(DAG->DbgBegin(), DAG->DbgEnd(), 864 [](const SDDbgValue *LHS, const SDDbgValue *RHS) { 865 return LHS->getOrder() < RHS->getOrder(); 866 }); 867 868 SDDbgInfo::DbgIterator DI = DAG->DbgBegin(); 869 SDDbgInfo::DbgIterator DE = DAG->DbgEnd(); 870 // Now emit the rest according to source order. 871 unsigned LastOrder = 0; 872 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) { 873 unsigned Order = Orders[i].first; 874 MachineInstr *MI = Orders[i].second; 875 // Insert all SDDbgValue's whose order(s) are before "Order". 876 if (!MI) 877 continue; 878 for (; DI != DE; ++DI) { 879 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) 880 break; 881 if ((*DI)->isInvalidated()) 882 continue; 883 884 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap); 885 if (DbgMI) { 886 if (!LastOrder) 887 // Insert to start of the BB (after PHIs). 888 BB->insert(BBBegin, DbgMI); 889 else { 890 // Insert at the instruction, which may be in a different 891 // block, if the block was split by a custom inserter. 892 MachineBasicBlock::iterator Pos = MI; 893 MI->getParent()->insert(Pos, DbgMI); 894 } 895 } 896 } 897 LastOrder = Order; 898 } 899 // Add trailing DbgValue's before the terminator. FIXME: May want to add 900 // some of them before one or more conditional branches? 901 SmallVector<MachineInstr*, 8> DbgMIs; 902 for (; DI != DE; ++DI) { 903 if ((*DI)->isInvalidated()) 904 continue; 905 assert((*DI)->getOrder() >= LastOrder && 906 "emitting DBG_VALUE out of order"); 907 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap)) 908 DbgMIs.push_back(DbgMI); 909 } 910 911 MachineBasicBlock *InsertBB = Emitter.getBlock(); 912 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator(); 913 InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end()); 914 915 SDDbgInfo::DbgLabelIterator DLI = DAG->DbgLabelBegin(); 916 SDDbgInfo::DbgLabelIterator DLE = DAG->DbgLabelEnd(); 917 // Now emit the rest according to source order. 918 LastOrder = 0; 919 for (const auto &InstrOrder : Orders) { 920 unsigned Order = InstrOrder.first; 921 MachineInstr *MI = InstrOrder.second; 922 if (!MI) 923 continue; 924 925 // Insert all SDDbgLabel's whose order(s) are before "Order". 926 for (; DLI != DLE && 927 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; 928 ++DLI) { 929 MachineInstr *DbgMI = Emitter.EmitDbgLabel(*DLI); 930 if (DbgMI) { 931 if (!LastOrder) 932 // Insert to start of the BB (after PHIs). 933 BB->insert(BBBegin, DbgMI); 934 else { 935 // Insert at the instruction, which may be in a different 936 // block, if the block was split by a custom inserter. 937 MachineBasicBlock::iterator Pos = MI; 938 MI->getParent()->insert(Pos, DbgMI); 939 } 940 } 941 } 942 if (DLI == DLE) 943 break; 944 945 LastOrder = Order; 946 } 947 } 948 949 InsertPos = Emitter.getInsertPos(); 950 return Emitter.getBlock(); 951 } 952 953 /// Return the basic block label. 954 std::string ScheduleDAGSDNodes::getDAGName() const { 955 return "sunit-dag." + BB->getFullName(); 956 } 957