1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing. 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // AArch64 Subtarget features. 21 // 22 23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 24 "Enable ARMv8 FP">; 25 26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 28 29 def FeatureSM4 : SubtargetFeature< 30 "sm4", "HasSM4", "true", 31 "Enable SM3 and SM4 support", [FeatureNEON]>; 32 33 def FeatureSHA2 : SubtargetFeature< 34 "sha2", "HasSHA2", "true", 35 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 36 37 def FeatureSHA3 : SubtargetFeature< 38 "sha3", "HasSHA3", "true", 39 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 40 41 def FeatureAES : SubtargetFeature< 42 "aes", "HasAES", "true", 43 "Enable AES support", [FeatureNEON]>; 44 45 // Crypto has been split up and any combination is now valid (see the 46 // crypto defintions above). Also, crypto is now context sensitive: 47 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 48 // Therefore, we rely on Clang, the user interacing tool, to pass on the 49 // appropriate crypto options. But here in the backend, crypto has very little 50 // meaning anymore. We kept the Crypto defintion here for backward 51 // compatibility, and now imply features SHA2 and AES, which was the 52 // "traditional" meaning of Crypto. 53 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 54 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 55 56 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 57 "Enable ARMv8 CRC-32 checksum instructions">; 58 59 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 60 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 61 62 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 63 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 64 65 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 66 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 67 68 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 69 "Enable ARMv8 PMUv3 Performance Monitors extension">; 70 71 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 72 "Full FP16", [FeatureFPARMv8]>; 73 74 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 75 "Enable Statistical Profiling extension">; 76 77 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 78 "Enable Scalable Vector Extension (SVE) instructions">; 79 80 /// Cyclone has register move instructions which are "free". 81 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 82 "Has zero-cycle register moves">; 83 84 /// Cyclone has instructions which zero registers for "free". 85 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 86 "Has zero-cycle zeroing instructions">; 87 88 /// ... but the floating-point version doesn't quite work in rare cases on older 89 /// CPUs. 90 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 91 "HasZeroCycleZeroingFPWorkaround", "true", 92 "The zero-cycle floating-point zeroing instruction has a bug">; 93 94 def FeatureStrictAlign : SubtargetFeature<"strict-align", 95 "StrictAlign", "true", 96 "Disallow all unaligned memory " 97 "access">; 98 99 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true", 100 "Reserve X18, making it unavailable " 101 "as a GPR">; 102 103 def FeatureReserveX20 : SubtargetFeature<"reserve-x20", "ReserveX20", "true", 104 "Reserve X20, making it unavailable " 105 "as a GPR">; 106 107 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 108 "Use alias analysis during codegen">; 109 110 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 111 "true", 112 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 113 114 def FeaturePredictableSelectIsExpensive : SubtargetFeature< 115 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 116 "Prefer likely predicted branches over selects">; 117 118 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 119 "CustomAsCheapAsMove", "true", 120 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">; 121 122 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 123 "ExynosAsCheapAsMove", "true", 124 "Use Exynos specific code in TargetInstrInfo::isAsCheapAsAMove()", 125 [FeatureCustomCheapAsMoveHandling]>; 126 127 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 128 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 129 130 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 131 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 132 133 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 134 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 135 136 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 137 "true", "STR of Q register with register offset is slow">; 138 139 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 140 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 141 "true", "Use alternative pattern for sextload convert to f32">; 142 143 def FeatureArithmeticBccFusion : SubtargetFeature< 144 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 145 "CPU fuses arithmetic+bcc operations">; 146 147 def FeatureArithmeticCbzFusion : SubtargetFeature< 148 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 149 "CPU fuses arithmetic + cbz/cbnz operations">; 150 151 def FeatureFuseAddress : SubtargetFeature< 152 "fuse-address", "HasFuseAddress", "true", 153 "CPU fuses address generation and memory operations">; 154 155 def FeatureFuseAES : SubtargetFeature< 156 "fuse-aes", "HasFuseAES", "true", 157 "CPU fuses AES crypto operations">; 158 159 def FeatureFuseCCSelect : SubtargetFeature< 160 "fuse-csel", "HasFuseCCSelect", "true", 161 "CPU fuses conditional select operations">; 162 163 def FeatureFuseLiterals : SubtargetFeature< 164 "fuse-literals", "HasFuseLiterals", "true", 165 "CPU fuses literal generation operations">; 166 167 def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 168 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 169 "Disable latency scheduling heuristic">; 170 171 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 172 "Enable support for RCPC extension">; 173 174 def FeatureUseRSqrt : SubtargetFeature< 175 "use-reciprocal-square-root", "UseRSqrt", "true", 176 "Use the reciprocal square root approximation">; 177 178 def FeatureDotProd : SubtargetFeature< 179 "dotprod", "HasDotProd", "true", 180 "Enable dot product support">; 181 182 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 183 "NegativeImmediates", "false", 184 "Convert immediates and instructions " 185 "to their negated or complemented " 186 "equivalent when the immediate does " 187 "not fit in the encoding.">; 188 189 def FeatureLSLFast : SubtargetFeature< 190 "lsl-fast", "HasLSLFast", "true", 191 "CPU has a fastpath logical shift of up to 3 places">; 192 193 def FeatureAggressiveFMA : 194 SubtargetFeature<"aggressive-fma", 195 "HasAggressiveFMA", 196 "true", 197 "Enable Aggressive FMA for floating-point.">; 198 199 //===----------------------------------------------------------------------===// 200 // Architectures. 201 // 202 203 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 204 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>; 205 206 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 207 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>; 208 209 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 210 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>; 211 212 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 213 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; 214 215 //===----------------------------------------------------------------------===// 216 // Register File Description 217 //===----------------------------------------------------------------------===// 218 219 include "AArch64RegisterInfo.td" 220 include "AArch64RegisterBanks.td" 221 include "AArch64CallingConvention.td" 222 223 //===----------------------------------------------------------------------===// 224 // Instruction Descriptions 225 //===----------------------------------------------------------------------===// 226 227 include "AArch64Schedule.td" 228 include "AArch64InstrInfo.td" 229 230 def AArch64InstrInfo : InstrInfo; 231 232 //===----------------------------------------------------------------------===// 233 // Named operands for MRS/MSR/TLBI/... 234 //===----------------------------------------------------------------------===// 235 236 include "AArch64SystemOperands.td" 237 238 //===----------------------------------------------------------------------===// 239 // AArch64 Processors supported. 240 // 241 include "AArch64SchedA53.td" 242 include "AArch64SchedA57.td" 243 include "AArch64SchedCyclone.td" 244 include "AArch64SchedFalkor.td" 245 include "AArch64SchedKryo.td" 246 include "AArch64SchedExynosM1.td" 247 include "AArch64SchedExynosM3.td" 248 include "AArch64SchedThunderX.td" 249 include "AArch64SchedThunderX2T99.td" 250 251 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 252 "Cortex-A35 ARM processors", [ 253 FeatureCRC, 254 FeatureCrypto, 255 FeatureFPARMv8, 256 FeatureNEON, 257 FeaturePerfMon 258 ]>; 259 260 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 261 "Cortex-A53 ARM processors", [ 262 FeatureBalanceFPOps, 263 FeatureCRC, 264 FeatureCrypto, 265 FeatureCustomCheapAsMoveHandling, 266 FeatureFPARMv8, 267 FeatureFuseAES, 268 FeatureNEON, 269 FeaturePerfMon, 270 FeaturePostRAScheduler, 271 FeatureUseAA 272 ]>; 273 274 def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 275 "Cortex-A55 ARM processors", [ 276 HasV8_2aOps, 277 FeatureCrypto, 278 FeatureFPARMv8, 279 FeatureFuseAES, 280 FeatureNEON, 281 FeatureFullFP16, 282 FeatureDotProd, 283 FeatureRCPC, 284 FeaturePerfMon 285 ]>; 286 287 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 288 "Cortex-A57 ARM processors", [ 289 FeatureBalanceFPOps, 290 FeatureCRC, 291 FeatureCrypto, 292 FeatureCustomCheapAsMoveHandling, 293 FeatureFPARMv8, 294 FeatureFuseAES, 295 FeatureFuseLiterals, 296 FeatureNEON, 297 FeaturePerfMon, 298 FeaturePostRAScheduler, 299 FeaturePredictableSelectIsExpensive 300 ]>; 301 302 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 303 "Cortex-A72 ARM processors", [ 304 FeatureCRC, 305 FeatureCrypto, 306 FeatureFPARMv8, 307 FeatureFuseAES, 308 FeatureNEON, 309 FeaturePerfMon 310 ]>; 311 312 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 313 "Cortex-A73 ARM processors", [ 314 FeatureCRC, 315 FeatureCrypto, 316 FeatureFPARMv8, 317 FeatureFuseAES, 318 FeatureNEON, 319 FeaturePerfMon 320 ]>; 321 322 def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 323 "Cortex-A75 ARM processors", [ 324 HasV8_2aOps, 325 FeatureCrypto, 326 FeatureFPARMv8, 327 FeatureFuseAES, 328 FeatureNEON, 329 FeatureFullFP16, 330 FeatureDotProd, 331 FeatureRCPC, 332 FeaturePerfMon 333 ]>; 334 335 // Note that cyclone does not fuse AES instructions, but newer apple chips do 336 // perform the fusion and cyclone is used by default when targetting apple OSes. 337 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", 338 "Cyclone", [ 339 FeatureAlternateSExtLoadCVTF32Pattern, 340 FeatureArithmeticBccFusion, 341 FeatureArithmeticCbzFusion, 342 FeatureCrypto, 343 FeatureDisableLatencySchedHeuristic, 344 FeatureFPARMv8, 345 FeatureFuseAES, 346 FeatureNEON, 347 FeaturePerfMon, 348 FeatureZCRegMove, 349 FeatureZCZeroing, 350 FeatureZCZeroingFPWorkaround 351 ]>; 352 353 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 354 "Samsung Exynos-M1 processors", 355 [FeatureSlowPaired128, 356 FeatureCRC, 357 FeatureCrypto, 358 FeatureExynosCheapAsMoveHandling, 359 FeatureFPARMv8, 360 FeatureFuseAES, 361 FeatureNEON, 362 FeaturePerfMon, 363 FeaturePostRAScheduler, 364 FeatureSlowMisaligned128Store, 365 FeatureUseRSqrt, 366 FeatureZCZeroing]>; 367 368 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1", 369 "Samsung Exynos-M2 processors", 370 [FeatureSlowPaired128, 371 FeatureCRC, 372 FeatureCrypto, 373 FeatureExynosCheapAsMoveHandling, 374 FeatureFPARMv8, 375 FeatureFuseAES, 376 FeatureNEON, 377 FeaturePerfMon, 378 FeaturePostRAScheduler, 379 FeatureSlowMisaligned128Store, 380 FeatureZCZeroing]>; 381 382 def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 383 "Samsung Exynos-M3 processors", 384 [FeatureCRC, 385 FeatureCrypto, 386 FeatureExynosCheapAsMoveHandling, 387 FeatureFPARMv8, 388 FeatureFuseAddress, 389 FeatureFuseAES, 390 FeatureFuseCCSelect, 391 FeatureFuseLiterals, 392 FeatureLSLFast, 393 FeatureNEON, 394 FeaturePerfMon, 395 FeaturePostRAScheduler, 396 FeaturePredictableSelectIsExpensive, 397 FeatureZCZeroing]>; 398 399 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 400 "Qualcomm Kryo processors", [ 401 FeatureCRC, 402 FeatureCrypto, 403 FeatureCustomCheapAsMoveHandling, 404 FeatureFPARMv8, 405 FeatureNEON, 406 FeaturePerfMon, 407 FeaturePostRAScheduler, 408 FeaturePredictableSelectIsExpensive, 409 FeatureZCZeroing, 410 FeatureLSLFast 411 ]>; 412 413 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 414 "Qualcomm Falkor processors", [ 415 FeatureCRC, 416 FeatureCrypto, 417 FeatureCustomCheapAsMoveHandling, 418 FeatureFPARMv8, 419 FeatureNEON, 420 FeaturePerfMon, 421 FeaturePostRAScheduler, 422 FeaturePredictableSelectIsExpensive, 423 FeatureRDM, 424 FeatureZCZeroing, 425 FeatureLSLFast, 426 FeatureSlowSTRQro 427 ]>; 428 429 def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 430 "Qualcomm Saphira processors", [ 431 FeatureCrypto, 432 FeatureCustomCheapAsMoveHandling, 433 FeatureFPARMv8, 434 FeatureNEON, 435 FeatureSPE, 436 FeaturePerfMon, 437 FeaturePostRAScheduler, 438 FeaturePredictableSelectIsExpensive, 439 FeatureZCZeroing, 440 FeatureLSLFast, 441 HasV8_3aOps]>; 442 443 def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 444 "ThunderX2T99", 445 "Cavium ThunderX2 processors", [ 446 FeatureAggressiveFMA, 447 FeatureCRC, 448 FeatureCrypto, 449 FeatureFPARMv8, 450 FeatureArithmeticBccFusion, 451 FeatureNEON, 452 FeaturePostRAScheduler, 453 FeaturePredictableSelectIsExpensive, 454 FeatureLSE, 455 HasV8_1aOps]>; 456 457 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 458 "Cavium ThunderX processors", [ 459 FeatureCRC, 460 FeatureCrypto, 461 FeatureFPARMv8, 462 FeaturePerfMon, 463 FeaturePostRAScheduler, 464 FeaturePredictableSelectIsExpensive, 465 FeatureNEON]>; 466 467 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 468 "ThunderXT88", 469 "Cavium ThunderX processors", [ 470 FeatureCRC, 471 FeatureCrypto, 472 FeatureFPARMv8, 473 FeaturePerfMon, 474 FeaturePostRAScheduler, 475 FeaturePredictableSelectIsExpensive, 476 FeatureNEON]>; 477 478 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 479 "ThunderXT81", 480 "Cavium ThunderX processors", [ 481 FeatureCRC, 482 FeatureCrypto, 483 FeatureFPARMv8, 484 FeaturePerfMon, 485 FeaturePostRAScheduler, 486 FeaturePredictableSelectIsExpensive, 487 FeatureNEON]>; 488 489 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 490 "ThunderXT83", 491 "Cavium ThunderX processors", [ 492 FeatureCRC, 493 FeatureCrypto, 494 FeatureFPARMv8, 495 FeaturePerfMon, 496 FeaturePostRAScheduler, 497 FeaturePredictableSelectIsExpensive, 498 FeatureNEON]>; 499 500 def : ProcessorModel<"generic", NoSchedModel, [ 501 FeatureFPARMv8, 502 FeatureFuseAES, 503 FeatureNEON, 504 FeaturePerfMon, 505 FeaturePostRAScheduler 506 ]>; 507 508 // FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53. 509 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 510 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 511 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; 512 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 513 // FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57. 514 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 515 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 516 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 517 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; 518 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; 519 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; 520 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 521 def : ProcessorModel<"exynos-m4", ExynosM3Model, [ProcExynosM3]>; 522 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 523 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 524 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 525 // Cavium ThunderX/ThunderX T8X Processors 526 def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 527 def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 528 def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 529 def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 530 // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 531 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 532 533 //===----------------------------------------------------------------------===// 534 // Assembly parser 535 //===----------------------------------------------------------------------===// 536 537 def GenericAsmParserVariant : AsmParserVariant { 538 int Variant = 0; 539 string Name = "generic"; 540 string BreakCharacters = "."; 541 string TokenizingCharacters = "[]*!/"; 542 } 543 544 def AppleAsmParserVariant : AsmParserVariant { 545 int Variant = 1; 546 string Name = "apple-neon"; 547 string BreakCharacters = "."; 548 string TokenizingCharacters = "[]*!/"; 549 } 550 551 //===----------------------------------------------------------------------===// 552 // Assembly printer 553 //===----------------------------------------------------------------------===// 554 // AArch64 Uses the MC printer for asm output, so make sure the TableGen 555 // AsmWriter bits get associated with the correct class. 556 def GenericAsmWriter : AsmWriter { 557 string AsmWriterClassName = "InstPrinter"; 558 int PassSubtarget = 1; 559 int Variant = 0; 560 bit isMCAsmWriter = 1; 561 } 562 563 def AppleAsmWriter : AsmWriter { 564 let AsmWriterClassName = "AppleInstPrinter"; 565 int PassSubtarget = 1; 566 int Variant = 1; 567 int isMCAsmWriter = 1; 568 } 569 570 //===----------------------------------------------------------------------===// 571 // Target Declaration 572 //===----------------------------------------------------------------------===// 573 574 def AArch64 : Target { 575 let InstructionSet = AArch64InstrInfo; 576 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 577 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 578 let AllowRegisterRenaming = 1; 579 } 580
