1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // AArch64 Instruction definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // ARM Instruction Predicate Definitions. 16 // 17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 19 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 20 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 21 def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 22 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 23 def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 24 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 25 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 26 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; 27 def HasNEON : Predicate<"Subtarget->hasNEON()">, 28 AssemblerPredicate<"FeatureNEON", "neon">; 29 def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 30 AssemblerPredicate<"FeatureCrypto", "crypto">; 31 def HasSM4 : Predicate<"Subtarget->hasSM4()">, 32 AssemblerPredicate<"FeatureSM4", "sm4">; 33 def HasSHA3 : Predicate<"Subtarget->hasSHA3()">, 34 AssemblerPredicate<"FeatureSHA3", "sha3">; 35 def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 36 AssemblerPredicate<"FeatureSHA2", "sha2">; 37 def HasAES : Predicate<"Subtarget->hasAES()">, 38 AssemblerPredicate<"FeatureAES", "aes">; 39 def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 40 AssemblerPredicate<"FeatureDotProd", "dotprod">; 41 def HasCRC : Predicate<"Subtarget->hasCRC()">, 42 AssemblerPredicate<"FeatureCRC", "crc">; 43 def HasLSE : Predicate<"Subtarget->hasLSE()">, 44 AssemblerPredicate<"FeatureLSE", "lse">; 45 def HasRAS : Predicate<"Subtarget->hasRAS()">, 46 AssemblerPredicate<"FeatureRAS", "ras">; 47 def HasRDM : Predicate<"Subtarget->hasRDM()">, 48 AssemblerPredicate<"FeatureRDM", "rdm">; 49 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">; 50 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 51 AssemblerPredicate<"FeatureFullFP16", "fullfp16">; 52 def HasSPE : Predicate<"Subtarget->hasSPE()">, 53 AssemblerPredicate<"FeatureSPE", "spe">; 54 def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, 55 AssemblerPredicate<"FeatureFuseAES", 56 "fuse-aes">; 57 def HasSVE : Predicate<"Subtarget->hasSVE()">, 58 AssemblerPredicate<"FeatureSVE", "sve">; 59 def HasRCPC : Predicate<"Subtarget->hasRCPC()">, 60 AssemblerPredicate<"FeatureRCPC", "rcpc">; 61 62 def IsLE : Predicate<"Subtarget->isLittleEndian()">; 63 def IsBE : Predicate<"!Subtarget->isLittleEndian()">; 64 def UseAlternateSExtLoadCVTF32 65 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">; 66 67 def UseNegativeImmediates 68 : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", 69 "NegativeImmediates">; 70 71 72 //===----------------------------------------------------------------------===// 73 // AArch64-specific DAG Nodes. 74 // 75 76 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS 77 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, SDTCisVT<1, i32>]>; 81 82 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS 83 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3, 84 [SDTCisSameAs<0, 1>, 85 SDTCisSameAs<0, 2>, 86 SDTCisInt<0>, 87 SDTCisVT<3, i32>]>; 88 89 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS 90 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 91 [SDTCisSameAs<0, 2>, 92 SDTCisSameAs<0, 3>, 93 SDTCisInt<0>, 94 SDTCisVT<1, i32>, 95 SDTCisVT<4, i32>]>; 96 97 def SDT_AArch64Brcond : SDTypeProfile<0, 3, 98 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, 99 SDTCisVT<2, i32>]>; 100 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>; 101 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, 102 SDTCisVT<2, OtherVT>]>; 103 104 105 def SDT_AArch64CSel : SDTypeProfile<1, 4, 106 [SDTCisSameAs<0, 1>, 107 SDTCisSameAs<0, 2>, 108 SDTCisInt<3>, 109 SDTCisVT<4, i32>]>; 110 def SDT_AArch64CCMP : SDTypeProfile<1, 5, 111 [SDTCisVT<0, i32>, 112 SDTCisInt<1>, 113 SDTCisSameAs<1, 2>, 114 SDTCisInt<3>, 115 SDTCisInt<4>, 116 SDTCisVT<5, i32>]>; 117 def SDT_AArch64FCCMP : SDTypeProfile<1, 5, 118 [SDTCisVT<0, i32>, 119 SDTCisFP<1>, 120 SDTCisSameAs<1, 2>, 121 SDTCisInt<3>, 122 SDTCisInt<4>, 123 SDTCisVT<5, i32>]>; 124 def SDT_AArch64FCmp : SDTypeProfile<0, 2, 125 [SDTCisFP<0>, 126 SDTCisSameAs<0, 1>]>; 127 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 128 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>; 129 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>, 130 SDTCisSameAs<0, 1>, 131 SDTCisSameAs<0, 2>]>; 132 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 133 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>; 134 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 135 SDTCisInt<2>, SDTCisInt<3>]>; 136 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 137 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 138 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 139 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>; 140 141 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 142 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>; 143 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>; 144 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 145 SDTCisSameAs<0,2>]>; 146 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 147 SDTCisSameAs<0,2>, 148 SDTCisSameAs<0,3>]>; 149 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; 150 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; 151 152 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>; 153 154 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, 155 SDTCisPtrTy<1>]>; 156 157 // Generates the general dynamic sequences, i.e. 158 // adrp x0, :tlsdesc:var 159 // ldr x1, [x0, #:tlsdesc_lo12:var] 160 // add x0, x0, #:tlsdesc_lo12:var 161 // .tlsdesccall var 162 // blr x1 163 164 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here) 165 // number of operands (the variable) 166 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1, 167 [SDTCisPtrTy<0>]>; 168 169 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4, 170 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, 171 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, 172 SDTCisSameAs<1, 4>]>; 173 174 175 // Node definitions. 176 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>; 177 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>; 178 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>; 179 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", 180 SDCallSeqStart<[ SDTCisVT<0, i32>, 181 SDTCisVT<1, i32> ]>, 182 [SDNPHasChain, SDNPOutGlue]>; 183 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", 184 SDCallSeqEnd<[ SDTCisVT<0, i32>, 185 SDTCisVT<1, i32> ]>, 186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 187 def AArch64call : SDNode<"AArch64ISD::CALL", 188 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 189 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 190 SDNPVariadic]>; 191 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond, 192 [SDNPHasChain]>; 193 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz, 194 [SDNPHasChain]>; 195 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz, 196 [SDNPHasChain]>; 197 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz, 198 [SDNPHasChain]>; 199 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz, 200 [SDNPHasChain]>; 201 202 203 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>; 204 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>; 205 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>; 206 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>; 207 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone, 208 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 209 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >; 210 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>; 211 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut, 212 [SDNPCommutative]>; 213 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>; 214 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut, 215 [SDNPCommutative]>; 216 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>; 217 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>; 218 219 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>; 220 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>; 221 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>; 222 223 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 224 225 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>; 226 227 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>; 228 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>; 229 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>; 230 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>; 231 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>; 232 233 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>; 234 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>; 235 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>; 236 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>; 237 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>; 238 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>; 239 240 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>; 241 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>; 242 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>; 243 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>; 244 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>; 245 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>; 246 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>; 247 248 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>; 249 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>; 250 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>; 251 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>; 252 253 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>; 254 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>; 255 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>; 256 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>; 257 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>; 258 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>; 259 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>; 260 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>; 261 262 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>; 263 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>; 264 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>; 265 266 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>; 267 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>; 268 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>; 269 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>; 270 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>; 271 272 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>; 273 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>; 274 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>; 275 276 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>; 277 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>; 278 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>; 279 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>; 280 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>; 281 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS), 282 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>; 283 284 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>; 285 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>; 286 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>; 287 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>; 288 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>; 289 290 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>; 291 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>; 292 293 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>; 294 295 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET, 296 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 297 298 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH, 299 [SDNPHasChain, SDNPSideEffect]>; 300 301 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>; 302 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>; 303 304 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ", 305 SDT_AArch64TLSDescCallSeq, 306 [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 307 SDNPVariadic]>; 308 309 310 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge", 311 SDT_AArch64WrapperLarge>; 312 313 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>; 314 315 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 316 SDTCisSameAs<1, 2>]>; 317 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>; 318 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>; 319 320 def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>; 321 def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>; 322 def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>; 323 def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>; 324 325 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>; 326 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>; 327 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>; 328 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; 329 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>; 330 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>; 331 332 //===----------------------------------------------------------------------===// 333 334 //===----------------------------------------------------------------------===// 335 336 // AArch64 Instruction Predicate Definitions. 337 // We could compute these on a per-module basis but doing so requires accessing 338 // the Function object through the <Target>Subtarget and objections were raised 339 // to that (see post-commit review comments for r301750). 340 let RecomputePerFunction = 1 in { 341 def ForCodeSize : Predicate<"MF->getFunction().optForSize()">; 342 def NotForCodeSize : Predicate<"!MF->getFunction().optForSize()">; 343 // Avoid generating STRQro if it is slow, unless we're optimizing for code size. 344 def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize()">; 345 } 346 347 include "AArch64InstrFormats.td" 348 include "SVEInstrFormats.td" 349 350 //===----------------------------------------------------------------------===// 351 352 //===----------------------------------------------------------------------===// 353 // Miscellaneous instructions. 354 //===----------------------------------------------------------------------===// 355 356 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in { 357 // We set Sched to empty list because we expect these instructions to simply get 358 // removed in most cases. 359 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 360 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>, 361 Sched<[]>; 362 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>, 364 Sched<[]>; 365 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 366 367 let isReMaterializable = 1, isCodeGenOnly = 1 in { 368 // FIXME: The following pseudo instructions are only needed because remat 369 // cannot handle multiple instructions. When that changes, they can be 370 // removed, along with the AArch64Wrapper node. 371 372 let AddedComplexity = 10 in 373 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), 374 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, 375 Sched<[WriteLDAdr]>; 376 377 // The MOVaddr instruction should match only when the add is not folded 378 // into a load or store address. 379 def MOVaddr 380 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 381 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), 382 tglobaladdr:$low))]>, 383 Sched<[WriteAdrAdr]>; 384 def MOVaddrJT 385 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 386 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), 387 tjumptable:$low))]>, 388 Sched<[WriteAdrAdr]>; 389 def MOVaddrCP 390 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 391 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), 392 tconstpool:$low))]>, 393 Sched<[WriteAdrAdr]>; 394 def MOVaddrBA 395 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 396 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), 397 tblockaddress:$low))]>, 398 Sched<[WriteAdrAdr]>; 399 def MOVaddrTLS 400 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 401 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), 402 tglobaltlsaddr:$low))]>, 403 Sched<[WriteAdrAdr]>; 404 def MOVaddrEXT 405 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 406 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), 407 texternalsym:$low))]>, 408 Sched<[WriteAdrAdr]>; 409 // Normally AArch64addlow either gets folded into a following ldr/str, 410 // or together with an adrp into MOVaddr above. For cases with TLS, it 411 // might appear without either of them, so allow lowering it into a plain 412 // add. 413 def ADDlowTLS 414 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low), 415 [(set GPR64:$dst, (AArch64addlow GPR64:$src, 416 tglobaltlsaddr:$low))]>, 417 Sched<[WriteAdr]>; 418 419 } // isReMaterializable, isCodeGenOnly 420 421 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr), 422 (LOADgot tglobaltlsaddr:$addr)>; 423 424 def : Pat<(AArch64LOADgot texternalsym:$addr), 425 (LOADgot texternalsym:$addr)>; 426 427 def : Pat<(AArch64LOADgot tconstpool:$addr), 428 (LOADgot tconstpool:$addr)>; 429 430 //===----------------------------------------------------------------------===// 431 // System instructions. 432 //===----------------------------------------------------------------------===// 433 434 def HINT : HintI<"hint">; 435 def : InstAlias<"nop", (HINT 0b000)>; 436 def : InstAlias<"yield",(HINT 0b001)>; 437 def : InstAlias<"wfe", (HINT 0b010)>; 438 def : InstAlias<"wfi", (HINT 0b011)>; 439 def : InstAlias<"sev", (HINT 0b100)>; 440 def : InstAlias<"sevl", (HINT 0b101)>; 441 def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; 442 def : InstAlias<"csdb", (HINT 20)>; 443 444 // v8.2a Statistical Profiling extension 445 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; 446 447 // As far as LLVM is concerned this writes to the system's exclusive monitors. 448 let mayLoad = 1, mayStore = 1 in 449 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">; 450 451 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot 452 // model patterns with sufficiently fine granularity. 453 let mayLoad = ?, mayStore = ? in { 454 def DMB : CRmSystemI<barrier_op, 0b101, "dmb", 455 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>; 456 457 def DSB : CRmSystemI<barrier_op, 0b100, "dsb", 458 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>; 459 460 def ISB : CRmSystemI<barrier_op, 0b110, "isb", 461 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>; 462 463 def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> { 464 let CRm = 0b0010; 465 let Inst{12} = 0; 466 let Predicates = [HasV8_4a]; 467 } 468 } 469 470 // ARMv8.2 Dot Product 471 let Predicates = [HasDotProd] in { 472 defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>; 473 defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>; 474 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>; 475 defm UDOTlane : SIMDThreeSameVectorDotIndex<1, "udot", int_aarch64_neon_udot>; 476 } 477 478 // Armv8.2-A Crypto extensions 479 let Predicates = [HasSHA3] in { 480 def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">; 481 def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">; 482 def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">; 483 def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">; 484 def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">; 485 def EOR3 : CryptoRRRR_16B<0b00, "eor3">; 486 def BCAX : CryptoRRRR_16B<0b01, "bcax">; 487 def XAR : CryptoRRRi6<"xar">; 488 } // HasSHA3 489 490 let Predicates = [HasSM4] in { 491 def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">; 492 def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">; 493 def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">; 494 def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">; 495 def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">; 496 def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">; 497 def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">; 498 def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">; 499 def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">; 500 } // HasSM4 501 502 let Predicates = [HasRCPC] in { 503 // v8.3 Release Consistent Processor Consistent support, optional in v8.2. 504 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>; 505 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>; 506 def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>; 507 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>; 508 } 509 510 // v8.3a complex add and multiply-accumulate. No predicate here, that is done 511 // inside the multiclass as the FP16 versions need different predicates. 512 defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop, 513 "fcmla", null_frag>; 514 defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd, 515 "fcadd", null_frag>; 516 defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla", 517 null_frag>; 518 519 // v8.3a Pointer Authentication 520 // These instructions inhabit part of the hint space and so can be used for 521 // armv8 targets 522 let Uses = [LR], Defs = [LR] in { 523 def PACIAZ : SystemNoOperands<0b000, "paciaz">; 524 def PACIBZ : SystemNoOperands<0b010, "pacibz">; 525 def AUTIAZ : SystemNoOperands<0b100, "autiaz">; 526 def AUTIBZ : SystemNoOperands<0b110, "autibz">; 527 } 528 let Uses = [LR, SP], Defs = [LR] in { 529 def PACIASP : SystemNoOperands<0b001, "paciasp">; 530 def PACIBSP : SystemNoOperands<0b011, "pacibsp">; 531 def AUTIASP : SystemNoOperands<0b101, "autiasp">; 532 def AUTIBSP : SystemNoOperands<0b111, "autibsp">; 533 } 534 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in { 535 def PACIA1716 : SystemNoOperands<0b000, "pacia1716">; 536 def PACIB1716 : SystemNoOperands<0b010, "pacib1716">; 537 def AUTIA1716 : SystemNoOperands<0b100, "autia1716">; 538 def AUTIB1716 : SystemNoOperands<0b110, "autib1716">; 539 } 540 541 let Uses = [LR], Defs = [LR], CRm = 0b0000 in { 542 def XPACLRI : SystemNoOperands<0b111, "xpaclri">; 543 } 544 545 // These pointer authentication isntructions require armv8.3a 546 let Predicates = [HasV8_3a] in { 547 multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> { 548 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>; 549 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>; 550 def DA : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>; 551 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>; 552 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>; 553 def DZA : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>; 554 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>; 555 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb")>; 556 } 557 558 defm PAC : SignAuth<0b000, 0b010, "pac">; 559 defm AUT : SignAuth<0b001, 0b011, "aut">; 560 561 def XPACI : SignAuthZero<0b100, 0b00, "xpaci">; 562 def XPACD : SignAuthZero<0b100, 0b01, "xpacd">; 563 def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>; 564 565 // Combined Instructions 566 def BRAA : AuthBranchTwoOperands<0, 0, "braa">; 567 def BRAB : AuthBranchTwoOperands<0, 1, "brab">; 568 def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">; 569 def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">; 570 571 def BRAAZ : AuthOneOperand<0b000, 0, "braaz">; 572 def BRABZ : AuthOneOperand<0b000, 1, "brabz">; 573 def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">; 574 def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">; 575 576 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 577 def RETAA : AuthReturn<0b010, 0, "retaa">; 578 def RETAB : AuthReturn<0b010, 1, "retab">; 579 def ERETAA : AuthReturn<0b100, 0, "eretaa">; 580 def ERETAB : AuthReturn<0b100, 1, "eretab">; 581 } 582 583 defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; 584 defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; 585 586 // v8.3a floating point conversion for javascript 587 let Predicates = [HasV8_3a, HasFPARMv8] in 588 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, 589 "fjcvtzs", []> { 590 let Inst{31} = 0; 591 } 592 593 } // HasV8_3a 594 595 // v8.4 Flag manipulation instructions 596 let Predicates = [HasV8_4a] in { 597 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> { 598 let Inst{20-5} = 0b0000001000000000; 599 } 600 def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">; 601 def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">; 602 def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif", 603 "{\t$Rn, $imm, $mask}">; 604 } // HasV8_4a 605 606 def : InstAlias<"clrex", (CLREX 0xf)>; 607 def : InstAlias<"isb", (ISB 0xf)>; 608 609 def MRS : MRSI; 610 def MSR : MSRI; 611 def MSRpstateImm1 : MSRpstateImm0_1; 612 def MSRpstateImm4 : MSRpstateImm0_15; 613 614 // The thread pointer (on Linux, at least, where this has been implemented) is 615 // TPIDR_EL0. 616 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins), 617 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>; 618 619 // The cycle counter PMC register is PMCCNTR_EL0. 620 let Predicates = [HasPerfMon] in 621 def : Pat<(readcyclecounter), (MRS 0xdce8)>; 622 623 // FPCR register 624 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>; 625 626 // Generic system instructions 627 def SYSxt : SystemXtI<0, "sys">; 628 def SYSLxt : SystemLXtI<1, "sysl">; 629 630 def : InstAlias<"sys $op1, $Cn, $Cm, $op2", 631 (SYSxt imm0_7:$op1, sys_cr_op:$Cn, 632 sys_cr_op:$Cm, imm0_7:$op2, XZR)>; 633 634 //===----------------------------------------------------------------------===// 635 // Move immediate instructions. 636 //===----------------------------------------------------------------------===// 637 638 defm MOVK : InsertImmediate<0b11, "movk">; 639 defm MOVN : MoveImmediate<0b00, "movn">; 640 641 let PostEncoderMethod = "fixMOVZ" in 642 defm MOVZ : MoveImmediate<0b10, "movz">; 643 644 // First group of aliases covers an implicit "lsl #0". 645 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>; 646 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>; 647 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>; 648 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>; 649 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>; 650 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>; 651 652 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. 653 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>; 654 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>; 655 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>; 656 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>; 657 658 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>; 659 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>; 660 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>; 661 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>; 662 663 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>; 664 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>; 665 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>; 666 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>; 667 668 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>; 669 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>; 670 671 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>; 672 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>; 673 674 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>; 675 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>; 676 677 // Final group of aliases covers true "mov $Rd, $imm" cases. 678 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR, 679 int width, int shift> { 680 def _asmoperand : AsmOperandClass { 681 let Name = basename # width # "_lsl" # shift # "MovAlias"; 682 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", " 683 # shift # ">"; 684 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">"; 685 } 686 687 def _movimm : Operand<i32> { 688 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand"); 689 } 690 691 def : InstAlias<"mov $Rd, $imm", 692 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>; 693 } 694 695 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; 696 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; 697 698 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; 699 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; 700 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; 701 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; 702 703 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>; 704 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>; 705 706 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>; 707 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>; 708 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>; 709 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>; 710 711 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1, 712 isAsCheapAsAMove = 1 in { 713 // FIXME: The following pseudo instructions are only needed because remat 714 // cannot handle multiple instructions. When that changes, we can select 715 // directly to the real instructions and get rid of these pseudos. 716 717 def MOVi32imm 718 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src), 719 [(set GPR32:$dst, imm:$src)]>, 720 Sched<[WriteImm]>; 721 def MOVi64imm 722 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src), 723 [(set GPR64:$dst, imm:$src)]>, 724 Sched<[WriteImm]>; 725 } // isReMaterializable, isCodeGenOnly 726 727 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the 728 // eventual expansion code fewer bits to worry about getting right. Marshalling 729 // the types is a little tricky though: 730 def i64imm_32bit : ImmLeaf<i64, [{ 731 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); 732 }]>; 733 734 def s64imm_32bit : ImmLeaf<i64, [{ 735 int64_t Imm64 = static_cast<int64_t>(Imm); 736 return Imm64 >= std::numeric_limits<int32_t>::min() && 737 Imm64 <= std::numeric_limits<int32_t>::max(); 738 }]>; 739 740 def trunc_imm : SDNodeXForm<imm, [{ 741 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32); 742 }]>; 743 744 def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">, 745 GISDNodeXFormEquiv<trunc_imm>; 746 747 def : Pat<(i64 i64imm_32bit:$src), 748 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; 749 750 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). 751 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ 752 return CurDAG->getTargetConstant( 753 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); 754 }]>; 755 756 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ 757 return CurDAG->getTargetConstant( 758 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); 759 }]>; 760 761 762 def : Pat<(f32 fpimm:$in), 763 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>; 764 def : Pat<(f64 fpimm:$in), 765 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>; 766 767 768 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK 769 // sequences. 770 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2, 771 tglobaladdr:$g1, tglobaladdr:$g0), 772 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0), 773 tglobaladdr:$g1, 16), 774 tglobaladdr:$g2, 32), 775 tglobaladdr:$g3, 48)>; 776 777 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2, 778 tblockaddress:$g1, tblockaddress:$g0), 779 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0), 780 tblockaddress:$g1, 16), 781 tblockaddress:$g2, 32), 782 tblockaddress:$g3, 48)>; 783 784 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2, 785 tconstpool:$g1, tconstpool:$g0), 786 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0), 787 tconstpool:$g1, 16), 788 tconstpool:$g2, 32), 789 tconstpool:$g3, 48)>; 790 791 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2, 792 tjumptable:$g1, tjumptable:$g0), 793 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0), 794 tjumptable:$g1, 16), 795 tjumptable:$g2, 32), 796 tjumptable:$g3, 48)>; 797 798 799 //===----------------------------------------------------------------------===// 800 // Arithmetic instructions. 801 //===----------------------------------------------------------------------===// 802 803 // Add/subtract with carry. 804 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>; 805 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>; 806 807 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>; 808 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>; 809 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>; 810 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>; 811 812 // Add/subtract 813 defm ADD : AddSub<0, "add", "sub", add>; 814 defm SUB : AddSub<1, "sub", "add">; 815 816 def : InstAlias<"mov $dst, $src", 817 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>; 818 def : InstAlias<"mov $dst, $src", 819 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>; 820 def : InstAlias<"mov $dst, $src", 821 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>; 822 def : InstAlias<"mov $dst, $src", 823 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>; 824 825 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">; 826 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">; 827 828 // Use SUBS instead of SUB to enable CSE between SUBS and SUB. 829 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm), 830 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>; 831 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm), 832 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>; 833 def : Pat<(sub GPR32:$Rn, GPR32:$Rm), 834 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>; 835 def : Pat<(sub GPR64:$Rn, GPR64:$Rm), 836 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>; 837 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm), 838 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>; 839 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm), 840 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>; 841 let AddedComplexity = 1 in { 842 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3), 843 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>; 844 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3), 845 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>; 846 } 847 848 // Because of the immediate format for add/sub-imm instructions, the 849 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 850 // These patterns capture that transformation. 851 let AddedComplexity = 1 in { 852 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 853 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 854 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 855 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 856 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 857 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 858 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 859 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 860 } 861 862 // Because of the immediate format for add/sub-imm instructions, the 863 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 864 // These patterns capture that transformation. 865 let AddedComplexity = 1 in { 866 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 867 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 868 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 869 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 870 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 871 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 872 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 873 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 874 } 875 876 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 877 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 878 def : InstAlias<"neg $dst, $src$shift", 879 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 880 def : InstAlias<"neg $dst, $src$shift", 881 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 882 883 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 884 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 885 def : InstAlias<"negs $dst, $src$shift", 886 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 887 def : InstAlias<"negs $dst, $src$shift", 888 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 889 890 891 // Unsigned/Signed divide 892 defm UDIV : Div<0, "udiv", udiv>; 893 defm SDIV : Div<1, "sdiv", sdiv>; 894 895 def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>; 896 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>; 897 def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>; 898 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>; 899 900 // Variable shift 901 defm ASRV : Shift<0b10, "asr", sra>; 902 defm LSLV : Shift<0b00, "lsl", shl>; 903 defm LSRV : Shift<0b01, "lsr", srl>; 904 defm RORV : Shift<0b11, "ror", rotr>; 905 906 def : ShiftAlias<"asrv", ASRVWr, GPR32>; 907 def : ShiftAlias<"asrv", ASRVXr, GPR64>; 908 def : ShiftAlias<"lslv", LSLVWr, GPR32>; 909 def : ShiftAlias<"lslv", LSLVXr, GPR64>; 910 def : ShiftAlias<"lsrv", LSRVWr, GPR32>; 911 def : ShiftAlias<"lsrv", LSRVXr, GPR64>; 912 def : ShiftAlias<"rorv", RORVWr, GPR32>; 913 def : ShiftAlias<"rorv", RORVXr, GPR64>; 914 915 // Multiply-add 916 let AddedComplexity = 5 in { 917 defm MADD : MulAccum<0, "madd", add>; 918 defm MSUB : MulAccum<1, "msub", sub>; 919 920 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)), 921 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 922 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)), 923 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 924 925 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))), 926 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 927 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))), 928 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 929 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)), 930 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 931 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)), 932 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 933 } // AddedComplexity = 5 934 935 let AddedComplexity = 5 in { 936 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>; 937 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>; 938 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>; 939 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>; 940 941 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))), 942 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 943 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))), 944 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 945 946 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))), 947 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 948 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))), 949 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 950 951 def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))), 952 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 953 def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))), 954 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 955 def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))), 956 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 957 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 958 959 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 960 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 961 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 962 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 963 def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))), 964 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 965 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 966 967 def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)), 968 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 969 def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)), 970 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 971 def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)), 972 GPR64:$Ra)), 973 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 974 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 975 976 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 977 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 978 def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 979 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 980 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32), 981 (s64imm_32bit:$C)))), 982 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 983 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 984 } // AddedComplexity = 5 985 986 def : MulAccumWAlias<"mul", MADDWrrr>; 987 def : MulAccumXAlias<"mul", MADDXrrr>; 988 def : MulAccumWAlias<"mneg", MSUBWrrr>; 989 def : MulAccumXAlias<"mneg", MSUBXrrr>; 990 def : WideMulAccumAlias<"smull", SMADDLrrr>; 991 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>; 992 def : WideMulAccumAlias<"umull", UMADDLrrr>; 993 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>; 994 995 // Multiply-high 996 def SMULHrr : MulHi<0b010, "smulh", mulhs>; 997 def UMULHrr : MulHi<0b110, "umulh", mulhu>; 998 999 // CRC32 1000 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">; 1001 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">; 1002 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">; 1003 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">; 1004 1005 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">; 1006 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">; 1007 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">; 1008 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">; 1009 1010 // v8.1 atomic CAS 1011 defm CAS : CompareAndSwap<0, 0, "">; 1012 defm CASA : CompareAndSwap<1, 0, "a">; 1013 defm CASL : CompareAndSwap<0, 1, "l">; 1014 defm CASAL : CompareAndSwap<1, 1, "al">; 1015 1016 // v8.1 atomic CASP 1017 defm CASP : CompareAndSwapPair<0, 0, "">; 1018 defm CASPA : CompareAndSwapPair<1, 0, "a">; 1019 defm CASPL : CompareAndSwapPair<0, 1, "l">; 1020 defm CASPAL : CompareAndSwapPair<1, 1, "al">; 1021 1022 // v8.1 atomic SWP 1023 defm SWP : Swap<0, 0, "">; 1024 defm SWPA : Swap<1, 0, "a">; 1025 defm SWPL : Swap<0, 1, "l">; 1026 defm SWPAL : Swap<1, 1, "al">; 1027 1028 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register) 1029 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">; 1030 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">; 1031 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">; 1032 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">; 1033 1034 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">; 1035 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">; 1036 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">; 1037 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">; 1038 1039 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">; 1040 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">; 1041 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">; 1042 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">; 1043 1044 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">; 1045 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">; 1046 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">; 1047 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">; 1048 1049 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">; 1050 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">; 1051 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">; 1052 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">; 1053 1054 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">; 1055 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">; 1056 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">; 1057 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">; 1058 1059 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">; 1060 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">; 1061 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">; 1062 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">; 1063 1064 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">; 1065 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">; 1066 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">; 1067 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">; 1068 1069 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR" 1070 defm : STOPregister<"stadd","LDADD">; // STADDx 1071 defm : STOPregister<"stclr","LDCLR">; // STCLRx 1072 defm : STOPregister<"steor","LDEOR">; // STEORx 1073 defm : STOPregister<"stset","LDSET">; // STSETx 1074 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx 1075 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx 1076 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx 1077 defm : STOPregister<"stumin","LDUMIN">;// STUMINx 1078 1079 //===----------------------------------------------------------------------===// 1080 // Logical instructions. 1081 //===----------------------------------------------------------------------===// 1082 1083 // (immediate) 1084 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">; 1085 defm AND : LogicalImm<0b00, "and", and, "bic">; 1086 defm EOR : LogicalImm<0b10, "eor", xor, "eon">; 1087 defm ORR : LogicalImm<0b01, "orr", or, "orn">; 1088 1089 // FIXME: these aliases *are* canonical sometimes (when movz can't be 1090 // used). Actually, it seems to be working right now, but putting logical_immXX 1091 // here is a bit dodgy on the AsmParser side too. 1092 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR, 1093 logical_imm32:$imm), 0>; 1094 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR, 1095 logical_imm64:$imm), 0>; 1096 1097 1098 // (register) 1099 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>; 1100 defm BICS : LogicalRegS<0b11, 1, "bics", 1101 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>; 1102 defm AND : LogicalReg<0b00, 0, "and", and>; 1103 defm BIC : LogicalReg<0b00, 1, "bic", 1104 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1105 defm EON : LogicalReg<0b10, 1, "eon", 1106 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>; 1107 defm EOR : LogicalReg<0b10, 0, "eor", xor>; 1108 defm ORN : LogicalReg<0b01, 1, "orn", 1109 BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 1110 defm ORR : LogicalReg<0b01, 0, "orr", or>; 1111 1112 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>; 1113 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>; 1114 1115 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>; 1116 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>; 1117 1118 def : InstAlias<"mvn $Wd, $Wm$sh", 1119 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>; 1120 def : InstAlias<"mvn $Xd, $Xm$sh", 1121 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>; 1122 1123 def : InstAlias<"tst $src1, $src2", 1124 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>; 1125 def : InstAlias<"tst $src1, $src2", 1126 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>; 1127 1128 def : InstAlias<"tst $src1, $src2", 1129 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>; 1130 def : InstAlias<"tst $src1, $src2", 1131 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>; 1132 1133 def : InstAlias<"tst $src1, $src2$sh", 1134 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>; 1135 def : InstAlias<"tst $src1, $src2$sh", 1136 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>; 1137 1138 1139 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>; 1140 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>; 1141 1142 1143 //===----------------------------------------------------------------------===// 1144 // One operand data processing instructions. 1145 //===----------------------------------------------------------------------===// 1146 1147 defm CLS : OneOperandData<0b101, "cls">; 1148 defm CLZ : OneOperandData<0b100, "clz", ctlz>; 1149 defm RBIT : OneOperandData<0b000, "rbit", bitreverse>; 1150 1151 def REV16Wr : OneWRegData<0b001, "rev16", 1152 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>; 1153 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>; 1154 1155 def : Pat<(cttz GPR32:$Rn), 1156 (CLZWr (RBITWr GPR32:$Rn))>; 1157 def : Pat<(cttz GPR64:$Rn), 1158 (CLZXr (RBITXr GPR64:$Rn))>; 1159 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)), 1160 (i32 1))), 1161 (CLSWr GPR32:$Rn)>; 1162 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)), 1163 (i64 1))), 1164 (CLSXr GPR64:$Rn)>; 1165 1166 // Unlike the other one operand instructions, the instructions with the "rev" 1167 // mnemonic do *not* just different in the size bit, but actually use different 1168 // opcode bits for the different sizes. 1169 def REVWr : OneWRegData<0b010, "rev", bswap>; 1170 def REVXr : OneXRegData<0b011, "rev", bswap>; 1171 def REV32Xr : OneXRegData<0b010, "rev32", 1172 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>; 1173 1174 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>; 1175 1176 // The bswap commutes with the rotr so we want a pattern for both possible 1177 // orders. 1178 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>; 1179 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>; 1180 1181 //===----------------------------------------------------------------------===// 1182 // Bitfield immediate extraction instruction. 1183 //===----------------------------------------------------------------------===// 1184 let hasSideEffects = 0 in 1185 defm EXTR : ExtractImm<"extr">; 1186 def : InstAlias<"ror $dst, $src, $shift", 1187 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>; 1188 def : InstAlias<"ror $dst, $src, $shift", 1189 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>; 1190 1191 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), 1192 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>; 1193 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), 1194 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; 1195 1196 //===----------------------------------------------------------------------===// 1197 // Other bitfield immediate instructions. 1198 //===----------------------------------------------------------------------===// 1199 let hasSideEffects = 0 in { 1200 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">; 1201 defm SBFM : BitfieldImm<0b00, "sbfm">; 1202 defm UBFM : BitfieldImm<0b10, "ubfm">; 1203 } 1204 1205 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{ 1206 uint64_t enc = (32 - N->getZExtValue()) & 0x1f; 1207 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1208 }]>; 1209 1210 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{ 1211 uint64_t enc = 31 - N->getZExtValue(); 1212 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1213 }]>; 1214 1215 // min(7, 31 - shift_amt) 1216 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 1217 uint64_t enc = 31 - N->getZExtValue(); 1218 enc = enc > 7 ? 7 : enc; 1219 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1220 }]>; 1221 1222 // min(15, 31 - shift_amt) 1223 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 1224 uint64_t enc = 31 - N->getZExtValue(); 1225 enc = enc > 15 ? 15 : enc; 1226 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1227 }]>; 1228 1229 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{ 1230 uint64_t enc = (64 - N->getZExtValue()) & 0x3f; 1231 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1232 }]>; 1233 1234 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{ 1235 uint64_t enc = 63 - N->getZExtValue(); 1236 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1237 }]>; 1238 1239 // min(7, 63 - shift_amt) 1240 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 1241 uint64_t enc = 63 - N->getZExtValue(); 1242 enc = enc > 7 ? 7 : enc; 1243 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1244 }]>; 1245 1246 // min(15, 63 - shift_amt) 1247 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 1248 uint64_t enc = 63 - N->getZExtValue(); 1249 enc = enc > 15 ? 15 : enc; 1250 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1251 }]>; 1252 1253 // min(31, 63 - shift_amt) 1254 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{ 1255 uint64_t enc = 63 - N->getZExtValue(); 1256 enc = enc > 31 ? 31 : enc; 1257 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 1258 }]>; 1259 1260 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)), 1261 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 1262 (i64 (i32shift_b imm0_31:$imm)))>; 1263 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)), 1264 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 1265 (i64 (i64shift_b imm0_63:$imm)))>; 1266 1267 let AddedComplexity = 10 in { 1268 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)), 1269 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 1270 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)), 1271 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 1272 } 1273 1274 def : InstAlias<"asr $dst, $src, $shift", 1275 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 1276 def : InstAlias<"asr $dst, $src, $shift", 1277 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 1278 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 1279 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 1280 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 1281 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 1282 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 1283 1284 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)), 1285 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 1286 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)), 1287 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 1288 1289 def : InstAlias<"lsr $dst, $src, $shift", 1290 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 1291 def : InstAlias<"lsr $dst, $src, $shift", 1292 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 1293 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 1294 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 1295 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 1296 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 1297 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 1298 1299 //===----------------------------------------------------------------------===// 1300 // Conditional comparison instructions. 1301 //===----------------------------------------------------------------------===// 1302 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>; 1303 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>; 1304 1305 //===----------------------------------------------------------------------===// 1306 // Conditional select instructions. 1307 //===----------------------------------------------------------------------===// 1308 defm CSEL : CondSelect<0, 0b00, "csel">; 1309 1310 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>; 1311 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>; 1312 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>; 1313 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>; 1314 1315 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1316 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1317 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1318 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1319 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1320 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1321 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1322 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1323 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 1324 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 1325 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 1326 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 1327 1328 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV), 1329 (CSINCWr WZR, WZR, (i32 imm:$cc))>; 1330 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV), 1331 (CSINCXr XZR, XZR, (i32 imm:$cc))>; 1332 def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV), 1333 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>; 1334 def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV), 1335 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>; 1336 def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV), 1337 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1338 def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV), 1339 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1340 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV), 1341 (CSINVWr WZR, WZR, (i32 imm:$cc))>; 1342 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV), 1343 (CSINVXr XZR, XZR, (i32 imm:$cc))>; 1344 def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV), 1345 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>; 1346 def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV), 1347 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>; 1348 def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV), 1349 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1350 def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV), 1351 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 1352 1353 // The inverse of the condition code from the alias instruction is what is used 1354 // in the aliased instruction. The parser all ready inverts the condition code 1355 // for these aliases. 1356 def : InstAlias<"cset $dst, $cc", 1357 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 1358 def : InstAlias<"cset $dst, $cc", 1359 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 1360 1361 def : InstAlias<"csetm $dst, $cc", 1362 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 1363 def : InstAlias<"csetm $dst, $cc", 1364 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 1365 1366 def : InstAlias<"cinc $dst, $src, $cc", 1367 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1368 def : InstAlias<"cinc $dst, $src, $cc", 1369 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1370 1371 def : InstAlias<"cinv $dst, $src, $cc", 1372 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1373 def : InstAlias<"cinv $dst, $src, $cc", 1374 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1375 1376 def : InstAlias<"cneg $dst, $src, $cc", 1377 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 1378 def : InstAlias<"cneg $dst, $src, $cc", 1379 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 1380 1381 //===----------------------------------------------------------------------===// 1382 // PC-relative instructions. 1383 //===----------------------------------------------------------------------===// 1384 let isReMaterializable = 1 in { 1385 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 1386 def ADR : ADRI<0, "adr", adrlabel, []>; 1387 } // hasSideEffects = 0 1388 1389 def ADRP : ADRI<1, "adrp", adrplabel, 1390 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>; 1391 } // isReMaterializable = 1 1392 1393 // page address of a constant pool entry, block address 1394 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>; 1395 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>; 1396 def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>; 1397 1398 //===----------------------------------------------------------------------===// 1399 // Unconditional branch (register) instructions. 1400 //===----------------------------------------------------------------------===// 1401 1402 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1403 def RET : BranchReg<0b0010, "ret", []>; 1404 def DRPS : SpecialReturn<0b0101, "drps">; 1405 def ERET : SpecialReturn<0b0100, "eret">; 1406 } // isReturn = 1, isTerminator = 1, isBarrier = 1 1407 1408 // Default to the LR register. 1409 def : InstAlias<"ret", (RET LR)>; 1410 1411 let isCall = 1, Defs = [LR], Uses = [SP] in { 1412 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>; 1413 } // isCall 1414 1415 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1416 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>; 1417 } // isBranch, isTerminator, isBarrier, isIndirectBranch 1418 1419 // Create a separate pseudo-instruction for codegen to use so that we don't 1420 // flag lr as used in every function. It'll be restored before the RET by the 1421 // epilogue if it's legitimately used. 1422 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>, 1423 Sched<[WriteBrReg]> { 1424 let isTerminator = 1; 1425 let isBarrier = 1; 1426 let isReturn = 1; 1427 } 1428 1429 // This is a directive-like pseudo-instruction. The purpose is to insert an 1430 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction 1431 // (which in the usual case is a BLR). 1432 let hasSideEffects = 1 in 1433 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> { 1434 let AsmString = ".tlsdesccall $sym"; 1435 } 1436 1437 // FIXME: maybe the scratch register used shouldn't be fixed to X1? 1438 // FIXME: can "hasSideEffects be dropped? 1439 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, 1440 isCodeGenOnly = 1 in 1441 def TLSDESC_CALLSEQ 1442 : Pseudo<(outs), (ins i64imm:$sym), 1443 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>, 1444 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>; 1445 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym), 1446 (TLSDESC_CALLSEQ texternalsym:$sym)>; 1447 1448 //===----------------------------------------------------------------------===// 1449 // Conditional branch (immediate) instruction. 1450 //===----------------------------------------------------------------------===// 1451 def Bcc : BranchCond; 1452 1453 //===----------------------------------------------------------------------===// 1454 // Compare-and-branch instructions. 1455 //===----------------------------------------------------------------------===// 1456 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>; 1457 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>; 1458 1459 //===----------------------------------------------------------------------===// 1460 // Test-bit-and-branch instructions. 1461 //===----------------------------------------------------------------------===// 1462 defm TBZ : TestBranch<0, "tbz", AArch64tbz>; 1463 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>; 1464 1465 //===----------------------------------------------------------------------===// 1466 // Unconditional branch (immediate) instructions. 1467 //===----------------------------------------------------------------------===// 1468 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1469 def B : BranchImm<0, "b", [(br bb:$addr)]>; 1470 } // isBranch, isTerminator, isBarrier 1471 1472 let isCall = 1, Defs = [LR], Uses = [SP] in { 1473 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>; 1474 } // isCall 1475 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>; 1476 1477 //===----------------------------------------------------------------------===// 1478 // Exception generation instructions. 1479 //===----------------------------------------------------------------------===// 1480 let isTrap = 1 in { 1481 def BRK : ExceptionGeneration<0b001, 0b00, "brk">; 1482 } 1483 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">; 1484 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; 1485 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">; 1486 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; 1487 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; 1488 def SMC : ExceptionGeneration<0b000, 0b11, "smc">; 1489 def SVC : ExceptionGeneration<0b000, 0b01, "svc">; 1490 1491 // DCPSn defaults to an immediate operand of zero if unspecified. 1492 def : InstAlias<"dcps1", (DCPS1 0)>; 1493 def : InstAlias<"dcps2", (DCPS2 0)>; 1494 def : InstAlias<"dcps3", (DCPS3 0)>; 1495 1496 //===----------------------------------------------------------------------===// 1497 // Load instructions. 1498 //===----------------------------------------------------------------------===// 1499 1500 // Pair (indexed, offset) 1501 defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; 1502 defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; 1503 defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; 1504 defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; 1505 defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; 1506 1507 defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1508 1509 // Pair (pre-indexed) 1510 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 1511 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 1512 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 1513 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 1514 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 1515 1516 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1517 1518 // Pair (post-indexed) 1519 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 1520 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 1521 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 1522 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 1523 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 1524 1525 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 1526 1527 1528 // Pair (no allocate) 1529 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; 1530 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; 1531 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; 1532 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; 1533 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; 1534 1535 //--- 1536 // (register offset) 1537 //--- 1538 1539 // Integer 1540 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>; 1541 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>; 1542 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; 1543 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; 1544 1545 // Floating-point 1546 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>; 1547 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; 1548 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; 1549 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; 1550 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; 1551 1552 // Load sign-extended half-word 1553 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; 1554 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>; 1555 1556 // Load sign-extended byte 1557 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>; 1558 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>; 1559 1560 // Load sign-extended word 1561 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>; 1562 1563 // Pre-fetch. 1564 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">; 1565 1566 // For regular load, we do not have any alignment requirement. 1567 // Thus, it is safe to directly map the vector loads with interesting 1568 // addressing modes. 1569 // FIXME: We could do the same for bitconvert to floating point vectors. 1570 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop, 1571 ValueType ScalTy, ValueType VecTy, 1572 Instruction LOADW, Instruction LOADX, 1573 SubRegIndex sub> { 1574 def : Pat<(VecTy (scalar_to_vector (ScalTy 1575 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))), 1576 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 1577 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset), 1578 sub)>; 1579 1580 def : Pat<(VecTy (scalar_to_vector (ScalTy 1581 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))), 1582 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 1583 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset), 1584 sub)>; 1585 } 1586 1587 let AddedComplexity = 10 in { 1588 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>; 1589 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>; 1590 1591 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>; 1592 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>; 1593 1594 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>; 1595 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>; 1596 1597 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>; 1598 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>; 1599 1600 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>; 1601 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>; 1602 1603 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>; 1604 1605 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>; 1606 1607 1608 def : Pat <(v1i64 (scalar_to_vector (i64 1609 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, 1610 ro_Wextend64:$extend))))), 1611 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; 1612 1613 def : Pat <(v1i64 (scalar_to_vector (i64 1614 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, 1615 ro_Xextend64:$extend))))), 1616 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; 1617 } 1618 1619 // Match all load 64 bits width whose type is compatible with FPR64 1620 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy, 1621 Instruction LOADW, Instruction LOADX> { 1622 1623 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 1624 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 1625 1626 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 1627 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 1628 } 1629 1630 let AddedComplexity = 10 in { 1631 let Predicates = [IsLE] in { 1632 // We must do vector loads with LD1 in big-endian. 1633 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>; 1634 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>; 1635 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>; 1636 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>; 1637 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>; 1638 } 1639 1640 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>; 1641 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 1642 1643 // Match all load 128 bits width whose type is compatible with FPR128 1644 let Predicates = [IsLE] in { 1645 // We must do vector loads with LD1 in big-endian. 1646 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>; 1647 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>; 1648 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>; 1649 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>; 1650 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>; 1651 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>; 1652 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>; 1653 } 1654 } // AddedComplexity = 10 1655 1656 // zextload -> i64 1657 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop, 1658 Instruction INSTW, Instruction INSTX> { 1659 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 1660 (SUBREG_TO_REG (i64 0), 1661 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 1662 sub_32)>; 1663 1664 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 1665 (SUBREG_TO_REG (i64 0), 1666 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 1667 sub_32)>; 1668 } 1669 1670 let AddedComplexity = 10 in { 1671 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>; 1672 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>; 1673 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>; 1674 1675 // zextloadi1 -> zextloadi8 1676 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 1677 1678 // extload -> zextload 1679 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 1680 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 1681 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 1682 1683 // extloadi1 -> zextloadi8 1684 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>; 1685 } 1686 1687 1688 // zextload -> i64 1689 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop, 1690 Instruction INSTW, Instruction INSTX> { 1691 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 1692 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 1693 1694 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 1695 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 1696 1697 } 1698 1699 let AddedComplexity = 10 in { 1700 // extload -> zextload 1701 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 1702 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 1703 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 1704 1705 // zextloadi1 -> zextloadi8 1706 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 1707 } 1708 1709 //--- 1710 // (unsigned immediate) 1711 //--- 1712 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", 1713 [(set GPR64z:$Rt, 1714 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 1715 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", 1716 [(set GPR32z:$Rt, 1717 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 1718 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", 1719 [(set FPR8Op:$Rt, 1720 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; 1721 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr", 1722 [(set (f16 FPR16Op:$Rt), 1723 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; 1724 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr", 1725 [(set (f32 FPR32Op:$Rt), 1726 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 1727 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", 1728 [(set (f64 FPR64Op:$Rt), 1729 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 1730 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", 1731 [(set (f128 FPR128Op:$Rt), 1732 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; 1733 1734 // For regular load, we do not have any alignment requirement. 1735 // Thus, it is safe to directly map the vector loads with interesting 1736 // addressing modes. 1737 // FIXME: We could do the same for bitconvert to floating point vectors. 1738 def : Pat <(v8i8 (scalar_to_vector (i32 1739 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 1740 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 1741 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 1742 def : Pat <(v16i8 (scalar_to_vector (i32 1743 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 1744 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 1745 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 1746 def : Pat <(v4i16 (scalar_to_vector (i32 1747 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 1748 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 1749 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 1750 def : Pat <(v8i16 (scalar_to_vector (i32 1751 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 1752 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 1753 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 1754 def : Pat <(v2i32 (scalar_to_vector (i32 1755 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 1756 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 1757 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 1758 def : Pat <(v4i32 (scalar_to_vector (i32 1759 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 1760 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 1761 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 1762 def : Pat <(v1i64 (scalar_to_vector (i64 1763 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 1764 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1765 def : Pat <(v2i64 (scalar_to_vector (i64 1766 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 1767 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1768 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>; 1769 1770 // Match all load 64 bits width whose type is compatible with FPR64 1771 let Predicates = [IsLE] in { 1772 // We must use LD1 to perform vector loads in big-endian. 1773 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1774 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1775 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1776 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1777 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1778 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1779 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1780 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1781 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1782 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1783 } 1784 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1785 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1786 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1787 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 1788 1789 // Match all load 128 bits width whose type is compatible with FPR128 1790 let Predicates = [IsLE] in { 1791 // We must use LD1 to perform vector loads in big-endian. 1792 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1793 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1794 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1795 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1796 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1797 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1798 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1799 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1800 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1801 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1802 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1803 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1804 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1805 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1806 } 1807 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1808 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 1809 1810 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh", 1811 [(set GPR32:$Rt, 1812 (zextloadi16 (am_indexed16 GPR64sp:$Rn, 1813 uimm12s2:$offset)))]>; 1814 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", 1815 [(set GPR32:$Rt, 1816 (zextloadi8 (am_indexed8 GPR64sp:$Rn, 1817 uimm12s1:$offset)))]>; 1818 // zextload -> i64 1819 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1820 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 1821 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 1822 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 1823 1824 // zextloadi1 -> zextloadi8 1825 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1826 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 1827 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1828 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 1829 1830 // extload -> zextload 1831 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 1832 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>; 1833 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1834 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 1835 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1836 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 1837 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 1838 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 1839 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 1840 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 1841 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1842 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 1843 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 1844 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 1845 1846 // load sign-extended half-word 1847 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", 1848 [(set GPR32:$Rt, 1849 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 1850 uimm12s2:$offset)))]>; 1851 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh", 1852 [(set GPR64:$Rt, 1853 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 1854 uimm12s2:$offset)))]>; 1855 1856 // load sign-extended byte 1857 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb", 1858 [(set GPR32:$Rt, 1859 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 1860 uimm12s1:$offset)))]>; 1861 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb", 1862 [(set GPR64:$Rt, 1863 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 1864 uimm12s1:$offset)))]>; 1865 1866 // load sign-extended word 1867 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", 1868 [(set GPR64:$Rt, 1869 (sextloadi32 (am_indexed32 GPR64sp:$Rn, 1870 uimm12s4:$offset)))]>; 1871 1872 // load zero-extended word 1873 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 1874 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 1875 1876 // Pre-fetch. 1877 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", 1878 [(AArch64Prefetch imm:$Rt, 1879 (am_indexed64 GPR64sp:$Rn, 1880 uimm12s8:$offset))]>; 1881 1882 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>; 1883 1884 //--- 1885 // (literal) 1886 def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr">; 1887 def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr">; 1888 def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr">; 1889 def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr">; 1890 def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr">; 1891 1892 // load sign-extended word 1893 def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw">; 1894 1895 // prefetch 1896 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; 1897 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>; 1898 1899 //--- 1900 // (unscaled immediate) 1901 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", 1902 [(set GPR64z:$Rt, 1903 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 1904 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", 1905 [(set GPR32z:$Rt, 1906 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 1907 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", 1908 [(set FPR8Op:$Rt, 1909 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 1910 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur", 1911 [(set FPR16Op:$Rt, 1912 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 1913 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur", 1914 [(set (f32 FPR32Op:$Rt), 1915 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 1916 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", 1917 [(set (f64 FPR64Op:$Rt), 1918 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 1919 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", 1920 [(set (f128 FPR128Op:$Rt), 1921 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; 1922 1923 defm LDURHH 1924 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh", 1925 [(set GPR32:$Rt, 1926 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 1927 defm LDURBB 1928 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb", 1929 [(set GPR32:$Rt, 1930 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 1931 1932 // Match all load 64 bits width whose type is compatible with FPR64 1933 let Predicates = [IsLE] in { 1934 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1935 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1936 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1937 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1938 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1939 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1940 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1941 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1942 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1943 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1944 } 1945 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1946 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1947 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 1948 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 1949 1950 // Match all load 128 bits width whose type is compatible with FPR128 1951 let Predicates = [IsLE] in { 1952 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1953 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1954 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1955 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1956 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1957 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1958 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1959 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1960 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1961 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1962 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1963 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1964 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1965 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 1966 } 1967 1968 // anyext -> zext 1969 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 1970 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 1971 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1972 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 1973 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1974 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 1975 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 1976 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1977 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 1978 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1979 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1980 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1981 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1982 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1983 // unscaled zext 1984 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 1985 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 1986 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1987 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 1988 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1989 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 1990 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 1991 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1992 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 1993 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1994 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1995 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1996 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 1997 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 1998 1999 2000 //--- 2001 // LDR mnemonics fall back to LDUR for negative or unaligned offsets. 2002 2003 // Define new assembler match classes as we want to only match these when 2004 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't 2005 // associate a DiagnosticType either, as we want the diagnostic for the 2006 // canonical form (the scaled operand) to take precedence. 2007 class SImm9OffsetOperand<int Width> : AsmOperandClass { 2008 let Name = "SImm9OffsetFB" # Width; 2009 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">"; 2010 let RenderMethod = "addImmOperands"; 2011 } 2012 2013 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>; 2014 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>; 2015 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>; 2016 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>; 2017 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>; 2018 2019 def simm9_offset_fb8 : Operand<i64> { 2020 let ParserMatchClass = SImm9OffsetFB8Operand; 2021 } 2022 def simm9_offset_fb16 : Operand<i64> { 2023 let ParserMatchClass = SImm9OffsetFB16Operand; 2024 } 2025 def simm9_offset_fb32 : Operand<i64> { 2026 let ParserMatchClass = SImm9OffsetFB32Operand; 2027 } 2028 def simm9_offset_fb64 : Operand<i64> { 2029 let ParserMatchClass = SImm9OffsetFB64Operand; 2030 } 2031 def simm9_offset_fb128 : Operand<i64> { 2032 let ParserMatchClass = SImm9OffsetFB128Operand; 2033 } 2034 2035 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2036 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2037 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2038 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2039 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2040 (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2041 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2042 (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2043 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2044 (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2045 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2046 (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2047 def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2048 (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 2049 2050 // zextload -> i64 2051 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2052 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2053 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2054 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2055 2056 // load sign-extended half-word 2057 defm LDURSHW 2058 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh", 2059 [(set GPR32:$Rt, 2060 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2061 defm LDURSHX 2062 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh", 2063 [(set GPR64:$Rt, 2064 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2065 2066 // load sign-extended byte 2067 defm LDURSBW 2068 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb", 2069 [(set GPR32:$Rt, 2070 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2071 defm LDURSBX 2072 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb", 2073 [(set GPR64:$Rt, 2074 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2075 2076 // load sign-extended word 2077 defm LDURSW 2078 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw", 2079 [(set GPR64:$Rt, 2080 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2081 2082 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*. 2083 def : InstAlias<"ldrb $Rt, [$Rn, $offset]", 2084 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2085 def : InstAlias<"ldrh $Rt, [$Rn, $offset]", 2086 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2087 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2088 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2089 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2090 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2091 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2092 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2093 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2094 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2095 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]", 2096 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2097 2098 // Pre-fetch. 2099 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum", 2100 [(AArch64Prefetch imm:$Rt, 2101 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2102 2103 //--- 2104 // (unscaled immediate, unprivileged) 2105 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">; 2106 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">; 2107 2108 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">; 2109 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">; 2110 2111 // load sign-extended half-word 2112 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">; 2113 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">; 2114 2115 // load sign-extended byte 2116 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">; 2117 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">; 2118 2119 // load sign-extended word 2120 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; 2121 2122 //--- 2123 // (immediate pre-indexed) 2124 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; 2125 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; 2126 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 2127 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 2128 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 2129 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 2130 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 2131 2132 // load sign-extended half-word 2133 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 2134 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 2135 2136 // load sign-extended byte 2137 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 2138 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 2139 2140 // load zero-extended byte 2141 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 2142 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 2143 2144 // load sign-extended word 2145 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 2146 2147 //--- 2148 // (immediate post-indexed) 2149 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; 2150 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; 2151 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 2152 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 2153 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 2154 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 2155 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 2156 2157 // load sign-extended half-word 2158 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 2159 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 2160 2161 // load sign-extended byte 2162 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 2163 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 2164 2165 // load zero-extended byte 2166 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 2167 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 2168 2169 // load sign-extended word 2170 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 2171 2172 //===----------------------------------------------------------------------===// 2173 // Store instructions. 2174 //===----------------------------------------------------------------------===// 2175 2176 // Pair (indexed, offset) 2177 // FIXME: Use dedicated range-checked addressing mode operand here. 2178 defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; 2179 defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; 2180 defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; 2181 defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; 2182 defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; 2183 2184 // Pair (pre-indexed) 2185 def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; 2186 def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; 2187 def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 2188 def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 2189 def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 2190 2191 // Pair (pre-indexed) 2192 def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; 2193 def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; 2194 def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 2195 def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 2196 def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 2197 2198 // Pair (no allocate) 2199 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; 2200 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; 2201 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; 2202 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; 2203 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; 2204 2205 //--- 2206 // (Register offset) 2207 2208 // Integer 2209 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>; 2210 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>; 2211 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>; 2212 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; 2213 2214 2215 // Floating-point 2216 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>; 2217 defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; 2218 defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; 2219 defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; 2220 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>; 2221 2222 let Predicates = [UseSTRQro], AddedComplexity = 10 in { 2223 def : Pat<(store (f128 FPR128:$Rt), 2224 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm, 2225 ro_Wextend128:$extend)), 2226 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>; 2227 def : Pat<(store (f128 FPR128:$Rt), 2228 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm, 2229 ro_Xextend128:$extend)), 2230 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>; 2231 } 2232 2233 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop, 2234 Instruction STRW, Instruction STRX> { 2235 2236 def : Pat<(storeop GPR64:$Rt, 2237 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2238 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32), 2239 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2240 2241 def : Pat<(storeop GPR64:$Rt, 2242 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2243 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32), 2244 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2245 } 2246 2247 let AddedComplexity = 10 in { 2248 // truncstore i64 2249 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>; 2250 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>; 2251 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>; 2252 } 2253 2254 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR, 2255 Instruction STRW, Instruction STRX> { 2256 def : Pat<(store (VecTy FPR:$Rt), 2257 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2258 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2259 2260 def : Pat<(store (VecTy FPR:$Rt), 2261 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2262 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2263 } 2264 2265 let AddedComplexity = 10 in { 2266 // Match all store 64 bits width whose type is compatible with FPR64 2267 let Predicates = [IsLE] in { 2268 // We must use ST1 to store vectors in big-endian. 2269 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>; 2270 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>; 2271 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>; 2272 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>; 2273 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>; 2274 } 2275 2276 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>; 2277 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 2278 2279 // Match all store 128 bits width whose type is compatible with FPR128 2280 let Predicates = [IsLE, UseSTRQro] in { 2281 // We must use ST1 to store vectors in big-endian. 2282 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>; 2283 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>; 2284 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>; 2285 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>; 2286 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>; 2287 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>; 2288 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>; 2289 } 2290 } // AddedComplexity = 10 2291 2292 // Match stores from lane 0 to the appropriate subreg's store. 2293 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop, 2294 ValueType VecTy, ValueType STy, 2295 SubRegIndex SubRegIdx, 2296 Instruction STRW, Instruction STRX> { 2297 2298 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 2299 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 2300 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2301 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2302 2303 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 2304 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 2305 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2306 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2307 } 2308 2309 let AddedComplexity = 19 in { 2310 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>; 2311 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>; 2312 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>; 2313 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>; 2314 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>; 2315 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>; 2316 } 2317 2318 //--- 2319 // (unsigned immediate) 2320 defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", 2321 [(store GPR64z:$Rt, 2322 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 2323 defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", 2324 [(store GPR32z:$Rt, 2325 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 2326 defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", 2327 [(store FPR8Op:$Rt, 2328 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; 2329 defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str", 2330 [(store (f16 FPR16Op:$Rt), 2331 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; 2332 defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str", 2333 [(store (f32 FPR32Op:$Rt), 2334 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 2335 defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", 2336 [(store (f64 FPR64Op:$Rt), 2337 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 2338 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; 2339 2340 defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", 2341 [(truncstorei16 GPR32z:$Rt, 2342 (am_indexed16 GPR64sp:$Rn, 2343 uimm12s2:$offset))]>; 2344 defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb", 2345 [(truncstorei8 GPR32z:$Rt, 2346 (am_indexed8 GPR64sp:$Rn, 2347 uimm12s1:$offset))]>; 2348 2349 let AddedComplexity = 10 in { 2350 2351 // Match all store 64 bits width whose type is compatible with FPR64 2352 def : Pat<(store (v1i64 FPR64:$Rt), 2353 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2354 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2355 def : Pat<(store (v1f64 FPR64:$Rt), 2356 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2357 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2358 2359 let Predicates = [IsLE] in { 2360 // We must use ST1 to store vectors in big-endian. 2361 def : Pat<(store (v2f32 FPR64:$Rt), 2362 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2363 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2364 def : Pat<(store (v8i8 FPR64:$Rt), 2365 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2366 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2367 def : Pat<(store (v4i16 FPR64:$Rt), 2368 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2369 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2370 def : Pat<(store (v2i32 FPR64:$Rt), 2371 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2372 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2373 def : Pat<(store (v4f16 FPR64:$Rt), 2374 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 2375 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 2376 } 2377 2378 // Match all store 128 bits width whose type is compatible with FPR128 2379 def : Pat<(store (f128 FPR128:$Rt), 2380 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2381 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2382 2383 let Predicates = [IsLE] in { 2384 // We must use ST1 to store vectors in big-endian. 2385 def : Pat<(store (v4f32 FPR128:$Rt), 2386 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2387 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2388 def : Pat<(store (v2f64 FPR128:$Rt), 2389 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2390 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2391 def : Pat<(store (v16i8 FPR128:$Rt), 2392 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2393 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2394 def : Pat<(store (v8i16 FPR128:$Rt), 2395 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2396 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2397 def : Pat<(store (v4i32 FPR128:$Rt), 2398 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2399 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2400 def : Pat<(store (v2i64 FPR128:$Rt), 2401 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2402 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2403 def : Pat<(store (v8f16 FPR128:$Rt), 2404 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 2405 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 2406 } 2407 2408 // truncstore i64 2409 def : Pat<(truncstorei32 GPR64:$Rt, 2410 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)), 2411 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>; 2412 def : Pat<(truncstorei16 GPR64:$Rt, 2413 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), 2414 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>; 2415 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), 2416 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>; 2417 2418 } // AddedComplexity = 10 2419 2420 // Match stores from lane 0 to the appropriate subreg's store. 2421 multiclass VecStoreLane0Pat<Operand UIAddrMode, SDPatternOperator storeop, 2422 ValueType VTy, ValueType STy, 2423 SubRegIndex SubRegIdx, Operand IndexType, 2424 Instruction STR> { 2425 def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)), 2426 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)), 2427 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 2428 GPR64sp:$Rn, IndexType:$offset)>; 2429 } 2430 2431 let AddedComplexity = 19 in { 2432 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>; 2433 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>; 2434 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>; 2435 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>; 2436 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>; 2437 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>; 2438 } 2439 2440 //--- 2441 // (unscaled immediate) 2442 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", 2443 [(store GPR64z:$Rt, 2444 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2445 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", 2446 [(store GPR32z:$Rt, 2447 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 2448 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", 2449 [(store FPR8Op:$Rt, 2450 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 2451 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur", 2452 [(store (f16 FPR16Op:$Rt), 2453 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 2454 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur", 2455 [(store (f32 FPR32Op:$Rt), 2456 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 2457 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", 2458 [(store (f64 FPR64Op:$Rt), 2459 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2460 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", 2461 [(store (f128 FPR128Op:$Rt), 2462 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; 2463 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", 2464 [(truncstorei16 GPR32z:$Rt, 2465 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 2466 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", 2467 [(truncstorei8 GPR32z:$Rt, 2468 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 2469 2470 // Armv8.4 LDAPR & STLR with Immediate Offset instruction 2471 let Predicates = [HasV8_4a] in { 2472 defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>; 2473 defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>; 2474 defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>; 2475 defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>; 2476 defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>; 2477 defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>; 2478 defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>; 2479 defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>; 2480 defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>; 2481 defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>; 2482 defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>; 2483 defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>; 2484 defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>; 2485 } 2486 2487 // Match all store 64 bits width whose type is compatible with FPR64 2488 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2489 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2490 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2491 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2492 2493 let AddedComplexity = 10 in { 2494 2495 let Predicates = [IsLE] in { 2496 // We must use ST1 to store vectors in big-endian. 2497 def : Pat<(store (v2f32 FPR64:$Rt), 2498 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2499 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2500 def : Pat<(store (v8i8 FPR64:$Rt), 2501 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2502 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2503 def : Pat<(store (v4i16 FPR64:$Rt), 2504 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2505 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2506 def : Pat<(store (v2i32 FPR64:$Rt), 2507 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2508 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2509 def : Pat<(store (v4f16 FPR64:$Rt), 2510 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2511 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2512 } 2513 2514 // Match all store 128 bits width whose type is compatible with FPR128 2515 def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2516 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2517 2518 let Predicates = [IsLE] in { 2519 // We must use ST1 to store vectors in big-endian. 2520 def : Pat<(store (v4f32 FPR128:$Rt), 2521 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2522 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2523 def : Pat<(store (v2f64 FPR128:$Rt), 2524 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2525 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2526 def : Pat<(store (v16i8 FPR128:$Rt), 2527 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2528 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2529 def : Pat<(store (v8i16 FPR128:$Rt), 2530 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2531 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2532 def : Pat<(store (v4i32 FPR128:$Rt), 2533 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2534 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2535 def : Pat<(store (v2i64 FPR128:$Rt), 2536 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2537 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2538 def : Pat<(store (v2f64 FPR128:$Rt), 2539 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2540 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2541 def : Pat<(store (v8f16 FPR128:$Rt), 2542 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 2543 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 2544 } 2545 2546 } // AddedComplexity = 10 2547 2548 // unscaled i64 truncating stores 2549 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), 2550 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2551 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), 2552 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2553 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), 2554 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 2555 2556 // Match stores from lane 0 to the appropriate subreg's store. 2557 multiclass VecStoreULane0Pat<SDPatternOperator StoreOp, 2558 ValueType VTy, ValueType STy, 2559 SubRegIndex SubRegIdx, Instruction STR> { 2560 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegIdx, simm9, STR>; 2561 } 2562 2563 let AddedComplexity = 19 in { 2564 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, hsub, STURHi>; 2565 defm : VecStoreULane0Pat<store, v8f16, f16, hsub, STURHi>; 2566 defm : VecStoreULane0Pat<store, v4i32, i32, ssub, STURSi>; 2567 defm : VecStoreULane0Pat<store, v4f32, f32, ssub, STURSi>; 2568 defm : VecStoreULane0Pat<store, v2i64, i64, dsub, STURDi>; 2569 defm : VecStoreULane0Pat<store, v2f64, f64, dsub, STURDi>; 2570 } 2571 2572 //--- 2573 // STR mnemonics fall back to STUR for negative or unaligned offsets. 2574 def : InstAlias<"str $Rt, [$Rn, $offset]", 2575 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2576 def : InstAlias<"str $Rt, [$Rn, $offset]", 2577 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2578 def : InstAlias<"str $Rt, [$Rn, $offset]", 2579 (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2580 def : InstAlias<"str $Rt, [$Rn, $offset]", 2581 (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2582 def : InstAlias<"str $Rt, [$Rn, $offset]", 2583 (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2584 def : InstAlias<"str $Rt, [$Rn, $offset]", 2585 (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2586 def : InstAlias<"str $Rt, [$Rn, $offset]", 2587 (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 2588 2589 def : InstAlias<"strb $Rt, [$Rn, $offset]", 2590 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2591 def : InstAlias<"strh $Rt, [$Rn, $offset]", 2592 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2593 2594 //--- 2595 // (unscaled immediate, unprivileged) 2596 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">; 2597 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">; 2598 2599 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">; 2600 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; 2601 2602 //--- 2603 // (immediate pre-indexed) 2604 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; 2605 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; 2606 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>; 2607 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; 2608 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; 2609 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; 2610 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; 2611 2612 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; 2613 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; 2614 2615 // truncstore i64 2616 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2617 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2618 simm9:$off)>; 2619 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2620 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2621 simm9:$off)>; 2622 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2623 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2624 simm9:$off)>; 2625 2626 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2627 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2628 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2629 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2630 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2631 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2632 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2633 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2634 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2635 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2636 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2637 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2638 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2639 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2640 2641 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2642 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2643 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2644 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2645 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2646 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2647 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2648 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2649 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2650 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2651 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2652 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2653 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2654 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2655 2656 //--- 2657 // (immediate post-indexed) 2658 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; 2659 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; 2660 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>; 2661 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; 2662 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; 2663 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; 2664 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; 2665 2666 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; 2667 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; 2668 2669 // truncstore i64 2670 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2671 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2672 simm9:$off)>; 2673 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2674 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2675 simm9:$off)>; 2676 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 2677 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 2678 simm9:$off)>; 2679 2680 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2681 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2682 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2683 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2684 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2685 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2686 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2687 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2688 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2689 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2690 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2691 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2692 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2693 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 2694 2695 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2696 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2697 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2698 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2699 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2700 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2701 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2702 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2703 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2704 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2705 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2706 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2707 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2708 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 2709 2710 //===----------------------------------------------------------------------===// 2711 // Load/store exclusive instructions. 2712 //===----------------------------------------------------------------------===// 2713 2714 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">; 2715 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">; 2716 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">; 2717 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">; 2718 2719 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">; 2720 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">; 2721 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">; 2722 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">; 2723 2724 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">; 2725 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">; 2726 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">; 2727 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">; 2728 2729 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">; 2730 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">; 2731 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">; 2732 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">; 2733 2734 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">; 2735 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">; 2736 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">; 2737 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">; 2738 2739 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">; 2740 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">; 2741 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">; 2742 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">; 2743 2744 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">; 2745 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">; 2746 2747 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">; 2748 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">; 2749 2750 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">; 2751 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">; 2752 2753 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">; 2754 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">; 2755 2756 let Predicates = [HasV8_1a] in { 2757 // v8.1a "Limited Order Region" extension load-acquire instructions 2758 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">; 2759 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">; 2760 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">; 2761 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">; 2762 2763 // v8.1a "Limited Order Region" extension store-release instructions 2764 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">; 2765 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">; 2766 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">; 2767 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">; 2768 } 2769 2770 //===----------------------------------------------------------------------===// 2771 // Scaled floating point to integer conversion instructions. 2772 //===----------------------------------------------------------------------===// 2773 2774 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>; 2775 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>; 2776 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>; 2777 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>; 2778 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>; 2779 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>; 2780 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>; 2781 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>; 2782 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>; 2783 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>; 2784 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>; 2785 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>; 2786 2787 multiclass FPToIntegerIntPats<Intrinsic round, string INST> { 2788 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>; 2789 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>; 2790 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>; 2791 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>; 2792 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>; 2793 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>; 2794 2795 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))), 2796 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>; 2797 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))), 2798 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>; 2799 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))), 2800 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>; 2801 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))), 2802 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>; 2803 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))), 2804 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>; 2805 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))), 2806 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>; 2807 } 2808 2809 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">; 2810 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">; 2811 2812 multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> { 2813 def : Pat<(i32 (to_int (round f32:$Rn))), 2814 (!cast<Instruction>(INST # UWSr) f32:$Rn)>; 2815 def : Pat<(i64 (to_int (round f32:$Rn))), 2816 (!cast<Instruction>(INST # UXSr) f32:$Rn)>; 2817 def : Pat<(i32 (to_int (round f64:$Rn))), 2818 (!cast<Instruction>(INST # UWDr) f64:$Rn)>; 2819 def : Pat<(i64 (to_int (round f64:$Rn))), 2820 (!cast<Instruction>(INST # UXDr) f64:$Rn)>; 2821 } 2822 2823 defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">; 2824 defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">; 2825 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">; 2826 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">; 2827 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">; 2828 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">; 2829 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">; 2830 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">; 2831 2832 //===----------------------------------------------------------------------===// 2833 // Scaled integer to floating point conversion instructions. 2834 //===----------------------------------------------------------------------===// 2835 2836 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>; 2837 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>; 2838 2839 //===----------------------------------------------------------------------===// 2840 // Unscaled integer to floating point conversion instruction. 2841 //===----------------------------------------------------------------------===// 2842 2843 defm FMOV : UnscaledConversion<"fmov">; 2844 2845 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable 2846 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { 2847 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, 2848 Sched<[WriteF]>, Requires<[HasFullFP16]>; 2849 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, 2850 Sched<[WriteF]>; 2851 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, 2852 Sched<[WriteF]>; 2853 } 2854 // Similarly add aliases 2855 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, 2856 Requires<[HasFullFP16]>; 2857 def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; 2858 def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; 2859 2860 //===----------------------------------------------------------------------===// 2861 // Floating point conversion instruction. 2862 //===----------------------------------------------------------------------===// 2863 2864 defm FCVT : FPConversion<"fcvt">; 2865 2866 //===----------------------------------------------------------------------===// 2867 // Floating point single operand instructions. 2868 //===----------------------------------------------------------------------===// 2869 2870 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>; 2871 defm FMOV : SingleOperandFPData<0b0000, "fmov">; 2872 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>; 2873 defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>; 2874 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>; 2875 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>; 2876 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>; 2877 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>; 2878 2879 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), 2880 (FRINTNDr FPR64:$Rn)>; 2881 2882 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>; 2883 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>; 2884 2885 let SchedRW = [WriteFDiv] in { 2886 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>; 2887 } 2888 2889 //===----------------------------------------------------------------------===// 2890 // Floating point two operand instructions. 2891 //===----------------------------------------------------------------------===// 2892 2893 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>; 2894 let SchedRW = [WriteFDiv] in { 2895 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>; 2896 } 2897 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>; 2898 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>; 2899 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>; 2900 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>; 2901 let SchedRW = [WriteFMul] in { 2902 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>; 2903 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>; 2904 } 2905 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>; 2906 2907 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 2908 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>; 2909 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 2910 (FMINDrr FPR64:$Rn, FPR64:$Rm)>; 2911 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 2912 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>; 2913 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 2914 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>; 2915 2916 //===----------------------------------------------------------------------===// 2917 // Floating point three operand instructions. 2918 //===----------------------------------------------------------------------===// 2919 2920 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>; 2921 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub", 2922 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >; 2923 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd", 2924 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >; 2925 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub", 2926 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >; 2927 2928 // The following def pats catch the case where the LHS of an FMA is negated. 2929 // The TriOpFrag above catches the case where the middle operand is negated. 2930 2931 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike 2932 // the NEON variant. 2933 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)), 2934 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2935 2936 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)), 2937 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2938 2939 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and 2940 // "(-a) + b*(-c)". 2941 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), 2942 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2943 2944 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), 2945 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2946 2947 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))), 2948 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2949 2950 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))), 2951 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2952 2953 //===----------------------------------------------------------------------===// 2954 // Floating point comparison instructions. 2955 //===----------------------------------------------------------------------===// 2956 2957 defm FCMPE : FPComparison<1, "fcmpe">; 2958 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>; 2959 2960 //===----------------------------------------------------------------------===// 2961 // Floating point conditional comparison instructions. 2962 //===----------------------------------------------------------------------===// 2963 2964 defm FCCMPE : FPCondComparison<1, "fccmpe">; 2965 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>; 2966 2967 //===----------------------------------------------------------------------===// 2968 // Floating point conditional select instruction. 2969 //===----------------------------------------------------------------------===// 2970 2971 defm FCSEL : FPCondSelect<"fcsel">; 2972 2973 // CSEL instructions providing f128 types need to be handled by a 2974 // pseudo-instruction since the eventual code will need to introduce basic 2975 // blocks and control flow. 2976 def F128CSEL : Pseudo<(outs FPR128:$Rd), 2977 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond), 2978 [(set (f128 FPR128:$Rd), 2979 (AArch64csel FPR128:$Rn, FPR128:$Rm, 2980 (i32 imm:$cond), NZCV))]> { 2981 let Uses = [NZCV]; 2982 let usesCustomInserter = 1; 2983 let hasNoSchedulingInfo = 1; 2984 } 2985 2986 2987 //===----------------------------------------------------------------------===// 2988 // Floating point immediate move. 2989 //===----------------------------------------------------------------------===// 2990 2991 let isReMaterializable = 1 in { 2992 defm FMOV : FPMoveImmediate<"fmov">; 2993 } 2994 2995 //===----------------------------------------------------------------------===// 2996 // Advanced SIMD two vector instructions. 2997 //===----------------------------------------------------------------------===// 2998 2999 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", 3000 int_aarch64_neon_uabd>; 3001 // Match UABDL in log2-shuffle patterns. 3002 def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)), 3003 (zext (v8i8 V64:$opB))))), 3004 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 3005 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 3006 (v8i16 (add (sub (zext (v8i8 V64:$opA)), 3007 (zext (v8i8 V64:$opB))), 3008 (AArch64vashr v8i16:$src, (i32 15))))), 3009 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 3010 def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)), 3011 (zext (extract_high_v16i8 V128:$opB))))), 3012 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 3013 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 3014 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)), 3015 (zext (extract_high_v16i8 V128:$opB))), 3016 (AArch64vashr v8i16:$src, (i32 15))))), 3017 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 3018 def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)), 3019 (zext (v4i16 V64:$opB))))), 3020 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>; 3021 def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 V128:$opA)), 3022 (zext (extract_high_v8i16 V128:$opB))))), 3023 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>; 3024 def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)), 3025 (zext (v2i32 V64:$opB))))), 3026 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>; 3027 def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 V128:$opA)), 3028 (zext (extract_high_v4i32 V128:$opB))))), 3029 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>; 3030 3031 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>; 3032 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>; 3033 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>; 3034 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>; 3035 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>; 3036 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>; 3037 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>; 3038 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>; 3039 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>; 3040 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>; 3041 3042 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 3043 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 3044 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 3045 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 3046 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 3047 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>; 3048 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>; 3049 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">; 3050 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))), 3051 (FCVTLv4i16 V64:$Rn)>; 3052 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn), 3053 (i64 4)))), 3054 (FCVTLv8i16 V128:$Rn)>; 3055 def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>; 3056 def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn), 3057 (i64 2))))), 3058 (FCVTLv4i32 V128:$Rn)>; 3059 3060 def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>; 3061 def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn), 3062 (i64 4))))), 3063 (FCVTLv8i16 V128:$Rn)>; 3064 3065 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>; 3066 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>; 3067 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>; 3068 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>; 3069 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">; 3070 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))), 3071 (FCVTNv4i16 V128:$Rn)>; 3072 def : Pat<(concat_vectors V64:$Rd, 3073 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))), 3074 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 3075 def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>; 3076 def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>; 3077 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))), 3078 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 3079 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>; 3080 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>; 3081 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn", 3082 int_aarch64_neon_fcvtxn>; 3083 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>; 3084 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>; 3085 3086 def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>; 3087 def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>; 3088 def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>; 3089 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>; 3090 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>; 3091 3092 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>; 3093 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>; 3094 def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>; 3095 def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>; 3096 def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>; 3097 3098 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>; 3099 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>; 3100 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>; 3101 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>; 3102 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>; 3103 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>; 3104 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>; 3105 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>; 3106 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>; 3107 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>; 3108 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>; 3109 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", 3110 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 3111 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; 3112 // Aliases for MVN -> NOT. 3113 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", 3114 (NOTv8i8 V64:$Vd, V64:$Vn)>; 3115 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", 3116 (NOTv16i8 V128:$Vd, V128:$Vn)>; 3117 3118 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>; 3119 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>; 3120 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>; 3121 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>; 3122 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>; 3123 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>; 3124 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>; 3125 3126 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3127 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3128 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3129 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3130 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3131 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3132 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3133 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3134 3135 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3136 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3137 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 3138 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3139 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 3140 3141 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>; 3142 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>; 3143 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>; 3144 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>; 3145 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp", 3146 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >; 3147 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>; 3148 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; 3149 defm SHLL : SIMDVectorLShiftLongBySizeBHS; 3150 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 3151 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 3152 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>; 3153 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>; 3154 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>; 3155 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp", 3156 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >; 3157 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", 3158 int_aarch64_neon_uaddlp>; 3159 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>; 3160 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>; 3161 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>; 3162 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>; 3163 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>; 3164 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>; 3165 3166 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>; 3167 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>; 3168 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>; 3169 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>; 3170 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>; 3171 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>; 3172 3173 // Patterns for vector long shift (by element width). These need to match all 3174 // three of zext, sext and anyext so it's easier to pull the patterns out of the 3175 // definition. 3176 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> { 3177 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)), 3178 (SHLLv8i8 V64:$Rn)>; 3179 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)), 3180 (SHLLv16i8 V128:$Rn)>; 3181 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)), 3182 (SHLLv4i16 V64:$Rn)>; 3183 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)), 3184 (SHLLv8i16 V128:$Rn)>; 3185 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)), 3186 (SHLLv2i32 V64:$Rn)>; 3187 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)), 3188 (SHLLv4i32 V128:$Rn)>; 3189 } 3190 3191 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>; 3192 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>; 3193 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>; 3194 3195 //===----------------------------------------------------------------------===// 3196 // Advanced SIMD three vector instructions. 3197 //===----------------------------------------------------------------------===// 3198 3199 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>; 3200 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>; 3201 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>; 3202 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>; 3203 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>; 3204 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>; 3205 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>; 3206 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>; 3207 defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>; 3208 let Predicates = [HasNEON] in { 3209 foreach VT = [ v2f32, v4f32, v2f64 ] in 3210 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 3211 } 3212 let Predicates = [HasNEON, HasFullFP16] in { 3213 foreach VT = [ v4f16, v8f16 ] in 3214 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 3215 } 3216 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>; 3217 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>; 3218 defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>; 3219 defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>; 3220 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 3221 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 3222 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 3223 defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>; 3224 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>; 3225 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>; 3226 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>; 3227 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>; 3228 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>; 3229 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>; 3230 defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>; 3231 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>; 3232 3233 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the 3234 // instruction expects the addend first, while the fma intrinsic puts it last. 3235 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", 3236 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 3237 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", 3238 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 3239 3240 // The following def pats catch the case where the LHS of an FMA is negated. 3241 // The TriOpFrag above catches the case where the middle operand is negated. 3242 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)), 3243 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>; 3244 3245 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), 3246 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>; 3247 3248 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), 3249 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>; 3250 3251 defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; 3252 defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; 3253 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; 3254 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>; 3255 defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>; 3256 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", 3257 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >; 3258 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", 3259 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >; 3260 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>; 3261 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>; 3262 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba", 3263 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >; 3264 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>; 3265 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>; 3266 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>; 3267 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>; 3268 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>; 3269 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>; 3270 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>; 3271 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>; 3272 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>; 3273 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>; 3274 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>; 3275 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>; 3276 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>; 3277 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>; 3278 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>; 3279 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>; 3280 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>; 3281 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba", 3282 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >; 3283 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>; 3284 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>; 3285 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>; 3286 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>; 3287 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>; 3288 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>; 3289 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>; 3290 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>; 3291 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>; 3292 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>; 3293 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>; 3294 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>; 3295 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>; 3296 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>; 3297 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah", 3298 int_aarch64_neon_sqadd>; 3299 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", 3300 int_aarch64_neon_sqsub>; 3301 3302 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; 3303 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", 3304 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; 3305 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">; 3306 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>; 3307 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl", 3308 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>; 3309 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>; 3310 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn", 3311 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >; 3312 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>; 3313 3314 3315 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm), 3316 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3317 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm), 3318 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3319 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm), 3320 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3321 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm), 3322 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 3323 3324 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm), 3325 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3326 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm), 3327 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3328 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), 3329 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3330 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), 3331 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 3332 3333 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", 3334 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; 3335 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", 3336 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3337 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}", 3338 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3339 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}", 3340 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 3341 3342 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}", 3343 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>; 3344 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}", 3345 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3346 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}", 3347 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3348 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}", 3349 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 3350 3351 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" # 3352 "|cmls.8b\t$dst, $src1, $src2}", 3353 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3354 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" # 3355 "|cmls.16b\t$dst, $src1, $src2}", 3356 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3357 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" # 3358 "|cmls.4h\t$dst, $src1, $src2}", 3359 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3360 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" # 3361 "|cmls.8h\t$dst, $src1, $src2}", 3362 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3363 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" # 3364 "|cmls.2s\t$dst, $src1, $src2}", 3365 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3366 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" # 3367 "|cmls.4s\t$dst, $src1, $src2}", 3368 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3369 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" # 3370 "|cmls.2d\t$dst, $src1, $src2}", 3371 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3372 3373 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" # 3374 "|cmlo.8b\t$dst, $src1, $src2}", 3375 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3376 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" # 3377 "|cmlo.16b\t$dst, $src1, $src2}", 3378 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3379 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" # 3380 "|cmlo.4h\t$dst, $src1, $src2}", 3381 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3382 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" # 3383 "|cmlo.8h\t$dst, $src1, $src2}", 3384 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3385 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" # 3386 "|cmlo.2s\t$dst, $src1, $src2}", 3387 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3388 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" # 3389 "|cmlo.4s\t$dst, $src1, $src2}", 3390 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3391 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" # 3392 "|cmlo.2d\t$dst, $src1, $src2}", 3393 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3394 3395 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" # 3396 "|cmle.8b\t$dst, $src1, $src2}", 3397 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3398 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" # 3399 "|cmle.16b\t$dst, $src1, $src2}", 3400 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3401 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" # 3402 "|cmle.4h\t$dst, $src1, $src2}", 3403 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3404 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" # 3405 "|cmle.8h\t$dst, $src1, $src2}", 3406 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3407 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" # 3408 "|cmle.2s\t$dst, $src1, $src2}", 3409 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3410 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" # 3411 "|cmle.4s\t$dst, $src1, $src2}", 3412 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3413 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" # 3414 "|cmle.2d\t$dst, $src1, $src2}", 3415 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3416 3417 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" # 3418 "|cmlt.8b\t$dst, $src1, $src2}", 3419 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 3420 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" # 3421 "|cmlt.16b\t$dst, $src1, $src2}", 3422 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 3423 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" # 3424 "|cmlt.4h\t$dst, $src1, $src2}", 3425 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 3426 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" # 3427 "|cmlt.8h\t$dst, $src1, $src2}", 3428 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 3429 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" # 3430 "|cmlt.2s\t$dst, $src1, $src2}", 3431 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 3432 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" # 3433 "|cmlt.4s\t$dst, $src1, $src2}", 3434 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 3435 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" # 3436 "|cmlt.2d\t$dst, $src1, $src2}", 3437 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 3438 3439 let Predicates = [HasNEON, HasFullFP16] in { 3440 def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" # 3441 "|fcmle.4h\t$dst, $src1, $src2}", 3442 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3443 def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" # 3444 "|fcmle.8h\t$dst, $src1, $src2}", 3445 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3446 } 3447 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" # 3448 "|fcmle.2s\t$dst, $src1, $src2}", 3449 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3450 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" # 3451 "|fcmle.4s\t$dst, $src1, $src2}", 3452 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3453 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" # 3454 "|fcmle.2d\t$dst, $src1, $src2}", 3455 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3456 3457 let Predicates = [HasNEON, HasFullFP16] in { 3458 def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" # 3459 "|fcmlt.4h\t$dst, $src1, $src2}", 3460 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3461 def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" # 3462 "|fcmlt.8h\t$dst, $src1, $src2}", 3463 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3464 } 3465 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" # 3466 "|fcmlt.2s\t$dst, $src1, $src2}", 3467 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3468 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" # 3469 "|fcmlt.4s\t$dst, $src1, $src2}", 3470 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3471 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" # 3472 "|fcmlt.2d\t$dst, $src1, $src2}", 3473 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3474 3475 let Predicates = [HasNEON, HasFullFP16] in { 3476 def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" # 3477 "|facle.4h\t$dst, $src1, $src2}", 3478 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3479 def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" # 3480 "|facle.8h\t$dst, $src1, $src2}", 3481 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3482 } 3483 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" # 3484 "|facle.2s\t$dst, $src1, $src2}", 3485 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3486 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" # 3487 "|facle.4s\t$dst, $src1, $src2}", 3488 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3489 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" # 3490 "|facle.2d\t$dst, $src1, $src2}", 3491 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3492 3493 let Predicates = [HasNEON, HasFullFP16] in { 3494 def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" # 3495 "|faclt.4h\t$dst, $src1, $src2}", 3496 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 3497 def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" # 3498 "|faclt.8h\t$dst, $src1, $src2}", 3499 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 3500 } 3501 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" # 3502 "|faclt.2s\t$dst, $src1, $src2}", 3503 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 3504 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # 3505 "|faclt.4s\t$dst, $src1, $src2}", 3506 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 3507 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # 3508 "|faclt.2d\t$dst, $src1, $src2}", 3509 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 3510 3511 //===----------------------------------------------------------------------===// 3512 // Advanced SIMD three scalar instructions. 3513 //===----------------------------------------------------------------------===// 3514 3515 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>; 3516 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>; 3517 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>; 3518 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>; 3519 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>; 3520 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>; 3521 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>; 3522 defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>; 3523 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3524 (FABD64 FPR64:$Rn, FPR64:$Rm)>; 3525 let Predicates = [HasFullFP16] in { 3526 def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>; 3527 } 3528 def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>; 3529 def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>; 3530 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge", 3531 int_aarch64_neon_facge>; 3532 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt", 3533 int_aarch64_neon_facgt>; 3534 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 3535 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 3536 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 3537 defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>; 3538 defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>; 3539 defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>; 3540 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>; 3541 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>; 3542 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 3543 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>; 3544 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>; 3545 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>; 3546 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>; 3547 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>; 3548 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>; 3549 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>; 3550 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>; 3551 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>; 3552 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>; 3553 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>; 3554 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>; 3555 let Predicates = [HasRDM] in { 3556 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">; 3557 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">; 3558 def : Pat<(i32 (int_aarch64_neon_sqadd 3559 (i32 FPR32:$Rd), 3560 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 3561 (i32 FPR32:$Rm))))), 3562 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 3563 def : Pat<(i32 (int_aarch64_neon_sqsub 3564 (i32 FPR32:$Rd), 3565 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 3566 (i32 FPR32:$Rm))))), 3567 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 3568 } 3569 3570 def : InstAlias<"cmls $dst, $src1, $src2", 3571 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3572 def : InstAlias<"cmle $dst, $src1, $src2", 3573 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3574 def : InstAlias<"cmlo $dst, $src1, $src2", 3575 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3576 def : InstAlias<"cmlt $dst, $src1, $src2", 3577 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3578 def : InstAlias<"fcmle $dst, $src1, $src2", 3579 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 3580 def : InstAlias<"fcmle $dst, $src1, $src2", 3581 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3582 def : InstAlias<"fcmlt $dst, $src1, $src2", 3583 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 3584 def : InstAlias<"fcmlt $dst, $src1, $src2", 3585 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3586 def : InstAlias<"facle $dst, $src1, $src2", 3587 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 3588 def : InstAlias<"facle $dst, $src1, $src2", 3589 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3590 def : InstAlias<"faclt $dst, $src1, $src2", 3591 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 3592 def : InstAlias<"faclt $dst, $src1, $src2", 3593 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 3594 3595 //===----------------------------------------------------------------------===// 3596 // Advanced SIMD three scalar instructions (mixed operands). 3597 //===----------------------------------------------------------------------===// 3598 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull", 3599 int_aarch64_neon_sqdmulls_scalar>; 3600 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">; 3601 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">; 3602 3603 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd), 3604 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 3605 (i32 FPR32:$Rm))))), 3606 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 3607 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd), 3608 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 3609 (i32 FPR32:$Rm))))), 3610 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 3611 3612 //===----------------------------------------------------------------------===// 3613 // Advanced SIMD two scalar instructions. 3614 //===----------------------------------------------------------------------===// 3615 3616 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>; 3617 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>; 3618 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>; 3619 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>; 3620 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>; 3621 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>; 3622 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 3623 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 3624 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 3625 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 3626 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 3627 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">; 3628 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">; 3629 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">; 3630 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">; 3631 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">; 3632 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">; 3633 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">; 3634 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">; 3635 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">; 3636 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">; 3637 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">; 3638 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">; 3639 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">; 3640 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">; 3641 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg", 3642 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 3643 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; 3644 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 3645 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 3646 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>; 3647 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>; 3648 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd", 3649 int_aarch64_neon_suqadd>; 3650 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>; 3651 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>; 3652 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd", 3653 int_aarch64_neon_usqadd>; 3654 3655 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>; 3656 3657 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))), 3658 (FCVTASv1i64 FPR64:$Rn)>; 3659 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))), 3660 (FCVTAUv1i64 FPR64:$Rn)>; 3661 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))), 3662 (FCVTMSv1i64 FPR64:$Rn)>; 3663 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))), 3664 (FCVTMUv1i64 FPR64:$Rn)>; 3665 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))), 3666 (FCVTNSv1i64 FPR64:$Rn)>; 3667 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))), 3668 (FCVTNUv1i64 FPR64:$Rn)>; 3669 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))), 3670 (FCVTPSv1i64 FPR64:$Rn)>; 3671 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))), 3672 (FCVTPUv1i64 FPR64:$Rn)>; 3673 3674 def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))), 3675 (FRECPEv1f16 FPR16:$Rn)>; 3676 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))), 3677 (FRECPEv1i32 FPR32:$Rn)>; 3678 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))), 3679 (FRECPEv1i64 FPR64:$Rn)>; 3680 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))), 3681 (FRECPEv1i64 FPR64:$Rn)>; 3682 3683 def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))), 3684 (FRECPEv1i32 FPR32:$Rn)>; 3685 def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))), 3686 (FRECPEv2f32 V64:$Rn)>; 3687 def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))), 3688 (FRECPEv4f32 FPR128:$Rn)>; 3689 def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))), 3690 (FRECPEv1i64 FPR64:$Rn)>; 3691 def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))), 3692 (FRECPEv1i64 FPR64:$Rn)>; 3693 def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))), 3694 (FRECPEv2f64 FPR128:$Rn)>; 3695 3696 def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 3697 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>; 3698 def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 3699 (FRECPSv2f32 V64:$Rn, V64:$Rm)>; 3700 def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 3701 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>; 3702 def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 3703 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>; 3704 def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 3705 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>; 3706 3707 def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))), 3708 (FRECPXv1f16 FPR16:$Rn)>; 3709 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))), 3710 (FRECPXv1i32 FPR32:$Rn)>; 3711 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))), 3712 (FRECPXv1i64 FPR64:$Rn)>; 3713 3714 def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))), 3715 (FRSQRTEv1f16 FPR16:$Rn)>; 3716 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))), 3717 (FRSQRTEv1i32 FPR32:$Rn)>; 3718 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))), 3719 (FRSQRTEv1i64 FPR64:$Rn)>; 3720 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))), 3721 (FRSQRTEv1i64 FPR64:$Rn)>; 3722 3723 def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))), 3724 (FRSQRTEv1i32 FPR32:$Rn)>; 3725 def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))), 3726 (FRSQRTEv2f32 V64:$Rn)>; 3727 def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))), 3728 (FRSQRTEv4f32 FPR128:$Rn)>; 3729 def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))), 3730 (FRSQRTEv1i64 FPR64:$Rn)>; 3731 def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))), 3732 (FRSQRTEv1i64 FPR64:$Rn)>; 3733 def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))), 3734 (FRSQRTEv2f64 FPR128:$Rn)>; 3735 3736 def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 3737 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>; 3738 def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 3739 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>; 3740 def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 3741 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>; 3742 def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 3743 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>; 3744 def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 3745 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>; 3746 3747 // If an integer is about to be converted to a floating point value, 3748 // just load it on the floating point unit. 3749 // Here are the patterns for 8 and 16-bits to float. 3750 // 8-bits -> float. 3751 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy, 3752 SDPatternOperator loadop, Instruction UCVTF, 3753 ROAddrMode ro, Instruction LDRW, Instruction LDRX, 3754 SubRegIndex sub> { 3755 def : Pat<(DstTy (uint_to_fp (SrcTy 3756 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, 3757 ro.Wext:$extend))))), 3758 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 3759 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 3760 sub))>; 3761 3762 def : Pat<(DstTy (uint_to_fp (SrcTy 3763 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, 3764 ro.Wext:$extend))))), 3765 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 3766 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 3767 sub))>; 3768 } 3769 3770 defm : UIntToFPROLoadPat<f32, i32, zextloadi8, 3771 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>; 3772 def : Pat <(f32 (uint_to_fp (i32 3773 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 3774 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 3775 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 3776 def : Pat <(f32 (uint_to_fp (i32 3777 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 3778 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 3779 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 3780 // 16-bits -> float. 3781 defm : UIntToFPROLoadPat<f32, i32, zextloadi16, 3782 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>; 3783 def : Pat <(f32 (uint_to_fp (i32 3784 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 3785 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 3786 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 3787 def : Pat <(f32 (uint_to_fp (i32 3788 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 3789 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 3790 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 3791 // 32-bits are handled in target specific dag combine: 3792 // performIntToFpCombine. 3793 // 64-bits integer to 32-bits floating point, not possible with 3794 // UCVTF on floating point registers (both source and destination 3795 // must have the same size). 3796 3797 // Here are the patterns for 8, 16, 32, and 64-bits to double. 3798 // 8-bits -> double. 3799 defm : UIntToFPROLoadPat<f64, i32, zextloadi8, 3800 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>; 3801 def : Pat <(f64 (uint_to_fp (i32 3802 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 3803 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3804 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 3805 def : Pat <(f64 (uint_to_fp (i32 3806 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 3807 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3808 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 3809 // 16-bits -> double. 3810 defm : UIntToFPROLoadPat<f64, i32, zextloadi16, 3811 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>; 3812 def : Pat <(f64 (uint_to_fp (i32 3813 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 3814 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3815 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 3816 def : Pat <(f64 (uint_to_fp (i32 3817 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 3818 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3819 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 3820 // 32-bits -> double. 3821 defm : UIntToFPROLoadPat<f64, i32, load, 3822 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>; 3823 def : Pat <(f64 (uint_to_fp (i32 3824 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 3825 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3826 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>; 3827 def : Pat <(f64 (uint_to_fp (i32 3828 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), 3829 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 3830 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>; 3831 // 64-bits -> double are handled in target specific dag combine: 3832 // performIntToFpCombine. 3833 3834 //===----------------------------------------------------------------------===// 3835 // Advanced SIMD three different-sized vector instructions. 3836 //===----------------------------------------------------------------------===// 3837 3838 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>; 3839 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>; 3840 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>; 3841 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>; 3842 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>; 3843 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", 3844 int_aarch64_neon_sabd>; 3845 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", 3846 int_aarch64_neon_sabd>; 3847 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl", 3848 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>; 3849 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw", 3850 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>; 3851 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal", 3852 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 3853 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl", 3854 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 3855 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>; 3856 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", 3857 int_aarch64_neon_sqadd>; 3858 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", 3859 int_aarch64_neon_sqsub>; 3860 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", 3861 int_aarch64_neon_sqdmull>; 3862 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl", 3863 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>; 3864 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw", 3865 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>; 3866 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", 3867 int_aarch64_neon_uabd>; 3868 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl", 3869 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>; 3870 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw", 3871 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>; 3872 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal", 3873 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 3874 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl", 3875 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 3876 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>; 3877 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl", 3878 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>; 3879 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw", 3880 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>; 3881 3882 // Additional patterns for SMULL and UMULL 3883 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode, 3884 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 3885 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 3886 (INST8B V64:$Rn, V64:$Rm)>; 3887 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 3888 (INST4H V64:$Rn, V64:$Rm)>; 3889 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 3890 (INST2S V64:$Rn, V64:$Rm)>; 3891 } 3892 3893 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16, 3894 SMULLv4i16_v4i32, SMULLv2i32_v2i64>; 3895 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16, 3896 UMULLv4i16_v4i32, UMULLv2i32_v2i64>; 3897 3898 // Patterns for smull2/umull2. 3899 multiclass Neon_mul_high_patterns<SDPatternOperator opnode, 3900 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 3901 def : Pat<(v8i16 (opnode (extract_high_v16i8 V128:$Rn), 3902 (extract_high_v16i8 V128:$Rm))), 3903 (INST8B V128:$Rn, V128:$Rm)>; 3904 def : Pat<(v4i32 (opnode (extract_high_v8i16 V128:$Rn), 3905 (extract_high_v8i16 V128:$Rm))), 3906 (INST4H V128:$Rn, V128:$Rm)>; 3907 def : Pat<(v2i64 (opnode (extract_high_v4i32 V128:$Rn), 3908 (extract_high_v4i32 V128:$Rm))), 3909 (INST2S V128:$Rn, V128:$Rm)>; 3910 } 3911 3912 defm : Neon_mul_high_patterns<AArch64smull, SMULLv16i8_v8i16, 3913 SMULLv8i16_v4i32, SMULLv4i32_v2i64>; 3914 defm : Neon_mul_high_patterns<AArch64umull, UMULLv16i8_v8i16, 3915 UMULLv8i16_v4i32, UMULLv4i32_v2i64>; 3916 3917 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL 3918 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode, 3919 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 3920 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 3921 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>; 3922 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 3923 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>; 3924 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 3925 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>; 3926 } 3927 3928 defm : Neon_mulacc_widen_patterns< 3929 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 3930 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>; 3931 defm : Neon_mulacc_widen_patterns< 3932 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 3933 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>; 3934 defm : Neon_mulacc_widen_patterns< 3935 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 3936 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>; 3937 defm : Neon_mulacc_widen_patterns< 3938 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 3939 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>; 3940 3941 // Patterns for 64-bit pmull 3942 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm), 3943 (PMULLv1i64 V64:$Rn, V64:$Rm)>; 3944 def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)), 3945 (extractelt (v2i64 V128:$Rm), (i64 1))), 3946 (PMULLv2i64 V128:$Rn, V128:$Rm)>; 3947 3948 // CodeGen patterns for addhn and subhn instructions, which can actually be 3949 // written in LLVM IR without too much difficulty. 3950 3951 // ADDHN 3952 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))), 3953 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 3954 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 3955 (i32 16))))), 3956 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 3957 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 3958 (i32 32))))), 3959 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 3960 def : Pat<(concat_vectors (v8i8 V64:$Rd), 3961 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), 3962 (i32 8))))), 3963 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3964 V128:$Rn, V128:$Rm)>; 3965 def : Pat<(concat_vectors (v4i16 V64:$Rd), 3966 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 3967 (i32 16))))), 3968 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3969 V128:$Rn, V128:$Rm)>; 3970 def : Pat<(concat_vectors (v2i32 V64:$Rd), 3971 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 3972 (i32 32))))), 3973 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3974 V128:$Rn, V128:$Rm)>; 3975 3976 // SUBHN 3977 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))), 3978 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 3979 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 3980 (i32 16))))), 3981 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 3982 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 3983 (i32 32))))), 3984 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 3985 def : Pat<(concat_vectors (v8i8 V64:$Rd), 3986 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 3987 (i32 8))))), 3988 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3989 V128:$Rn, V128:$Rm)>; 3990 def : Pat<(concat_vectors (v4i16 V64:$Rd), 3991 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 3992 (i32 16))))), 3993 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3994 V128:$Rn, V128:$Rm)>; 3995 def : Pat<(concat_vectors (v2i32 V64:$Rd), 3996 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 3997 (i32 32))))), 3998 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 3999 V128:$Rn, V128:$Rm)>; 4000 4001 //---------------------------------------------------------------------------- 4002 // AdvSIMD bitwise extract from vector instruction. 4003 //---------------------------------------------------------------------------- 4004 4005 defm EXT : SIMDBitwiseExtract<"ext">; 4006 4007 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 4008 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 4009 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4010 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4011 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 4012 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 4013 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 4014 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 4015 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4016 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4017 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4018 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4019 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4020 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4021 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4022 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4023 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 4024 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 4025 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 4026 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 4027 4028 // We use EXT to handle extract_subvector to copy the upper 64-bits of a 4029 // 128-bit vector. 4030 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))), 4031 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4032 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))), 4033 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4034 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))), 4035 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4036 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))), 4037 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4038 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))), 4039 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4040 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))), 4041 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4042 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))), 4043 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 4044 4045 4046 //---------------------------------------------------------------------------- 4047 // AdvSIMD zip vector 4048 //---------------------------------------------------------------------------- 4049 4050 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>; 4051 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>; 4052 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>; 4053 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>; 4054 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>; 4055 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>; 4056 4057 //---------------------------------------------------------------------------- 4058 // AdvSIMD TBL/TBX instructions 4059 //---------------------------------------------------------------------------- 4060 4061 defm TBL : SIMDTableLookup< 0, "tbl">; 4062 defm TBX : SIMDTableLookupTied<1, "tbx">; 4063 4064 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 4065 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>; 4066 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 4067 (TBLv16i8One V128:$Ri, V128:$Rn)>; 4068 4069 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd), 4070 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 4071 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; 4072 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd), 4073 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 4074 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>; 4075 4076 4077 //---------------------------------------------------------------------------- 4078 // AdvSIMD scalar CPY instruction 4079 //---------------------------------------------------------------------------- 4080 4081 defm CPY : SIMDScalarCPY<"cpy">; 4082 4083 //---------------------------------------------------------------------------- 4084 // AdvSIMD scalar pairwise instructions 4085 //---------------------------------------------------------------------------- 4086 4087 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">; 4088 defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">; 4089 defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">; 4090 defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">; 4091 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">; 4092 defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">; 4093 def : Pat<(v2i64 (AArch64saddv V128:$Rn)), 4094 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 4095 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)), 4096 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 4097 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))), 4098 (FADDPv2i32p V64:$Rn)>; 4099 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))), 4100 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>; 4101 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))), 4102 (FADDPv2i64p V128:$Rn)>; 4103 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))), 4104 (FMAXNMPv2i32p V64:$Rn)>; 4105 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))), 4106 (FMAXNMPv2i64p V128:$Rn)>; 4107 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))), 4108 (FMAXPv2i32p V64:$Rn)>; 4109 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))), 4110 (FMAXPv2i64p V128:$Rn)>; 4111 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))), 4112 (FMINNMPv2i32p V64:$Rn)>; 4113 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))), 4114 (FMINNMPv2i64p V128:$Rn)>; 4115 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))), 4116 (FMINPv2i32p V64:$Rn)>; 4117 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))), 4118 (FMINPv2i64p V128:$Rn)>; 4119 4120 //---------------------------------------------------------------------------- 4121 // AdvSIMD INS/DUP instructions 4122 //---------------------------------------------------------------------------- 4123 4124 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>; 4125 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>; 4126 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>; 4127 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>; 4128 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>; 4129 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>; 4130 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>; 4131 4132 def DUPv2i64lane : SIMDDup64FromElement; 4133 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>; 4134 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>; 4135 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>; 4136 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>; 4137 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>; 4138 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>; 4139 4140 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))), 4141 (v2f32 (DUPv2i32lane 4142 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 4143 (i64 0)))>; 4144 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))), 4145 (v4f32 (DUPv4i32lane 4146 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 4147 (i64 0)))>; 4148 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))), 4149 (v2f64 (DUPv2i64lane 4150 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub), 4151 (i64 0)))>; 4152 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))), 4153 (v4f16 (DUPv4i16lane 4154 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 4155 (i64 0)))>; 4156 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))), 4157 (v8f16 (DUPv8i16lane 4158 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 4159 (i64 0)))>; 4160 4161 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 4162 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>; 4163 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 4164 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>; 4165 4166 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 4167 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>; 4168 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 4169 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>; 4170 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)), 4171 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>; 4172 4173 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane 4174 // instruction even if the types don't match: we just have to remap the lane 4175 // carefully. N.b. this trick only applies to truncations. 4176 def VecIndex_x2 : SDNodeXForm<imm, [{ 4177 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64); 4178 }]>; 4179 def VecIndex_x4 : SDNodeXForm<imm, [{ 4180 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64); 4181 }]>; 4182 def VecIndex_x8 : SDNodeXForm<imm, [{ 4183 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64); 4184 }]>; 4185 4186 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT, 4187 ValueType Src128VT, ValueType ScalVT, 4188 Instruction DUP, SDNodeXForm IdxXFORM> { 4189 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn), 4190 imm:$idx)))), 4191 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 4192 4193 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn), 4194 imm:$idx)))), 4195 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 4196 } 4197 4198 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>; 4199 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>; 4200 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>; 4201 4202 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>; 4203 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>; 4204 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>; 4205 4206 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP, 4207 SDNodeXForm IdxXFORM> { 4208 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn), 4209 imm:$idx))))), 4210 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 4211 4212 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn), 4213 imm:$idx))))), 4214 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 4215 } 4216 4217 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>; 4218 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>; 4219 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>; 4220 4221 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>; 4222 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>; 4223 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>; 4224 4225 // SMOV and UMOV definitions, with some extra patterns for convenience 4226 defm SMOV : SMov; 4227 defm UMOV : UMov; 4228 4229 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 4230 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; 4231 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 4232 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 4233 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4234 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 4235 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4236 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 4237 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 4238 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 4239 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))), 4240 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>; 4241 4242 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), 4243 VectorIndexB:$idx)))), i8), 4244 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 4245 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), 4246 VectorIndexH:$idx)))), i16), 4247 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 4248 4249 // Extracting i8 or i16 elements will have the zero-extend transformed to 4250 // an 'and' mask by type legalization since neither i8 nor i16 are legal types 4251 // for AArch64. Match these patterns here since UMOV already zeroes out the high 4252 // bits of the destination register. 4253 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), 4254 (i32 0xff)), 4255 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>; 4256 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), 4257 (i32 0xffff)), 4258 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>; 4259 4260 defm INS : SIMDIns; 4261 4262 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), 4263 (SUBREG_TO_REG (i32 0), 4264 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4265 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), 4266 (SUBREG_TO_REG (i32 0), 4267 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4268 4269 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)), 4270 (SUBREG_TO_REG (i32 0), 4271 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4272 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)), 4273 (SUBREG_TO_REG (i32 0), 4274 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 4275 4276 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 4277 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4278 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 4279 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4280 4281 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))), 4282 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 4283 (i32 FPR32:$Rn), ssub))>; 4284 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))), 4285 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4286 (i32 FPR32:$Rn), ssub))>; 4287 4288 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))), 4289 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 4290 (i64 FPR64:$Rn), dsub))>; 4291 4292 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 4293 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4294 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 4295 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 4296 4297 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), 4298 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 4299 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), 4300 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 4301 4302 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))), 4303 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>; 4304 4305 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn), 4306 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))), 4307 (EXTRACT_SUBREG 4308 (INSvi16lane 4309 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)), 4310 VectorIndexS:$imm, 4311 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 4312 (i64 0)), 4313 dsub)>; 4314 4315 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn), 4316 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))), 4317 (INSvi16lane 4318 V128:$Rn, VectorIndexH:$imm, 4319 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 4320 (i64 0))>; 4321 4322 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn), 4323 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 4324 (EXTRACT_SUBREG 4325 (INSvi32lane 4326 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)), 4327 VectorIndexS:$imm, 4328 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 4329 (i64 0)), 4330 dsub)>; 4331 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn), 4332 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 4333 (INSvi32lane 4334 V128:$Rn, VectorIndexS:$imm, 4335 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 4336 (i64 0))>; 4337 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn), 4338 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))), 4339 (INSvi64lane 4340 V128:$Rn, VectorIndexD:$imm, 4341 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)), 4342 (i64 0))>; 4343 4344 // Copy an element at a constant index in one vector into a constant indexed 4345 // element of another. 4346 // FIXME refactor to a shared class/dev parameterized on vector type, vector 4347 // index type and INS extension 4348 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane 4349 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs), 4350 VectorIndexB:$idx2)), 4351 (v16i8 (INSvi8lane 4352 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2) 4353 )>; 4354 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane 4355 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs), 4356 VectorIndexH:$idx2)), 4357 (v8i16 (INSvi16lane 4358 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2) 4359 )>; 4360 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane 4361 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs), 4362 VectorIndexS:$idx2)), 4363 (v4i32 (INSvi32lane 4364 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2) 4365 )>; 4366 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane 4367 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs), 4368 VectorIndexD:$idx2)), 4369 (v2i64 (INSvi64lane 4370 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2) 4371 )>; 4372 4373 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, 4374 ValueType VTScal, Instruction INS> { 4375 def : Pat<(VT128 (vector_insert V128:$src, 4376 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 4377 imm:$Immd)), 4378 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; 4379 4380 def : Pat<(VT128 (vector_insert V128:$src, 4381 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 4382 imm:$Immd)), 4383 (INS V128:$src, imm:$Immd, 4384 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; 4385 4386 def : Pat<(VT64 (vector_insert V64:$src, 4387 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 4388 imm:$Immd)), 4389 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), 4390 imm:$Immd, V128:$Rn, imm:$Immn), 4391 dsub)>; 4392 4393 def : Pat<(VT64 (vector_insert V64:$src, 4394 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 4395 imm:$Immd)), 4396 (EXTRACT_SUBREG 4397 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, 4398 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), 4399 dsub)>; 4400 } 4401 4402 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>; 4403 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>; 4404 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>; 4405 4406 4407 // Floating point vector extractions are codegen'd as either a sequence of 4408 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if 4409 // the lane number is anything other than zero. 4410 def : Pat<(vector_extract (v2f64 V128:$Rn), 0), 4411 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>; 4412 def : Pat<(vector_extract (v4f32 V128:$Rn), 0), 4413 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>; 4414 def : Pat<(vector_extract (v8f16 V128:$Rn), 0), 4415 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>; 4416 4417 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx), 4418 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>; 4419 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx), 4420 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>; 4421 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx), 4422 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; 4423 4424 // All concat_vectors operations are canonicalised to act on i64 vectors for 4425 // AArch64. In the general case we need an instruction, which had just as well be 4426 // INS. 4427 class ConcatPat<ValueType DstTy, ValueType SrcTy> 4428 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)), 4429 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1, 4430 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>; 4431 4432 def : ConcatPat<v2i64, v1i64>; 4433 def : ConcatPat<v2f64, v1f64>; 4434 def : ConcatPat<v4i32, v2i32>; 4435 def : ConcatPat<v4f32, v2f32>; 4436 def : ConcatPat<v8i16, v4i16>; 4437 def : ConcatPat<v8f16, v4f16>; 4438 def : ConcatPat<v16i8, v8i8>; 4439 4440 // If the high lanes are undef, though, we can just ignore them: 4441 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy> 4442 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), 4443 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>; 4444 4445 def : ConcatUndefPat<v2i64, v1i64>; 4446 def : ConcatUndefPat<v2f64, v1f64>; 4447 def : ConcatUndefPat<v4i32, v2i32>; 4448 def : ConcatUndefPat<v4f32, v2f32>; 4449 def : ConcatUndefPat<v8i16, v4i16>; 4450 def : ConcatUndefPat<v16i8, v8i8>; 4451 4452 //---------------------------------------------------------------------------- 4453 // AdvSIMD across lanes instructions 4454 //---------------------------------------------------------------------------- 4455 4456 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">; 4457 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">; 4458 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">; 4459 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">; 4460 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">; 4461 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">; 4462 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">; 4463 defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>; 4464 defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>; 4465 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>; 4466 defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>; 4467 4468 // Patterns for across-vector intrinsics, that have a node equivalent, that 4469 // returns a vector (with only the low lane defined) instead of a scalar. 4470 // In effect, opNode is the same as (scalar_to_vector (IntNode)). 4471 multiclass SIMDAcrossLanesIntrinsic<string baseOpc, 4472 SDPatternOperator opNode> { 4473 // If a lane instruction caught the vector_extract around opNode, we can 4474 // directly match the latter to the instruction. 4475 def : Pat<(v8i8 (opNode V64:$Rn)), 4476 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 4477 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>; 4478 def : Pat<(v16i8 (opNode V128:$Rn)), 4479 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4480 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>; 4481 def : Pat<(v4i16 (opNode V64:$Rn)), 4482 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 4483 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>; 4484 def : Pat<(v8i16 (opNode V128:$Rn)), 4485 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 4486 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>; 4487 def : Pat<(v4i32 (opNode V128:$Rn)), 4488 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4489 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>; 4490 4491 4492 // If none did, fallback to the explicit patterns, consuming the vector_extract. 4493 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)), 4494 (i32 0)), (i64 0))), 4495 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 4496 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), 4497 bsub), ssub)>; 4498 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))), 4499 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4500 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), 4501 bsub), ssub)>; 4502 def : Pat<(i32 (vector_extract (insert_subvector undef, 4503 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))), 4504 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 4505 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), 4506 hsub), ssub)>; 4507 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))), 4508 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 4509 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), 4510 hsub), ssub)>; 4511 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))), 4512 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 4513 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), 4514 ssub), ssub)>; 4515 4516 } 4517 4518 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, 4519 SDPatternOperator opNode> 4520 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 4521 // If there is a sign extension after this intrinsic, consume it as smov already 4522 // performed it 4523 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 4524 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)), 4525 (i32 (SMOVvi8to32 4526 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4527 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 4528 (i64 0)))>; 4529 def : Pat<(i32 (sext_inreg (i32 (vector_extract 4530 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)), 4531 (i32 (SMOVvi8to32 4532 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4533 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 4534 (i64 0)))>; 4535 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 4536 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)), 4537 (i32 (SMOVvi16to32 4538 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4539 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 4540 (i64 0)))>; 4541 def : Pat<(i32 (sext_inreg (i32 (vector_extract 4542 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)), 4543 (i32 (SMOVvi16to32 4544 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4545 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 4546 (i64 0)))>; 4547 } 4548 4549 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, 4550 SDPatternOperator opNode> 4551 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 4552 // If there is a masking operation keeping only what has been actually 4553 // generated, consume it. 4554 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 4555 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)), 4556 (i32 (EXTRACT_SUBREG 4557 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4558 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 4559 ssub))>; 4560 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))), 4561 maski8_or_more)), 4562 (i32 (EXTRACT_SUBREG 4563 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4564 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 4565 ssub))>; 4566 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 4567 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)), 4568 (i32 (EXTRACT_SUBREG 4569 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4570 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 4571 ssub))>; 4572 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))), 4573 maski16_or_more)), 4574 (i32 (EXTRACT_SUBREG 4575 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4576 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 4577 ssub))>; 4578 } 4579 4580 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>; 4581 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 4582 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))), 4583 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 4584 4585 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>; 4586 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 4587 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))), 4588 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 4589 4590 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>; 4591 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))), 4592 (SMAXPv2i32 V64:$Rn, V64:$Rn)>; 4593 4594 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>; 4595 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))), 4596 (SMINPv2i32 V64:$Rn, V64:$Rn)>; 4597 4598 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>; 4599 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))), 4600 (UMAXPv2i32 V64:$Rn, V64:$Rn)>; 4601 4602 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>; 4603 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))), 4604 (UMINPv2i32 V64:$Rn, V64:$Rn)>; 4605 4606 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> { 4607 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 4608 (i32 (SMOVvi16to32 4609 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4610 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 4611 (i64 0)))>; 4612 def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 4613 (i32 (SMOVvi16to32 4614 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4615 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 4616 (i64 0)))>; 4617 4618 def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 4619 (i32 (EXTRACT_SUBREG 4620 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4621 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 4622 ssub))>; 4623 def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 4624 (i32 (EXTRACT_SUBREG 4625 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4626 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 4627 ssub))>; 4628 4629 def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 4630 (i64 (EXTRACT_SUBREG 4631 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4632 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 4633 dsub))>; 4634 } 4635 4636 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc, 4637 Intrinsic intOp> { 4638 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 4639 (i32 (EXTRACT_SUBREG 4640 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4641 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 4642 ssub))>; 4643 def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 4644 (i32 (EXTRACT_SUBREG 4645 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4646 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 4647 ssub))>; 4648 4649 def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 4650 (i32 (EXTRACT_SUBREG 4651 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4652 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 4653 ssub))>; 4654 def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 4655 (i32 (EXTRACT_SUBREG 4656 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4657 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 4658 ssub))>; 4659 4660 def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 4661 (i64 (EXTRACT_SUBREG 4662 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4663 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 4664 dsub))>; 4665 } 4666 4667 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>; 4668 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>; 4669 4670 // The vaddlv_s32 intrinsic gets mapped to SADDLP. 4671 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))), 4672 (i64 (EXTRACT_SUBREG 4673 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4674 (SADDLPv2i32_v1i64 V64:$Rn), dsub), 4675 dsub))>; 4676 // The vaddlv_u32 intrinsic gets mapped to UADDLP. 4677 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))), 4678 (i64 (EXTRACT_SUBREG 4679 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 4680 (UADDLPv2i32_v1i64 V64:$Rn), dsub), 4681 dsub))>; 4682 4683 //------------------------------------------------------------------------------ 4684 // AdvSIMD modified immediate instructions 4685 //------------------------------------------------------------------------------ 4686 4687 // AdvSIMD BIC 4688 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; 4689 // AdvSIMD ORR 4690 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; 4691 4692 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 4693 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 4694 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 4695 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 4696 4697 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 4698 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 4699 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 4700 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 4701 4702 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 4703 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 4704 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 4705 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 4706 4707 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 4708 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 4709 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 4710 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 4711 4712 // AdvSIMD FMOV 4713 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, 4714 "fmov", ".2d", 4715 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 4716 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8, 4717 "fmov", ".2s", 4718 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 4719 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8, 4720 "fmov", ".4s", 4721 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 4722 let Predicates = [HasNEON, HasFullFP16] in { 4723 def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8, 4724 "fmov", ".4h", 4725 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 4726 def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8, 4727 "fmov", ".8h", 4728 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 4729 } // Predicates = [HasNEON, HasFullFP16] 4730 4731 // AdvSIMD MOVI 4732 4733 // EDIT byte mask: scalar 4734 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 4735 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi", 4736 [(set FPR64:$Rd, simdimmtype10:$imm8)]>; 4737 // The movi_edit node has the immediate value already encoded, so we use 4738 // a plain imm0_255 here. 4739 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)), 4740 (MOVID imm0_255:$shift)>; 4741 4742 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>; 4743 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>; 4744 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>; 4745 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>; 4746 4747 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>; 4748 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>; 4749 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>; 4750 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>; 4751 4752 // EDIT byte mask: 2d 4753 4754 // The movi_edit node has the immediate value already encoded, so we use 4755 // a plain imm0_255 in the pattern 4756 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 4757 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128, 4758 simdimmtype10, 4759 "movi", ".2d", 4760 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>; 4761 4762 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>; 4763 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>; 4764 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>; 4765 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>; 4766 4767 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; 4768 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>; 4769 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>; 4770 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>; 4771 4772 // EDIT per word & halfword: 2s, 4h, 4s, & 8h 4773 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 4774 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; 4775 4776 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 4777 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 4778 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 4779 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 4780 4781 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 4782 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 4783 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 4784 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 4785 4786 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 4787 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; 4788 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 4789 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>; 4790 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 4791 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>; 4792 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 4793 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>; 4794 4795 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 4796 // EDIT per word: 2s & 4s with MSL shifter 4797 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", 4798 [(set (v2i32 V64:$Rd), 4799 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 4800 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", 4801 [(set (v4i32 V128:$Rd), 4802 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 4803 4804 // Per byte: 8b & 16b 4805 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255, 4806 "movi", ".8b", 4807 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>; 4808 4809 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, 4810 "movi", ".16b", 4811 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>; 4812 } 4813 4814 // AdvSIMD MVNI 4815 4816 // EDIT per word & halfword: 2s, 4h, 4s, & 8h 4817 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 4818 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; 4819 4820 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 4821 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 4822 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 4823 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 4824 4825 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 4826 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 4827 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 4828 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 4829 4830 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 4831 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; 4832 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 4833 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>; 4834 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 4835 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>; 4836 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 4837 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>; 4838 4839 // EDIT per word: 2s & 4s with MSL shifter 4840 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 4841 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", 4842 [(set (v2i32 V64:$Rd), 4843 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 4844 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", 4845 [(set (v4i32 V128:$Rd), 4846 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 4847 } 4848 4849 //---------------------------------------------------------------------------- 4850 // AdvSIMD indexed element 4851 //---------------------------------------------------------------------------- 4852 4853 let hasSideEffects = 0 in { 4854 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">; 4855 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">; 4856 } 4857 4858 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the 4859 // instruction expects the addend first, while the intrinsic expects it last. 4860 4861 // On the other hand, there are quite a few valid combinatorial options due to 4862 // the commutativity of multiplication and the fact that (-x) * y = x * (-y). 4863 defm : SIMDFPIndexedTiedPatterns<"FMLA", 4864 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>; 4865 defm : SIMDFPIndexedTiedPatterns<"FMLA", 4866 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>; 4867 4868 defm : SIMDFPIndexedTiedPatterns<"FMLS", 4869 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 4870 defm : SIMDFPIndexedTiedPatterns<"FMLS", 4871 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >; 4872 defm : SIMDFPIndexedTiedPatterns<"FMLS", 4873 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >; 4874 defm : SIMDFPIndexedTiedPatterns<"FMLS", 4875 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >; 4876 4877 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> { 4878 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit 4879 // and DUP scalar. 4880 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 4881 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 4882 VectorIndexS:$idx))), 4883 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; 4884 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 4885 (v2f32 (AArch64duplane32 4886 (v4f32 (insert_subvector undef, 4887 (v2f32 (fneg V64:$Rm)), 4888 (i32 0))), 4889 VectorIndexS:$idx)))), 4890 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 4891 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 4892 VectorIndexS:$idx)>; 4893 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 4894 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 4895 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 4896 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 4897 4898 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit 4899 // and DUP scalar. 4900 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 4901 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 4902 VectorIndexS:$idx))), 4903 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm, 4904 VectorIndexS:$idx)>; 4905 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 4906 (v4f32 (AArch64duplane32 4907 (v4f32 (insert_subvector undef, 4908 (v2f32 (fneg V64:$Rm)), 4909 (i32 0))), 4910 VectorIndexS:$idx)))), 4911 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 4912 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 4913 VectorIndexS:$idx)>; 4914 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 4915 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 4916 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 4917 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 4918 4919 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar 4920 // (DUPLANE from 64-bit would be trivial). 4921 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 4922 (AArch64duplane64 (v2f64 (fneg V128:$Rm)), 4923 VectorIndexD:$idx))), 4924 (FMLSv2i64_indexed 4925 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; 4926 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 4927 (AArch64dup (f64 (fneg FPR64Op:$Rm))))), 4928 (FMLSv2i64_indexed V128:$Rd, V128:$Rn, 4929 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; 4930 4931 // 2 variants for 32-bit scalar version: extract from .2s or from .4s 4932 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 4933 (vector_extract (v4f32 (fneg V128:$Rm)), 4934 VectorIndexS:$idx))), 4935 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 4936 V128:$Rm, VectorIndexS:$idx)>; 4937 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 4938 (vector_extract (v4f32 (insert_subvector undef, 4939 (v2f32 (fneg V64:$Rm)), 4940 (i32 0))), 4941 VectorIndexS:$idx))), 4942 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 4943 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; 4944 4945 // 1 variant for 64-bit scalar version: extract from .1d or from .2d 4946 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), 4947 (vector_extract (v2f64 (fneg V128:$Rm)), 4948 VectorIndexS:$idx))), 4949 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn, 4950 V128:$Rm, VectorIndexS:$idx)>; 4951 } 4952 4953 defm : FMLSIndexedAfterNegPatterns< 4954 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 4955 defm : FMLSIndexedAfterNegPatterns< 4956 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >; 4957 4958 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>; 4959 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>; 4960 4961 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 4962 (FMULv2i32_indexed V64:$Rn, 4963 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 4964 (i64 0))>; 4965 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 4966 (FMULv4i32_indexed V128:$Rn, 4967 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 4968 (i64 0))>; 4969 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))), 4970 (FMULv2i64_indexed V128:$Rn, 4971 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub), 4972 (i64 0))>; 4973 4974 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>; 4975 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 4976 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", 4977 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>; 4978 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls", 4979 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>; 4980 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>; 4981 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal", 4982 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4983 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl", 4984 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4985 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", 4986 int_aarch64_neon_smull>; 4987 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal", 4988 int_aarch64_neon_sqadd>; 4989 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl", 4990 int_aarch64_neon_sqsub>; 4991 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah", 4992 int_aarch64_neon_sqadd>; 4993 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh", 4994 int_aarch64_neon_sqsub>; 4995 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>; 4996 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal", 4997 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 4998 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl", 4999 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 5000 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull", 5001 int_aarch64_neon_umull>; 5002 5003 // A scalar sqdmull with the second operand being a vector lane can be 5004 // handled directly with the indexed instruction encoding. 5005 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 5006 (vector_extract (v4i32 V128:$Vm), 5007 VectorIndexS:$idx)), 5008 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>; 5009 5010 //---------------------------------------------------------------------------- 5011 // AdvSIMD scalar shift instructions 5012 //---------------------------------------------------------------------------- 5013 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">; 5014 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">; 5015 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; 5016 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">; 5017 // Codegen patterns for the above. We don't put these directly on the 5018 // instructions because TableGen's type inference can't handle the truth. 5019 // Having the same base pattern for fp <--> int totally freaks it out. 5020 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm), 5021 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>; 5022 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm), 5023 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>; 5024 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)), 5025 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 5026 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)), 5027 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 5028 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn), 5029 vecshiftR64:$imm)), 5030 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 5031 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn), 5032 vecshiftR64:$imm)), 5033 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 5034 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm), 5035 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 5036 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 5037 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5038 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn), 5039 vecshiftR64:$imm)), 5040 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5041 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 5042 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5043 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn), 5044 vecshiftR64:$imm)), 5045 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 5046 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm), 5047 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 5048 5049 // Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported. 5050 5051 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)), 5052 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5053 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)), 5054 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5055 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp 5056 (and FPR32:$Rn, (i32 65535)), 5057 vecshiftR16:$imm)), 5058 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5059 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)), 5060 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 5061 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), 5062 (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; 5063 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)), 5064 (i32 (INSERT_SUBREG 5065 (i32 (IMPLICIT_DEF)), 5066 (FCVTZSh FPR16:$Rn, vecshiftR32:$imm), 5067 hsub))>; 5068 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)), 5069 (i64 (INSERT_SUBREG 5070 (i64 (IMPLICIT_DEF)), 5071 (FCVTZSh FPR16:$Rn, vecshiftR64:$imm), 5072 hsub))>; 5073 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)), 5074 (i32 (INSERT_SUBREG 5075 (i32 (IMPLICIT_DEF)), 5076 (FCVTZUh FPR16:$Rn, vecshiftR32:$imm), 5077 hsub))>; 5078 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)), 5079 (i64 (INSERT_SUBREG 5080 (i64 (IMPLICIT_DEF)), 5081 (FCVTZUh FPR16:$Rn, vecshiftR64:$imm), 5082 hsub))>; 5083 5084 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>; 5085 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">; 5086 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn", 5087 int_aarch64_neon_sqrshrn>; 5088 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun", 5089 int_aarch64_neon_sqrshrun>; 5090 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 5091 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 5092 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn", 5093 int_aarch64_neon_sqshrn>; 5094 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun", 5095 int_aarch64_neon_sqshrun>; 5096 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">; 5097 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>; 5098 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra", 5099 TriOpFrag<(add node:$LHS, 5100 (AArch64srshri node:$MHS, node:$RHS))>>; 5101 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>; 5102 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra", 5103 TriOpFrag<(add node:$LHS, 5104 (AArch64vashr node:$MHS, node:$RHS))>>; 5105 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn", 5106 int_aarch64_neon_uqrshrn>; 5107 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 5108 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn", 5109 int_aarch64_neon_uqshrn>; 5110 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>; 5111 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra", 5112 TriOpFrag<(add node:$LHS, 5113 (AArch64urshri node:$MHS, node:$RHS))>>; 5114 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>; 5115 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra", 5116 TriOpFrag<(add node:$LHS, 5117 (AArch64vlshr node:$MHS, node:$RHS))>>; 5118 5119 //---------------------------------------------------------------------------- 5120 // AdvSIMD vector shift instructions 5121 //---------------------------------------------------------------------------- 5122 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>; 5123 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>; 5124 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", 5125 int_aarch64_neon_vcvtfxs2fp>; 5126 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", 5127 int_aarch64_neon_rshrn>; 5128 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>; 5129 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn", 5130 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>; 5131 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>; 5132 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 5133 (i32 vecshiftL64:$imm))), 5134 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>; 5135 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn", 5136 int_aarch64_neon_sqrshrn>; 5137 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun", 5138 int_aarch64_neon_sqrshrun>; 5139 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 5140 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 5141 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn", 5142 int_aarch64_neon_sqshrn>; 5143 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun", 5144 int_aarch64_neon_sqshrun>; 5145 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>; 5146 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 5147 (i32 vecshiftR64:$imm))), 5148 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>; 5149 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>; 5150 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra", 5151 TriOpFrag<(add node:$LHS, 5152 (AArch64srshri node:$MHS, node:$RHS))> >; 5153 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll", 5154 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>; 5155 5156 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>; 5157 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra", 5158 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>; 5159 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf", 5160 int_aarch64_neon_vcvtfxu2fp>; 5161 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn", 5162 int_aarch64_neon_uqrshrn>; 5163 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 5164 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn", 5165 int_aarch64_neon_uqshrn>; 5166 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>; 5167 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra", 5168 TriOpFrag<(add node:$LHS, 5169 (AArch64urshri node:$MHS, node:$RHS))> >; 5170 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll", 5171 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>; 5172 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>; 5173 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra", 5174 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >; 5175 5176 // SHRN patterns for when a logical right shift was used instead of arithmetic 5177 // (the immediate guarantees no sign bits actually end up in the result so it 5178 // doesn't matter). 5179 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))), 5180 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>; 5181 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))), 5182 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>; 5183 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))), 5184 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>; 5185 5186 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd), 5187 (trunc (AArch64vlshr (v8i16 V128:$Rn), 5188 vecshiftR16Narrow:$imm)))), 5189 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5190 V128:$Rn, vecshiftR16Narrow:$imm)>; 5191 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd), 5192 (trunc (AArch64vlshr (v4i32 V128:$Rn), 5193 vecshiftR32Narrow:$imm)))), 5194 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5195 V128:$Rn, vecshiftR32Narrow:$imm)>; 5196 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd), 5197 (trunc (AArch64vlshr (v2i64 V128:$Rn), 5198 vecshiftR64Narrow:$imm)))), 5199 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 5200 V128:$Rn, vecshiftR32Narrow:$imm)>; 5201 5202 // Vector sign and zero extensions are implemented with SSHLL and USSHLL. 5203 // Anyexts are implemented as zexts. 5204 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>; 5205 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 5206 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 5207 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>; 5208 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 5209 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 5210 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>; 5211 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 5212 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 5213 // Also match an extend from the upper half of a 128 bit source register. 5214 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5215 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 5216 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5217 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 5218 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 5219 (SSHLLv16i8_shift V128:$Rn, (i32 0))>; 5220 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5221 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 5222 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5223 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 5224 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 5225 (SSHLLv8i16_shift V128:$Rn, (i32 0))>; 5226 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5227 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 5228 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5229 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 5230 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 5231 (SSHLLv4i32_shift V128:$Rn, (i32 0))>; 5232 5233 // Vector shift sxtl aliases 5234 def : InstAlias<"sxtl.8h $dst, $src1", 5235 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5236 def : InstAlias<"sxtl $dst.8h, $src1.8b", 5237 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5238 def : InstAlias<"sxtl.4s $dst, $src1", 5239 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5240 def : InstAlias<"sxtl $dst.4s, $src1.4h", 5241 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5242 def : InstAlias<"sxtl.2d $dst, $src1", 5243 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5244 def : InstAlias<"sxtl $dst.2d, $src1.2s", 5245 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5246 5247 // Vector shift sxtl2 aliases 5248 def : InstAlias<"sxtl2.8h $dst, $src1", 5249 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5250 def : InstAlias<"sxtl2 $dst.8h, $src1.16b", 5251 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5252 def : InstAlias<"sxtl2.4s $dst, $src1", 5253 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5254 def : InstAlias<"sxtl2 $dst.4s, $src1.8h", 5255 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5256 def : InstAlias<"sxtl2.2d $dst, $src1", 5257 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5258 def : InstAlias<"sxtl2 $dst.2d, $src1.4s", 5259 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5260 5261 // Vector shift uxtl aliases 5262 def : InstAlias<"uxtl.8h $dst, $src1", 5263 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5264 def : InstAlias<"uxtl $dst.8h, $src1.8b", 5265 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 5266 def : InstAlias<"uxtl.4s $dst, $src1", 5267 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5268 def : InstAlias<"uxtl $dst.4s, $src1.4h", 5269 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 5270 def : InstAlias<"uxtl.2d $dst, $src1", 5271 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5272 def : InstAlias<"uxtl $dst.2d, $src1.2s", 5273 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 5274 5275 // Vector shift uxtl2 aliases 5276 def : InstAlias<"uxtl2.8h $dst, $src1", 5277 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5278 def : InstAlias<"uxtl2 $dst.8h, $src1.16b", 5279 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 5280 def : InstAlias<"uxtl2.4s $dst, $src1", 5281 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5282 def : InstAlias<"uxtl2 $dst.4s, $src1.8h", 5283 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 5284 def : InstAlias<"uxtl2.2d $dst, $src1", 5285 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5286 def : InstAlias<"uxtl2 $dst.2d, $src1.4s", 5287 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 5288 5289 // If an integer is about to be converted to a floating point value, 5290 // just load it on the floating point unit. 5291 // These patterns are more complex because floating point loads do not 5292 // support sign extension. 5293 // The sign extension has to be explicitly added and is only supported for 5294 // one step: byte-to-half, half-to-word, word-to-doubleword. 5295 // SCVTF GPR -> FPR is 9 cycles. 5296 // SCVTF FPR -> FPR is 4 cyclces. 5297 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles. 5298 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR 5299 // and still being faster. 5300 // However, this is not good for code size. 5301 // 8-bits -> float. 2 sizes step-up. 5302 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST> 5303 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))), 5304 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 5305 (SSHLLv4i16_shift 5306 (f64 5307 (EXTRACT_SUBREG 5308 (SSHLLv8i8_shift 5309 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5310 INST, 5311 bsub), 5312 0), 5313 dsub)), 5314 0), 5315 ssub)))>, 5316 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 5317 5318 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), 5319 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; 5320 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext), 5321 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>; 5322 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), 5323 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>; 5324 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset), 5325 (LDURBi GPR64sp:$Rn, simm9:$offset)>; 5326 5327 // 16-bits -> float. 1 size step-up. 5328 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST> 5329 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))), 5330 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 5331 (SSHLLv4i16_shift 5332 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5333 INST, 5334 hsub), 5335 0), 5336 ssub)))>, Requires<[NotForCodeSize]>; 5337 5338 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 5339 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 5340 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 5341 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 5342 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 5343 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 5344 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 5345 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 5346 5347 // 32-bits to 32-bits are handled in target specific dag combine: 5348 // performIntToFpCombine. 5349 // 64-bits integer to 32-bits floating point, not possible with 5350 // SCVTF on floating point registers (both source and destination 5351 // must have the same size). 5352 5353 // Here are the patterns for 8, 16, 32, and 64-bits to double. 5354 // 8-bits -> double. 3 size step-up: give up. 5355 // 16-bits -> double. 2 size step. 5356 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST> 5357 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))), 5358 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 5359 (SSHLLv2i32_shift 5360 (f64 5361 (EXTRACT_SUBREG 5362 (SSHLLv4i16_shift 5363 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5364 INST, 5365 hsub), 5366 0), 5367 dsub)), 5368 0), 5369 dsub)))>, 5370 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 5371 5372 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 5373 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 5374 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 5375 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 5376 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 5377 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 5378 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 5379 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 5380 // 32-bits -> double. 1 size step-up. 5381 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST> 5382 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))), 5383 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 5384 (SSHLLv2i32_shift 5385 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5386 INST, 5387 ssub), 5388 0), 5389 dsub)))>, Requires<[NotForCodeSize]>; 5390 5391 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext), 5392 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>; 5393 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext), 5394 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>; 5395 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), 5396 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>; 5397 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset), 5398 (LDURSi GPR64sp:$Rn, simm9:$offset)>; 5399 5400 // 64-bits -> double are handled in target specific dag combine: 5401 // performIntToFpCombine. 5402 5403 5404 //---------------------------------------------------------------------------- 5405 // AdvSIMD Load-Store Structure 5406 //---------------------------------------------------------------------------- 5407 defm LD1 : SIMDLd1Multiple<"ld1">; 5408 defm LD2 : SIMDLd2Multiple<"ld2">; 5409 defm LD3 : SIMDLd3Multiple<"ld3">; 5410 defm LD4 : SIMDLd4Multiple<"ld4">; 5411 5412 defm ST1 : SIMDSt1Multiple<"st1">; 5413 defm ST2 : SIMDSt2Multiple<"st2">; 5414 defm ST3 : SIMDSt3Multiple<"st3">; 5415 defm ST4 : SIMDSt4Multiple<"st4">; 5416 5417 class Ld1Pat<ValueType ty, Instruction INST> 5418 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>; 5419 5420 def : Ld1Pat<v16i8, LD1Onev16b>; 5421 def : Ld1Pat<v8i16, LD1Onev8h>; 5422 def : Ld1Pat<v4i32, LD1Onev4s>; 5423 def : Ld1Pat<v2i64, LD1Onev2d>; 5424 def : Ld1Pat<v8i8, LD1Onev8b>; 5425 def : Ld1Pat<v4i16, LD1Onev4h>; 5426 def : Ld1Pat<v2i32, LD1Onev2s>; 5427 def : Ld1Pat<v1i64, LD1Onev1d>; 5428 5429 class St1Pat<ValueType ty, Instruction INST> 5430 : Pat<(store ty:$Vt, GPR64sp:$Rn), 5431 (INST ty:$Vt, GPR64sp:$Rn)>; 5432 5433 def : St1Pat<v16i8, ST1Onev16b>; 5434 def : St1Pat<v8i16, ST1Onev8h>; 5435 def : St1Pat<v4i32, ST1Onev4s>; 5436 def : St1Pat<v2i64, ST1Onev2d>; 5437 def : St1Pat<v8i8, ST1Onev8b>; 5438 def : St1Pat<v4i16, ST1Onev4h>; 5439 def : St1Pat<v2i32, ST1Onev2s>; 5440 def : St1Pat<v1i64, ST1Onev1d>; 5441 5442 //--- 5443 // Single-element 5444 //--- 5445 5446 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>; 5447 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>; 5448 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>; 5449 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>; 5450 let mayLoad = 1, hasSideEffects = 0 in { 5451 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>; 5452 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>; 5453 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>; 5454 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>; 5455 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>; 5456 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>; 5457 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>; 5458 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>; 5459 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>; 5460 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>; 5461 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>; 5462 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>; 5463 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>; 5464 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>; 5465 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>; 5466 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>; 5467 } 5468 5469 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 5470 (LD1Rv8b GPR64sp:$Rn)>; 5471 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 5472 (LD1Rv16b GPR64sp:$Rn)>; 5473 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 5474 (LD1Rv4h GPR64sp:$Rn)>; 5475 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 5476 (LD1Rv8h GPR64sp:$Rn)>; 5477 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 5478 (LD1Rv2s GPR64sp:$Rn)>; 5479 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 5480 (LD1Rv4s GPR64sp:$Rn)>; 5481 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 5482 (LD1Rv2d GPR64sp:$Rn)>; 5483 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 5484 (LD1Rv1d GPR64sp:$Rn)>; 5485 // Grab the floating point version too 5486 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 5487 (LD1Rv2s GPR64sp:$Rn)>; 5488 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 5489 (LD1Rv4s GPR64sp:$Rn)>; 5490 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 5491 (LD1Rv2d GPR64sp:$Rn)>; 5492 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 5493 (LD1Rv1d GPR64sp:$Rn)>; 5494 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 5495 (LD1Rv4h GPR64sp:$Rn)>; 5496 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 5497 (LD1Rv8h GPR64sp:$Rn)>; 5498 5499 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex, 5500 ValueType VTy, ValueType STy, Instruction LD1> 5501 : Pat<(vector_insert (VTy VecListOne128:$Rd), 5502 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 5503 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; 5504 5505 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>; 5506 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>; 5507 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>; 5508 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>; 5509 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>; 5510 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>; 5511 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>; 5512 5513 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex, 5514 ValueType VTy, ValueType STy, Instruction LD1> 5515 : Pat<(vector_insert (VTy VecListOne64:$Rd), 5516 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 5517 (EXTRACT_SUBREG 5518 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), 5519 VecIndex:$idx, GPR64sp:$Rn), 5520 dsub)>; 5521 5522 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>; 5523 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>; 5524 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>; 5525 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>; 5526 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>; 5527 5528 5529 defm LD1 : SIMDLdSt1SingleAliases<"ld1">; 5530 defm LD2 : SIMDLdSt2SingleAliases<"ld2">; 5531 defm LD3 : SIMDLdSt3SingleAliases<"ld3">; 5532 defm LD4 : SIMDLdSt4SingleAliases<"ld4">; 5533 5534 // Stores 5535 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>; 5536 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>; 5537 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>; 5538 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>; 5539 5540 let AddedComplexity = 19 in 5541 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex, 5542 ValueType VTy, ValueType STy, Instruction ST1> 5543 : Pat<(scalar_store 5544 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 5545 GPR64sp:$Rn), 5546 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>; 5547 5548 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>; 5549 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>; 5550 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>; 5551 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>; 5552 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>; 5553 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>; 5554 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>; 5555 5556 let AddedComplexity = 19 in 5557 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex, 5558 ValueType VTy, ValueType STy, Instruction ST1> 5559 : Pat<(scalar_store 5560 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 5561 GPR64sp:$Rn), 5562 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 5563 VecIndex:$idx, GPR64sp:$Rn)>; 5564 5565 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>; 5566 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>; 5567 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>; 5568 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>; 5569 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>; 5570 5571 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex, 5572 ValueType VTy, ValueType STy, Instruction ST1, 5573 int offset> { 5574 def : Pat<(scalar_store 5575 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 5576 GPR64sp:$Rn, offset), 5577 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 5578 VecIndex:$idx, GPR64sp:$Rn, XZR)>; 5579 5580 def : Pat<(scalar_store 5581 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 5582 GPR64sp:$Rn, GPR64:$Rm), 5583 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 5584 VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 5585 } 5586 5587 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>; 5588 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST, 5589 2>; 5590 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>; 5591 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>; 5592 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>; 5593 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>; 5594 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>; 5595 5596 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex, 5597 ValueType VTy, ValueType STy, Instruction ST1, 5598 int offset> { 5599 def : Pat<(scalar_store 5600 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 5601 GPR64sp:$Rn, offset), 5602 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>; 5603 5604 def : Pat<(scalar_store 5605 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 5606 GPR64sp:$Rn, GPR64:$Rm), 5607 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 5608 } 5609 5610 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST, 5611 1>; 5612 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST, 5613 2>; 5614 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>; 5615 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>; 5616 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>; 5617 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>; 5618 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>; 5619 5620 let mayStore = 1, hasSideEffects = 0 in { 5621 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>; 5622 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>; 5623 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>; 5624 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>; 5625 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>; 5626 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>; 5627 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>; 5628 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>; 5629 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>; 5630 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>; 5631 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>; 5632 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>; 5633 } 5634 5635 defm ST1 : SIMDLdSt1SingleAliases<"st1">; 5636 defm ST2 : SIMDLdSt2SingleAliases<"st2">; 5637 defm ST3 : SIMDLdSt3SingleAliases<"st3">; 5638 defm ST4 : SIMDLdSt4SingleAliases<"st4">; 5639 5640 //---------------------------------------------------------------------------- 5641 // Crypto extensions 5642 //---------------------------------------------------------------------------- 5643 5644 let Predicates = [HasAES] in { 5645 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>; 5646 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>; 5647 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>; 5648 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; 5649 } 5650 5651 // Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required 5652 // for AES fusion on some CPUs. 5653 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 5654 def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 5655 Sched<[WriteV]>; 5656 def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 5657 Sched<[WriteV]>; 5658 } 5659 5660 // Only use constrained versions of AES(I)MC instructions if they are paired with 5661 // AESE/AESD. 5662 def : Pat<(v16i8 (int_aarch64_crypto_aesmc 5663 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1), 5664 (v16i8 V128:$src2))))), 5665 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1), 5666 (v16i8 V128:$src2)))))>, 5667 Requires<[HasFuseAES]>; 5668 5669 def : Pat<(v16i8 (int_aarch64_crypto_aesimc 5670 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1), 5671 (v16i8 V128:$src2))))), 5672 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1), 5673 (v16i8 V128:$src2)))))>, 5674 Requires<[HasFuseAES]>; 5675 5676 let Predicates = [HasSHA2] in { 5677 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>; 5678 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>; 5679 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>; 5680 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>; 5681 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>; 5682 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>; 5683 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>; 5684 5685 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>; 5686 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>; 5687 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>; 5688 } 5689 5690 //---------------------------------------------------------------------------- 5691 // Compiler-pseudos 5692 //---------------------------------------------------------------------------- 5693 // FIXME: Like for X86, these should go in their own separate .td file. 5694 5695 def def32 : PatLeaf<(i32 GPR32:$src), [{ 5696 return isDef32(*N); 5697 }]>; 5698 5699 // In the case of a 32-bit def that is known to implicitly zero-extend, 5700 // we can use a SUBREG_TO_REG. 5701 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>; 5702 5703 // For an anyext, we don't care what the high bits are, so we can perform an 5704 // INSERT_SUBREF into an IMPLICIT_DEF. 5705 def : Pat<(i64 (anyext GPR32:$src)), 5706 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 5707 5708 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and 5709 // then assert the extension has happened. 5710 def : Pat<(i64 (zext GPR32:$src)), 5711 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; 5712 5713 // To sign extend, we use a signed bitfield move instruction (SBFM) on the 5714 // containing super-reg. 5715 def : Pat<(i64 (sext GPR32:$src)), 5716 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>; 5717 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>; 5718 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>; 5719 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>; 5720 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>; 5721 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>; 5722 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>; 5723 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>; 5724 5725 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)), 5726 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 5727 (i64 (i32shift_sext_i8 imm0_31:$imm)))>; 5728 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)), 5729 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 5730 (i64 (i64shift_sext_i8 imm0_63:$imm)))>; 5731 5732 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)), 5733 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 5734 (i64 (i32shift_sext_i16 imm0_31:$imm)))>; 5735 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)), 5736 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 5737 (i64 (i64shift_sext_i16 imm0_63:$imm)))>; 5738 5739 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)), 5740 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 5741 (i64 (i64shift_a imm0_63:$imm)), 5742 (i64 (i64shift_sext_i32 imm0_63:$imm)))>; 5743 5744 // sra patterns have an AddedComplexity of 10, so make sure we have a higher 5745 // AddedComplexity for the following patterns since we want to match sext + sra 5746 // patterns before we attempt to match a single sra node. 5747 let AddedComplexity = 20 in { 5748 // We support all sext + sra combinations which preserve at least one bit of the 5749 // original value which is to be sign extended. E.g. we support shifts up to 5750 // bitwidth-1 bits. 5751 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)), 5752 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>; 5753 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)), 5754 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>; 5755 5756 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)), 5757 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>; 5758 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)), 5759 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>; 5760 5761 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)), 5762 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 5763 (i64 imm0_31:$imm), 31)>; 5764 } // AddedComplexity = 20 5765 5766 // To truncate, we can simply extract from a subregister. 5767 def : Pat<(i32 (trunc GPR64sp:$src)), 5768 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>; 5769 5770 // __builtin_trap() uses the BRK instruction on AArch64. 5771 def : Pat<(trap), (BRK 1)>; 5772 5773 // Conversions within AdvSIMD types in the same register size are free. 5774 // But because we need a consistent lane ordering, in big endian many 5775 // conversions require one or more REV instructions. 5776 // 5777 // Consider a simple memory load followed by a bitconvert then a store. 5778 // v0 = load v2i32 5779 // v1 = BITCAST v2i32 v0 to v4i16 5780 // store v4i16 v2 5781 // 5782 // In big endian mode every memory access has an implicit byte swap. LDR and 5783 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that 5784 // is, they treat the vector as a sequence of elements to be byte-swapped. 5785 // The two pairs of instructions are fundamentally incompatible. We've decided 5786 // to use LD1/ST1 only to simplify compiler implementation. 5787 // 5788 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes 5789 // the original code sequence: 5790 // v0 = load v2i32 5791 // v1 = REV v2i32 (implicit) 5792 // v2 = BITCAST v2i32 v1 to v4i16 5793 // v3 = REV v4i16 v2 (implicit) 5794 // store v4i16 v3 5795 // 5796 // But this is now broken - the value stored is different to the value loaded 5797 // due to lane reordering. To fix this, on every BITCAST we must perform two 5798 // other REVs: 5799 // v0 = load v2i32 5800 // v1 = REV v2i32 (implicit) 5801 // v2 = REV v2i32 5802 // v3 = BITCAST v2i32 v2 to v4i16 5803 // v4 = REV v4i16 5804 // v5 = REV v4i16 v4 (implicit) 5805 // store v4i16 v5 5806 // 5807 // This means an extra two instructions, but actually in most cases the two REV 5808 // instructions can be combined into one. For example: 5809 // (REV64_2s (REV64_4h X)) === (REV32_4h X) 5810 // 5811 // There is also no 128-bit REV instruction. This must be synthesized with an 5812 // EXT instruction. 5813 // 5814 // Most bitconverts require some sort of conversion. The only exceptions are: 5815 // a) Identity conversions - vNfX <-> vNiX 5816 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX 5817 // 5818 5819 // Natural vector casts (64 bit) 5820 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 5821 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 5822 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 5823 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>; 5824 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 5825 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 5826 5827 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 5828 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>; 5829 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 5830 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 5831 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 5832 5833 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>; 5834 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 5835 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 5836 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 5837 def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 5838 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 5839 5840 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 5841 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 5842 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 5843 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 5844 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 5845 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 5846 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 5847 5848 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 5849 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 5850 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 5851 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; 5852 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 5853 5854 // Natural vector casts (128 bit) 5855 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 5856 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 5857 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 5858 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>; 5859 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 5860 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 5861 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 5862 5863 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 5864 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>; 5865 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 5866 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 5867 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 5868 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 5869 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 5870 5871 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>; 5872 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 5873 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 5874 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 5875 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 5876 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 5877 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 5878 5879 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 5880 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 5881 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 5882 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 5883 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>; 5884 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 5885 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 5886 5887 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 5888 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 5889 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 5890 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>; 5891 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 5892 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 5893 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 5894 5895 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 5896 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 5897 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 5898 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 5899 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>; 5900 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 5901 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 5902 5903 let Predicates = [IsLE] in { 5904 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5905 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5906 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5907 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5908 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5909 5910 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 5911 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5912 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 5913 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5914 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 5915 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5916 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 5917 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5918 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 5919 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5920 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 5921 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5922 } 5923 let Predicates = [IsBE] in { 5924 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), 5925 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 5926 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), 5927 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 5928 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), 5929 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 5930 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), 5931 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 5932 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), 5933 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 5934 5935 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 5936 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 5937 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 5938 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 5939 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 5940 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 5941 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 5942 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 5943 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 5944 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 5945 } 5946 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5947 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5948 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), 5949 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5950 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), 5951 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5952 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), 5953 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5954 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>; 5955 5956 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), 5957 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>; 5958 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), 5959 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>; 5960 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), 5961 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 5962 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), 5963 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>; 5964 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 5965 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5966 5967 let Predicates = [IsLE] in { 5968 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 5969 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 5970 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 5971 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>; 5972 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 5973 } 5974 let Predicates = [IsBE] in { 5975 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), 5976 (v1i64 (REV64v2i32 FPR64:$src))>; 5977 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), 5978 (v1i64 (REV64v4i16 FPR64:$src))>; 5979 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), 5980 (v1i64 (REV64v8i8 FPR64:$src))>; 5981 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), 5982 (v1i64 (REV64v4i16 FPR64:$src))>; 5983 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), 5984 (v1i64 (REV64v2i32 FPR64:$src))>; 5985 } 5986 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>; 5987 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 5988 5989 let Predicates = [IsLE] in { 5990 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>; 5991 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 5992 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 5993 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 5994 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>; 5995 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>; 5996 } 5997 let Predicates = [IsBE] in { 5998 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), 5999 (v2i32 (REV64v2i32 FPR64:$src))>; 6000 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), 6001 (v2i32 (REV32v4i16 FPR64:$src))>; 6002 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), 6003 (v2i32 (REV32v8i8 FPR64:$src))>; 6004 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), 6005 (v2i32 (REV64v2i32 FPR64:$src))>; 6006 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), 6007 (v2i32 (REV64v2i32 FPR64:$src))>; 6008 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), 6009 (v2i32 (REV32v4i16 FPR64:$src))>; 6010 } 6011 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 6012 6013 let Predicates = [IsLE] in { 6014 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>; 6015 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 6016 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 6017 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 6018 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 6019 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>; 6020 } 6021 let Predicates = [IsBE] in { 6022 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), 6023 (v4i16 (REV64v4i16 FPR64:$src))>; 6024 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), 6025 (v4i16 (REV32v4i16 FPR64:$src))>; 6026 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), 6027 (v4i16 (REV16v8i8 FPR64:$src))>; 6028 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), 6029 (v4i16 (REV64v4i16 FPR64:$src))>; 6030 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), 6031 (v4i16 (REV32v4i16 FPR64:$src))>; 6032 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), 6033 (v4i16 (REV64v4i16 FPR64:$src))>; 6034 } 6035 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>; 6036 6037 let Predicates = [IsLE] in { 6038 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>; 6039 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 6040 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 6041 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 6042 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>; 6043 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>; 6044 } 6045 let Predicates = [IsBE] in { 6046 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), 6047 (v4f16 (REV64v4i16 FPR64:$src))>; 6048 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), 6049 (v4f16 (REV32v4i16 FPR64:$src))>; 6050 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), 6051 (v4f16 (REV16v8i8 FPR64:$src))>; 6052 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), 6053 (v4f16 (REV64v4i16 FPR64:$src))>; 6054 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), 6055 (v4f16 (REV32v4i16 FPR64:$src))>; 6056 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), 6057 (v4f16 (REV64v4i16 FPR64:$src))>; 6058 } 6059 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 6060 6061 let Predicates = [IsLE] in { 6062 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>; 6063 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 6064 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 6065 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 6066 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 6067 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>; 6068 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>; 6069 } 6070 let Predicates = [IsBE] in { 6071 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), 6072 (v8i8 (REV64v8i8 FPR64:$src))>; 6073 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), 6074 (v8i8 (REV32v8i8 FPR64:$src))>; 6075 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), 6076 (v8i8 (REV16v8i8 FPR64:$src))>; 6077 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), 6078 (v8i8 (REV64v8i8 FPR64:$src))>; 6079 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), 6080 (v8i8 (REV32v8i8 FPR64:$src))>; 6081 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), 6082 (v8i8 (REV64v8i8 FPR64:$src))>; 6083 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), 6084 (v8i8 (REV16v8i8 FPR64:$src))>; 6085 } 6086 6087 let Predicates = [IsLE] in { 6088 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>; 6089 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>; 6090 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>; 6091 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>; 6092 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>; 6093 } 6094 let Predicates = [IsBE] in { 6095 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), 6096 (f64 (REV64v2i32 FPR64:$src))>; 6097 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), 6098 (f64 (REV64v4i16 FPR64:$src))>; 6099 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), 6100 (f64 (REV64v2i32 FPR64:$src))>; 6101 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), 6102 (f64 (REV64v8i8 FPR64:$src))>; 6103 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), 6104 (f64 (REV64v4i16 FPR64:$src))>; 6105 } 6106 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>; 6107 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>; 6108 6109 let Predicates = [IsLE] in { 6110 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>; 6111 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>; 6112 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>; 6113 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; 6114 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>; 6115 } 6116 let Predicates = [IsBE] in { 6117 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), 6118 (v1f64 (REV64v2i32 FPR64:$src))>; 6119 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), 6120 (v1f64 (REV64v4i16 FPR64:$src))>; 6121 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), 6122 (v1f64 (REV64v8i8 FPR64:$src))>; 6123 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), 6124 (v1f64 (REV64v2i32 FPR64:$src))>; 6125 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), 6126 (v1f64 (REV64v4i16 FPR64:$src))>; 6127 } 6128 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>; 6129 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 6130 6131 let Predicates = [IsLE] in { 6132 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>; 6133 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>; 6134 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 6135 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>; 6136 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 6137 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>; 6138 } 6139 let Predicates = [IsBE] in { 6140 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), 6141 (v2f32 (REV64v2i32 FPR64:$src))>; 6142 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), 6143 (v2f32 (REV32v4i16 FPR64:$src))>; 6144 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), 6145 (v2f32 (REV32v8i8 FPR64:$src))>; 6146 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), 6147 (v2f32 (REV64v2i32 FPR64:$src))>; 6148 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), 6149 (v2f32 (REV64v2i32 FPR64:$src))>; 6150 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), 6151 (v2f32 (REV32v4i16 FPR64:$src))>; 6152 } 6153 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 6154 6155 let Predicates = [IsLE] in { 6156 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>; 6157 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>; 6158 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>; 6159 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>; 6160 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>; 6161 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>; 6162 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>; 6163 } 6164 let Predicates = [IsBE] in { 6165 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), 6166 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 6167 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), 6168 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 6169 (REV64v4i32 FPR128:$src), (i32 8)))>; 6170 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), 6171 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 6172 (REV64v8i16 FPR128:$src), (i32 8)))>; 6173 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), 6174 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 6175 (REV64v8i16 FPR128:$src), (i32 8)))>; 6176 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), 6177 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 6178 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), 6179 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 6180 (REV64v4i32 FPR128:$src), (i32 8)))>; 6181 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), 6182 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src), 6183 (REV64v16i8 FPR128:$src), (i32 8)))>; 6184 } 6185 6186 let Predicates = [IsLE] in { 6187 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>; 6188 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 6189 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 6190 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>; 6191 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 6192 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 6193 } 6194 let Predicates = [IsBE] in { 6195 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), 6196 (v2f64 (EXTv16i8 FPR128:$src, 6197 FPR128:$src, (i32 8)))>; 6198 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), 6199 (v2f64 (REV64v4i32 FPR128:$src))>; 6200 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), 6201 (v2f64 (REV64v8i16 FPR128:$src))>; 6202 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), 6203 (v2f64 (REV64v8i16 FPR128:$src))>; 6204 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), 6205 (v2f64 (REV64v16i8 FPR128:$src))>; 6206 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), 6207 (v2f64 (REV64v4i32 FPR128:$src))>; 6208 } 6209 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 6210 6211 let Predicates = [IsLE] in { 6212 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>; 6213 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 6214 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>; 6215 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 6216 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 6217 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 6218 } 6219 let Predicates = [IsBE] in { 6220 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), 6221 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src), 6222 (REV64v4i32 FPR128:$src), (i32 8)))>; 6223 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), 6224 (v4f32 (REV32v8i16 FPR128:$src))>; 6225 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), 6226 (v4f32 (REV32v8i16 FPR128:$src))>; 6227 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), 6228 (v4f32 (REV32v16i8 FPR128:$src))>; 6229 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), 6230 (v4f32 (REV64v4i32 FPR128:$src))>; 6231 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), 6232 (v4f32 (REV64v4i32 FPR128:$src))>; 6233 } 6234 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 6235 6236 let Predicates = [IsLE] in { 6237 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>; 6238 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 6239 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 6240 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 6241 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 6242 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>; 6243 } 6244 let Predicates = [IsBE] in { 6245 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), 6246 (v2i64 (EXTv16i8 FPR128:$src, 6247 FPR128:$src, (i32 8)))>; 6248 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), 6249 (v2i64 (REV64v4i32 FPR128:$src))>; 6250 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), 6251 (v2i64 (REV64v8i16 FPR128:$src))>; 6252 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), 6253 (v2i64 (REV64v16i8 FPR128:$src))>; 6254 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), 6255 (v2i64 (REV64v4i32 FPR128:$src))>; 6256 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), 6257 (v2i64 (REV64v8i16 FPR128:$src))>; 6258 } 6259 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 6260 6261 let Predicates = [IsLE] in { 6262 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>; 6263 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 6264 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 6265 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 6266 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 6267 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>; 6268 } 6269 let Predicates = [IsBE] in { 6270 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), 6271 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src), 6272 (REV64v4i32 FPR128:$src), 6273 (i32 8)))>; 6274 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), 6275 (v4i32 (REV64v4i32 FPR128:$src))>; 6276 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), 6277 (v4i32 (REV32v8i16 FPR128:$src))>; 6278 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), 6279 (v4i32 (REV32v16i8 FPR128:$src))>; 6280 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), 6281 (v4i32 (REV64v4i32 FPR128:$src))>; 6282 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), 6283 (v4i32 (REV32v8i16 FPR128:$src))>; 6284 } 6285 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 6286 6287 let Predicates = [IsLE] in { 6288 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>; 6289 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 6290 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 6291 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 6292 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 6293 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 6294 } 6295 let Predicates = [IsBE] in { 6296 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), 6297 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src), 6298 (REV64v8i16 FPR128:$src), 6299 (i32 8)))>; 6300 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), 6301 (v8i16 (REV64v8i16 FPR128:$src))>; 6302 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), 6303 (v8i16 (REV32v8i16 FPR128:$src))>; 6304 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), 6305 (v8i16 (REV16v16i8 FPR128:$src))>; 6306 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), 6307 (v8i16 (REV64v8i16 FPR128:$src))>; 6308 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), 6309 (v8i16 (REV32v8i16 FPR128:$src))>; 6310 } 6311 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>; 6312 6313 let Predicates = [IsLE] in { 6314 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>; 6315 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 6316 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 6317 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 6318 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 6319 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 6320 } 6321 let Predicates = [IsBE] in { 6322 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), 6323 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src), 6324 (REV64v8i16 FPR128:$src), 6325 (i32 8)))>; 6326 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), 6327 (v8f16 (REV64v8i16 FPR128:$src))>; 6328 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), 6329 (v8f16 (REV32v8i16 FPR128:$src))>; 6330 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), 6331 (v8f16 (REV16v16i8 FPR128:$src))>; 6332 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), 6333 (v8f16 (REV64v8i16 FPR128:$src))>; 6334 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), 6335 (v8f16 (REV32v8i16 FPR128:$src))>; 6336 } 6337 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 6338 6339 let Predicates = [IsLE] in { 6340 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>; 6341 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 6342 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 6343 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 6344 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 6345 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 6346 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>; 6347 } 6348 let Predicates = [IsBE] in { 6349 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), 6350 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src), 6351 (REV64v16i8 FPR128:$src), 6352 (i32 8)))>; 6353 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), 6354 (v16i8 (REV64v16i8 FPR128:$src))>; 6355 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), 6356 (v16i8 (REV32v16i8 FPR128:$src))>; 6357 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), 6358 (v16i8 (REV16v16i8 FPR128:$src))>; 6359 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), 6360 (v16i8 (REV64v16i8 FPR128:$src))>; 6361 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), 6362 (v16i8 (REV32v16i8 FPR128:$src))>; 6363 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), 6364 (v16i8 (REV16v16i8 FPR128:$src))>; 6365 } 6366 6367 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))), 6368 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6369 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))), 6370 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6371 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))), 6372 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6373 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))), 6374 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6375 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))), 6376 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6377 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))), 6378 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6379 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))), 6380 (EXTRACT_SUBREG V128:$Rn, dsub)>; 6381 6382 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))), 6383 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6384 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))), 6385 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6386 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))), 6387 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6388 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))), 6389 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 6390 6391 // A 64-bit subvector insert to the first 128-bit vector position 6392 // is a subregister copy that needs no instruction. 6393 multiclass InsertSubvectorUndef<ValueType Ty> { 6394 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)), 6395 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6396 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)), 6397 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6398 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)), 6399 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6400 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)), 6401 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6402 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)), 6403 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6404 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)), 6405 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6406 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)), 6407 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 6408 } 6409 6410 defm : InsertSubvectorUndef<i32>; 6411 defm : InsertSubvectorUndef<i64>; 6412 6413 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64 6414 // or v2f32. 6415 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)), 6416 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))), 6417 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>; 6418 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)), 6419 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))), 6420 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>; 6421 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector, 6422 // so we match on v4f32 here, not v2f32. This will also catch adding 6423 // the low two lanes of a true v4f32 vector. 6424 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)), 6425 (vector_extract (v4f32 FPR128:$Rn), (i64 1))), 6426 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>; 6427 6428 // Scalar 64-bit shifts in FPR64 registers. 6429 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6430 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6431 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6432 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6433 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6434 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6435 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 6436 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 6437 6438 // Patterns for nontemporal/no-allocate stores. 6439 // We have to resort to tricks to turn a single-input store into a store pair, 6440 // because there is no single-input nontemporal store, only STNP. 6441 let Predicates = [IsLE] in { 6442 let AddedComplexity = 15 in { 6443 class NTStore128Pat<ValueType VT> : 6444 Pat<(nontemporalstore (VT FPR128:$Rt), 6445 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), 6446 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub), 6447 (CPYi64 FPR128:$Rt, (i64 1)), 6448 GPR64sp:$Rn, simm7s8:$offset)>; 6449 6450 def : NTStore128Pat<v2i64>; 6451 def : NTStore128Pat<v4i32>; 6452 def : NTStore128Pat<v8i16>; 6453 def : NTStore128Pat<v16i8>; 6454 6455 class NTStore64Pat<ValueType VT> : 6456 Pat<(nontemporalstore (VT FPR64:$Rt), 6457 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 6458 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), 6459 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), 6460 GPR64sp:$Rn, simm7s4:$offset)>; 6461 6462 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? 6463 def : NTStore64Pat<v1f64>; 6464 def : NTStore64Pat<v1i64>; 6465 def : NTStore64Pat<v2i32>; 6466 def : NTStore64Pat<v4i16>; 6467 def : NTStore64Pat<v8i8>; 6468 6469 def : Pat<(nontemporalstore GPR64:$Rt, 6470 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 6471 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), 6472 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32), 6473 GPR64sp:$Rn, simm7s4:$offset)>; 6474 } // AddedComplexity=10 6475 } // Predicates = [IsLE] 6476 6477 // Tail call return handling. These are all compiler pseudo-instructions, 6478 // so no encoding information or anything like that. 6479 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 6480 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>, 6481 Sched<[WriteBrReg]>; 6482 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>, 6483 Sched<[WriteBrReg]>; 6484 } 6485 6486 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)), 6487 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>; 6488 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)), 6489 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 6490 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 6491 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 6492 6493 include "AArch64InstrAtomics.td" 6494 include "AArch64SVEInstrInfo.td" 6495
