1 //==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the ARM Cortex A53 processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // ===---------------------------------------------------------------------===// 15 // The following definitions describe the simpler per-operand machine model. 16 // This works with MachineScheduler. See MCSchedule.h for details. 17 18 // Cortex-A53 machine model for scheduling and other instruction cost heuristics. 19 def CortexA53Model : SchedMachineModel { 20 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order. 21 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 22 let LoadLatency = 3; // Optimistic load latency assuming bypass. 23 // This is overriden by OperandCycles if the 24 // Itineraries are queried instead. 25 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation 26 // Specification - Instruction Timings" 27 // v 1.0 Spreadsheet 28 let CompleteModel = 1; 29 30 list<Predicate> UnsupportedFeatures = [HasSVE]; 31 } 32 33 34 //===----------------------------------------------------------------------===// 35 // Define each kind of processor resource and number available. 36 37 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since 38 // Cortex-A53 is in-order. 39 40 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 41 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 42 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 43 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store 44 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch 45 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU 46 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt 47 48 49 //===----------------------------------------------------------------------===// 50 // Subtarget-specific SchedWrite types which both map the ProcResources and 51 // set the latency. 52 53 let SchedModel = CortexA53Model in { 54 55 // ALU - Despite having a full latency of 4, most of the ALU instructions can 56 // forward a cycle earlier and then two cycles earlier in the case of a 57 // shift-only instruction. These latencies will be incorrect when the 58 // result cannot be forwarded, but modeling isn't rocket surgery. 59 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; } 60 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; } 61 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; } 62 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; } 63 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; } 64 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; } 65 66 // MAC 67 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; } 68 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; } 69 70 // Div 71 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; } 72 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; } 73 74 // Load 75 def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; } 76 def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; } 77 def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; } 78 79 // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd 80 // below, choosing the median of 3 which makes the latency 6. 81 // May model this more carefully in the future. The remaining 82 // A53WriteVLD# types represent the 1-5 cycle issues explicitly. 83 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6; 84 let ResourceCycles = [3]; } 85 def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } 86 def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; 87 let ResourceCycles = [2]; } 88 def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; 89 let ResourceCycles = [3]; } 90 def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7; 91 let ResourceCycles = [4]; } 92 def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8; 93 let ResourceCycles = [5]; } 94 95 // Pre/Post Indexing - Performed as part of address generation which is already 96 // accounted for in the WriteST* latencies below 97 def : WriteRes<WriteAdr, []> { let Latency = 0; } 98 99 // Store 100 def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; } 101 def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; } 102 def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; } 103 def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; } 104 105 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue. 106 def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5; 107 let ResourceCycles = [2];} 108 def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } 109 def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; 110 let ResourceCycles = [2]; } 111 def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; 112 let ResourceCycles = [3]; } 113 114 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 115 116 // Branch 117 def : WriteRes<WriteBr, [A53UnitB]>; 118 def : WriteRes<WriteBrReg, [A53UnitB]>; 119 def : WriteRes<WriteSys, [A53UnitB]>; 120 def : WriteRes<WriteBarrier, [A53UnitB]>; 121 def : WriteRes<WriteHint, [A53UnitB]>; 122 123 // FP ALU 124 def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; } 125 def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; } 126 def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; } 127 def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; } 128 def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; } 129 def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; } 130 131 // FP Mul, Div, Sqrt 132 def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; } 133 def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33; 134 let ResourceCycles = [29]; } 135 def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; } 136 def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18; 137 let ResourceCycles = [14]; } 138 def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33; 139 let ResourceCycles = [29]; } 140 def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17; 141 let ResourceCycles = [13]; } 142 def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32; 143 let ResourceCycles = [28]; } 144 145 //===----------------------------------------------------------------------===// 146 // Subtarget-specific SchedRead types. 147 148 // No forwarding for these reads. 149 def : ReadAdvance<ReadExtrHi, 0>; 150 def : ReadAdvance<ReadAdrBase, 0>; 151 def : ReadAdvance<ReadVLD, 0>; 152 153 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable 154 // operands are needed one cycle later if and only if they are to be 155 // shifted. Otherwise, they too are needed two cycles later. This same 156 // ReadAdvance applies to Extended registers as well, even though there is 157 // a separate SchedPredicate for them. 158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, 159 WriteISReg, WriteIEReg,WriteIS, 160 WriteID32,WriteID64, 161 WriteIM32,WriteIM64]>; 162 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI, 163 WriteISReg, WriteIEReg,WriteIS, 164 WriteID32,WriteID64, 165 WriteIM32,WriteIM64]>; 166 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI, 167 WriteISReg, WriteIEReg,WriteIS, 168 WriteID32,WriteID64, 169 WriteIM32,WriteIM64]>; 170 def A53ReadISReg : SchedReadVariant<[ 171 SchedVar<RegShiftedPred, [A53ReadShifted]>, 172 SchedVar<NoSchedPred, [A53ReadNotShifted]>]>; 173 def : SchedAlias<ReadISReg, A53ReadISReg>; 174 175 def A53ReadIEReg : SchedReadVariant<[ 176 SchedVar<RegExtendedPred, [A53ReadShifted]>, 177 SchedVar<NoSchedPred, [A53ReadNotShifted]>]>; 178 def : SchedAlias<ReadIEReg, A53ReadIEReg>; 179 180 // MAC - Operands are generally needed one cycle later in the MAC pipe. 181 // Accumulator operands are needed two cycles later. 182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, 183 WriteISReg, WriteIEReg,WriteIS, 184 WriteID32,WriteID64, 185 WriteIM32,WriteIM64]>; 186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI, 187 WriteISReg, WriteIEReg,WriteIS, 188 WriteID32,WriteID64, 189 WriteIM32,WriteIM64]>; 190 191 // Div 192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI, 193 WriteISReg, WriteIEReg,WriteIS, 194 WriteID32,WriteID64, 195 WriteIM32,WriteIM64]>; 196 197 //===----------------------------------------------------------------------===// 198 // Subtarget-specific InstRWs. 199 200 //--- 201 // Miscellaneous 202 //--- 203 def : InstRW<[WriteI], (instrs COPY)>; 204 205 //--- 206 // Vector Loads 207 //--- 208 def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; 209 def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 210 def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 211 def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 212 def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 213 def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 214 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; 215 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 216 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 217 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 218 def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 219 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 220 221 def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>; 222 def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 223 def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>; 224 def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 225 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; 226 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 227 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 228 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 229 230 def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>; 231 def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 232 def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 233 def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>; 234 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; 235 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 236 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 237 def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>; 238 239 def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; 240 def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 241 def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 242 def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>; 243 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; 244 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 245 def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 246 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 247 248 //--- 249 // Vector Stores 250 //--- 251 def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>; 252 def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 253 def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 254 def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 255 def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 256 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; 257 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 258 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 259 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 260 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 261 262 def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>; 263 def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>; 264 def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 265 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; 266 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 267 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 268 269 def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>; 270 def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 271 def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>; 272 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; 273 def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 274 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 275 276 def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>; 277 def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 278 def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>; 279 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; 280 def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 281 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 282 283 //--- 284 // Floating Point MAC, DIV, SQRT 285 //--- 286 def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>; 287 def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>; 288 def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>; 289 def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>; 290 def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>; 291 def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>; 292 def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>; 293 def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>; 294 295 } 296
