1 //=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach 11 // below is to define a generic SchedWriteRes for every combination of 12 // latency and microOps. The naming conventions is to use a prefix, one field 13 // for latency, and one or more microOp count/type designators. 14 // Prefix: A57Write 15 // Latency: #cyc 16 // MicroOp Count/Types: #(B|I|M|L|S|X|W|V) 17 // 18 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are 19 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes. 20 // 21 //===----------------------------------------------------------------------===// 22 23 //===----------------------------------------------------------------------===// 24 // Define Generic 1 micro-op types 25 26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; } 27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; } 28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; } 29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; } 31 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17; 32 let ResourceCycles = [17]; } 33 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; 34 let ResourceCycles = [19]; } 35 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } 36 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } 37 def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } 38 def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } 39 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32; 40 let ResourceCycles = [32]; } 41 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; 42 let ResourceCycles = [35]; } 43 def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; } 44 def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; } 45 def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; } 46 def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; } 47 def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; } 48 def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 49 def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 50 def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } 51 def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; } 52 53 54 //===----------------------------------------------------------------------===// 55 // Define Generic 2 micro-op types 56 57 def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 58 let Latency = 64; 59 let NumMicroOps = 2; 60 let ResourceCycles = [32, 32]; 61 } 62 def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI, 63 A57UnitL]> { 64 let Latency = 6; 65 let NumMicroOps = 2; 66 } 67 def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV, 68 A57UnitX]> { 69 let Latency = 7; 70 let NumMicroOps = 2; 71 } 72 def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL, 73 A57UnitV]> { 74 let Latency = 8; 75 let NumMicroOps = 2; 76 } 77 def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 78 let Latency = 9; 79 let NumMicroOps = 2; 80 } 81 def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 82 let Latency = 8; 83 let NumMicroOps = 2; 84 } 85 def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> { 86 let Latency = 6; 87 let NumMicroOps = 2; 88 } 89 def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 90 let Latency = 6; 91 let NumMicroOps = 2; 92 } 93 def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 94 let Latency = 6; 95 let NumMicroOps = 2; 96 } 97 def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI, 98 A57UnitL]> { 99 let Latency = 5; 100 let NumMicroOps = 2; 101 } 102 def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 103 let Latency = 5; 104 let NumMicroOps = 2; 105 } 106 def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 107 let Latency = 5; 108 let NumMicroOps = 2; 109 } 110 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL, 111 A57UnitV]> { 112 let Latency = 10; 113 let NumMicroOps = 2; 114 } 115 def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 116 let Latency = 10; 117 let NumMicroOps = 2; 118 } 119 def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB, 120 A57UnitI]> { 121 let Latency = 1; 122 let NumMicroOps = 2; 123 } 124 def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI, 125 A57UnitS]> { 126 let Latency = 1; 127 let NumMicroOps = 2; 128 } 129 def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB, 130 A57UnitI]> { 131 let Latency = 2; 132 let NumMicroOps = 2; 133 } 134 def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> { 135 let Latency = 2; 136 let NumMicroOps = 2; 137 } 138 def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 139 let Latency = 2; 140 let NumMicroOps = 2; 141 } 142 def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 143 let Latency = 34; 144 let NumMicroOps = 2; 145 let ResourceCycles = [17, 17]; 146 } 147 def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI, 148 A57UnitM]> { 149 let Latency = 3; 150 let NumMicroOps = 2; 151 } 152 def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI, 153 A57UnitS]> { 154 let Latency = 3; 155 let NumMicroOps = 2; 156 } 157 def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS, 158 A57UnitV]> { 159 let Latency = 3; 160 let NumMicroOps = 2; 161 } 162 def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 163 let Latency = 3; 164 let NumMicroOps = 2; 165 } 166 def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI, 167 A57UnitL]> { 168 let Latency = 4; 169 let NumMicroOps = 2; 170 } 171 def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 172 let Latency = 4; 173 let NumMicroOps = 2; 174 } 175 176 177 //===----------------------------------------------------------------------===// 178 // Define Generic 3 micro-op types 179 180 def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 181 let Latency = 10; 182 let NumMicroOps = 3; 183 } 184 def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI, 185 A57UnitS, A57UnitS]> { 186 let Latency = 2; 187 let NumMicroOps = 3; 188 } 189 def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI, 190 A57UnitS, 191 A57UnitV]> { 192 let Latency = 3; 193 let NumMicroOps = 3; 194 } 195 def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM, 196 A57UnitS, A57UnitS]> { 197 let Latency = 3; 198 let NumMicroOps = 3; 199 } 200 def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> { 201 let Latency = 3; 202 let NumMicroOps = 3; 203 } 204 def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS, 205 A57UnitV]> { 206 let Latency = 3; 207 let NumMicroOps = 3; 208 } 209 def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI, 210 A57UnitL, A57UnitL]> { 211 let Latency = 5; 212 let NumMicroOps = 3; 213 } 214 def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI, 215 A57UnitL, A57UnitL]> { 216 let Latency = 6; 217 let NumMicroOps = 3; 218 } 219 def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 220 let Latency = 6; 221 let NumMicroOps = 3; 222 } 223 def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> { 224 let Latency = 7; 225 let NumMicroOps = 3; 226 } 227 def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI, 228 A57UnitL, 229 A57UnitV]> { 230 let Latency = 8; 231 let NumMicroOps = 3; 232 } 233 def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL, 234 A57UnitV, A57UnitV]> { 235 let Latency = 8; 236 let NumMicroOps = 3; 237 } 238 def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 239 let Latency = 8; 240 let NumMicroOps = 3; 241 } 242 def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 243 let Latency = 9; 244 let NumMicroOps = 3; 245 } 246 247 248 //===----------------------------------------------------------------------===// 249 // Define Generic 4 micro-op types 250 251 def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 252 A57UnitS, A57UnitS]> { 253 let Latency = 2; 254 let NumMicroOps = 4; 255 } 256 def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 257 A57UnitS, A57UnitS]> { 258 let Latency = 3; 259 let NumMicroOps = 4; 260 } 261 def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI, 262 A57UnitS, A57UnitS, A57UnitS]> { 263 let Latency = 3; 264 let NumMicroOps = 4; 265 } 266 def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI, 267 A57UnitS, A57UnitS, 268 A57UnitV]> { 269 let Latency = 3; 270 let NumMicroOps = 4; 271 } 272 def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS, 273 A57UnitS, A57UnitS]> { 274 let Latency = 4; 275 let NumMicroOps = 4; 276 } 277 def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI, 278 A57UnitL, A57UnitL, A57UnitL]> { 279 let Latency = 7; 280 let NumMicroOps = 4; 281 } 282 def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI, 283 A57UnitL, A57UnitL]> { 284 let Latency = 5; 285 let NumMicroOps = 4; 286 } 287 def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI, 288 A57UnitL, 289 A57UnitV, A57UnitV]> { 290 let Latency = 8; 291 let NumMicroOps = 4; 292 } 293 def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL, 294 A57UnitL, A57UnitL]> { 295 let Latency = 8; 296 let NumMicroOps = 4; 297 } 298 def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL, 299 A57UnitV, A57UnitV]> { 300 let Latency = 9; 301 let NumMicroOps = 4; 302 } 303 def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL, 304 A57UnitV, A57UnitV, A57UnitV]> { 305 let Latency = 9; 306 let NumMicroOps = 4; 307 } 308 def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV, 309 A57UnitV, A57UnitV]> { 310 let Latency = 12; 311 let NumMicroOps = 4; 312 } 313 314 315 //===----------------------------------------------------------------------===// 316 // Define Generic 5 micro-op types 317 318 def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 319 A57UnitV, A57UnitV]> { 320 let Latency = 3; 321 let NumMicroOps = 5; 322 } 323 def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI, 324 A57UnitL, A57UnitL, 325 A57UnitL, A57UnitL]> { 326 let Latency = 8; 327 let NumMicroOps = 5; 328 } 329 def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI, 330 A57UnitS, A57UnitS, 331 A57UnitS, A57UnitS]> { 332 let Latency = 4; 333 let NumMicroOps = 5; 334 } 335 def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI, 336 A57UnitL, A57UnitL, 337 A57UnitV, A57UnitV]> { 338 let Latency = 9; 339 let NumMicroOps = 5; 340 } 341 def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI, 342 A57UnitL, 343 A57UnitV, A57UnitV, A57UnitV]> { 344 let Latency = 9; 345 let NumMicroOps = 5; 346 } 347 def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL, 348 A57UnitV, A57UnitV, A57UnitV]> { 349 let Latency = 9; 350 let NumMicroOps = 5; 351 } 352 def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 353 A57UnitV, A57UnitV]> { 354 let Latency = 9; 355 let NumMicroOps = 5; 356 } 357 358 359 //===----------------------------------------------------------------------===// 360 // Define Generic 6 micro-op types 361 362 def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI, 363 A57UnitS, A57UnitS, A57UnitS, 364 A57UnitV, A57UnitV]> { 365 let Latency = 3; 366 let NumMicroOps = 6; 367 } 368 def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI, 369 A57UnitS, A57UnitS, 370 A57UnitS, A57UnitS]> { 371 let Latency = 4; 372 let NumMicroOps = 6; 373 } 374 def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS, 375 A57UnitS, A57UnitS, 376 A57UnitV, A57UnitV]> { 377 let Latency = 4; 378 let NumMicroOps = 6; 379 } 380 def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 381 A57UnitS, A57UnitS, A57UnitS]> { 382 let Latency = 6; 383 let NumMicroOps = 6; 384 } 385 def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI, 386 A57UnitL, A57UnitL, 387 A57UnitV, A57UnitV, A57UnitV]> { 388 let Latency = 9; 389 let NumMicroOps = 6; 390 } 391 def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI, 392 A57UnitL, 393 A57UnitV, A57UnitV, 394 A57UnitV, A57UnitV]> { 395 let Latency = 9; 396 let NumMicroOps = 6; 397 } 398 def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 399 A57UnitV, A57UnitV, 400 A57UnitV, A57UnitV]> { 401 let Latency = 9; 402 let NumMicroOps = 6; 403 } 404 405 406 //===----------------------------------------------------------------------===// 407 // Define Generic 7 micro-op types 408 409 def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, 410 A57UnitV, A57UnitV, 411 A57UnitV, A57UnitV]> { 412 let Latency = 10; 413 let NumMicroOps = 7; 414 } 415 def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI, 416 A57UnitS, A57UnitS, 417 A57UnitS, A57UnitS, 418 A57UnitV, A57UnitV]> { 419 let Latency = 4; 420 let NumMicroOps = 7; 421 } 422 def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI, 423 A57UnitS, A57UnitS, A57UnitS, 424 A57UnitS, A57UnitS, A57UnitS]> { 425 let Latency = 6; 426 let NumMicroOps = 7; 427 } 428 def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI, 429 A57UnitL, A57UnitL, 430 A57UnitV, A57UnitV, 431 A57UnitV, A57UnitV]> { 432 let Latency = 9; 433 let NumMicroOps = 7; 434 } 435 def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 436 A57UnitV, A57UnitV, 437 A57UnitV, A57UnitV]> { 438 let Latency = 12; 439 let NumMicroOps = 7; 440 } 441 442 443 //===----------------------------------------------------------------------===// 444 // Define Generic 8 micro-op types 445 446 def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI, 447 A57UnitL, A57UnitL, A57UnitL, 448 A57UnitV, A57UnitV, 449 A57UnitV, A57UnitV]> { 450 let Latency = 10; 451 let NumMicroOps = 8; 452 } 453 def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 454 A57UnitL, A57UnitL, 455 A57UnitV, A57UnitV, 456 A57UnitV, A57UnitV]> { 457 let Latency = 11; 458 let NumMicroOps = 8; 459 } 460 def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS, 461 A57UnitS, A57UnitS, 462 A57UnitS, A57UnitS, 463 A57UnitS, A57UnitS]> { 464 let Latency = 8; 465 let NumMicroOps = 8; 466 } 467 468 469 //===----------------------------------------------------------------------===// 470 // Define Generic 9 micro-op types 471 472 def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI, 473 A57UnitS, A57UnitS, 474 A57UnitS, A57UnitS, 475 A57UnitS, A57UnitS, 476 A57UnitS, A57UnitS]> { 477 let Latency = 8; 478 let NumMicroOps = 9; 479 } 480 def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI, 481 A57UnitL, A57UnitL, 482 A57UnitL, A57UnitL, 483 A57UnitV, A57UnitV, 484 A57UnitV, A57UnitV]> { 485 let Latency = 11; 486 let NumMicroOps = 9; 487 } 488 def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 489 A57UnitV, A57UnitV, A57UnitV, 490 A57UnitV, A57UnitV, A57UnitV]> { 491 let Latency = 15; 492 let NumMicroOps = 9; 493 } 494 495 496 //===----------------------------------------------------------------------===// 497 // Define Generic 10 micro-op types 498 499 def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 500 A57UnitS, A57UnitS, A57UnitS, 501 A57UnitV, A57UnitV, 502 A57UnitV, A57UnitV]> { 503 let Latency = 6; 504 let NumMicroOps = 10; 505 } 506 507 508 //===----------------------------------------------------------------------===// 509 // Define Generic 11 micro-op types 510 511 def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI, 512 A57UnitS, A57UnitS, A57UnitS, 513 A57UnitS, A57UnitS, A57UnitS, 514 A57UnitV, A57UnitV, 515 A57UnitV, A57UnitV]> { 516 let Latency = 6; 517 let NumMicroOps = 11; 518 } 519 520 521 //===----------------------------------------------------------------------===// 522 // Define Generic 12 micro-op types 523 524 def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, 525 A57UnitS, A57UnitS, A57UnitS, A57UnitS, 526 A57UnitV, A57UnitV, 527 A57UnitV, A57UnitV]> { 528 let Latency = 8; 529 let NumMicroOps = 12; 530 } 531 532 //===----------------------------------------------------------------------===// 533 // Define Generic 13 micro-op types 534 535 def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI, 536 A57UnitS, A57UnitS, A57UnitS, 537 A57UnitS, A57UnitS, A57UnitS, 538 A57UnitS, A57UnitS, 539 A57UnitV, A57UnitV, 540 A57UnitV, A57UnitV]> { 541 let Latency = 8; 542 let NumMicroOps = 13; 543 } 544 545
