1 //=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the machine model for the Samsung Exynos M3 to support 11 // instruction scheduling and other instruction cost heuristics. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 17 // in-order stage for decode and dispatch and a wider issue stage. 18 // The execution units and loads and stores are out-of-order. 19 20 def ExynosM3Model : SchedMachineModel { 21 let IssueWidth = 6; // Up to 6 uops per cycle. 22 let MicroOpBufferSize = 228; // ROB size. 23 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 24 let LoadLatency = 4; // Optimistic load cases. 25 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 26 let CompleteModel = 1; // Use the default model otherwise. 27 28 list<Predicate> UnsupportedFeatures = [HasSVE]; 29 30 // FIXME: Remove when all errors have been fixed. 31 let FullInstRWOverlapCheck = 0; 32 } 33 34 //===----------------------------------------------------------------------===// 35 // Define each kind of processor resource and number available on the Exynos-M3, 36 // which has 12 pipelines, each with its own queue with out-of-order dispatch. 37 38 let SchedModel = ExynosM3Model in { 39 40 def M3UnitA : ProcResource<2>; // Simple integer 41 def M3UnitC : ProcResource<2>; // Simple and complex integer 42 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 43 def M3UnitB : ProcResource<2>; // Branch 44 def M3UnitL : ProcResource<2>; // Load 45 def M3UnitS : ProcResource<1>; // Store 46 def M3PipeF0 : ProcResource<1>; // FP #0 47 let Super = M3PipeF0 in { 48 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 49 def M3UnitFADD0 : ProcResource<1>; // Simple FP 50 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 51 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 52 def M3UnitNALU0 : ProcResource<1>; // Simple vector 53 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 54 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 55 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 56 } 57 def M3PipeF1 : ProcResource<1>; // FP #1 58 let Super = M3PipeF1 in { 59 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 60 def M3UnitFADD1 : ProcResource<1>; // Simple FP 61 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 62 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 63 def M3UnitFST0 : ProcResource<1>; // FP store 64 def M3UnitNALU1 : ProcResource<1>; // Simple vector 65 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 66 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 67 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 68 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 69 } 70 def M3PipeF2 : ProcResource<1>; // FP #2 71 let Super = M3PipeF2 in { 72 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 73 def M3UnitFADD2 : ProcResource<1>; // Simple FP 74 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 75 def M3UnitFST1 : ProcResource<1>; // FP store 76 def M3UnitNALU2 : ProcResource<1>; // Simple vector 77 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 78 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 79 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 80 } 81 82 83 def M3UnitALU : ProcResGroup<[M3UnitA, 84 M3UnitC]>; 85 def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 86 M3UnitFMAC1, 87 M3UnitFMAC2]>; 88 def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 89 M3UnitFADD1, 90 M3UnitFADD2]>; 91 def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 92 M3UnitFDIV1]>; 93 def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 94 M3UnitFCVT1]>; 95 def M3UnitFST : ProcResGroup<[M3UnitFST0, 96 M3UnitFST1]>; 97 def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 98 M3UnitNALU1, 99 M3UnitNALU2]>; 100 def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 101 M3UnitNCRY1]>; 102 def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 103 M3UnitNSHT1, 104 M3UnitNSHT2]>; 105 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 106 M3UnitNSHF1, 107 M3UnitNSHF2]>; 108 109 //===----------------------------------------------------------------------===// 110 // Predicates. 111 112 def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR && 113 MI->getOperand(0).isReg() && 114 MI->getOperand(0).getReg() != AArch64::LR}]>; 115 def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>; 116 def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri || 117 MI->getOpcode() == AArch64::EXTRXrri) && 118 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() && 119 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>; 120 def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>; 121 122 //===----------------------------------------------------------------------===// 123 // Coarse scheduling model. 124 125 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 126 let NumMicroOps = 1; } 127 128 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 129 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 130 let ResourceCycles = [2]; } 131 def M3WriteAB : SchedWriteRes<[M3UnitALU, 132 M3UnitC]> { let Latency = 1; 133 let NumMicroOps = 2; } 134 def M3WriteAC : SchedWriteRes<[M3UnitALU, 135 M3UnitALU, 136 M3UnitC]> { let Latency = 2; 137 let NumMicroOps = 3; } 138 def M3WriteAD : SchedWriteRes<[M3UnitALU, 139 M3UnitC]> { let Latency = 2; 140 let NumMicroOps = 2; } 141 def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 142 def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 143 def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>, 144 SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>, 145 SchedVar<NoSchedPred, [M3WriteAA]>]>; 146 def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>, 147 SchedVar<NoSchedPred, [M3WriteAA]>]>; 148 149 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 150 def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>, 151 SchedVar<NoSchedPred, [M3WriteAC]>]>; 152 153 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 154 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 155 def M3WriteLA : SchedWriteRes<[M3UnitL, 156 M3UnitL]> { let Latency = 5; 157 let NumMicroOps = 1; } 158 def M3WriteLB : SchedWriteRes<[M3UnitA, 159 M3UnitL]> { let Latency = 5; 160 let NumMicroOps = 2; } 161 def M3WriteLC : SchedWriteRes<[M3UnitA, 162 M3UnitL, 163 M3UnitL]> { let Latency = 5; 164 let NumMicroOps = 2; } 165 def M3WriteLD : SchedWriteRes<[M3UnitA, 166 M3UnitL]> { let Latency = 4; 167 let NumMicroOps = 2; } 168 def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 169 let NumMicroOps = 0; } 170 171 def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteL5]>, 172 SchedVar<NoSchedPred, [M3WriteLB]>]>; 173 174 def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 175 def M3WriteSA : SchedWriteRes<[M3UnitA, 176 M3UnitS, 177 M3UnitFST]> { let Latency = 2; 178 let NumMicroOps = 2; } 179 def M3WriteSB : SchedWriteRes<[M3UnitA, 180 M3UnitS]> { let Latency = 1; 181 let NumMicroOps = 2; } 182 def M3WriteSC : SchedWriteRes<[M3UnitA, 183 M3UnitS]> { let Latency = 2; 184 let NumMicroOps = 2; } 185 186 def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>, 187 SchedVar<NoSchedPred, [M3WriteSB]>]>; 188 def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>, 189 SchedVar<NoSchedPred, [M3WriteSC]>]>; 190 191 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>, 192 SchedVar<NoSchedPred, [ReadDefault]>]>; 193 194 // Branch instructions. 195 def : SchedAlias<WriteBr, M3WriteZ0>; 196 def : WriteRes<WriteBrReg, [M3UnitC]> { let Latency = 1; } 197 198 // Arithmetic and logical integer instructions. 199 def : WriteRes<WriteI, [M3UnitALU]> { let Latency = 1; } 200 def : WriteRes<WriteISReg, [M3UnitALU]> { let Latency = 1; } 201 def : WriteRes<WriteIEReg, [M3UnitALU]> { let Latency = 1; } 202 def : WriteRes<WriteIS, [M3UnitALU]> { let Latency = 1; } 203 204 // Move instructions. 205 def : WriteRes<WriteImm, [M3UnitALU]> { let Latency = 1; } 206 207 // Divide and multiply instructions. 208 def : WriteRes<WriteID32, [M3UnitC, 209 M3UnitD]> { let Latency = 12; 210 let ResourceCycles = [1, 12]; } 211 def : WriteRes<WriteID64, [M3UnitC, 212 M3UnitD]> { let Latency = 21; 213 let ResourceCycles = [1, 21]; } 214 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 215 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 216 let ResourceCycles = [2]; } 217 218 // Miscellaneous instructions. 219 def : WriteRes<WriteExtr, [M3UnitALU, 220 M3UnitALU]> { let Latency = 1; 221 let NumMicroOps = 2; } 222 223 // Addressing modes. 224 def : WriteRes<WriteAdr, []> { let Latency = 1; 225 let NumMicroOps = 0; } 226 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 227 228 // Load instructions. 229 def : SchedAlias<WriteLD, M3WriteL4>; 230 def : WriteRes<WriteLDHi, []> { let Latency = 4; 231 let NumMicroOps = 0; } 232 def : SchedAlias<WriteLDIdx, M3WriteLX>; 233 234 // Store instructions. 235 def : SchedAlias<WriteST, M3WriteS1>; 236 def : SchedAlias<WriteSTP, M3WriteS1>; 237 def : SchedAlias<WriteSTX, M3WriteS1>; 238 def : SchedAlias<WriteSTIdx, M3WriteSX>; 239 240 // FP data instructions. 241 def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 242 def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 243 def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 244 let ResourceCycles = [12]; } 245 def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 246 247 // FP miscellaneous instructions. 248 // TODO: Conversion between register files is much different. 249 def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 250 def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 251 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 252 253 // FP load instructions. 254 def : SchedAlias<WriteVLD, M3WriteL5>; 255 256 // FP store instructions. 257 def : WriteRes<WriteVST, [M3UnitS, 258 M3UnitFST]> { let Latency = 1; 259 let NumMicroOps = 1; } 260 261 // ASIMD FP instructions. 262 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; } 263 264 // Other miscellaneous instructions. 265 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 266 def : WriteRes<WriteBarrier, []> { let Latency = 1; } 267 def : WriteRes<WriteHint, []> { let Latency = 1; } 268 def : WriteRes<WriteSys, []> { let Latency = 1; } 269 270 //===----------------------------------------------------------------------===// 271 // Generic fast forwarding. 272 273 // TODO: Add FP register forwarding rules. 274 275 def : ReadAdvance<ReadI, 0>; 276 def : ReadAdvance<ReadISReg, 0>; 277 def : ReadAdvance<ReadIEReg, 0>; 278 def : ReadAdvance<ReadIM, 0>; 279 // TODO: The forwarding for 32 bits actually saves 2 cycles. 280 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 281 def : ReadAdvance<ReadID, 0>; 282 def : ReadAdvance<ReadExtrHi, 0>; 283 def : ReadAdvance<ReadAdrBase, 0>; 284 def : ReadAdvance<ReadVLD, 0>; 285 286 //===----------------------------------------------------------------------===// 287 // Finer scheduling model. 288 289 def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 290 M3UnitFADD]> { let Latency = 3; 291 let NumMicroOps = 2; } 292 def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 293 M3UnitFST]> { let Latency = 10; 294 let NumMicroOps = 2; } 295 def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 296 M3UnitFST]> { let Latency = 6; 297 let NumMicroOps = 2; } 298 def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 299 M3UnitS]> { let Latency = 5; 300 let NumMicroOps = 2; } 301 def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 302 M3UnitS]> { let Latency = 5; 303 let NumMicroOps = 2; } 304 def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 305 M3UnitFDIV1]> { let Latency = 7; 306 let NumMicroOps = 2; 307 let ResourceCycles = [8, 8]; } 308 def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 309 M3UnitFDIV1]> { let Latency = 12; 310 let NumMicroOps = 2; 311 let ResourceCycles = [13, 13]; } 312 def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 313 M3UnitFSQR]> { let Latency = 18; 314 let NumMicroOps = 2; 315 let ResourceCycles = [19, 19]; } 316 def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 317 M3UnitFSQR]> { let Latency = 25; 318 let NumMicroOps = 2; 319 let ResourceCycles = [26, 26]; } 320 def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 321 M3UnitNMSC]> { let Latency = 5; 322 let NumMicroOps = 2; } 323 def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 324 def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 325 def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 326 def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 327 def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 328 def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 329 def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 330 let ResourceCycles = [8]; } 331 def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 332 let ResourceCycles = [13]; } 333 def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 334 def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 335 def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 336 def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 337 let ResourceCycles = [19]; } 338 def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 339 let ResourceCycles = [26]; } 340 def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 341 def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 342 def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 343 def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 344 def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 345 def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 346 def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 347 def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 348 def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 349 def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 350 def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 351 def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 352 def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 353 def M3WriteVLDA : SchedWriteRes<[M3UnitL, 354 M3UnitL]> { let Latency = 5; 355 let NumMicroOps = 2; } 356 def M3WriteVLDB : SchedWriteRes<[M3UnitL, 357 M3UnitL, 358 M3UnitL]> { let Latency = 6; 359 let NumMicroOps = 3; } 360 def M3WriteVLDC : SchedWriteRes<[M3UnitL, 361 M3UnitL, 362 M3UnitL, 363 M3UnitL]> { let Latency = 6; 364 let NumMicroOps = 4; } 365 def M3WriteVLDD : SchedWriteRes<[M3UnitL, 366 M3UnitNALU]> { let Latency = 7; 367 let NumMicroOps = 2; 368 let ResourceCycles = [2, 1]; } 369 def M3WriteVLDE : SchedWriteRes<[M3UnitL, 370 M3UnitNALU]> { let Latency = 6; 371 let NumMicroOps = 2; 372 let ResourceCycles = [2, 1]; } 373 def M3WriteVLDF : SchedWriteRes<[M3UnitL, 374 M3UnitL]> { let Latency = 10; 375 let NumMicroOps = 2; 376 let ResourceCycles = [5, 5]; } 377 def M3WriteVLDG : SchedWriteRes<[M3UnitL, 378 M3UnitNALU, 379 M3UnitNALU]> { let Latency = 7; 380 let NumMicroOps = 3; 381 let ResourceCycles = [2, 1, 1]; } 382 def M3WriteVLDH : SchedWriteRes<[M3UnitL, 383 M3UnitNALU, 384 M3UnitNALU]> { let Latency = 6; 385 let NumMicroOps = 3; 386 let ResourceCycles = [2, 1, 1]; } 387 def M3WriteVLDI : SchedWriteRes<[M3UnitL, 388 M3UnitL, 389 M3UnitL]> { let Latency = 12; 390 let NumMicroOps = 3; 391 let ResourceCycles = [6, 6, 6]; } 392 def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 393 M3UnitNALU, 394 M3UnitNALU, 395 M3UnitNALU]> { let Latency = 7; 396 let NumMicroOps = 4; 397 let ResourceCycles = [2, 1, 1, 1]; } 398 def M3WriteVLDK : SchedWriteRes<[M3UnitL, 399 M3UnitNALU, 400 M3UnitNALU, 401 M3UnitNALU, 402 M3UnitNALU]> { let Latency = 9; 403 let NumMicroOps = 5; 404 let ResourceCycles = [4, 1, 1, 1, 1]; } 405 def M3WriteVLDL : SchedWriteRes<[M3UnitL, 406 M3UnitNALU, 407 M3UnitNALU, 408 M3UnitL, 409 M3UnitNALU]> { let Latency = 6; 410 let NumMicroOps = 5; 411 let ResourceCycles = [6, 1, 1, 6, 1]; } 412 def M3WriteVLDM : SchedWriteRes<[M3UnitL, 413 M3UnitNALU, 414 M3UnitNALU, 415 M3UnitL, 416 M3UnitNALU, 417 M3UnitNALU]> { let Latency = 7; 418 let NumMicroOps = 6; 419 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 420 def M3WriteVLDN : SchedWriteRes<[M3UnitL, 421 M3UnitL, 422 M3UnitL, 423 M3UnitL]> { let Latency = 14; 424 let NumMicroOps = 4; 425 let ResourceCycles = [6, 6, 6, 6]; } 426 def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 427 def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 428 def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 429 def M3WriteVSTD : SchedWriteRes<[M3UnitS, 430 M3UnitFST, 431 M3UnitS, 432 M3UnitFST]> { let Latency = 7; 433 let NumMicroOps = 4; 434 let ResourceCycles = [1, 3, 1, 3]; } 435 def M3WriteVSTE : SchedWriteRes<[M3UnitS, 436 M3UnitFST, 437 M3UnitS, 438 M3UnitFST, 439 M3UnitS, 440 M3UnitFST]> { let Latency = 8; 441 let NumMicroOps = 6; 442 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 443 def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 444 M3UnitFST, 445 M3UnitFST, 446 M3UnitS, 447 M3UnitFST, 448 M3UnitS, 449 M3UnitFST]> { let Latency = 15; 450 let NumMicroOps = 7; 451 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 452 def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 453 M3UnitFST, 454 M3UnitFST, 455 M3UnitS, 456 M3UnitFST, 457 M3UnitS, 458 M3UnitFST, 459 M3UnitS, 460 M3UnitFST]> { let Latency = 16; 461 let NumMicroOps = 9; 462 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 463 def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 464 M3UnitFST, 465 M3UnitFST, 466 M3UnitS, 467 M3UnitFST]> { let Latency = 14; 468 let NumMicroOps = 5; 469 let ResourceCycles = [1, 3, 3, 1, 3]; } 470 def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 471 M3UnitFST, 472 M3UnitFST, 473 M3UnitS, 474 M3UnitFST, 475 M3UnitS, 476 M3UnitFST, 477 M3UnitS, 478 M3UnitFST]> { let Latency = 17; 479 let NumMicroOps = 9; 480 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 481 482 // Special cases. 483 def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 484 def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 485 def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 486 M3WriteFMAC5]>; 487 def M3WriteMOVI : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>, 488 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 489 def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 490 491 // Branch instructions 492 def : InstRW<[M3WriteB1], (instrs Bcc)>; 493 def : InstRW<[M3WriteA1], (instrs BL)>; 494 def : InstRW<[M3WriteBX], (instrs BLR)>; 495 def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 496 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 497 498 // Arithmetic and logical integer instructions. 499 def : InstRW<[M3WriteA1], (instrs COPY)>; 500 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?Xrx64")>; 501 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[sx]$")>; 502 def : InstRW<[M3WriteAX], (instregex "^(ADD|BIC|SUB)S[WX]r[sx]$")>; 503 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|EOR|ORR|SUB)[WX]ri")>; 504 505 // Move instructions. 506 def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 507 def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 508 509 // Divide and multiply instructions. 510 511 // Miscellaneous instructions. 512 def : InstRW<[M3WriteAY], (instrs EXTRWrri, EXTRXrri)>; 513 514 // Load instructions. 515 def : InstRW<[M3WriteLD, 516 WriteLDHi, 517 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 518 def : InstRW<[M3WriteLX, 519 ReadAdrBase], (instregex "^PRFMro[WX]")>; 520 521 // Store instructions. 522 523 // FP data instructions. 524 def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 525 def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 526 def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 527 def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 528 def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 529 def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 530 def : InstRW<[M3WriteFMAC4, 531 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 532 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 533 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 534 def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 535 def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 536 def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 537 538 // FP miscellaneous instructions. 539 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 540 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 541 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 542 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 543 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 544 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 545 def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 546 def : InstRW<[M3WriteFMAC4, 547 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 548 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 549 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 550 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 551 552 // FP load instructions. 553 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 554 def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 555 def : InstRW<[WriteVLD, 556 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 557 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 558 def : InstRW<[M3WriteLX, 559 ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>; 560 def : InstRW<[M3WriteLB, 561 ReadAdrBase], (instregex "^LDRQro[WX]")>; 562 def : InstRW<[WriteVLD, 563 M3WriteLH], (instregex "^LDN?P[DS]i")>; 564 def : InstRW<[M3WriteLA, 565 M3WriteLH], (instregex "^LDN?PQi")>; 566 def : InstRW<[M3WriteLB, 567 M3WriteLH, 568 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 569 def : InstRW<[M3WriteLC, 570 M3WriteLH, 571 WriteAdr], (instregex "^LDPQ(post|pre)")>; 572 573 // FP store instructions. 574 def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 575 def : InstRW<[WriteVST, 576 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 577 def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 578 def : InstRW<[M3WriteSY, 579 ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>; 580 def : InstRW<[M3WriteSA, 581 ReadAdrBase], (instregex "^STRQro[WX]")>; 582 def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 583 def : InstRW<[WriteVST, 584 WriteAdr], (instregex "^STP[DS](post|pre)")>; 585 def : InstRW<[M3WriteSA, 586 WriteAdr], (instregex "^STPQ(post|pre)")>; 587 588 // ASIMD instructions. 589 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 590 def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 591 def : InstRW<[M3WriteNMSC1], (instregex "^(SQ)?(ABS|NEG)v")>; 592 def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 593 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 594 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 595 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 596 def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 597 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 598 def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 599 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 600 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Vv")>; 601 def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 602 def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 603 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 604 def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 605 def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 606 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 607 def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 608 def : InstRW<[M3WriteNMUL3, 609 M3ReadNMUL], (instregex "^ML[AS]v")>; 610 def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 611 def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 612 def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 613 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 614 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 615 def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 616 def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 617 def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 618 def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 619 def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 620 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 621 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 622 623 // ASIMD FP instructions. 624 def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 625 def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 626 def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 627 def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 628 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 629 def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 630 def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 631 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 632 def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 633 def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 634 def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 635 def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 636 def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 637 def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 638 def : InstRW<[M3WriteFMAC4, 639 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 640 def : InstRW<[M3WriteFMAC5, 641 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 642 def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 643 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 644 def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 645 def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 646 def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 647 648 // ASIMD miscellaneous instructions. 649 def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 650 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 651 def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 652 def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 653 def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 654 def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 655 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 656 def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 657 def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 658 def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 659 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 660 def : InstRW<[M3WriteFMAC4, 661 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 662 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 663 def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 664 def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 665 def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 666 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 667 668 // ASIMD load instructions. 669 def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 670 def : InstRW<[M3WriteL5, 671 WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 672 def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 673 def : InstRW<[M3WriteL5, 674 WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 675 676 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 677 def : InstRW<[M3WriteVLDA, 678 WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 679 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 680 def : InstRW<[M3WriteVLDA, 681 WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 682 683 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 684 def : InstRW<[M3WriteVLDB, 685 WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 686 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 687 def : InstRW<[M3WriteVLDB, 688 WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 689 690 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 691 def : InstRW<[M3WriteVLDC, 692 WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 693 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 694 def : InstRW<[M3WriteVLDC, 695 WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 696 697 def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 698 def : InstRW<[M3WriteVLDD, 699 WriteAdr], (instregex "LD1i(8|16|32)_POST")>; 700 def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 701 def : InstRW<[M3WriteVLDE, 702 WriteAdr], (instregex "LD1i(64)_POST")>; 703 704 def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 705 def : InstRW<[M3WriteL5, 706 WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 707 def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 708 def : InstRW<[M3WriteL5, 709 WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 710 711 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 712 def : InstRW<[M3WriteVLDF, 713 WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST")>; 714 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 715 def : InstRW<[M3WriteVLDF, 716 WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 717 718 def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 719 def : InstRW<[M3WriteVLDG, 720 WriteAdr], (instregex "LD2i(8|16|32)_POST")>; 721 def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 722 def : InstRW<[M3WriteVLDH, 723 WriteAdr], (instregex "LD2i(64)_POST")>; 724 725 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 726 def : InstRW<[M3WriteVLDA, 727 WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 728 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 729 def : InstRW<[M3WriteVLDA, 730 WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 731 732 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 733 def : InstRW<[M3WriteVLDI, 734 WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST")>; 735 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 736 def : InstRW<[M3WriteVLDI, 737 WriteAdr], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 738 739 def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 740 def : InstRW<[M3WriteVLDJ, 741 WriteAdr], (instregex "LD3i(8|16|32)_POST")>; 742 def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 743 def : InstRW<[M3WriteVLDL, 744 WriteAdr], (instregex "LD3i(64)_POST")>; 745 746 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 747 def : InstRW<[M3WriteVLDB, 748 WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 749 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 750 def : InstRW<[M3WriteVLDB, 751 WriteAdr], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 752 753 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 754 def : InstRW<[M3WriteVLDN, 755 WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 756 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 757 def : InstRW<[M3WriteVLDN, 758 WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 759 760 def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 761 def : InstRW<[M3WriteVLDK, 762 WriteAdr], (instregex "LD4i(8|16|32)_POST")>; 763 def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 764 def : InstRW<[M3WriteVLDM, 765 WriteAdr], (instregex "LD4i(64)_POST")>; 766 767 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 768 def : InstRW<[M3WriteVLDC, 769 WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 770 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 771 def : InstRW<[M3WriteVLDC, 772 WriteAdr], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 773 774 // ASIMD store instructions. 775 def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 776 def : InstRW<[WriteVST, 777 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 778 def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 779 def : InstRW<[WriteVST, 780 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 781 782 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 783 def : InstRW<[M3WriteVSTA, 784 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 785 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 786 def : InstRW<[M3WriteVSTA, 787 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 788 789 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 790 def : InstRW<[M3WriteVSTB, 791 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 792 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 793 def : InstRW<[M3WriteVSTB, 794 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 795 796 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 797 def : InstRW<[M3WriteVSTC, 798 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 799 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 800 def : InstRW<[M3WriteVSTC, 801 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 802 803 def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 804 def : InstRW<[M3WriteVSTD, 805 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 806 807 def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 808 def : InstRW<[M3WriteVSTD, 809 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 810 def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 811 def : InstRW<[M3WriteVSTE, 812 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 813 814 def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 815 def : InstRW<[M3WriteVSTD, 816 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 817 def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 818 def : InstRW<[M3WriteVSTD, 819 WriteAdr], (instregex "ST2i(64)_POST")>; 820 821 def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 822 def : InstRW<[M3WriteVSTF, 823 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 824 def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 825 def : InstRW<[M3WriteVSTG, 826 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 827 828 def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 829 def : InstRW<[M3WriteVSTH, 830 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 831 def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 832 def : InstRW<[M3WriteVSTF, 833 WriteAdr], (instregex "ST3i(64)_POST")>; 834 835 def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 836 def : InstRW<[M3WriteVSTF, 837 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 838 def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 839 def : InstRW<[M3WriteVSTI, 840 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 841 842 def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 843 def : InstRW<[M3WriteVSTF, 844 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 845 846 // Cryptography instructions. 847 def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 848 def : InstRW<[M3WriteAES, 849 M3ReadAES], (instregex "^AESI?MC")>; 850 851 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 852 853 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 854 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 855 def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 856 857 // CRC instructions. 858 def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 859 860 } // SchedModel = ExynosM3Model 861
