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      1 //==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the machine model for Qualcomm Falkor to support
     11 // instruction scheduling and other instruction cost heuristics.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 //===----------------------------------------------------------------------===//
     16 // Define the SchedMachineModel and provide basic properties for coarse grained
     17 // instruction cost model.
     18 
     19 def FalkorModel : SchedMachineModel {
     20   let IssueWidth = 8;          // 8 uops are dispatched per cycle.
     21   let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
     22   let LoopMicroOpBufferSize = 16;
     23   let LoadLatency = 3;         // Optimistic load latency.
     24   let MispredictPenalty = 11;  // Minimum branch misprediction penalty.
     25   let CompleteModel = 1;
     26 
     27   list<Predicate> UnsupportedFeatures = [HasSVE];
     28 
     29   // FIXME: Remove when all errors have been fixed.
     30   let FullInstRWOverlapCheck = 0;
     31 }
     32 
     33 //===----------------------------------------------------------------------===//
     34 // Define each kind of processor resource and number available on Falkor.
     35 
     36 let SchedModel = FalkorModel in {
     37 
     38   def FalkorUnitB    : ProcResource<1>; // Branch
     39   def FalkorUnitLD   : ProcResource<1>; // Load pipe
     40   def FalkorUnitSD   : ProcResource<1>; // Store data
     41   def FalkorUnitST   : ProcResource<1>; // Store pipe
     42   def FalkorUnitX    : ProcResource<1>; // Complex arithmetic
     43   def FalkorUnitY    : ProcResource<1>; // Simple arithmetic
     44   def FalkorUnitZ    : ProcResource<1>; // Simple arithmetic
     45 
     46   def FalkorUnitVSD  : ProcResource<1>; // Vector store data
     47   def FalkorUnitVX   : ProcResource<1>; // Vector X-pipe
     48   def FalkorUnitVY   : ProcResource<1>; // Vector Y-pipe
     49 
     50   def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector
     51   def FalkorUnitVTOG : ProcResource<1>; // Vector to Scalar
     52 
     53   // Define the resource groups.
     54   def FalkorUnitXY   : ProcResGroup<[FalkorUnitX, FalkorUnitY]>;
     55   def FalkorUnitXYZ  : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>;
     56   def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ,
     57                                      FalkorUnitB]>;
     58   def FalkorUnitZB   : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>;
     59   def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>;
     60 
     61 }
     62 
     63 //===----------------------------------------------------------------------===//
     64 // Map the target-defined scheduler read/write resources and latency for
     65 // Falkor.
     66 
     67 let SchedModel = FalkorModel in {
     68 
     69 // These WriteRes entries are not used in the Falkor sched model.
     70 def : WriteRes<WriteImm, []>     { let Unsupported = 1; }
     71 def : WriteRes<WriteI, []>       { let Unsupported = 1; }
     72 def : WriteRes<WriteISReg, []>   { let Unsupported = 1; }
     73 def : WriteRes<WriteIEReg, []>   { let Unsupported = 1; }
     74 def : WriteRes<WriteExtr, []>    { let Unsupported = 1; }
     75 def : WriteRes<WriteIS, []>      { let Unsupported = 1; }
     76 def : WriteRes<WriteID32, []>    { let Unsupported = 1; }
     77 def : WriteRes<WriteID64, []>    { let Unsupported = 1; }
     78 def : WriteRes<WriteIM32, []>    { let Unsupported = 1; }
     79 def : WriteRes<WriteIM64, []>    { let Unsupported = 1; }
     80 def : WriteRes<WriteBr, []>      { let Unsupported = 1; }
     81 def : WriteRes<WriteBrReg, []>   { let Unsupported = 1; }
     82 def : WriteRes<WriteLD, []>      { let Unsupported = 1; }
     83 def : WriteRes<WriteST, []>      { let Unsupported = 1; }
     84 def : WriteRes<WriteSTP, []>     { let Unsupported = 1; }
     85 def : WriteRes<WriteAdr, []>     { let Unsupported = 1; }
     86 def : WriteRes<WriteLDIdx, []>   { let Unsupported = 1; }
     87 def : WriteRes<WriteSTIdx, []>   { let Unsupported = 1; }
     88 def : WriteRes<WriteF, []>       { let Unsupported = 1; }
     89 def : WriteRes<WriteFCmp, []>    { let Unsupported = 1; }
     90 def : WriteRes<WriteFCvt, []>    { let Unsupported = 1; }
     91 def : WriteRes<WriteFCopy, []>   { let Unsupported = 1; }
     92 def : WriteRes<WriteFImm, []>    { let Unsupported = 1; }
     93 def : WriteRes<WriteFMul, []>    { let Unsupported = 1; }
     94 def : WriteRes<WriteFDiv, []>    { let Unsupported = 1; }
     95 def : WriteRes<WriteV, []>       { let Unsupported = 1; }
     96 def : WriteRes<WriteVLD, []>     { let Unsupported = 1; }
     97 def : WriteRes<WriteVST, []>     { let Unsupported = 1; }
     98 def : WriteRes<WriteSys, []>     { let Unsupported = 1; }
     99 def : WriteRes<WriteBarrier, []> { let Unsupported = 1; }
    100 def : WriteRes<WriteHint, []>    { let Unsupported = 1; }
    101 def : WriteRes<WriteLDHi, []>    { let Unsupported = 1; }
    102 def : WriteRes<WriteAtomic, []>  { let Unsupported = 1; }
    103 
    104 // These ReadAdvance entries are not used in the Falkor sched model.
    105 def : ReadAdvance<ReadI,       0>;
    106 def : ReadAdvance<ReadISReg,   0>;
    107 def : ReadAdvance<ReadIEReg,   0>;
    108 def : ReadAdvance<ReadIM,      0>;
    109 def : ReadAdvance<ReadIMA,     0>;
    110 def : ReadAdvance<ReadID,      0>;
    111 def : ReadAdvance<ReadExtrHi,  0>;
    112 def : ReadAdvance<ReadAdrBase, 0>;
    113 def : ReadAdvance<ReadVLD,     0>;
    114 
    115 // Detailed Refinements
    116 // -----------------------------------------------------------------------------
    117 include "AArch64SchedFalkorDetails.td"
    118 
    119 }
    120