1 //==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Define TII for use in SchedVariant Predicates. 11 // const MachineInstr *MI and const TargetSchedModel *SchedModel 12 // are defined by default. 13 def : PredicateProlog<[{ 14 const AArch64InstrInfo *TII = 15 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo()); 16 (void)TII; 17 }]>; 18 19 // AArch64 Scheduler Definitions 20 21 def WriteImm : SchedWrite; // MOVN, MOVZ 22 // TODO: Provide variants for MOV32/64imm Pseudos that dynamically 23 // select the correct sequence of WriteImms. 24 25 def WriteI : SchedWrite; // ALU 26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg 27 def WriteIEReg : SchedWrite; // ALU of Extended-Reg 28 def ReadI : SchedRead; // ALU 29 def ReadISReg : SchedRead; // ALU of Shifted-Reg 30 def ReadIEReg : SchedRead; // ALU of Extended-Reg 31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair 32 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair 33 def WriteIS : SchedWrite; // Shift/Scale 34 def WriteID32 : SchedWrite; // 32-bit Divide 35 def WriteID64 : SchedWrite; // 64-bit Divide 36 def ReadID : SchedRead; // 32/64-bit Divide 37 def WriteIM32 : SchedWrite; // 32-bit Multiply 38 def WriteIM64 : SchedWrite; // 64-bit Multiply 39 def ReadIM : SchedRead; // 32/64-bit Multiply 40 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate 41 def WriteBr : SchedWrite; // Branch 42 def WriteBrReg : SchedWrite; // Indirect Branch 43 44 def WriteLD : SchedWrite; // Load from base addr plus immediate offset 45 def WriteST : SchedWrite; // Store to base addr plus immediate offset 46 def WriteSTP : SchedWrite; // Store a register pair. 47 def WriteAdr : SchedWrite; // Address pre/post increment. 48 49 def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). 50 def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). 51 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. 52 53 // Predicate for determining when a shiftable register is shifted. 54 def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>; 55 56 // Predicate for determining when a extendedable register is extended. 57 def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>; 58 59 // ScaledIdxPred is true if a WriteLDIdx operand will be 60 // scaled. Subtargets can use this to dynamically select resources and 61 // latency for WriteLDIdx and ReadAdrBase. 62 def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(*MI)}]>; 63 64 // Serialized two-level address load. 65 // EXAMPLE: LOADGot 66 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; 67 68 // Serialized two-level address lookup. 69 // EXAMPLE: MOVaddr... 70 def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>; 71 72 // The second register of a load-pair. 73 // LDP,LDPSW,LDNP,LDXP,LDAXP 74 def WriteLDHi : SchedWrite; 75 76 // Store-exclusive is a store followed by a dependent load. 77 def WriteSTX : WriteSequence<[WriteST, WriteLD]>; 78 79 def WriteSys : SchedWrite; // Long, variable latency system ops. 80 def WriteBarrier : SchedWrite; // Memory barrier. 81 def WriteHint : SchedWrite; // Hint instruction. 82 83 def WriteF : SchedWrite; // General floating-point ops. 84 def WriteFCmp : SchedWrite; // Floating-point compare. 85 def WriteFCvt : SchedWrite; // Float conversion. 86 def WriteFCopy : SchedWrite; // Float-int register copy. 87 def WriteFImm : SchedWrite; // Floating-point immediate. 88 def WriteFMul : SchedWrite; // Floating-point multiply. 89 def WriteFDiv : SchedWrite; // Floating-point division. 90 91 def WriteV : SchedWrite; // Vector ops. 92 def WriteVLD : SchedWrite; // Vector loads. 93 def WriteVST : SchedWrite; // Vector stores. 94 95 def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP) 96 97 // Read the unwritten lanes of the VLD's destination registers. 98 def ReadVLD : SchedRead; 99 100 // Sequential vector load and shuffle. 101 def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>; 102 def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>; 103 104 // Store a shuffled vector. 105 def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>; 106 def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>; 107
