1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 62 uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 65 unsigned RegNo, uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 71 unsigned RegNo, uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 117 uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 140 uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 143 uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 152 uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 155 uint64_t Address, 156 const void *Decoder); 157 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 158 uint64_t Address, 159 const void *Decoder); 160 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 171 uint64_t Address, const void *Decoder); 172 173 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 177 uint64_t Addr, const void *Decoder); 178 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const void *Decoder); 181 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 182 uint64_t Addr, const void *Decoder); 183 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 184 uint64_t Addr, 185 const void *Decoder); 186 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 187 uint64_t Addr, const void *Decoder); 188 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 189 uint64_t Addr, 190 const void *Decoder); 191 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, const void *Decoder); 193 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 194 uint64_t Addr, const void *Decoder); 195 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, const void *Decoder); 199 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, const void *Decoder); 201 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 206 unsigned RegNo, 207 uint64_t Addr, 208 const void *Decoder); 209 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 210 uint32_t insn, 211 uint64_t Address, 212 const void *Decoder); 213 template<int Bits> 214 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 215 uint64_t Address, const void *Decoder); 216 template <int ElementWidth> 217 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, const void *Decoder); 219 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, const void *Decoder); 221 222 static bool Check(DecodeStatus &Out, DecodeStatus In) { 223 switch (In) { 224 case MCDisassembler::Success: 225 // Out stays the same. 226 return true; 227 case MCDisassembler::SoftFail: 228 Out = In; 229 return true; 230 case MCDisassembler::Fail: 231 Out = In; 232 return false; 233 } 234 llvm_unreachable("Invalid DecodeStatus!"); 235 } 236 237 #include "AArch64GenDisassemblerTables.inc" 238 #include "AArch64GenInstrInfo.inc" 239 240 #define Success MCDisassembler::Success 241 #define Fail MCDisassembler::Fail 242 #define SoftFail MCDisassembler::SoftFail 243 244 static MCDisassembler *createAArch64Disassembler(const Target &T, 245 const MCSubtargetInfo &STI, 246 MCContext &Ctx) { 247 return new AArch64Disassembler(STI, Ctx); 248 } 249 250 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 251 ArrayRef<uint8_t> Bytes, 252 uint64_t Address, 253 raw_ostream &OS, 254 raw_ostream &CS) const { 255 CommentStream = &CS; 256 257 Size = 0; 258 // We want to read exactly 4 bytes of data. 259 if (Bytes.size() < 4) 260 return Fail; 261 Size = 4; 262 263 // Encoded as a small-endian 32-bit word in the stream. 264 uint32_t Insn = 265 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 266 267 // Calling the auto-generated decoder function. 268 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 269 } 270 271 static MCSymbolizer * 272 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 273 LLVMSymbolLookupCallback SymbolLookUp, 274 void *DisInfo, MCContext *Ctx, 275 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 276 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 277 SymbolLookUp, DisInfo); 278 } 279 280 extern "C" void LLVMInitializeAArch64Disassembler() { 281 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 282 createAArch64Disassembler); 283 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 284 createAArch64Disassembler); 285 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 286 createAArch64ExternalSymbolizer); 287 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 288 createAArch64ExternalSymbolizer); 289 290 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 291 createAArch64Disassembler); 292 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 293 createAArch64ExternalSymbolizer); 294 } 295 296 static const unsigned FPR128DecoderTable[] = { 297 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 298 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 299 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 300 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 301 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 302 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 303 AArch64::Q30, AArch64::Q31 304 }; 305 306 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 307 uint64_t Addr, 308 const void *Decoder) { 309 if (RegNo > 31) 310 return Fail; 311 312 unsigned Register = FPR128DecoderTable[RegNo]; 313 Inst.addOperand(MCOperand::createReg(Register)); 314 return Success; 315 } 316 317 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 318 uint64_t Addr, 319 const void *Decoder) { 320 if (RegNo > 15) 321 return Fail; 322 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 323 } 324 325 static const unsigned FPR64DecoderTable[] = { 326 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 327 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 328 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 329 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 330 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 331 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 332 AArch64::D30, AArch64::D31 333 }; 334 335 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 336 uint64_t Addr, 337 const void *Decoder) { 338 if (RegNo > 31) 339 return Fail; 340 341 unsigned Register = FPR64DecoderTable[RegNo]; 342 Inst.addOperand(MCOperand::createReg(Register)); 343 return Success; 344 } 345 346 static const unsigned FPR32DecoderTable[] = { 347 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 348 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 349 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 350 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 351 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 352 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 353 AArch64::S30, AArch64::S31 354 }; 355 356 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 357 uint64_t Addr, 358 const void *Decoder) { 359 if (RegNo > 31) 360 return Fail; 361 362 unsigned Register = FPR32DecoderTable[RegNo]; 363 Inst.addOperand(MCOperand::createReg(Register)); 364 return Success; 365 } 366 367 static const unsigned FPR16DecoderTable[] = { 368 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 369 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 370 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 371 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 372 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 373 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 374 AArch64::H30, AArch64::H31 375 }; 376 377 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 378 uint64_t Addr, 379 const void *Decoder) { 380 if (RegNo > 31) 381 return Fail; 382 383 unsigned Register = FPR16DecoderTable[RegNo]; 384 Inst.addOperand(MCOperand::createReg(Register)); 385 return Success; 386 } 387 388 static const unsigned FPR8DecoderTable[] = { 389 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 390 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 391 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 392 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 393 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 394 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 395 AArch64::B30, AArch64::B31 396 }; 397 398 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 399 uint64_t Addr, 400 const void *Decoder) { 401 if (RegNo > 31) 402 return Fail; 403 404 unsigned Register = FPR8DecoderTable[RegNo]; 405 Inst.addOperand(MCOperand::createReg(Register)); 406 return Success; 407 } 408 409 static const unsigned GPR64DecoderTable[] = { 410 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 411 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 412 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 413 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 414 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 415 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 416 AArch64::LR, AArch64::XZR 417 }; 418 419 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 420 uint64_t Addr, 421 const void *Decoder) { 422 if (RegNo > 30) 423 return Fail; 424 425 unsigned Register = GPR64DecoderTable[RegNo]; 426 Inst.addOperand(MCOperand::createReg(Register)); 427 return Success; 428 } 429 430 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 431 uint64_t Addr, 432 const void *Decoder) { 433 if (RegNo > 31) 434 return Fail; 435 436 unsigned Register = GPR64DecoderTable[RegNo]; 437 Inst.addOperand(MCOperand::createReg(Register)); 438 return Success; 439 } 440 441 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 442 uint64_t Addr, 443 const void *Decoder) { 444 if (RegNo > 31) 445 return Fail; 446 unsigned Register = GPR64DecoderTable[RegNo]; 447 if (Register == AArch64::XZR) 448 Register = AArch64::SP; 449 Inst.addOperand(MCOperand::createReg(Register)); 450 return Success; 451 } 452 453 static const unsigned GPR32DecoderTable[] = { 454 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 455 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 456 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 457 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 458 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 459 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 460 AArch64::W30, AArch64::WZR 461 }; 462 463 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 464 uint64_t Addr, 465 const void *Decoder) { 466 if (RegNo > 31) 467 return Fail; 468 469 unsigned Register = GPR32DecoderTable[RegNo]; 470 Inst.addOperand(MCOperand::createReg(Register)); 471 return Success; 472 } 473 474 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 475 uint64_t Addr, 476 const void *Decoder) { 477 if (RegNo > 31) 478 return Fail; 479 480 unsigned Register = GPR32DecoderTable[RegNo]; 481 if (Register == AArch64::WZR) 482 Register = AArch64::WSP; 483 Inst.addOperand(MCOperand::createReg(Register)); 484 return Success; 485 } 486 static const unsigned ZPRDecoderTable[] = { 487 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 488 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 489 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 490 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 491 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 492 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 493 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 494 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 495 }; 496 497 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 498 uint64_t Address, 499 const void* Decoder) { 500 if (RegNo > 31) 501 return Fail; 502 503 unsigned Register = ZPRDecoderTable[RegNo]; 504 Inst.addOperand(MCOperand::createReg(Register)); 505 return Success; 506 } 507 508 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 509 uint64_t Address, 510 const void *Decoder) { 511 if (RegNo > 15) 512 return Fail; 513 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 514 } 515 516 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 517 uint64_t Address, 518 const void *Decoder) { 519 if (RegNo > 7) 520 return Fail; 521 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 522 } 523 524 static const unsigned ZZDecoderTable[] = { 525 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 526 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 527 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 528 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 529 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 530 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 531 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 532 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 533 }; 534 535 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 536 uint64_t Address, 537 const void* Decoder) { 538 if (RegNo > 31) 539 return Fail; 540 unsigned Register = ZZDecoderTable[RegNo]; 541 Inst.addOperand(MCOperand::createReg(Register)); 542 return Success; 543 } 544 545 static const unsigned ZZZDecoderTable[] = { 546 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 547 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 548 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 549 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 550 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 551 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 552 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 553 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 554 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 555 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 556 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 557 }; 558 559 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 560 uint64_t Address, 561 const void* Decoder) { 562 if (RegNo > 31) 563 return Fail; 564 unsigned Register = ZZZDecoderTable[RegNo]; 565 Inst.addOperand(MCOperand::createReg(Register)); 566 return Success; 567 } 568 569 static const unsigned ZZZZDecoderTable[] = { 570 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 571 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 572 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 573 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 574 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 575 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 576 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 577 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 578 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 579 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 580 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 581 }; 582 583 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 584 uint64_t Address, 585 const void* Decoder) { 586 if (RegNo > 31) 587 return Fail; 588 unsigned Register = ZZZZDecoderTable[RegNo]; 589 Inst.addOperand(MCOperand::createReg(Register)); 590 return Success; 591 } 592 593 static const unsigned PPRDecoderTable[] = { 594 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 595 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 596 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 597 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 598 }; 599 600 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 601 uint64_t Addr, const void *Decoder) { 602 if (RegNo > 15) 603 return Fail; 604 605 unsigned Register = PPRDecoderTable[RegNo]; 606 Inst.addOperand(MCOperand::createReg(Register)); 607 return Success; 608 } 609 610 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 611 uint64_t Addr, 612 const void* Decoder) { 613 if (RegNo > 7) 614 return Fail; 615 616 // Just reuse the PPR decode table 617 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 618 } 619 620 static const unsigned VectorDecoderTable[] = { 621 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 622 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 623 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 624 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 625 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 626 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 627 AArch64::Q30, AArch64::Q31 628 }; 629 630 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 631 uint64_t Addr, 632 const void *Decoder) { 633 if (RegNo > 31) 634 return Fail; 635 636 unsigned Register = VectorDecoderTable[RegNo]; 637 Inst.addOperand(MCOperand::createReg(Register)); 638 return Success; 639 } 640 641 static const unsigned QQDecoderTable[] = { 642 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 643 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 644 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 645 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 646 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 647 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 648 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 649 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 650 }; 651 652 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 653 uint64_t Addr, const void *Decoder) { 654 if (RegNo > 31) 655 return Fail; 656 unsigned Register = QQDecoderTable[RegNo]; 657 Inst.addOperand(MCOperand::createReg(Register)); 658 return Success; 659 } 660 661 static const unsigned QQQDecoderTable[] = { 662 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 663 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 664 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 665 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 666 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 667 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 668 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 669 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 670 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 671 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 672 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 673 }; 674 675 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 676 uint64_t Addr, const void *Decoder) { 677 if (RegNo > 31) 678 return Fail; 679 unsigned Register = QQQDecoderTable[RegNo]; 680 Inst.addOperand(MCOperand::createReg(Register)); 681 return Success; 682 } 683 684 static const unsigned QQQQDecoderTable[] = { 685 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 686 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 687 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 688 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 689 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 690 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 691 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 692 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 693 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 694 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 695 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 696 }; 697 698 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 699 uint64_t Addr, 700 const void *Decoder) { 701 if (RegNo > 31) 702 return Fail; 703 unsigned Register = QQQQDecoderTable[RegNo]; 704 Inst.addOperand(MCOperand::createReg(Register)); 705 return Success; 706 } 707 708 static const unsigned DDDecoderTable[] = { 709 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 710 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 711 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 712 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 713 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 714 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 715 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 716 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 717 }; 718 719 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 720 uint64_t Addr, const void *Decoder) { 721 if (RegNo > 31) 722 return Fail; 723 unsigned Register = DDDecoderTable[RegNo]; 724 Inst.addOperand(MCOperand::createReg(Register)); 725 return Success; 726 } 727 728 static const unsigned DDDDecoderTable[] = { 729 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 730 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 731 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 732 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 733 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 734 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 735 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 736 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 737 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 738 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 739 AArch64::D30_D31_D0, AArch64::D31_D0_D1 740 }; 741 742 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 743 uint64_t Addr, const void *Decoder) { 744 if (RegNo > 31) 745 return Fail; 746 unsigned Register = DDDDecoderTable[RegNo]; 747 Inst.addOperand(MCOperand::createReg(Register)); 748 return Success; 749 } 750 751 static const unsigned DDDDDecoderTable[] = { 752 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 753 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 754 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 755 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 756 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 757 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 758 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 759 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 760 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 761 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 762 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 763 }; 764 765 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 766 uint64_t Addr, 767 const void *Decoder) { 768 if (RegNo > 31) 769 return Fail; 770 unsigned Register = DDDDDecoderTable[RegNo]; 771 Inst.addOperand(MCOperand::createReg(Register)); 772 return Success; 773 } 774 775 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 776 uint64_t Addr, 777 const void *Decoder) { 778 // scale{5} is asserted as 1 in tblgen. 779 Imm |= 0x20; 780 Inst.addOperand(MCOperand::createImm(64 - Imm)); 781 return Success; 782 } 783 784 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 785 uint64_t Addr, 786 const void *Decoder) { 787 Inst.addOperand(MCOperand::createImm(64 - Imm)); 788 return Success; 789 } 790 791 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 792 uint64_t Addr, const void *Decoder) { 793 int64_t ImmVal = Imm; 794 const AArch64Disassembler *Dis = 795 static_cast<const AArch64Disassembler *>(Decoder); 796 797 // Sign-extend 19-bit immediate. 798 if (ImmVal & (1 << (19 - 1))) 799 ImmVal |= ~((1LL << 19) - 1); 800 801 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 802 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 803 Inst.addOperand(MCOperand::createImm(ImmVal)); 804 return Success; 805 } 806 807 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 808 uint64_t Address, const void *Decoder) { 809 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 810 Inst.addOperand(MCOperand::createImm(Imm & 1)); 811 return Success; 812 } 813 814 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 815 uint64_t Address, 816 const void *Decoder) { 817 Inst.addOperand(MCOperand::createImm(Imm)); 818 819 // Every system register in the encoding space is valid with the syntax 820 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 821 return Success; 822 } 823 824 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 825 uint64_t Address, 826 const void *Decoder) { 827 Inst.addOperand(MCOperand::createImm(Imm)); 828 829 return Success; 830 } 831 832 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 833 uint64_t Address, 834 const void *Decoder) { 835 // This decoder exists to add the dummy Lane operand to the MCInst, which must 836 // be 1 in assembly but has no other real manifestation. 837 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 838 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 839 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 840 841 if (IsToVec) { 842 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 843 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 844 } else { 845 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 846 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 847 } 848 849 // Add the lane 850 Inst.addOperand(MCOperand::createImm(1)); 851 852 return Success; 853 } 854 855 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 856 unsigned Add) { 857 Inst.addOperand(MCOperand::createImm(Add - Imm)); 858 return Success; 859 } 860 861 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 862 unsigned Add) { 863 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 864 return Success; 865 } 866 867 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 868 uint64_t Addr, const void *Decoder) { 869 return DecodeVecShiftRImm(Inst, Imm, 64); 870 } 871 872 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 873 uint64_t Addr, 874 const void *Decoder) { 875 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 876 } 877 878 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 879 uint64_t Addr, const void *Decoder) { 880 return DecodeVecShiftRImm(Inst, Imm, 32); 881 } 882 883 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 884 uint64_t Addr, 885 const void *Decoder) { 886 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 887 } 888 889 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 890 uint64_t Addr, const void *Decoder) { 891 return DecodeVecShiftRImm(Inst, Imm, 16); 892 } 893 894 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 895 uint64_t Addr, 896 const void *Decoder) { 897 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 898 } 899 900 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 901 uint64_t Addr, const void *Decoder) { 902 return DecodeVecShiftRImm(Inst, Imm, 8); 903 } 904 905 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 906 uint64_t Addr, const void *Decoder) { 907 return DecodeVecShiftLImm(Inst, Imm, 64); 908 } 909 910 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 911 uint64_t Addr, const void *Decoder) { 912 return DecodeVecShiftLImm(Inst, Imm, 32); 913 } 914 915 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 916 uint64_t Addr, const void *Decoder) { 917 return DecodeVecShiftLImm(Inst, Imm, 16); 918 } 919 920 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 921 uint64_t Addr, const void *Decoder) { 922 return DecodeVecShiftLImm(Inst, Imm, 8); 923 } 924 925 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 926 uint64_t Addr, 927 const void *Decoder) { 928 unsigned Rd = fieldFromInstruction(insn, 0, 5); 929 unsigned Rn = fieldFromInstruction(insn, 5, 5); 930 unsigned Rm = fieldFromInstruction(insn, 16, 5); 931 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 932 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 933 unsigned shift = (shiftHi << 6) | shiftLo; 934 switch (Inst.getOpcode()) { 935 default: 936 return Fail; 937 case AArch64::ADDWrs: 938 case AArch64::ADDSWrs: 939 case AArch64::SUBWrs: 940 case AArch64::SUBSWrs: 941 // if shift == '11' then ReservedValue() 942 if (shiftHi == 0x3) 943 return Fail; 944 LLVM_FALLTHROUGH; 945 case AArch64::ANDWrs: 946 case AArch64::ANDSWrs: 947 case AArch64::BICWrs: 948 case AArch64::BICSWrs: 949 case AArch64::ORRWrs: 950 case AArch64::ORNWrs: 951 case AArch64::EORWrs: 952 case AArch64::EONWrs: { 953 // if sf == '0' and imm6<5> == '1' then ReservedValue() 954 if (shiftLo >> 5 == 1) 955 return Fail; 956 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 957 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 958 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 959 break; 960 } 961 case AArch64::ADDXrs: 962 case AArch64::ADDSXrs: 963 case AArch64::SUBXrs: 964 case AArch64::SUBSXrs: 965 // if shift == '11' then ReservedValue() 966 if (shiftHi == 0x3) 967 return Fail; 968 LLVM_FALLTHROUGH; 969 case AArch64::ANDXrs: 970 case AArch64::ANDSXrs: 971 case AArch64::BICXrs: 972 case AArch64::BICSXrs: 973 case AArch64::ORRXrs: 974 case AArch64::ORNXrs: 975 case AArch64::EORXrs: 976 case AArch64::EONXrs: 977 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 978 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 979 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 980 break; 981 } 982 983 Inst.addOperand(MCOperand::createImm(shift)); 984 return Success; 985 } 986 987 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 988 uint64_t Addr, 989 const void *Decoder) { 990 unsigned Rd = fieldFromInstruction(insn, 0, 5); 991 unsigned imm = fieldFromInstruction(insn, 5, 16); 992 unsigned shift = fieldFromInstruction(insn, 21, 2); 993 shift <<= 4; 994 switch (Inst.getOpcode()) { 995 default: 996 return Fail; 997 case AArch64::MOVZWi: 998 case AArch64::MOVNWi: 999 case AArch64::MOVKWi: 1000 if (shift & (1U << 5)) 1001 return Fail; 1002 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1003 break; 1004 case AArch64::MOVZXi: 1005 case AArch64::MOVNXi: 1006 case AArch64::MOVKXi: 1007 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1008 break; 1009 } 1010 1011 if (Inst.getOpcode() == AArch64::MOVKWi || 1012 Inst.getOpcode() == AArch64::MOVKXi) 1013 Inst.addOperand(Inst.getOperand(0)); 1014 1015 Inst.addOperand(MCOperand::createImm(imm)); 1016 Inst.addOperand(MCOperand::createImm(shift)); 1017 return Success; 1018 } 1019 1020 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1021 uint64_t Addr, 1022 const void *Decoder) { 1023 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1024 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1025 unsigned offset = fieldFromInstruction(insn, 10, 12); 1026 const AArch64Disassembler *Dis = 1027 static_cast<const AArch64Disassembler *>(Decoder); 1028 1029 switch (Inst.getOpcode()) { 1030 default: 1031 return Fail; 1032 case AArch64::PRFMui: 1033 // Rt is an immediate in prefetch. 1034 Inst.addOperand(MCOperand::createImm(Rt)); 1035 break; 1036 case AArch64::STRBBui: 1037 case AArch64::LDRBBui: 1038 case AArch64::LDRSBWui: 1039 case AArch64::STRHHui: 1040 case AArch64::LDRHHui: 1041 case AArch64::LDRSHWui: 1042 case AArch64::STRWui: 1043 case AArch64::LDRWui: 1044 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1045 break; 1046 case AArch64::LDRSBXui: 1047 case AArch64::LDRSHXui: 1048 case AArch64::LDRSWui: 1049 case AArch64::STRXui: 1050 case AArch64::LDRXui: 1051 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1052 break; 1053 case AArch64::LDRQui: 1054 case AArch64::STRQui: 1055 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1056 break; 1057 case AArch64::LDRDui: 1058 case AArch64::STRDui: 1059 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1060 break; 1061 case AArch64::LDRSui: 1062 case AArch64::STRSui: 1063 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1064 break; 1065 case AArch64::LDRHui: 1066 case AArch64::STRHui: 1067 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1068 break; 1069 case AArch64::LDRBui: 1070 case AArch64::STRBui: 1071 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1072 break; 1073 } 1074 1075 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1076 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1077 Inst.addOperand(MCOperand::createImm(offset)); 1078 return Success; 1079 } 1080 1081 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1082 uint64_t Addr, 1083 const void *Decoder) { 1084 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1085 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1086 int64_t offset = fieldFromInstruction(insn, 12, 9); 1087 1088 // offset is a 9-bit signed immediate, so sign extend it to 1089 // fill the unsigned. 1090 if (offset & (1 << (9 - 1))) 1091 offset |= ~((1LL << 9) - 1); 1092 1093 // First operand is always the writeback to the address register, if needed. 1094 switch (Inst.getOpcode()) { 1095 default: 1096 break; 1097 case AArch64::LDRSBWpre: 1098 case AArch64::LDRSHWpre: 1099 case AArch64::STRBBpre: 1100 case AArch64::LDRBBpre: 1101 case AArch64::STRHHpre: 1102 case AArch64::LDRHHpre: 1103 case AArch64::STRWpre: 1104 case AArch64::LDRWpre: 1105 case AArch64::LDRSBWpost: 1106 case AArch64::LDRSHWpost: 1107 case AArch64::STRBBpost: 1108 case AArch64::LDRBBpost: 1109 case AArch64::STRHHpost: 1110 case AArch64::LDRHHpost: 1111 case AArch64::STRWpost: 1112 case AArch64::LDRWpost: 1113 case AArch64::LDRSBXpre: 1114 case AArch64::LDRSHXpre: 1115 case AArch64::STRXpre: 1116 case AArch64::LDRSWpre: 1117 case AArch64::LDRXpre: 1118 case AArch64::LDRSBXpost: 1119 case AArch64::LDRSHXpost: 1120 case AArch64::STRXpost: 1121 case AArch64::LDRSWpost: 1122 case AArch64::LDRXpost: 1123 case AArch64::LDRQpre: 1124 case AArch64::STRQpre: 1125 case AArch64::LDRQpost: 1126 case AArch64::STRQpost: 1127 case AArch64::LDRDpre: 1128 case AArch64::STRDpre: 1129 case AArch64::LDRDpost: 1130 case AArch64::STRDpost: 1131 case AArch64::LDRSpre: 1132 case AArch64::STRSpre: 1133 case AArch64::LDRSpost: 1134 case AArch64::STRSpost: 1135 case AArch64::LDRHpre: 1136 case AArch64::STRHpre: 1137 case AArch64::LDRHpost: 1138 case AArch64::STRHpost: 1139 case AArch64::LDRBpre: 1140 case AArch64::STRBpre: 1141 case AArch64::LDRBpost: 1142 case AArch64::STRBpost: 1143 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1144 break; 1145 } 1146 1147 switch (Inst.getOpcode()) { 1148 default: 1149 return Fail; 1150 case AArch64::PRFUMi: 1151 // Rt is an immediate in prefetch. 1152 Inst.addOperand(MCOperand::createImm(Rt)); 1153 break; 1154 case AArch64::STURBBi: 1155 case AArch64::LDURBBi: 1156 case AArch64::LDURSBWi: 1157 case AArch64::STURHHi: 1158 case AArch64::LDURHHi: 1159 case AArch64::LDURSHWi: 1160 case AArch64::STURWi: 1161 case AArch64::LDURWi: 1162 case AArch64::LDTRSBWi: 1163 case AArch64::LDTRSHWi: 1164 case AArch64::STTRWi: 1165 case AArch64::LDTRWi: 1166 case AArch64::STTRHi: 1167 case AArch64::LDTRHi: 1168 case AArch64::LDTRBi: 1169 case AArch64::STTRBi: 1170 case AArch64::LDRSBWpre: 1171 case AArch64::LDRSHWpre: 1172 case AArch64::STRBBpre: 1173 case AArch64::LDRBBpre: 1174 case AArch64::STRHHpre: 1175 case AArch64::LDRHHpre: 1176 case AArch64::STRWpre: 1177 case AArch64::LDRWpre: 1178 case AArch64::LDRSBWpost: 1179 case AArch64::LDRSHWpost: 1180 case AArch64::STRBBpost: 1181 case AArch64::LDRBBpost: 1182 case AArch64::STRHHpost: 1183 case AArch64::LDRHHpost: 1184 case AArch64::STRWpost: 1185 case AArch64::LDRWpost: 1186 case AArch64::STLURBi: 1187 case AArch64::STLURHi: 1188 case AArch64::STLURWi: 1189 case AArch64::LDAPURBi: 1190 case AArch64::LDAPURSBWi: 1191 case AArch64::LDAPURHi: 1192 case AArch64::LDAPURSHWi: 1193 case AArch64::LDAPURi: 1194 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1195 break; 1196 case AArch64::LDURSBXi: 1197 case AArch64::LDURSHXi: 1198 case AArch64::LDURSWi: 1199 case AArch64::STURXi: 1200 case AArch64::LDURXi: 1201 case AArch64::LDTRSBXi: 1202 case AArch64::LDTRSHXi: 1203 case AArch64::LDTRSWi: 1204 case AArch64::STTRXi: 1205 case AArch64::LDTRXi: 1206 case AArch64::LDRSBXpre: 1207 case AArch64::LDRSHXpre: 1208 case AArch64::STRXpre: 1209 case AArch64::LDRSWpre: 1210 case AArch64::LDRXpre: 1211 case AArch64::LDRSBXpost: 1212 case AArch64::LDRSHXpost: 1213 case AArch64::STRXpost: 1214 case AArch64::LDRSWpost: 1215 case AArch64::LDRXpost: 1216 case AArch64::LDAPURSWi: 1217 case AArch64::LDAPURSHXi: 1218 case AArch64::LDAPURSBXi: 1219 case AArch64::STLURXi: 1220 case AArch64::LDAPURXi: 1221 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1222 break; 1223 case AArch64::LDURQi: 1224 case AArch64::STURQi: 1225 case AArch64::LDRQpre: 1226 case AArch64::STRQpre: 1227 case AArch64::LDRQpost: 1228 case AArch64::STRQpost: 1229 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1230 break; 1231 case AArch64::LDURDi: 1232 case AArch64::STURDi: 1233 case AArch64::LDRDpre: 1234 case AArch64::STRDpre: 1235 case AArch64::LDRDpost: 1236 case AArch64::STRDpost: 1237 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1238 break; 1239 case AArch64::LDURSi: 1240 case AArch64::STURSi: 1241 case AArch64::LDRSpre: 1242 case AArch64::STRSpre: 1243 case AArch64::LDRSpost: 1244 case AArch64::STRSpost: 1245 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1246 break; 1247 case AArch64::LDURHi: 1248 case AArch64::STURHi: 1249 case AArch64::LDRHpre: 1250 case AArch64::STRHpre: 1251 case AArch64::LDRHpost: 1252 case AArch64::STRHpost: 1253 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1254 break; 1255 case AArch64::LDURBi: 1256 case AArch64::STURBi: 1257 case AArch64::LDRBpre: 1258 case AArch64::STRBpre: 1259 case AArch64::LDRBpost: 1260 case AArch64::STRBpost: 1261 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1262 break; 1263 } 1264 1265 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1266 Inst.addOperand(MCOperand::createImm(offset)); 1267 1268 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1269 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1270 bool IsFP = fieldFromInstruction(insn, 26, 1); 1271 1272 // Cannot write back to a transfer register (but xzr != sp). 1273 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1274 return SoftFail; 1275 1276 return Success; 1277 } 1278 1279 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1280 uint64_t Addr, 1281 const void *Decoder) { 1282 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1283 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1284 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1285 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1286 1287 unsigned Opcode = Inst.getOpcode(); 1288 switch (Opcode) { 1289 default: 1290 return Fail; 1291 case AArch64::STLXRW: 1292 case AArch64::STLXRB: 1293 case AArch64::STLXRH: 1294 case AArch64::STXRW: 1295 case AArch64::STXRB: 1296 case AArch64::STXRH: 1297 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1298 LLVM_FALLTHROUGH; 1299 case AArch64::LDARW: 1300 case AArch64::LDARB: 1301 case AArch64::LDARH: 1302 case AArch64::LDAXRW: 1303 case AArch64::LDAXRB: 1304 case AArch64::LDAXRH: 1305 case AArch64::LDXRW: 1306 case AArch64::LDXRB: 1307 case AArch64::LDXRH: 1308 case AArch64::STLRW: 1309 case AArch64::STLRB: 1310 case AArch64::STLRH: 1311 case AArch64::STLLRW: 1312 case AArch64::STLLRB: 1313 case AArch64::STLLRH: 1314 case AArch64::LDLARW: 1315 case AArch64::LDLARB: 1316 case AArch64::LDLARH: 1317 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1318 break; 1319 case AArch64::STLXRX: 1320 case AArch64::STXRX: 1321 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1322 LLVM_FALLTHROUGH; 1323 case AArch64::LDARX: 1324 case AArch64::LDAXRX: 1325 case AArch64::LDXRX: 1326 case AArch64::STLRX: 1327 case AArch64::LDLARX: 1328 case AArch64::STLLRX: 1329 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1330 break; 1331 case AArch64::STLXPW: 1332 case AArch64::STXPW: 1333 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1334 LLVM_FALLTHROUGH; 1335 case AArch64::LDAXPW: 1336 case AArch64::LDXPW: 1337 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1338 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1339 break; 1340 case AArch64::STLXPX: 1341 case AArch64::STXPX: 1342 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1343 LLVM_FALLTHROUGH; 1344 case AArch64::LDAXPX: 1345 case AArch64::LDXPX: 1346 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1347 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1348 break; 1349 } 1350 1351 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1352 1353 // You shouldn't load to the same register twice in an instruction... 1354 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1355 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1356 Rt == Rt2) 1357 return SoftFail; 1358 1359 return Success; 1360 } 1361 1362 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1363 uint64_t Addr, 1364 const void *Decoder) { 1365 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1366 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1367 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1368 int64_t offset = fieldFromInstruction(insn, 15, 7); 1369 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1370 1371 // offset is a 7-bit signed immediate, so sign extend it to 1372 // fill the unsigned. 1373 if (offset & (1 << (7 - 1))) 1374 offset |= ~((1LL << 7) - 1); 1375 1376 unsigned Opcode = Inst.getOpcode(); 1377 bool NeedsDisjointWritebackTransfer = false; 1378 1379 // First operand is always writeback of base register. 1380 switch (Opcode) { 1381 default: 1382 break; 1383 case AArch64::LDPXpost: 1384 case AArch64::STPXpost: 1385 case AArch64::LDPSWpost: 1386 case AArch64::LDPXpre: 1387 case AArch64::STPXpre: 1388 case AArch64::LDPSWpre: 1389 case AArch64::LDPWpost: 1390 case AArch64::STPWpost: 1391 case AArch64::LDPWpre: 1392 case AArch64::STPWpre: 1393 case AArch64::LDPQpost: 1394 case AArch64::STPQpost: 1395 case AArch64::LDPQpre: 1396 case AArch64::STPQpre: 1397 case AArch64::LDPDpost: 1398 case AArch64::STPDpost: 1399 case AArch64::LDPDpre: 1400 case AArch64::STPDpre: 1401 case AArch64::LDPSpost: 1402 case AArch64::STPSpost: 1403 case AArch64::LDPSpre: 1404 case AArch64::STPSpre: 1405 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1406 break; 1407 } 1408 1409 switch (Opcode) { 1410 default: 1411 return Fail; 1412 case AArch64::LDPXpost: 1413 case AArch64::STPXpost: 1414 case AArch64::LDPSWpost: 1415 case AArch64::LDPXpre: 1416 case AArch64::STPXpre: 1417 case AArch64::LDPSWpre: 1418 NeedsDisjointWritebackTransfer = true; 1419 LLVM_FALLTHROUGH; 1420 case AArch64::LDNPXi: 1421 case AArch64::STNPXi: 1422 case AArch64::LDPXi: 1423 case AArch64::STPXi: 1424 case AArch64::LDPSWi: 1425 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1426 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1427 break; 1428 case AArch64::LDPWpost: 1429 case AArch64::STPWpost: 1430 case AArch64::LDPWpre: 1431 case AArch64::STPWpre: 1432 NeedsDisjointWritebackTransfer = true; 1433 LLVM_FALLTHROUGH; 1434 case AArch64::LDNPWi: 1435 case AArch64::STNPWi: 1436 case AArch64::LDPWi: 1437 case AArch64::STPWi: 1438 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1439 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1440 break; 1441 case AArch64::LDNPQi: 1442 case AArch64::STNPQi: 1443 case AArch64::LDPQpost: 1444 case AArch64::STPQpost: 1445 case AArch64::LDPQi: 1446 case AArch64::STPQi: 1447 case AArch64::LDPQpre: 1448 case AArch64::STPQpre: 1449 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1450 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1451 break; 1452 case AArch64::LDNPDi: 1453 case AArch64::STNPDi: 1454 case AArch64::LDPDpost: 1455 case AArch64::STPDpost: 1456 case AArch64::LDPDi: 1457 case AArch64::STPDi: 1458 case AArch64::LDPDpre: 1459 case AArch64::STPDpre: 1460 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1461 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1462 break; 1463 case AArch64::LDNPSi: 1464 case AArch64::STNPSi: 1465 case AArch64::LDPSpost: 1466 case AArch64::STPSpost: 1467 case AArch64::LDPSi: 1468 case AArch64::STPSi: 1469 case AArch64::LDPSpre: 1470 case AArch64::STPSpre: 1471 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1472 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1473 break; 1474 } 1475 1476 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1477 Inst.addOperand(MCOperand::createImm(offset)); 1478 1479 // You shouldn't load to the same register twice in an instruction... 1480 if (IsLoad && Rt == Rt2) 1481 return SoftFail; 1482 1483 // ... or do any operation that writes-back to a transfer register. But note 1484 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1485 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1486 return SoftFail; 1487 1488 return Success; 1489 } 1490 1491 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1492 uint64_t Addr, 1493 const void *Decoder) { 1494 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1495 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1496 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1497 unsigned extend = fieldFromInstruction(insn, 10, 6); 1498 1499 unsigned shift = extend & 0x7; 1500 if (shift > 4) 1501 return Fail; 1502 1503 switch (Inst.getOpcode()) { 1504 default: 1505 return Fail; 1506 case AArch64::ADDWrx: 1507 case AArch64::SUBWrx: 1508 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1509 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1510 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1511 break; 1512 case AArch64::ADDSWrx: 1513 case AArch64::SUBSWrx: 1514 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1515 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1516 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1517 break; 1518 case AArch64::ADDXrx: 1519 case AArch64::SUBXrx: 1520 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1521 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1522 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1523 break; 1524 case AArch64::ADDSXrx: 1525 case AArch64::SUBSXrx: 1526 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1527 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1528 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1529 break; 1530 case AArch64::ADDXrx64: 1531 case AArch64::SUBXrx64: 1532 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1533 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1534 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1535 break; 1536 case AArch64::SUBSXrx64: 1537 case AArch64::ADDSXrx64: 1538 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1539 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1540 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1541 break; 1542 } 1543 1544 Inst.addOperand(MCOperand::createImm(extend)); 1545 return Success; 1546 } 1547 1548 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1549 uint64_t Addr, 1550 const void *Decoder) { 1551 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1552 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1553 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1554 unsigned imm; 1555 1556 if (Datasize) { 1557 if (Inst.getOpcode() == AArch64::ANDSXri) 1558 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1559 else 1560 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1561 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1562 imm = fieldFromInstruction(insn, 10, 13); 1563 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1564 return Fail; 1565 } else { 1566 if (Inst.getOpcode() == AArch64::ANDSWri) 1567 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1568 else 1569 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1570 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1571 imm = fieldFromInstruction(insn, 10, 12); 1572 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1573 return Fail; 1574 } 1575 Inst.addOperand(MCOperand::createImm(imm)); 1576 return Success; 1577 } 1578 1579 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1580 uint64_t Addr, 1581 const void *Decoder) { 1582 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1583 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1584 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1585 imm |= fieldFromInstruction(insn, 5, 5); 1586 1587 if (Inst.getOpcode() == AArch64::MOVID) 1588 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1589 else 1590 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1591 1592 Inst.addOperand(MCOperand::createImm(imm)); 1593 1594 switch (Inst.getOpcode()) { 1595 default: 1596 break; 1597 case AArch64::MOVIv4i16: 1598 case AArch64::MOVIv8i16: 1599 case AArch64::MVNIv4i16: 1600 case AArch64::MVNIv8i16: 1601 case AArch64::MOVIv2i32: 1602 case AArch64::MOVIv4i32: 1603 case AArch64::MVNIv2i32: 1604 case AArch64::MVNIv4i32: 1605 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1606 break; 1607 case AArch64::MOVIv2s_msl: 1608 case AArch64::MOVIv4s_msl: 1609 case AArch64::MVNIv2s_msl: 1610 case AArch64::MVNIv4s_msl: 1611 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1612 break; 1613 } 1614 1615 return Success; 1616 } 1617 1618 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1619 uint64_t Addr, 1620 const void *Decoder) { 1621 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1622 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1623 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1624 imm |= fieldFromInstruction(insn, 5, 5); 1625 1626 // Tied operands added twice. 1627 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1628 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1629 1630 Inst.addOperand(MCOperand::createImm(imm)); 1631 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1632 1633 return Success; 1634 } 1635 1636 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1637 uint64_t Addr, const void *Decoder) { 1638 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1639 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1640 imm |= fieldFromInstruction(insn, 29, 2); 1641 const AArch64Disassembler *Dis = 1642 static_cast<const AArch64Disassembler *>(Decoder); 1643 1644 // Sign-extend the 21-bit immediate. 1645 if (imm & (1 << (21 - 1))) 1646 imm |= ~((1LL << 21) - 1); 1647 1648 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1649 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1650 Inst.addOperand(MCOperand::createImm(imm)); 1651 1652 return Success; 1653 } 1654 1655 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1656 uint64_t Addr, const void *Decoder) { 1657 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1658 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1659 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1660 unsigned S = fieldFromInstruction(insn, 29, 1); 1661 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1662 1663 unsigned ShifterVal = (Imm >> 12) & 3; 1664 unsigned ImmVal = Imm & 0xFFF; 1665 const AArch64Disassembler *Dis = 1666 static_cast<const AArch64Disassembler *>(Decoder); 1667 1668 if (ShifterVal != 0 && ShifterVal != 1) 1669 return Fail; 1670 1671 if (Datasize) { 1672 if (Rd == 31 && !S) 1673 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1674 else 1675 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1676 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1677 } else { 1678 if (Rd == 31 && !S) 1679 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1680 else 1681 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1682 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1683 } 1684 1685 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1686 Inst.addOperand(MCOperand::createImm(ImmVal)); 1687 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1688 return Success; 1689 } 1690 1691 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1692 uint64_t Addr, 1693 const void *Decoder) { 1694 int64_t imm = fieldFromInstruction(insn, 0, 26); 1695 const AArch64Disassembler *Dis = 1696 static_cast<const AArch64Disassembler *>(Decoder); 1697 1698 // Sign-extend the 26-bit immediate. 1699 if (imm & (1 << (26 - 1))) 1700 imm |= ~((1LL << 26) - 1); 1701 1702 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1703 Inst.addOperand(MCOperand::createImm(imm)); 1704 1705 return Success; 1706 } 1707 1708 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1709 uint64_t Addr, 1710 const void *Decoder) { 1711 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1712 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1713 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1714 1715 uint64_t pstate_field = (op1 << 3) | op2; 1716 1717 if ((pstate_field == AArch64PState::PAN || 1718 pstate_field == AArch64PState::UAO) && crm > 1) 1719 return Fail; 1720 1721 Inst.addOperand(MCOperand::createImm(pstate_field)); 1722 Inst.addOperand(MCOperand::createImm(crm)); 1723 1724 const AArch64Disassembler *Dis = 1725 static_cast<const AArch64Disassembler *>(Decoder); 1726 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1727 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1728 return Success; 1729 return Fail; 1730 } 1731 1732 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1733 uint64_t Addr, const void *Decoder) { 1734 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1735 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1736 bit |= fieldFromInstruction(insn, 19, 5); 1737 int64_t dst = fieldFromInstruction(insn, 5, 14); 1738 const AArch64Disassembler *Dis = 1739 static_cast<const AArch64Disassembler *>(Decoder); 1740 1741 // Sign-extend 14-bit immediate. 1742 if (dst & (1 << (14 - 1))) 1743 dst |= ~((1LL << 14) - 1); 1744 1745 if (fieldFromInstruction(insn, 31, 1) == 0) 1746 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1747 else 1748 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1749 Inst.addOperand(MCOperand::createImm(bit)); 1750 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1751 Inst.addOperand(MCOperand::createImm(dst)); 1752 1753 return Success; 1754 } 1755 1756 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1757 unsigned RegClassID, 1758 unsigned RegNo, 1759 uint64_t Addr, 1760 const void *Decoder) { 1761 // Register number must be even (see CASP instruction) 1762 if (RegNo & 0x1) 1763 return Fail; 1764 1765 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1766 Inst.addOperand(MCOperand::createReg(Register)); 1767 return Success; 1768 } 1769 1770 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1771 unsigned RegNo, 1772 uint64_t Addr, 1773 const void *Decoder) { 1774 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1775 AArch64::WSeqPairsClassRegClassID, 1776 RegNo, Addr, Decoder); 1777 } 1778 1779 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1780 unsigned RegNo, 1781 uint64_t Addr, 1782 const void *Decoder) { 1783 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1784 AArch64::XSeqPairsClassRegClassID, 1785 RegNo, Addr, Decoder); 1786 } 1787 1788 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1789 uint32_t insn, 1790 uint64_t Addr, 1791 const void *Decoder) { 1792 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1793 unsigned imm = fieldFromInstruction(insn, 5, 13); 1794 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1795 return Fail; 1796 1797 // The same (tied) operand is added twice to the instruction. 1798 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1799 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1800 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1801 Inst.addOperand(MCOperand::createImm(imm)); 1802 return Success; 1803 } 1804 1805 template<int Bits> 1806 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1807 uint64_t Address, const void *Decoder) { 1808 if (Imm & ~((1LL << Bits) - 1)) 1809 return Fail; 1810 1811 // Imm is a signed immediate, so sign extend it. 1812 if (Imm & (1 << (Bits - 1))) 1813 Imm |= ~((1LL << Bits) - 1); 1814 1815 Inst.addOperand(MCOperand::createImm(Imm)); 1816 return Success; 1817 } 1818 1819 // Decode 8-bit signed/unsigned immediate for a given element width. 1820 template <int ElementWidth> 1821 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1822 uint64_t Addr, const void *Decoder) { 1823 unsigned Val = (uint8_t)Imm; 1824 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1825 if (ElementWidth == 8 && Shift) 1826 return Fail; 1827 Inst.addOperand(MCOperand::createImm(Val)); 1828 Inst.addOperand(MCOperand::createImm(Shift)); 1829 return Success; 1830 } 1831 1832 // Decode uimm4 ranged from 1-16. 1833 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1834 uint64_t Addr, const void *Decoder) { 1835 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1836 return Success; 1837 } 1838
