1 //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def SVEPatternOperand : AsmOperandClass { 15 let Name = "SVEPattern"; 16 let ParserMethod = "tryParseSVEPattern"; 17 let PredicateMethod = "isSVEPattern"; 18 let RenderMethod = "addImmOperands"; 19 let DiagnosticType = "InvalidSVEPattern"; 20 } 21 22 def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{ 23 return (((uint32_t)Imm) < 32); 24 }]> { 25 26 let PrintMethod = "printSVEPattern"; 27 let ParserMatchClass = SVEPatternOperand; 28 } 29 30 def SVEPrefetchOperand : AsmOperandClass { 31 let Name = "SVEPrefetch"; 32 let ParserMethod = "tryParsePrefetch<true>"; 33 let PredicateMethod = "isPrefetch"; 34 let RenderMethod = "addPrefetchOperands"; 35 } 36 37 def sve_prfop : Operand<i32>, ImmLeaf<i32, [{ 38 return (((uint32_t)Imm) <= 15); 39 }]> { 40 let PrintMethod = "printPrefetchOp<true>"; 41 let ParserMatchClass = SVEPrefetchOperand; 42 } 43 44 class SVELogicalImmOperand<int Width> : AsmOperandClass { 45 let Name = "SVELogicalImm" # Width; 46 let DiagnosticType = "LogicalSecondSource"; 47 let PredicateMethod = "isLogicalImm<int" # Width # "_t>"; 48 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>"; 49 } 50 51 def sve_logical_imm8 : Operand<i64> { 52 let ParserMatchClass = SVELogicalImmOperand<8>; 53 let PrintMethod = "printLogicalImm<int8_t>"; 54 55 let MCOperandPredicate = [{ 56 if (!MCOp.isImm()) 57 return false; 58 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 59 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); 60 }]; 61 } 62 63 def sve_logical_imm16 : Operand<i64> { 64 let ParserMatchClass = SVELogicalImmOperand<16>; 65 let PrintMethod = "printLogicalImm<int16_t>"; 66 67 let MCOperandPredicate = [{ 68 if (!MCOp.isImm()) 69 return false; 70 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 71 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); 72 }]; 73 } 74 75 def sve_logical_imm32 : Operand<i64> { 76 let ParserMatchClass = SVELogicalImmOperand<32>; 77 let PrintMethod = "printLogicalImm<int32_t>"; 78 79 let MCOperandPredicate = [{ 80 if (!MCOp.isImm()) 81 return false; 82 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 83 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); 84 }]; 85 } 86 87 class SVEPreferredLogicalImmOperand<int Width> : AsmOperandClass { 88 let Name = "SVEPreferredLogicalImm" # Width; 89 let PredicateMethod = "isSVEPreferredLogicalImm<int" # Width # "_t>"; 90 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>"; 91 } 92 93 def sve_preferred_logical_imm16 : Operand<i64> { 94 let ParserMatchClass = SVEPreferredLogicalImmOperand<16>; 95 let PrintMethod = "printSVELogicalImm<int16_t>"; 96 97 let MCOperandPredicate = [{ 98 if (!MCOp.isImm()) 99 return false; 100 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 101 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && 102 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 103 }]; 104 } 105 106 def sve_preferred_logical_imm32 : Operand<i64> { 107 let ParserMatchClass = SVEPreferredLogicalImmOperand<32>; 108 let PrintMethod = "printSVELogicalImm<int32_t>"; 109 110 let MCOperandPredicate = [{ 111 if (!MCOp.isImm()) 112 return false; 113 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 114 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && 115 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 116 }]; 117 } 118 119 def sve_preferred_logical_imm64 : Operand<i64> { 120 let ParserMatchClass = SVEPreferredLogicalImmOperand<64>; 121 let PrintMethod = "printSVELogicalImm<int64_t>"; 122 123 let MCOperandPredicate = [{ 124 if (!MCOp.isImm()) 125 return false; 126 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 127 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && 128 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 129 }]; 130 } 131 132 class SVELogicalImmNotOperand<int Width> : AsmOperandClass { 133 let Name = "SVELogicalImm" # Width # "Not"; 134 let DiagnosticType = "LogicalSecondSource"; 135 let PredicateMethod = "isLogicalImm<int" # Width # "_t>"; 136 let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>"; 137 } 138 139 def sve_logical_imm8_not : Operand<i64> { 140 let ParserMatchClass = SVELogicalImmNotOperand<8>; 141 } 142 143 def sve_logical_imm16_not : Operand<i64> { 144 let ParserMatchClass = SVELogicalImmNotOperand<16>; 145 } 146 147 def sve_logical_imm32_not : Operand<i64> { 148 let ParserMatchClass = SVELogicalImmNotOperand<32>; 149 } 150 151 class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate> 152 : AsmOperandClass { 153 let Name = "SVE" # Infix # "Imm" # ElementWidth; 154 let DiagnosticType = "Invalid" # Name; 155 let RenderMethod = "addImmWithOptionalShiftOperands<8>"; 156 let ParserMethod = "tryParseImmWithOptionalShift"; 157 let PredicateMethod = Predicate; 158 } 159 160 def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm<int8_t>">; 161 def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm<int16_t>">; 162 def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm<int32_t>">; 163 def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm<int64_t>">; 164 165 def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">; 166 def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">; 167 def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">; 168 def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">; 169 170 class imm8_opt_lsl<int ElementWidth, string printType, 171 AsmOperandClass OpndClass, code Predicate> 172 : Operand<i32>, ImmLeaf<i32, Predicate> { 173 let EncoderMethod = "getImm8OptLsl"; 174 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">"; 175 let PrintMethod = "printImm8OptLsl<" # printType # ">"; 176 let ParserMatchClass = OpndClass; 177 let MIOperandInfo = (ops i32imm, i32imm); 178 } 179 180 def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{ 181 return AArch64_AM::isSVECpyImm<int8_t>(Imm); 182 }]>; 183 def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{ 184 return AArch64_AM::isSVECpyImm<int16_t>(Imm); 185 }]>; 186 def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{ 187 return AArch64_AM::isSVECpyImm<int32_t>(Imm); 188 }]>; 189 def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{ 190 return AArch64_AM::isSVECpyImm<int64_t>(Imm); 191 }]>; 192 193 def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{ 194 return AArch64_AM::isSVEAddSubImm<int8_t>(Imm); 195 }]>; 196 def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{ 197 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm); 198 }]>; 199 def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{ 200 return AArch64_AM::isSVEAddSubImm<int32_t>(Imm); 201 }]>; 202 def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{ 203 return AArch64_AM::isSVEAddSubImm<int64_t>(Imm); 204 }]>; 205 206 class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass { 207 let Name = "SVEExactFPImmOperand" # Suffix; 208 let DiagnosticType = "Invalid" # Name; 209 let ParserMethod = "tryParseFPImm<false>"; 210 let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">"; 211 let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">"; 212 } 213 214 class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> { 215 let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">"; 216 let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>; 217 } 218 219 def sve_fpimm_half_one 220 : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half", 221 "AArch64ExactFPImm::one">; 222 def sve_fpimm_half_two 223 : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half", 224 "AArch64ExactFPImm::two">; 225 def sve_fpimm_zero_one 226 : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero", 227 "AArch64ExactFPImm::one">; 228 229 def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{ 230 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 231 }]> { 232 let ParserMatchClass = Imm1_16Operand; 233 let EncoderMethod = "getSVEIncDecImm"; 234 let DecoderMethod = "DecodeSVEIncDecImm"; 235 } 236 237 //===----------------------------------------------------------------------===// 238 // SVE PTrue - These are used extensively throughout the pattern matching so 239 // it's important we define them first. 240 //===----------------------------------------------------------------------===// 241 242 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty> 243 : I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern), 244 asm, "\t$Pd, $pattern", 245 "", 246 []>, Sched<[]> { 247 bits<4> Pd; 248 bits<5> pattern; 249 let Inst{31-24} = 0b00100101; 250 let Inst{23-22} = sz8_64; 251 let Inst{21-19} = 0b011; 252 let Inst{18-17} = opc{2-1}; 253 let Inst{16} = opc{0}; 254 let Inst{15-10} = 0b111000; 255 let Inst{9-5} = pattern; 256 let Inst{4} = 0b0; 257 let Inst{3-0} = Pd; 258 259 let Defs = !if(!eq (opc{0}, 1), [NZCV], []); 260 } 261 262 multiclass sve_int_ptrue<bits<3> opc, string asm> { 263 def _B : sve_int_ptrue<0b00, opc, asm, PPR8>; 264 def _H : sve_int_ptrue<0b01, opc, asm, PPR16>; 265 def _S : sve_int_ptrue<0b10, opc, asm, PPR32>; 266 def _D : sve_int_ptrue<0b11, opc, asm, PPR64>; 267 268 def : InstAlias<asm # "\t$Pd", 269 (!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>; 270 def : InstAlias<asm # "\t$Pd", 271 (!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>; 272 def : InstAlias<asm # "\t$Pd", 273 (!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>; 274 def : InstAlias<asm # "\t$Pd", 275 (!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>; 276 } 277 278 let Predicates = [HasSVE] in { 279 defm PTRUE : sve_int_ptrue<0b000, "ptrue">; 280 defm PTRUES : sve_int_ptrue<0b001, "ptrues">; 281 } 282 283 284 //===----------------------------------------------------------------------===// 285 // SVE Predicate Misc Group 286 //===----------------------------------------------------------------------===// 287 288 class sve_int_pfalse<bits<6> opc, string asm> 289 : I<(outs PPR8:$Pd), (ins), 290 asm, "\t$Pd", 291 "", 292 []>, Sched<[]> { 293 bits<4> Pd; 294 let Inst{31-24} = 0b00100101; 295 let Inst{23-22} = opc{5-4}; 296 let Inst{21-19} = 0b011; 297 let Inst{18-16} = opc{3-1}; 298 let Inst{15-10} = 0b111001; 299 let Inst{9} = opc{0}; 300 let Inst{8-4} = 0b00000; 301 let Inst{3-0} = Pd; 302 } 303 304 class sve_int_ptest<bits<6> opc, string asm> 305 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), 306 asm, "\t$Pg, $Pn", 307 "", 308 []>, Sched<[]> { 309 bits<4> Pg; 310 bits<4> Pn; 311 let Inst{31-24} = 0b00100101; 312 let Inst{23-22} = opc{5-4}; 313 let Inst{21-19} = 0b010; 314 let Inst{18-16} = opc{3-1}; 315 let Inst{15-14} = 0b11; 316 let Inst{13-10} = Pg; 317 let Inst{9} = opc{0}; 318 let Inst{8-5} = Pn; 319 let Inst{4-0} = 0b00000; 320 321 let Defs = [NZCV]; 322 } 323 324 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm, 325 PPRRegOp pprty> 326 : I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn), 327 asm, "\t$Pdn, $Pg, $_Pdn", 328 "", 329 []>, Sched<[]> { 330 bits<4> Pdn; 331 bits<4> Pg; 332 let Inst{31-24} = 0b00100101; 333 let Inst{23-22} = sz8_64; 334 let Inst{21-19} = 0b011; 335 let Inst{18-16} = opc{4-2}; 336 let Inst{15-11} = 0b11000; 337 let Inst{10-9} = opc{1-0}; 338 let Inst{8-5} = Pg; 339 let Inst{4} = 0; 340 let Inst{3-0} = Pdn; 341 342 let Constraints = "$Pdn = $_Pdn"; 343 let Defs = [NZCV]; 344 } 345 346 multiclass sve_int_pfirst<bits<5> opc, string asm> { 347 def : sve_int_pfirst_next<0b01, opc, asm, PPR8>; 348 } 349 350 multiclass sve_int_pnext<bits<5> opc, string asm> { 351 def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>; 352 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>; 353 def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>; 354 def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>; 355 } 356 357 //===----------------------------------------------------------------------===// 358 // SVE Predicate Count Group 359 //===----------------------------------------------------------------------===// 360 361 class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm, 362 RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty> 363 : I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn), 364 asm, "\t$Rdn, $Pg", 365 "", 366 []>, Sched<[]> { 367 bits<5> Rdn; 368 bits<4> Pg; 369 let Inst{31-24} = 0b00100101; 370 let Inst{23-22} = sz8_64; 371 let Inst{21-19} = 0b101; 372 let Inst{18-16} = opc{4-2}; 373 let Inst{15-11} = 0b10001; 374 let Inst{10-9} = opc{1-0}; 375 let Inst{8-5} = Pg; 376 let Inst{4-0} = Rdn; 377 378 // Signed 32bit forms require their GPR operand printed. 379 let AsmString = !if(!eq(opc{4,2-0}, 0b0000), 380 !strconcat(asm, "\t$Rdn, $Pg, $_Rdn"), 381 !strconcat(asm, "\t$Rdn, $Pg")); 382 let Constraints = "$Rdn = $_Rdn"; 383 } 384 385 multiclass sve_int_count_r_s32<bits<5> opc, string asm> { 386 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>; 387 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>; 388 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>; 389 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>; 390 } 391 392 multiclass sve_int_count_r_u32<bits<5> opc, string asm> { 393 def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>; 394 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>; 395 def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>; 396 def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>; 397 } 398 399 multiclass sve_int_count_r_x64<bits<5> opc, string asm> { 400 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>; 401 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>; 402 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>; 403 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>; 404 } 405 406 class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm, 407 ZPRRegOp zprty> 408 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg), 409 asm, "\t$Zdn, $Pg", 410 "", 411 []>, Sched<[]> { 412 bits<4> Pg; 413 bits<5> Zdn; 414 let Inst{31-24} = 0b00100101; 415 let Inst{23-22} = sz8_64; 416 let Inst{21-19} = 0b101; 417 let Inst{18-16} = opc{4-2}; 418 let Inst{15-11} = 0b10000; 419 let Inst{10-9} = opc{1-0}; 420 let Inst{8-5} = Pg; 421 let Inst{4-0} = Zdn; 422 423 let Constraints = "$Zdn = $_Zdn"; 424 let DestructiveInstType = Destructive; 425 let ElementSize = ElementSizeNone; 426 } 427 428 multiclass sve_int_count_v<bits<5> opc, string asm> { 429 def _H : sve_int_count_v<0b01, opc, asm, ZPR16>; 430 def _S : sve_int_count_v<0b10, opc, asm, ZPR32>; 431 def _D : sve_int_count_v<0b11, opc, asm, ZPR64>; 432 } 433 434 class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm, 435 PPRRegOp pprty> 436 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), 437 asm, "\t$Rd, $Pg, $Pn", 438 "", 439 []>, Sched<[]> { 440 bits<4> Pg; 441 bits<4> Pn; 442 bits<5> Rd; 443 let Inst{31-24} = 0b00100101; 444 let Inst{23-22} = sz8_64; 445 let Inst{21-19} = 0b100; 446 let Inst{18-16} = opc{3-1}; 447 let Inst{15-14} = 0b10; 448 let Inst{13-10} = Pg; 449 let Inst{9} = opc{0}; 450 let Inst{8-5} = Pn; 451 let Inst{4-0} = Rd; 452 } 453 454 multiclass sve_int_pcount_pred<bits<4> opc, string asm> { 455 def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; 456 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; 457 def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; 458 def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; 459 } 460 461 //===----------------------------------------------------------------------===// 462 // SVE Element Count Group 463 //===----------------------------------------------------------------------===// 464 465 class sve_int_count<bits<3> opc, string asm> 466 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 467 asm, "\t$Rd, $pattern, mul $imm4", 468 "", 469 []>, Sched<[]> { 470 bits<5> Rd; 471 bits<4> imm4; 472 bits<5> pattern; 473 let Inst{31-24} = 0b00000100; 474 let Inst{23-22} = opc{2-1}; 475 let Inst{21-20} = 0b10; 476 let Inst{19-16} = imm4; 477 let Inst{15-11} = 0b11100; 478 let Inst{10} = opc{0}; 479 let Inst{9-5} = pattern; 480 let Inst{4-0} = Rd; 481 } 482 483 multiclass sve_int_count<bits<3> opc, string asm> { 484 def NAME : sve_int_count<opc, asm>; 485 486 def : InstAlias<asm # "\t$Rd, $pattern", 487 (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>; 488 def : InstAlias<asm # "\t$Rd", 489 (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>; 490 } 491 492 class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> 493 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 494 asm, "\t$Zdn, $pattern, mul $imm4", 495 "", 496 []>, Sched<[]> { 497 bits<5> Zdn; 498 bits<5> pattern; 499 bits<4> imm4; 500 let Inst{31-24} = 0b00000100; 501 let Inst{23-22} = opc{4-3}; 502 let Inst{21} = 0b1; 503 let Inst{20} = opc{2}; 504 let Inst{19-16} = imm4; 505 let Inst{15-12} = 0b1100; 506 let Inst{11-10} = opc{1-0}; 507 let Inst{9-5} = pattern; 508 let Inst{4-0} = Zdn; 509 510 let Constraints = "$Zdn = $_Zdn"; 511 let DestructiveInstType = Destructive; 512 let ElementSize = ElementSizeNone; 513 } 514 515 multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> { 516 def NAME : sve_int_countvlv<opc, asm, zprty>; 517 518 def : InstAlias<asm # "\t$Zdn, $pattern", 519 (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>; 520 def : InstAlias<asm # "\t$Zdn", 521 (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>; 522 } 523 524 class sve_int_pred_pattern_a<bits<3> opc, string asm> 525 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 526 asm, "\t$Rdn, $pattern, mul $imm4", 527 "", 528 []>, Sched<[]> { 529 bits<5> Rdn; 530 bits<5> pattern; 531 bits<4> imm4; 532 let Inst{31-24} = 0b00000100; 533 let Inst{23-22} = opc{2-1}; 534 let Inst{21-20} = 0b11; 535 let Inst{19-16} = imm4; 536 let Inst{15-11} = 0b11100; 537 let Inst{10} = opc{0}; 538 let Inst{9-5} = pattern; 539 let Inst{4-0} = Rdn; 540 541 let Constraints = "$Rdn = $_Rdn"; 542 } 543 544 multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> { 545 def NAME : sve_int_pred_pattern_a<opc, asm>; 546 547 def : InstAlias<asm # "\t$Rdn, $pattern", 548 (!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>; 549 def : InstAlias<asm # "\t$Rdn", 550 (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>; 551 } 552 553 class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt, 554 RegisterOperand st> 555 : I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 556 asm, "\t$Rdn, $pattern, mul $imm4", 557 "", 558 []>, Sched<[]> { 559 bits<5> Rdn; 560 bits<5> pattern; 561 bits<4> imm4; 562 let Inst{31-24} = 0b00000100; 563 let Inst{23-22} = opc{4-3}; 564 let Inst{21} = 0b1; 565 let Inst{20} = opc{2}; 566 let Inst{19-16} = imm4; 567 let Inst{15-12} = 0b1111; 568 let Inst{11-10} = opc{1-0}; 569 let Inst{9-5} = pattern; 570 let Inst{4-0} = Rdn; 571 572 // Signed 32bit forms require their GPR operand printed. 573 let AsmString = !if(!eq(opc{2,0}, 0b00), 574 !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"), 575 !strconcat(asm, "\t$Rdn, $pattern, mul $imm4")); 576 577 let Constraints = "$Rdn = $_Rdn"; 578 } 579 580 multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> { 581 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>; 582 583 def : InstAlias<asm # "\t$Rd, $Rn, $pattern", 584 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>; 585 def : InstAlias<asm # "\t$Rd, $Rn", 586 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>; 587 } 588 589 multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> { 590 def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>; 591 592 def : InstAlias<asm # "\t$Rdn, $pattern", 593 (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>; 594 def : InstAlias<asm # "\t$Rdn", 595 (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>; 596 } 597 598 multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> { 599 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>; 600 601 def : InstAlias<asm # "\t$Rdn, $pattern", 602 (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>; 603 def : InstAlias<asm # "\t$Rdn", 604 (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>; 605 } 606 607 608 //===----------------------------------------------------------------------===// 609 // SVE Permute - Cross Lane Group 610 //===----------------------------------------------------------------------===// 611 612 class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty, 613 RegisterClass srcRegType> 614 : I<(outs zprty:$Zd), (ins srcRegType:$Rn), 615 asm, "\t$Zd, $Rn", 616 "", 617 []>, Sched<[]> { 618 bits<5> Rn; 619 bits<5> Zd; 620 let Inst{31-24} = 0b00000101; 621 let Inst{23-22} = sz8_64; 622 let Inst{21-10} = 0b100000001110; 623 let Inst{9-5} = Rn; 624 let Inst{4-0} = Zd; 625 } 626 627 multiclass sve_int_perm_dup_r<string asm> { 628 def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>; 629 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>; 630 def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>; 631 def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>; 632 633 def : InstAlias<"mov $Zd, $Rn", 634 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>; 635 def : InstAlias<"mov $Zd, $Rn", 636 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>; 637 def : InstAlias<"mov $Zd, $Rn", 638 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>; 639 def : InstAlias<"mov $Zd, $Rn", 640 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>; 641 } 642 643 class sve_int_perm_dup_i<bits<5> tsz, Operand immtype, string asm, 644 ZPRRegOp zprty> 645 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx), 646 asm, "\t$Zd, $Zn$idx", 647 "", 648 []>, Sched<[]> { 649 bits<5> Zd; 650 bits<5> Zn; 651 bits<7> idx; 652 let Inst{31-24} = 0b00000101; 653 let Inst{23-22} = {?,?}; // imm3h 654 let Inst{21} = 0b1; 655 let Inst{20-16} = tsz; 656 let Inst{15-10} = 0b001000; 657 let Inst{9-5} = Zn; 658 let Inst{4-0} = Zd; 659 } 660 661 multiclass sve_int_perm_dup_i<string asm> { 662 def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> { 663 let Inst{23-22} = idx{5-4}; 664 let Inst{20-17} = idx{3-0}; 665 } 666 def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> { 667 let Inst{23-22} = idx{4-3}; 668 let Inst{20-18} = idx{2-0}; 669 } 670 def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> { 671 let Inst{23-22} = idx{3-2}; 672 let Inst{20-19} = idx{1-0}; 673 } 674 def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> { 675 let Inst{23-22} = idx{2-1}; 676 let Inst{20} = idx{0}; 677 } 678 def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> { 679 let Inst{23-22} = idx{1-0}; 680 } 681 682 def : InstAlias<"mov $Zd, $Zn$idx", 683 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>; 684 def : InstAlias<"mov $Zd, $Zn$idx", 685 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>; 686 def : InstAlias<"mov $Zd, $Zn$idx", 687 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>; 688 def : InstAlias<"mov $Zd, $Zn$idx", 689 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>; 690 def : InstAlias<"mov $Zd, $Zn$idx", 691 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>; 692 def : InstAlias<"mov $Zd, $Bn", 693 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>; 694 def : InstAlias<"mov $Zd, $Hn", 695 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>; 696 def : InstAlias<"mov $Zd, $Sn", 697 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>; 698 def : InstAlias<"mov $Zd, $Dn", 699 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>; 700 def : InstAlias<"mov $Zd, $Qn", 701 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; 702 } 703 704 class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty, 705 RegisterOperand VecList> 706 : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), 707 asm, "\t$Zd, $Zn, $Zm", 708 "", 709 []>, Sched<[]> { 710 bits<5> Zd; 711 bits<5> Zm; 712 bits<5> Zn; 713 let Inst{31-24} = 0b00000101; 714 let Inst{23-22} = sz8_64; 715 let Inst{21} = 0b1; 716 let Inst{20-16} = Zm; 717 let Inst{15-10} = 0b001100; 718 let Inst{9-5} = Zn; 719 let Inst{4-0} = Zd; 720 } 721 722 multiclass sve_int_perm_tbl<string asm> { 723 def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>; 724 def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>; 725 def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>; 726 def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>; 727 728 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 729 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; 730 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 731 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>; 732 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 733 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>; 734 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 735 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; 736 } 737 738 class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty> 739 : I<(outs zprty:$Zd), (ins zprty:$Zn), 740 asm, "\t$Zd, $Zn", 741 "", 742 []>, Sched<[]> { 743 bits<5> Zd; 744 bits<5> Zn; 745 let Inst{31-24} = 0b00000101; 746 let Inst{23-22} = sz8_64; 747 let Inst{21-10} = 0b111000001110; 748 let Inst{9-5} = Zn; 749 let Inst{4-0} = Zd; 750 } 751 752 multiclass sve_int_perm_reverse_z<string asm> { 753 def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>; 754 def _H : sve_int_perm_reverse_z<0b01, asm, ZPR16>; 755 def _S : sve_int_perm_reverse_z<0b10, asm, ZPR32>; 756 def _D : sve_int_perm_reverse_z<0b11, asm, ZPR64>; 757 } 758 759 class sve_int_perm_reverse_p<bits<2> sz8_64, string asm, PPRRegOp pprty> 760 : I<(outs pprty:$Pd), (ins pprty:$Pn), 761 asm, "\t$Pd, $Pn", 762 "", 763 []>, Sched<[]> { 764 bits<4> Pd; 765 bits<4> Pn; 766 let Inst{31-24} = 0b00000101; 767 let Inst{23-22} = sz8_64; 768 let Inst{21-9} = 0b1101000100000; 769 let Inst{8-5} = Pn; 770 let Inst{4} = 0b0; 771 let Inst{3-0} = Pd; 772 } 773 774 multiclass sve_int_perm_reverse_p<string asm> { 775 def _B : sve_int_perm_reverse_p<0b00, asm, PPR8>; 776 def _H : sve_int_perm_reverse_p<0b01, asm, PPR16>; 777 def _S : sve_int_perm_reverse_p<0b10, asm, PPR32>; 778 def _D : sve_int_perm_reverse_p<0b11, asm, PPR64>; 779 } 780 781 class sve_int_perm_unpk<bits<2> sz16_64, bits<2> opc, string asm, 782 ZPRRegOp zprty1, ZPRRegOp zprty2> 783 : I<(outs zprty1:$Zd), (ins zprty2:$Zn), 784 asm, "\t$Zd, $Zn", 785 "", []>, Sched<[]> { 786 bits<5> Zd; 787 bits<5> Zn; 788 let Inst{31-24} = 0b00000101; 789 let Inst{23-22} = sz16_64; 790 let Inst{21-18} = 0b1100; 791 let Inst{17-16} = opc; 792 let Inst{15-10} = 0b001110; 793 let Inst{9-5} = Zn; 794 let Inst{4-0} = Zd; 795 } 796 797 multiclass sve_int_perm_unpk<bits<2> opc, string asm> { 798 def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>; 799 def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>; 800 def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>; 801 } 802 803 class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty, 804 RegisterClass srcRegType> 805 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm), 806 asm, "\t$Zdn, $Rm", 807 "", 808 []>, Sched<[]> { 809 bits<5> Rm; 810 bits<5> Zdn; 811 let Inst{31-24} = 0b00000101; 812 let Inst{23-22} = sz8_64; 813 let Inst{21-10} = 0b100100001110; 814 let Inst{9-5} = Rm; 815 let Inst{4-0} = Zdn; 816 817 let Constraints = "$Zdn = $_Zdn"; 818 let DestructiveInstType = Destructive; 819 let ElementSize = ElementSizeNone; 820 } 821 822 multiclass sve_int_perm_insrs<string asm> { 823 def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>; 824 def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>; 825 def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>; 826 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>; 827 } 828 829 class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty, 830 RegisterClass srcRegType> 831 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm), 832 asm, "\t$Zdn, $Vm", 833 "", 834 []>, Sched<[]> { 835 bits<5> Vm; 836 bits<5> Zdn; 837 let Inst{31-24} = 0b00000101; 838 let Inst{23-22} = sz8_64; 839 let Inst{21-10} = 0b110100001110; 840 let Inst{9-5} = Vm; 841 let Inst{4-0} = Zdn; 842 843 let Constraints = "$Zdn = $_Zdn"; 844 let DestructiveInstType = Destructive; 845 let ElementSize = ElementSizeNone; 846 } 847 848 multiclass sve_int_perm_insrv<string asm> { 849 def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>; 850 def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>; 851 def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>; 852 def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>; 853 } 854 855 //===----------------------------------------------------------------------===// 856 // SVE Permute - Extract Group 857 //===----------------------------------------------------------------------===// 858 859 class sve_int_perm_extract_i<string asm> 860 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8), 861 asm, "\t$Zdn, $_Zdn, $Zm, $imm8", 862 "", []>, Sched<[]> { 863 bits<5> Zdn; 864 bits<5> Zm; 865 bits<8> imm8; 866 let Inst{31-21} = 0b00000101001; 867 let Inst{20-16} = imm8{7-3}; 868 let Inst{15-13} = 0b000; 869 let Inst{12-10} = imm8{2-0}; 870 let Inst{9-5} = Zm; 871 let Inst{4-0} = Zdn; 872 873 let Constraints = "$Zdn = $_Zdn"; 874 let DestructiveInstType = Destructive; 875 let ElementSize = ElementSizeNone; 876 } 877 878 //===----------------------------------------------------------------------===// 879 // SVE Vector Select Group 880 //===----------------------------------------------------------------------===// 881 882 class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty> 883 : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm), 884 asm, "\t$Zd, $Pg, $Zn, $Zm", 885 "", 886 []>, Sched<[]> { 887 bits<4> Pg; 888 bits<5> Zd; 889 bits<5> Zm; 890 bits<5> Zn; 891 let Inst{31-24} = 0b00000101; 892 let Inst{23-22} = sz8_64; 893 let Inst{21} = 0b1; 894 let Inst{20-16} = Zm; 895 let Inst{15-14} = 0b11; 896 let Inst{13-10} = Pg; 897 let Inst{9-5} = Zn; 898 let Inst{4-0} = Zd; 899 } 900 901 multiclass sve_int_sel_vvv<string asm> { 902 def _B : sve_int_sel_vvv<0b00, asm, ZPR8>; 903 def _H : sve_int_sel_vvv<0b01, asm, ZPR16>; 904 def _S : sve_int_sel_vvv<0b10, asm, ZPR32>; 905 def _D : sve_int_sel_vvv<0b11, asm, ZPR64>; 906 907 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 908 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>; 909 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 910 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>; 911 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 912 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>; 913 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 914 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>; 915 } 916 917 918 //===----------------------------------------------------------------------===// 919 // SVE Predicate Logical Operations Group 920 //===----------------------------------------------------------------------===// 921 922 class sve_int_pred_log<bits<4> opc, string asm> 923 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), 924 asm, "\t$Pd, $Pg/z, $Pn, $Pm", 925 "", 926 []>, Sched<[]> { 927 bits<4> Pd; 928 bits<4> Pg; 929 bits<4> Pm; 930 bits<4> Pn; 931 let Inst{31-24} = 0b00100101; 932 let Inst{23-22} = opc{3-2}; 933 let Inst{21-20} = 0b00; 934 let Inst{19-16} = Pm; 935 let Inst{15-14} = 0b01; 936 let Inst{13-10} = Pg; 937 let Inst{9} = opc{1}; 938 let Inst{8-5} = Pn; 939 let Inst{4} = opc{0}; 940 let Inst{3-0} = Pd; 941 942 // SEL has no predication qualifier. 943 let AsmString = !if(!eq(opc, 0b0011), 944 !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"), 945 !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm")); 946 947 let Defs = !if(!eq (opc{2}, 1), [NZCV], []); 948 } 949 950 951 //===----------------------------------------------------------------------===// 952 // SVE Logical Mask Immediate Group 953 //===----------------------------------------------------------------------===// 954 955 class sve_int_log_imm<bits<2> opc, string asm> 956 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13), 957 asm, "\t$Zdn, $_Zdn, $imms13", 958 "", []>, Sched<[]> { 959 bits<5> Zdn; 960 bits<13> imms13; 961 let Inst{31-24} = 0b00000101; 962 let Inst{23-22} = opc; 963 let Inst{21-18} = 0b0000; 964 let Inst{17-5} = imms13; 965 let Inst{4-0} = Zdn; 966 967 let Constraints = "$Zdn = $_Zdn"; 968 let DecoderMethod = "DecodeSVELogicalImmInstruction"; 969 let DestructiveInstType = Destructive; 970 let ElementSize = ElementSizeNone; 971 } 972 973 multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> { 974 def NAME : sve_int_log_imm<opc, asm>; 975 976 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 977 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>; 978 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 979 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>; 980 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 981 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>; 982 983 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 984 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>; 985 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 986 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>; 987 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 988 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>; 989 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 990 (!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>; 991 } 992 993 class sve_int_dup_mask_imm<string asm> 994 : I<(outs ZPR64:$Zd), (ins logical_imm64:$imms), 995 asm, "\t$Zd, $imms", 996 "", 997 []>, Sched<[]> { 998 bits<5> Zd; 999 bits<13> imms; 1000 let Inst{31-18} = 0b00000101110000; 1001 let Inst{17-5} = imms; 1002 let Inst{4-0} = Zd; 1003 1004 let isReMaterializable = 1; 1005 let DecoderMethod = "DecodeSVELogicalImmInstruction"; 1006 } 1007 1008 multiclass sve_int_dup_mask_imm<string asm> { 1009 def NAME : sve_int_dup_mask_imm<asm>; 1010 1011 def : InstAlias<"dupm $Zd, $imm", 1012 (!cast<Instruction>(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>; 1013 def : InstAlias<"dupm $Zd, $imm", 1014 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>; 1015 def : InstAlias<"dupm $Zd, $imm", 1016 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>; 1017 1018 // All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here. 1019 def : InstAlias<"mov $Zd, $imm", 1020 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>; 1021 def : InstAlias<"mov $Zd, $imm", 1022 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>; 1023 def : InstAlias<"mov $Zd, $imm", 1024 (!cast<Instruction>(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>; 1025 } 1026 1027 //===----------------------------------------------------------------------===// 1028 // SVE Integer Arithmetic - Unpredicated Group. 1029 //===----------------------------------------------------------------------===// 1030 1031 class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm, 1032 ZPRRegOp zprty> 1033 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1034 asm, "\t$Zd, $Zn, $Zm", 1035 "", []>, Sched<[]> { 1036 bits<5> Zd; 1037 bits<5> Zm; 1038 bits<5> Zn; 1039 let Inst{31-24} = 0b00000100; 1040 let Inst{23-22} = sz8_64; 1041 let Inst{21} = 0b1; 1042 let Inst{20-16} = Zm; 1043 let Inst{15-13} = 0b000; 1044 let Inst{12-10} = opc; 1045 let Inst{9-5} = Zn; 1046 let Inst{4-0} = Zd; 1047 } 1048 1049 multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> { 1050 def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; 1051 def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; 1052 def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; 1053 def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; 1054 } 1055 1056 //===----------------------------------------------------------------------===// 1057 // SVE Floating Point Arithmetic - Predicated Group 1058 //===----------------------------------------------------------------------===// 1059 1060 class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm, 1061 ZPRRegOp zprty, 1062 Operand imm_ty> 1063 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1), 1064 asm, "\t$Zdn, $Pg/m, $_Zdn, $i1", 1065 "", 1066 []>, Sched<[]> { 1067 bits<3> Pg; 1068 bits<5> Zdn; 1069 bit i1; 1070 let Inst{31-24} = 0b01100101; 1071 let Inst{23-22} = sz; 1072 let Inst{21-19} = 0b011; 1073 let Inst{18-16} = opc; 1074 let Inst{15-13} = 0b100; 1075 let Inst{12-10} = Pg; 1076 let Inst{9-6} = 0b0000; 1077 let Inst{5} = i1; 1078 let Inst{4-0} = Zdn; 1079 1080 let Constraints = "$Zdn = $_Zdn"; 1081 let DestructiveInstType = Destructive; 1082 let ElementSize = zprty.ElementSize; 1083 } 1084 1085 multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> { 1086 def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; 1087 def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; 1088 def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; 1089 } 1090 1091 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm, 1092 ZPRRegOp zprty> 1093 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 1094 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", 1095 "", 1096 []>, Sched<[]> { 1097 bits<3> Pg; 1098 bits<5> Zdn; 1099 bits<5> Zm; 1100 let Inst{31-24} = 0b01100101; 1101 let Inst{23-22} = sz; 1102 let Inst{21-20} = 0b00; 1103 let Inst{19-16} = opc; 1104 let Inst{15-13} = 0b100; 1105 let Inst{12-10} = Pg; 1106 let Inst{9-5} = Zm; 1107 let Inst{4-0} = Zdn; 1108 1109 let Constraints = "$Zdn = $_Zdn"; 1110 let DestructiveInstType = Destructive; 1111 let ElementSize = zprty.ElementSize; 1112 } 1113 1114 multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> { 1115 def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>; 1116 def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>; 1117 def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; 1118 } 1119 1120 class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty> 1121 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3), 1122 asm, "\t$Zdn, $_Zdn, $Zm, $imm3", 1123 "", 1124 []>, Sched<[]> { 1125 bits<5> Zdn; 1126 bits<5> Zm; 1127 bits<3> imm3; 1128 let Inst{31-24} = 0b01100101; 1129 let Inst{23-22} = sz; 1130 let Inst{21-19} = 0b010; 1131 let Inst{18-16} = imm3; 1132 let Inst{15-10} = 0b100000; 1133 let Inst{9-5} = Zm; 1134 let Inst{4-0} = Zdn; 1135 1136 let Constraints = "$Zdn = $_Zdn"; 1137 let DestructiveInstType = Destructive; 1138 let ElementSize = ElementSizeNone; 1139 } 1140 1141 multiclass sve_fp_ftmad<string asm> { 1142 def _H : sve_fp_ftmad<0b01, asm, ZPR16>; 1143 def _S : sve_fp_ftmad<0b10, asm, ZPR32>; 1144 def _D : sve_fp_ftmad<0b11, asm, ZPR64>; 1145 } 1146 1147 1148 //===----------------------------------------------------------------------===// 1149 // SVE Floating Point Arithmetic - Unpredicated Group 1150 //===----------------------------------------------------------------------===// 1151 1152 class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm, 1153 ZPRRegOp zprty> 1154 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1155 asm, "\t$Zd, $Zn, $Zm", 1156 "", []>, Sched<[]> { 1157 bits<5> Zd; 1158 bits<5> Zm; 1159 bits<5> Zn; 1160 let Inst{31-24} = 0b01100101; 1161 let Inst{23-22} = sz; 1162 let Inst{21} = 0b0; 1163 let Inst{20-16} = Zm; 1164 let Inst{15-13} = 0b000; 1165 let Inst{12-10} = opc; 1166 let Inst{9-5} = Zn; 1167 let Inst{4-0} = Zd; 1168 } 1169 1170 multiclass sve_fp_3op_u_zd<bits<3> opc, string asm> { 1171 def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>; 1172 def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>; 1173 def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>; 1174 } 1175 1176 //===----------------------------------------------------------------------===// 1177 // SVE Floating Point Fused Multiply-Add Group 1178 //===----------------------------------------------------------------------===// 1179 1180 class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty> 1181 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), 1182 asm, "\t$Zda, $Pg/m, $Zn, $Zm", 1183 "", 1184 []>, Sched<[]> { 1185 bits<3> Pg; 1186 bits<5> Zda; 1187 bits<5> Zm; 1188 bits<5> Zn; 1189 let Inst{31-24} = 0b01100101; 1190 let Inst{23-22} = sz; 1191 let Inst{21} = 0b1; 1192 let Inst{20-16} = Zm; 1193 let Inst{15} = 0b0; 1194 let Inst{14-13} = opc; 1195 let Inst{12-10} = Pg; 1196 let Inst{9-5} = Zn; 1197 let Inst{4-0} = Zda; 1198 1199 let Constraints = "$Zda = $_Zda"; 1200 let DestructiveInstType = Destructive; 1201 let ElementSize = zprty.ElementSize; 1202 } 1203 1204 multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> { 1205 def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>; 1206 def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>; 1207 def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>; 1208 } 1209 1210 class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm, 1211 ZPRRegOp zprty> 1212 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), 1213 asm, "\t$Zdn, $Pg/m, $Zm, $Za", 1214 "", 1215 []>, Sched<[]> { 1216 bits<3> Pg; 1217 bits<5> Za; 1218 bits<5> Zdn; 1219 bits<5> Zm; 1220 let Inst{31-24} = 0b01100101; 1221 let Inst{23-22} = sz; 1222 let Inst{21} = 0b1; 1223 let Inst{20-16} = Za; 1224 let Inst{15} = 0b1; 1225 let Inst{14-13} = opc; 1226 let Inst{12-10} = Pg; 1227 let Inst{9-5} = Zm; 1228 let Inst{4-0} = Zdn; 1229 1230 let Constraints = "$Zdn = $_Zdn"; 1231 let DestructiveInstType = Destructive; 1232 let ElementSize = zprty.ElementSize; 1233 } 1234 1235 multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> { 1236 def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>; 1237 def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>; 1238 def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>; 1239 } 1240 1241 //===----------------------------------------------------------------------===// 1242 // SVE Floating Point Multiply-Add - Indexed Group 1243 //===----------------------------------------------------------------------===// 1244 1245 class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm, 1246 ZPRRegOp zprty1, 1247 ZPRRegOp zprty2, Operand itype> 1248 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop), 1249 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { 1250 bits<5> Zda; 1251 bits<5> Zn; 1252 let Inst{31-24} = 0b01100100; 1253 let Inst{23-22} = sz; 1254 let Inst{21} = 0b1; 1255 let Inst{15-11} = 0; 1256 let Inst{10} = opc; 1257 let Inst{9-5} = Zn; 1258 let Inst{4-0} = Zda; 1259 1260 let Constraints = "$Zda = $_Zda"; 1261 let DestructiveInstType = Destructive; 1262 let ElementSize = ElementSizeNone; 1263 } 1264 1265 multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> { 1266 def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> { 1267 bits<3> Zm; 1268 bits<3> iop; 1269 let Inst{22} = iop{2}; 1270 let Inst{20-19} = iop{1-0}; 1271 let Inst{18-16} = Zm; 1272 } 1273 def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> { 1274 bits<3> Zm; 1275 bits<2> iop; 1276 let Inst{20-19} = iop; 1277 let Inst{18-16} = Zm; 1278 } 1279 def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> { 1280 bits<4> Zm; 1281 bit iop; 1282 let Inst{20} = iop; 1283 let Inst{19-16} = Zm; 1284 } 1285 } 1286 1287 1288 //===----------------------------------------------------------------------===// 1289 // SVE Floating Point Multiply - Indexed Group 1290 //===----------------------------------------------------------------------===// 1291 1292 class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty, 1293 ZPRRegOp zprty2, Operand itype> 1294 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop), 1295 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { 1296 bits<5> Zd; 1297 bits<5> Zn; 1298 let Inst{31-24} = 0b01100100; 1299 let Inst{23-22} = sz; 1300 let Inst{21} = 0b1; 1301 let Inst{15-10} = 0b001000; 1302 let Inst{9-5} = Zn; 1303 let Inst{4-0} = Zd; 1304 } 1305 1306 multiclass sve_fp_fmul_by_indexed_elem<string asm> { 1307 def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH> { 1308 bits<3> Zm; 1309 bits<3> iop; 1310 let Inst{22} = iop{2}; 1311 let Inst{20-19} = iop{1-0}; 1312 let Inst{18-16} = Zm; 1313 } 1314 def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS> { 1315 bits<3> Zm; 1316 bits<2> iop; 1317 let Inst{20-19} = iop; 1318 let Inst{18-16} = Zm; 1319 } 1320 def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD> { 1321 bits<4> Zm; 1322 bit iop; 1323 let Inst{20} = iop; 1324 let Inst{19-16} = Zm; 1325 } 1326 } 1327 1328 //===----------------------------------------------------------------------===// 1329 // SVE Floating Point Complex Multiply-Add Group 1330 //===----------------------------------------------------------------------===// 1331 1332 class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty> 1333 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm, 1334 complexrotateop:$imm), 1335 asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm", 1336 "", []>, Sched<[]> { 1337 bits<5> Zda; 1338 bits<3> Pg; 1339 bits<5> Zn; 1340 bits<5> Zm; 1341 bits<2> imm; 1342 let Inst{31-24} = 0b01100100; 1343 let Inst{23-22} = sz; 1344 let Inst{21} = 0; 1345 let Inst{20-16} = Zm; 1346 let Inst{15} = 0; 1347 let Inst{14-13} = imm; 1348 let Inst{12-10} = Pg; 1349 let Inst{9-5} = Zn; 1350 let Inst{4-0} = Zda; 1351 1352 let Constraints = "$Zda = $_Zda"; 1353 let DestructiveInstType = Destructive; 1354 let ElementSize = zprty.ElementSize; 1355 } 1356 1357 multiclass sve_fp_fcmla<string asm> { 1358 def _H : sve_fp_fcmla<0b01, asm, ZPR16>; 1359 def _S : sve_fp_fcmla<0b10, asm, ZPR32>; 1360 def _D : sve_fp_fcmla<0b11, asm, ZPR64>; 1361 } 1362 1363 //===----------------------------------------------------------------------===// 1364 // SVE Floating Point Complex Multiply-Add - Indexed Group 1365 //===----------------------------------------------------------------------===// 1366 1367 class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm, 1368 ZPRRegOp zprty, 1369 ZPRRegOp zprty2, Operand itype> 1370 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop, 1371 complexrotateop:$imm), 1372 asm, "\t$Zda, $Zn, $Zm$iop, $imm", 1373 "", []>, Sched<[]> { 1374 bits<5> Zda; 1375 bits<5> Zn; 1376 bits<2> imm; 1377 let Inst{31-24} = 0b01100100; 1378 let Inst{23-22} = sz; 1379 let Inst{21} = 0b1; 1380 let Inst{15-12} = 0b0001; 1381 let Inst{11-10} = imm; 1382 let Inst{9-5} = Zn; 1383 let Inst{4-0} = Zda; 1384 1385 let Constraints = "$Zda = $_Zda"; 1386 let DestructiveInstType = Destructive; 1387 let ElementSize = ElementSizeNone; 1388 } 1389 1390 multiclass sve_fp_fcmla_by_indexed_elem<string asm> { 1391 def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> { 1392 bits<3> Zm; 1393 bits<2> iop; 1394 let Inst{20-19} = iop; 1395 let Inst{18-16} = Zm; 1396 } 1397 def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> { 1398 bits<4> Zm; 1399 bits<1> iop; 1400 let Inst{20} = iop; 1401 let Inst{19-16} = Zm; 1402 } 1403 } 1404 1405 //===----------------------------------------------------------------------===// 1406 // SVE Floating Point Complex Addition Group 1407 //===----------------------------------------------------------------------===// 1408 1409 class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty> 1410 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, 1411 complexrotateopodd:$imm), 1412 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm", 1413 "", 1414 []>, Sched<[]> { 1415 bits<5> Zdn; 1416 bits<5> Zm; 1417 bits<3> Pg; 1418 bit imm; 1419 let Inst{31-24} = 0b01100100; 1420 let Inst{23-22} = sz; 1421 let Inst{21-17} = 0; 1422 let Inst{16} = imm; 1423 let Inst{15-13} = 0b100; 1424 let Inst{12-10} = Pg; 1425 let Inst{9-5} = Zm; 1426 let Inst{4-0} = Zdn; 1427 1428 let Constraints = "$Zdn = $_Zdn"; 1429 let DestructiveInstType = Destructive; 1430 let ElementSize = zprty.ElementSize; 1431 } 1432 1433 multiclass sve_fp_fcadd<string asm> { 1434 def _H : sve_fp_fcadd<0b01, asm, ZPR16>; 1435 def _S : sve_fp_fcadd<0b10, asm, ZPR32>; 1436 def _D : sve_fp_fcadd<0b11, asm, ZPR64>; 1437 } 1438 1439 //===----------------------------------------------------------------------===// 1440 // SVE Stack Allocation Group 1441 //===----------------------------------------------------------------------===// 1442 1443 class sve_int_arith_vl<bit opc, string asm> 1444 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6), 1445 asm, "\t$Rd, $Rn, $imm6", 1446 "", 1447 []>, Sched<[]> { 1448 bits<5> Rd; 1449 bits<5> Rn; 1450 bits<6> imm6; 1451 let Inst{31-23} = 0b000001000; 1452 let Inst{22} = opc; 1453 let Inst{21} = 0b1; 1454 let Inst{20-16} = Rn; 1455 let Inst{15-11} = 0b01010; 1456 let Inst{10-5} = imm6; 1457 let Inst{4-0} = Rd; 1458 } 1459 1460 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm> 1461 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6), 1462 asm, "\t$Rd, $imm6", 1463 "", 1464 []>, Sched<[]> { 1465 bits<5> Rd; 1466 bits<6> imm6; 1467 let Inst{31-23} = 0b000001001; 1468 let Inst{22} = op; 1469 let Inst{21} = 0b1; 1470 let Inst{20-16} = opc2{4-0}; 1471 let Inst{15-11} = 0b01010; 1472 let Inst{10-5} = imm6; 1473 let Inst{4-0} = Rd; 1474 } 1475 1476 //===----------------------------------------------------------------------===// 1477 // SVE Permute - In Lane Group 1478 //===----------------------------------------------------------------------===// 1479 1480 class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm, 1481 ZPRRegOp zprty> 1482 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1483 asm, "\t$Zd, $Zn, $Zm", 1484 "", 1485 []>, Sched<[]> { 1486 bits<5> Zd; 1487 bits<5> Zm; 1488 bits<5> Zn; 1489 let Inst{31-24} = 0b00000101; 1490 let Inst{23-22} = sz8_64; 1491 let Inst{21} = 0b1; 1492 let Inst{20-16} = Zm; 1493 let Inst{15-13} = 0b011; 1494 let Inst{12-10} = opc; 1495 let Inst{9-5} = Zn; 1496 let Inst{4-0} = Zd; 1497 } 1498 1499 multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> { 1500 def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>; 1501 def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>; 1502 def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>; 1503 def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>; 1504 } 1505 1506 //===----------------------------------------------------------------------===// 1507 // SVE Floating Point Unary Operations Group 1508 //===----------------------------------------------------------------------===// 1509 1510 class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype, 1511 RegisterOperand o_zprtype, ElementSizeEnum size> 1512 : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn), 1513 asm, "\t$Zd, $Pg/m, $Zn", 1514 "", 1515 []>, Sched<[]> { 1516 bits<3> Pg; 1517 bits<5> Zd; 1518 bits<5> Zn; 1519 let Inst{31-24} = 0b01100101; 1520 let Inst{23-22} = opc{6-5}; 1521 let Inst{21} = 0b0; 1522 let Inst{20-16} = opc{4-0}; 1523 let Inst{15-13} = 0b101; 1524 let Inst{12-10} = Pg; 1525 let Inst{9-5} = Zn; 1526 let Inst{4-0} = Zd; 1527 1528 let Constraints = "$Zd = $_Zd"; 1529 let DestructiveInstType = Destructive; 1530 let ElementSize = size; 1531 } 1532 1533 multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> { 1534 def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>; 1535 def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>; 1536 def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>; 1537 } 1538 1539 //===----------------------------------------------------------------------===// 1540 // SVE Floating Point Unary Operations - Unpredicated Group 1541 //===----------------------------------------------------------------------===// 1542 1543 class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm, 1544 ZPRRegOp zprty> 1545 : I<(outs zprty:$Zd), (ins zprty:$Zn), 1546 asm, "\t$Zd, $Zn", 1547 "", 1548 []>, Sched<[]> { 1549 bits<5> Zd; 1550 bits<5> Zn; 1551 let Inst{31-24} = 0b01100101; 1552 let Inst{23-22} = sz; 1553 let Inst{21-19} = 0b001; 1554 let Inst{18-16} = opc; 1555 let Inst{15-10} = 0b001100; 1556 let Inst{9-5} = Zn; 1557 let Inst{4-0} = Zd; 1558 } 1559 1560 multiclass sve_fp_2op_u_zd<bits<3> opc, string asm> { 1561 def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>; 1562 def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>; 1563 def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>; 1564 } 1565 1566 //===----------------------------------------------------------------------===// 1567 // SVE Integer Arithmetic - Binary Predicated Group 1568 //===----------------------------------------------------------------------===// 1569 1570 class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc, 1571 string asm, ZPRRegOp zprty> 1572 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 1573 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { 1574 bits<3> Pg; 1575 bits<5> Zdn; 1576 bits<5> Zm; 1577 let Inst{31-24} = 0b00000100; 1578 let Inst{23-22} = sz8_64; 1579 let Inst{21} = 0b0; 1580 let Inst{20-19} = fmt; 1581 let Inst{18-16} = opc; 1582 let Inst{15-13} = 0b000; 1583 let Inst{12-10} = Pg; 1584 let Inst{9-5} = Zm; 1585 let Inst{4-0} = Zdn; 1586 1587 let Constraints = "$Zdn = $_Zdn"; 1588 let DestructiveInstType = Destructive; 1589 let ElementSize = zprty.ElementSize; 1590 } 1591 1592 multiclass sve_int_bin_pred_log<bits<3> opc, string asm> { 1593 def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; 1594 def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; 1595 def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; 1596 def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; 1597 } 1598 1599 multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { 1600 def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; 1601 def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; 1602 def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; 1603 def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; 1604 } 1605 1606 multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> { 1607 def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; 1608 def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; 1609 def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; 1610 def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; 1611 } 1612 1613 multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> { 1614 def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>; 1615 def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>; 1616 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; 1617 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; 1618 } 1619 1620 // Special case for divides which are not defined for 8b/16b elements. 1621 multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> { 1622 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; 1623 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; 1624 } 1625 1626 //===----------------------------------------------------------------------===// 1627 // SVE Integer Multiply-Add Group 1628 //===----------------------------------------------------------------------===// 1629 1630 class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm, 1631 ZPRRegOp zprty> 1632 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), 1633 asm, "\t$Zdn, $Pg/m, $Zm, $Za", 1634 "", 1635 []>, Sched<[]> { 1636 bits<3> Pg; 1637 bits<5> Zdn; 1638 bits<5> Za; 1639 bits<5> Zm; 1640 let Inst{31-24} = 0b00000100; 1641 let Inst{23-22} = sz8_64; 1642 let Inst{21} = 0b0; 1643 let Inst{20-16} = Zm; 1644 let Inst{15-14} = 0b11; 1645 let Inst{13} = opc; 1646 let Inst{12-10} = Pg; 1647 let Inst{9-5} = Za; 1648 let Inst{4-0} = Zdn; 1649 1650 let Constraints = "$Zdn = $_Zdn"; 1651 let DestructiveInstType = Destructive; 1652 let ElementSize = zprty.ElementSize; 1653 } 1654 1655 multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> { 1656 def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>; 1657 def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>; 1658 def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>; 1659 def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>; 1660 } 1661 1662 class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm, 1663 ZPRRegOp zprty> 1664 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), 1665 asm, "\t$Zda, $Pg/m, $Zn, $Zm", 1666 "", 1667 []>, Sched<[]> { 1668 bits<3> Pg; 1669 bits<5> Zda; 1670 bits<5> Zm; 1671 bits<5> Zn; 1672 let Inst{31-24} = 0b00000100; 1673 let Inst{23-22} = sz8_64; 1674 let Inst{21} = 0b0; 1675 let Inst{20-16} = Zm; 1676 let Inst{15-14} = 0b01; 1677 let Inst{13} = opc; 1678 let Inst{12-10} = Pg; 1679 let Inst{9-5} = Zn; 1680 let Inst{4-0} = Zda; 1681 1682 let Constraints = "$Zda = $_Zda"; 1683 let DestructiveInstType = Destructive; 1684 let ElementSize = zprty.ElementSize; 1685 } 1686 1687 multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> { 1688 def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>; 1689 def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>; 1690 def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>; 1691 def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>; 1692 } 1693 1694 //===----------------------------------------------------------------------===// 1695 // SVE Integer Dot Product Group 1696 //===----------------------------------------------------------------------===// 1697 1698 class sve_intx_dot<bit sz, bit U, string asm, ZPRRegOp zprty1, 1699 ZPRRegOp zprty2> 1700 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm, 1701 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { 1702 bits<5> Zda; 1703 bits<5> Zn; 1704 bits<5> Zm; 1705 let Inst{31-23} = 0b010001001; 1706 let Inst{22} = sz; 1707 let Inst{21} = 0; 1708 let Inst{20-16} = Zm; 1709 let Inst{15-11} = 0; 1710 let Inst{10} = U; 1711 let Inst{9-5} = Zn; 1712 let Inst{4-0} = Zda; 1713 1714 let Constraints = "$Zda = $_Zda"; 1715 let DestructiveInstType = Destructive; 1716 let ElementSize = zprty1.ElementSize; 1717 } 1718 1719 multiclass sve_intx_dot<bit opc, string asm> { 1720 def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>; 1721 def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>; 1722 } 1723 1724 //===----------------------------------------------------------------------===// 1725 // SVE Integer Dot Product Group - Indexed Group 1726 //===----------------------------------------------------------------------===// 1727 1728 class sve_intx_dot_by_indexed_elem<bit sz, bit U, string asm, 1729 ZPRRegOp zprty1, ZPRRegOp zprty2, 1730 ZPRRegOp zprty3, Operand itype> 1731 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), 1732 asm, "\t$Zda, $Zn, $Zm$iop", 1733 "", []>, Sched<[]> { 1734 bits<5> Zda; 1735 bits<5> Zn; 1736 let Inst{31-23} = 0b010001001; 1737 let Inst{22} = sz; 1738 let Inst{21} = 0b1; 1739 let Inst{15-11} = 0; 1740 let Inst{10} = U; 1741 let Inst{9-5} = Zn; 1742 let Inst{4-0} = Zda; 1743 1744 let Constraints = "$Zda = $_Zda"; 1745 let DestructiveInstType = Destructive; 1746 let ElementSize = ElementSizeNone; 1747 } 1748 1749 multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> { 1750 def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { 1751 bits<2> iop; 1752 bits<3> Zm; 1753 let Inst{20-19} = iop; 1754 let Inst{18-16} = Zm; 1755 } 1756 def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { 1757 bits<1> iop; 1758 bits<4> Zm; 1759 let Inst{20} = iop; 1760 let Inst{19-16} = Zm; 1761 } 1762 } 1763 1764 //===----------------------------------------------------------------------===// 1765 // SVE Integer Arithmetic - Unary Predicated Group 1766 //===----------------------------------------------------------------------===// 1767 1768 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc, 1769 string asm, ZPRRegOp zprty> 1770 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), 1771 asm, "\t$Zd, $Pg/m, $Zn", 1772 "", 1773 []>, Sched<[]> { 1774 bits<3> Pg; 1775 bits<5> Zd; 1776 bits<5> Zn; 1777 let Inst{31-24} = 0b00000100; 1778 let Inst{23-22} = sz8_64; 1779 let Inst{21-20} = 0b01; 1780 let Inst{19} = opc{0}; 1781 let Inst{18-16} = opc{3-1}; 1782 let Inst{15-13} = 0b101; 1783 let Inst{12-10} = Pg; 1784 let Inst{9-5} = Zn; 1785 let Inst{4-0} = Zd; 1786 1787 let Constraints = "$Zd = $_Zd"; 1788 let DestructiveInstType = Destructive; 1789 let ElementSize = zprty.ElementSize; 1790 } 1791 1792 multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> { 1793 def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>; 1794 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; 1795 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 1796 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 1797 } 1798 1799 multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> { 1800 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; 1801 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 1802 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 1803 } 1804 1805 multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> { 1806 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 1807 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 1808 } 1809 1810 multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> { 1811 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 1812 } 1813 1814 multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm> { 1815 def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>; 1816 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; 1817 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; 1818 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; 1819 } 1820 1821 multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> { 1822 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; 1823 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; 1824 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; 1825 } 1826 1827 //===----------------------------------------------------------------------===// 1828 // SVE Integer Wide Immediate - Unpredicated Group 1829 //===----------------------------------------------------------------------===// 1830 class sve_int_dup_imm<bits<2> sz8_64, string asm, 1831 ZPRRegOp zprty, Operand immtype> 1832 : I<(outs zprty:$Zd), (ins immtype:$imm), 1833 asm, "\t$Zd, $imm", 1834 "", 1835 []>, Sched<[]> { 1836 bits<5> Zd; 1837 bits<9> imm; 1838 let Inst{31-24} = 0b00100101; 1839 let Inst{23-22} = sz8_64; 1840 let Inst{21-14} = 0b11100011; 1841 let Inst{13} = imm{8}; // sh 1842 let Inst{12-5} = imm{7-0}; // imm8 1843 let Inst{4-0} = Zd; 1844 1845 let isReMaterializable = 1; 1846 } 1847 1848 multiclass sve_int_dup_imm<string asm> { 1849 def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>; 1850 def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>; 1851 def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>; 1852 def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>; 1853 1854 def : InstAlias<"mov $Zd, $imm", 1855 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>; 1856 def : InstAlias<"mov $Zd, $imm", 1857 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>; 1858 def : InstAlias<"mov $Zd, $imm", 1859 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>; 1860 def : InstAlias<"mov $Zd, $imm", 1861 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>; 1862 1863 def : InstAlias<"fmov $Zd, #0.0", 1864 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>; 1865 def : InstAlias<"fmov $Zd, #0.0", 1866 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>; 1867 def : InstAlias<"fmov $Zd, #0.0", 1868 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>; 1869 } 1870 1871 class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype, 1872 string asm, ZPRRegOp zprty> 1873 : I<(outs zprty:$Zd), (ins fpimmtype:$imm8), 1874 asm, "\t$Zd, $imm8", 1875 "", 1876 []>, Sched<[]> { 1877 bits<5> Zd; 1878 bits<8> imm8; 1879 let Inst{31-24} = 0b00100101; 1880 let Inst{23-22} = sz8_64; 1881 let Inst{21-14} = 0b11100111; 1882 let Inst{13} = 0b0; 1883 let Inst{12-5} = imm8; 1884 let Inst{4-0} = Zd; 1885 1886 let isReMaterializable = 1; 1887 } 1888 1889 multiclass sve_int_dup_fpimm<string asm> { 1890 def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>; 1891 def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>; 1892 def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>; 1893 1894 def : InstAlias<"fmov $Zd, $imm8", 1895 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>; 1896 def : InstAlias<"fmov $Zd, $imm8", 1897 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>; 1898 def : InstAlias<"fmov $Zd, $imm8", 1899 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>; 1900 } 1901 1902 class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm, 1903 ZPRRegOp zprty, Operand immtype> 1904 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), 1905 asm, "\t$Zdn, $_Zdn, $imm", 1906 "", 1907 []>, Sched<[]> { 1908 bits<5> Zdn; 1909 bits<9> imm; 1910 let Inst{31-24} = 0b00100101; 1911 let Inst{23-22} = sz8_64; 1912 let Inst{21-19} = 0b100; 1913 let Inst{18-16} = opc; 1914 let Inst{15-14} = 0b11; 1915 let Inst{13} = imm{8}; // sh 1916 let Inst{12-5} = imm{7-0}; // imm8 1917 let Inst{4-0} = Zdn; 1918 1919 let Constraints = "$Zdn = $_Zdn"; 1920 let DestructiveInstType = Destructive; 1921 let ElementSize = ElementSizeNone; 1922 } 1923 1924 multiclass sve_int_arith_imm0<bits<3> opc, string asm> { 1925 def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>; 1926 def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>; 1927 def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>; 1928 def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; 1929 } 1930 1931 class sve_int_arith_imm<bits<2> sz8_64, bits<6> opc, string asm, 1932 ZPRRegOp zprty, Operand immtype> 1933 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), 1934 asm, "\t$Zdn, $_Zdn, $imm", 1935 "", 1936 []>, Sched<[]> { 1937 bits<5> Zdn; 1938 bits<8> imm; 1939 let Inst{31-24} = 0b00100101; 1940 let Inst{23-22} = sz8_64; 1941 let Inst{21-16} = opc; 1942 let Inst{15-13} = 0b110; 1943 let Inst{12-5} = imm; 1944 let Inst{4-0} = Zdn; 1945 1946 let Constraints = "$Zdn = $_Zdn"; 1947 let DestructiveInstType = Destructive; 1948 let ElementSize = ElementSizeNone; 1949 } 1950 1951 multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> { 1952 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>; 1953 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>; 1954 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>; 1955 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>; 1956 } 1957 1958 multiclass sve_int_arith_imm2<string asm> { 1959 def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>; 1960 def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>; 1961 def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>; 1962 def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>; 1963 } 1964 1965 //===----------------------------------------------------------------------===// 1966 // SVE Bitwise Logical - Unpredicated Group 1967 //===----------------------------------------------------------------------===// 1968 1969 class sve_int_bin_cons_log<bits<2> opc, string asm> 1970 : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), 1971 asm, "\t$Zd, $Zn, $Zm", 1972 "", 1973 []>, Sched<[]> { 1974 bits<5> Zd; 1975 bits<5> Zm; 1976 bits<5> Zn; 1977 let Inst{31-24} = 0b00000100; 1978 let Inst{23-22} = opc{1-0}; 1979 let Inst{21} = 0b1; 1980 let Inst{20-16} = Zm; 1981 let Inst{15-10} = 0b001100; 1982 let Inst{9-5} = Zn; 1983 let Inst{4-0} = Zd; 1984 } 1985 1986 1987 //===----------------------------------------------------------------------===// 1988 // SVE Integer Wide Immediate - Predicated Group 1989 //===----------------------------------------------------------------------===// 1990 1991 class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype, 1992 string asm, ZPRRegOp zprty> 1993 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8), 1994 asm, "\t$Zd, $Pg/m, $imm8", 1995 "", 1996 []>, Sched<[]> { 1997 bits<4> Pg; 1998 bits<5> Zd; 1999 bits<8> imm8; 2000 let Inst{31-24} = 0b00000101; 2001 let Inst{23-22} = sz; 2002 let Inst{21-20} = 0b01; 2003 let Inst{19-16} = Pg; 2004 let Inst{15-13} = 0b110; 2005 let Inst{12-5} = imm8; 2006 let Inst{4-0} = Zd; 2007 2008 let Constraints = "$Zd = $_Zd"; 2009 let DestructiveInstType = Destructive; 2010 let ElementSize = zprty.ElementSize; 2011 } 2012 2013 multiclass sve_int_dup_fpimm_pred<string asm> { 2014 def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>; 2015 def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>; 2016 def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>; 2017 2018 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 2019 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>; 2020 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 2021 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>; 2022 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 2023 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>; 2024 } 2025 2026 class sve_int_dup_imm_pred<bits<2> sz8_64, bit m, string asm, 2027 ZPRRegOp zprty, string pred_qual, dag iops> 2028 : I<(outs zprty:$Zd), iops, 2029 asm, "\t$Zd, $Pg"#pred_qual#", $imm", 2030 "", []>, Sched<[]> { 2031 bits<5> Zd; 2032 bits<4> Pg; 2033 bits<9> imm; 2034 let Inst{31-24} = 0b00000101; 2035 let Inst{23-22} = sz8_64; 2036 let Inst{21-20} = 0b01; 2037 let Inst{19-16} = Pg; 2038 let Inst{15} = 0b0; 2039 let Inst{14} = m; 2040 let Inst{13} = imm{8}; // sh 2041 let Inst{12-5} = imm{7-0}; // imm8 2042 let Inst{4-0} = Zd; 2043 2044 let DestructiveInstType = Destructive; 2045 let ElementSize = zprty.ElementSize; 2046 } 2047 2048 multiclass sve_int_dup_imm_pred_merge<string asm> { 2049 let Constraints = "$Zd = $_Zd" in { 2050 def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; 2051 def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; 2052 def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; 2053 def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; 2054 } 2055 2056 def : InstAlias<"mov $Zd, $Pg/m, $imm", 2057 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; 2058 def : InstAlias<"mov $Zd, $Pg/m, $imm", 2059 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; 2060 def : InstAlias<"mov $Zd, $Pg/m, $imm", 2061 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; 2062 def : InstAlias<"mov $Zd, $Pg/m, $imm", 2063 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; 2064 2065 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 2066 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>; 2067 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 2068 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>; 2069 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 2070 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>; 2071 } 2072 2073 multiclass sve_int_dup_imm_pred_zero<string asm> { 2074 def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; 2075 def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; 2076 def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; 2077 def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; 2078 2079 def : InstAlias<"mov $Zd, $Pg/z, $imm", 2080 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; 2081 def : InstAlias<"mov $Zd, $Pg/z, $imm", 2082 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; 2083 def : InstAlias<"mov $Zd, $Pg/z, $imm", 2084 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; 2085 def : InstAlias<"mov $Zd, $Pg/z, $imm", 2086 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; 2087 } 2088 2089 //===----------------------------------------------------------------------===// 2090 // SVE Integer Compare - Vectors Group 2091 //===----------------------------------------------------------------------===// 2092 2093 class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm, 2094 PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2> 2095 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm), 2096 asm, "\t$Pd, $Pg/z, $Zn, $Zm", 2097 "", 2098 []>, Sched<[]> { 2099 bits<4> Pd; 2100 bits<3> Pg; 2101 bits<5> Zm; 2102 bits<5> Zn; 2103 let Inst{31-24} = 0b00100100; 2104 let Inst{23-22} = sz8_64; 2105 let Inst{21} = 0b0; 2106 let Inst{20-16} = Zm; 2107 let Inst{15} = opc{2}; 2108 let Inst{14} = cmp_1; 2109 let Inst{13} = opc{1}; 2110 let Inst{12-10} = Pg; 2111 let Inst{9-5} = Zn; 2112 let Inst{4} = opc{0}; 2113 let Inst{3-0} = Pd; 2114 2115 let Defs = [NZCV]; 2116 } 2117 2118 multiclass sve_int_cmp_0<bits<3> opc, string asm> { 2119 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>; 2120 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>; 2121 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>; 2122 def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>; 2123 } 2124 2125 multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> { 2126 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; 2127 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; 2128 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; 2129 } 2130 2131 multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> { 2132 def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; 2133 def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; 2134 def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; 2135 } 2136 2137 2138 //===----------------------------------------------------------------------===// 2139 // SVE Integer Compare - Signed Immediate Group 2140 //===----------------------------------------------------------------------===// 2141 2142 class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty, 2143 ZPRRegOp zprty, 2144 Operand immtype> 2145 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5), 2146 asm, "\t$Pd, $Pg/z, $Zn, $imm5", 2147 "", 2148 []>, Sched<[]> { 2149 bits<4> Pd; 2150 bits<3> Pg; 2151 bits<5> Zn; 2152 bits<5> imm5; 2153 let Inst{31-24} = 0b00100101; 2154 let Inst{23-22} = sz8_64; 2155 let Inst{21} = 0b0; 2156 let Inst{20-16} = imm5; 2157 let Inst{15} = opc{2}; 2158 let Inst{14} = 0b0; 2159 let Inst{13} = opc{1}; 2160 let Inst{12-10} = Pg; 2161 let Inst{9-5} = Zn; 2162 let Inst{4} = opc{0}; 2163 let Inst{3-0} = Pd; 2164 2165 let Defs = [NZCV]; 2166 } 2167 2168 multiclass sve_int_scmp_vi<bits<3> opc, string asm> { 2169 def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>; 2170 def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>; 2171 def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>; 2172 def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>; 2173 } 2174 2175 2176 //===----------------------------------------------------------------------===// 2177 // SVE Integer Compare - Unsigned Immediate Group 2178 //===----------------------------------------------------------------------===// 2179 2180 class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty, 2181 ZPRRegOp zprty, Operand immtype> 2182 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7), 2183 asm, "\t$Pd, $Pg/z, $Zn, $imm7", 2184 "", 2185 []>, Sched<[]> { 2186 bits<4> Pd; 2187 bits<3> Pg; 2188 bits<5> Zn; 2189 bits<7> imm7; 2190 let Inst{31-24} = 0b00100100; 2191 let Inst{23-22} = sz8_64; 2192 let Inst{21} = 1; 2193 let Inst{20-14} = imm7; 2194 let Inst{13} = opc{1}; 2195 let Inst{12-10} = Pg; 2196 let Inst{9-5} = Zn; 2197 let Inst{4} = opc{0}; 2198 let Inst{3-0} = Pd; 2199 2200 let Defs = [NZCV]; 2201 } 2202 2203 multiclass sve_int_ucmp_vi<bits<2> opc, string asm> { 2204 def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>; 2205 def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>; 2206 def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>; 2207 def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>; 2208 } 2209 2210 2211 //===----------------------------------------------------------------------===// 2212 // SVE Integer Compare - Scalars Group 2213 //===----------------------------------------------------------------------===// 2214 2215 class sve_int_cterm<bit sz, bit opc, string asm, RegisterClass rt> 2216 : I<(outs), (ins rt:$Rn, rt:$Rm), 2217 asm, "\t$Rn, $Rm", 2218 "", 2219 []>, Sched<[]> { 2220 bits<5> Rm; 2221 bits<5> Rn; 2222 let Inst{31-23} = 0b001001011; 2223 let Inst{22} = sz; 2224 let Inst{21} = 0b1; 2225 let Inst{20-16} = Rm; 2226 let Inst{15-10} = 0b001000; 2227 let Inst{9-5} = Rn; 2228 let Inst{4} = opc; 2229 let Inst{3-0} = 0b0000; 2230 2231 let Defs = [NZCV]; 2232 } 2233 2234 class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm, 2235 RegisterClass gprty, PPRRegOp pprty> 2236 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm), 2237 asm, "\t$Pd, $Rn, $Rm", 2238 "", []>, Sched<[]> { 2239 bits<4> Pd; 2240 bits<5> Rm; 2241 bits<5> Rn; 2242 let Inst{31-24} = 0b00100101; 2243 let Inst{23-22} = sz8_64; 2244 let Inst{21} = 0b1; 2245 let Inst{20-16} = Rm; 2246 let Inst{15-13} = 0b000; 2247 let Inst{12-10} = opc{3-1}; 2248 let Inst{9-5} = Rn; 2249 let Inst{4} = opc{0}; 2250 let Inst{3-0} = Pd; 2251 2252 let Defs = [NZCV]; 2253 } 2254 2255 multiclass sve_int_while4_rr<bits<3> opc, string asm> { 2256 def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>; 2257 def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>; 2258 def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>; 2259 def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64>; 2260 } 2261 2262 multiclass sve_int_while8_rr<bits<3> opc, string asm> { 2263 def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>; 2264 def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>; 2265 def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>; 2266 def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; 2267 } 2268 2269 2270 //===----------------------------------------------------------------------===// 2271 // SVE Floating Point Fast Reduction Group 2272 //===----------------------------------------------------------------------===// 2273 2274 class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm, 2275 ZPRRegOp zprty, RegisterClass dstRegClass> 2276 : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 2277 asm, "\t$Vd, $Pg, $Zn", 2278 "", 2279 []>, Sched<[]> { 2280 bits<5> Zn; 2281 bits<5> Vd; 2282 bits<3> Pg; 2283 let Inst{31-24} = 0b01100101; 2284 let Inst{23-22} = sz; 2285 let Inst{21-19} = 0b000; 2286 let Inst{18-16} = opc; 2287 let Inst{15-13} = 0b001; 2288 let Inst{12-10} = Pg; 2289 let Inst{9-5} = Zn; 2290 let Inst{4-0} = Vd; 2291 } 2292 2293 multiclass sve_fp_fast_red<bits<3> opc, string asm> { 2294 def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>; 2295 def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>; 2296 def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>; 2297 } 2298 2299 2300 //===----------------------------------------------------------------------===// 2301 // SVE Floating Point Accumulating Reduction Group 2302 //===----------------------------------------------------------------------===// 2303 2304 class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm, 2305 ZPRRegOp zprty, RegisterClass dstRegClass> 2306 : I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm), 2307 asm, "\t$Vdn, $Pg, $_Vdn, $Zm", 2308 "", 2309 []>, 2310 Sched<[]> { 2311 bits<3> Pg; 2312 bits<5> Vdn; 2313 bits<5> Zm; 2314 let Inst{31-24} = 0b01100101; 2315 let Inst{23-22} = sz; 2316 let Inst{21-19} = 0b011; 2317 let Inst{18-16} = opc; 2318 let Inst{15-13} = 0b001; 2319 let Inst{12-10} = Pg; 2320 let Inst{9-5} = Zm; 2321 let Inst{4-0} = Vdn; 2322 2323 let Constraints = "$Vdn = $_Vdn"; 2324 } 2325 2326 multiclass sve_fp_2op_p_vd<bits<3> opc, string asm> { 2327 def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>; 2328 def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>; 2329 def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>; 2330 } 2331 2332 //===----------------------------------------------------------------------===// 2333 // SVE Floating Point Compare - Vectors Group 2334 //===----------------------------------------------------------------------===// 2335 2336 class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty, 2337 ZPRRegOp zprty> 2338 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), 2339 asm, "\t$Pd, $Pg/z, $Zn, $Zm", 2340 "", 2341 []>, Sched<[]> { 2342 bits<4> Pd; 2343 bits<3> Pg; 2344 bits<5> Zm; 2345 bits<5> Zn; 2346 let Inst{31-24} = 0b01100101; 2347 let Inst{23-22} = sz; 2348 let Inst{21} = 0b0; 2349 let Inst{20-16} = Zm; 2350 let Inst{15} = opc{2}; 2351 let Inst{14} = 0b1; 2352 let Inst{13} = opc{1}; 2353 let Inst{12-10} = Pg; 2354 let Inst{9-5} = Zn; 2355 let Inst{4} = opc{0}; 2356 let Inst{3-0} = Pd; 2357 } 2358 2359 multiclass sve_fp_3op_p_pd<bits<3> opc, string asm> { 2360 def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>; 2361 def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>; 2362 def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>; 2363 } 2364 2365 2366 //===----------------------------------------------------------------------===// 2367 // SVE Floating Point Compare - with Zero Group 2368 //===----------------------------------------------------------------------===// 2369 2370 class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty, 2371 ZPRRegOp zprty> 2372 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn), 2373 asm, "\t$Pd, $Pg/z, $Zn, #0.0", 2374 "", 2375 []>, Sched<[]> { 2376 bits<4> Pd; 2377 bits<3> Pg; 2378 bits<5> Zn; 2379 let Inst{31-24} = 0b01100101; 2380 let Inst{23-22} = sz; 2381 let Inst{21-18} = 0b0100; 2382 let Inst{17-16} = opc{2-1}; 2383 let Inst{15-13} = 0b001; 2384 let Inst{12-10} = Pg; 2385 let Inst{9-5} = Zn; 2386 let Inst{4} = opc{0}; 2387 let Inst{3-0} = Pd; 2388 } 2389 2390 multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> { 2391 def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>; 2392 def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>; 2393 def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>; 2394 } 2395 2396 2397 //===----------------------------------------------------------------------===// 2398 //SVE Index Generation Group 2399 //===----------------------------------------------------------------------===// 2400 2401 class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty, 2402 Operand imm_ty> 2403 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b), 2404 asm, "\t$Zd, $imm5, $imm5b", 2405 "", []>, Sched<[]> { 2406 bits<5> Zd; 2407 bits<5> imm5; 2408 bits<5> imm5b; 2409 let Inst{31-24} = 0b00000100; 2410 let Inst{23-22} = sz8_64; 2411 let Inst{21} = 0b1; 2412 let Inst{20-16} = imm5b; 2413 let Inst{15-10} = 0b010000; 2414 let Inst{9-5} = imm5; 2415 let Inst{4-0} = Zd; 2416 } 2417 2418 multiclass sve_int_index_ii<string asm> { 2419 def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>; 2420 def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>; 2421 def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>; 2422 def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>; 2423 } 2424 2425 class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty, 2426 RegisterClass srcRegType, Operand imm_ty> 2427 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm), 2428 asm, "\t$Zd, $imm5, $Rm", 2429 "", []>, Sched<[]> { 2430 bits<5> Rm; 2431 bits<5> Zd; 2432 bits<5> imm5; 2433 let Inst{31-24} = 0b00000100; 2434 let Inst{23-22} = sz8_64; 2435 let Inst{21} = 0b1; 2436 let Inst{20-16} = Rm; 2437 let Inst{15-10} = 0b010010; 2438 let Inst{9-5} = imm5; 2439 let Inst{4-0} = Zd; 2440 } 2441 2442 multiclass sve_int_index_ir<string asm> { 2443 def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>; 2444 def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>; 2445 def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>; 2446 def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>; 2447 } 2448 2449 class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty, 2450 RegisterClass srcRegType, Operand imm_ty> 2451 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5), 2452 asm, "\t$Zd, $Rn, $imm5", 2453 "", []>, Sched<[]> { 2454 bits<5> Rn; 2455 bits<5> Zd; 2456 bits<5> imm5; 2457 let Inst{31-24} = 0b00000100; 2458 let Inst{23-22} = sz8_64; 2459 let Inst{21} = 0b1; 2460 let Inst{20-16} = imm5; 2461 let Inst{15-10} = 0b010001; 2462 let Inst{9-5} = Rn; 2463 let Inst{4-0} = Zd; 2464 } 2465 2466 multiclass sve_int_index_ri<string asm> { 2467 def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>; 2468 def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>; 2469 def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>; 2470 def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>; 2471 } 2472 2473 class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty, 2474 RegisterClass srcRegType> 2475 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm), 2476 asm, "\t$Zd, $Rn, $Rm", 2477 "", []>, Sched<[]> { 2478 bits<5> Zd; 2479 bits<5> Rm; 2480 bits<5> Rn; 2481 let Inst{31-24} = 0b00000100; 2482 let Inst{23-22} = sz8_64; 2483 let Inst{21} = 0b1; 2484 let Inst{20-16} = Rm; 2485 let Inst{15-10} = 0b010011; 2486 let Inst{9-5} = Rn; 2487 let Inst{4-0} = Zd; 2488 } 2489 2490 multiclass sve_int_index_rr<string asm> { 2491 def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>; 2492 def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; 2493 def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>; 2494 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>; 2495 } 2496 // 2497 //===----------------------------------------------------------------------===// 2498 // SVE Bitwise Shift - Predicated Group 2499 //===----------------------------------------------------------------------===// 2500 class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, 2501 ZPRRegOp zprty, Operand immtype, 2502 ElementSizeEnum size> 2503 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), 2504 asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", 2505 "", 2506 []>, Sched<[]> { 2507 bits<3> Pg; 2508 bits<5> Zdn; 2509 bits<6> imm; 2510 let Inst{31-24} = 0b00000100; 2511 let Inst{23-22} = tsz8_64{3-2}; 2512 let Inst{21-19} = 0b000; 2513 let Inst{18-16} = opc; 2514 let Inst{15-13} = 0b100; 2515 let Inst{12-10} = Pg; 2516 let Inst{9-8} = tsz8_64{1-0}; 2517 let Inst{7-5} = imm{2-0}; // imm3 2518 let Inst{4-0} = Zdn; 2519 2520 let Constraints = "$Zdn = $_Zdn"; 2521 let DestructiveInstType = Destructive; 2522 let ElementSize = size; 2523 } 2524 2525 multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { 2526 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, 2527 ElementSizeB>; 2528 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, 2529 ElementSizeH> { 2530 let Inst{8} = imm{3}; 2531 } 2532 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32, 2533 ElementSizeS> { 2534 let Inst{9-8} = imm{4-3}; 2535 } 2536 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64, 2537 ElementSizeD> { 2538 let Inst{22} = imm{5}; 2539 let Inst{9-8} = imm{4-3}; 2540 } 2541 } 2542 2543 multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> { 2544 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, 2545 ElementSizeB>; 2546 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, 2547 ElementSizeH> { 2548 let Inst{8} = imm{3}; 2549 } 2550 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32, 2551 ElementSizeS> { 2552 let Inst{9-8} = imm{4-3}; 2553 } 2554 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64, 2555 ElementSizeD> { 2556 let Inst{22} = imm{5}; 2557 let Inst{9-8} = imm{4-3}; 2558 } 2559 } 2560 2561 class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc, 2562 string asm, ZPRRegOp zprty, ZPRRegOp zprty2> 2563 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), 2564 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", 2565 "", 2566 []>, Sched<[]> { 2567 bits<3> Pg; 2568 bits<5> Zdn; 2569 bits<5> Zm; 2570 let Inst{31-24} = 0b00000100; 2571 let Inst{23-22} = sz8_64; 2572 let Inst{21-20} = 0b01; 2573 let Inst{19} = wide; 2574 let Inst{18-16} = opc; 2575 let Inst{15-13} = 0b100; 2576 let Inst{12-10} = Pg; 2577 let Inst{9-5} = Zm; 2578 let Inst{4-0} = Zdn; 2579 2580 let Constraints = "$Zdn = $_Zdn"; 2581 let DestructiveInstType = Destructive; 2582 let ElementSize = zprty.ElementSize; 2583 } 2584 2585 multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> { 2586 def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; 2587 def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; 2588 def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; 2589 def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; 2590 } 2591 2592 multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm> { 2593 def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; 2594 def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; 2595 def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; 2596 } 2597 2598 //===----------------------------------------------------------------------===// 2599 // SVE Shift - Unpredicated Group 2600 //===----------------------------------------------------------------------===// 2601 2602 class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm, 2603 ZPRRegOp zprty> 2604 : I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm), 2605 asm, "\t$Zd, $Zn, $Zm", 2606 "", 2607 []>, Sched<[]> { 2608 bits<5> Zd; 2609 bits<5> Zm; 2610 bits<5> Zn; 2611 let Inst{31-24} = 0b00000100; 2612 let Inst{23-22} = sz8_64; 2613 let Inst{21} = 0b1; 2614 let Inst{20-16} = Zm; 2615 let Inst{15-12} = 0b1000; 2616 let Inst{11-10} = opc; 2617 let Inst{9-5} = Zn; 2618 let Inst{4-0} = Zd; 2619 } 2620 2621 multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> { 2622 def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>; 2623 def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>; 2624 def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>; 2625 } 2626 2627 class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm, 2628 ZPRRegOp zprty, Operand immtype> 2629 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), 2630 asm, "\t$Zd, $Zn, $imm", 2631 "", []>, Sched<[]> { 2632 bits<5> Zd; 2633 bits<5> Zn; 2634 bits<6> imm; 2635 let Inst{31-24} = 0b00000100; 2636 let Inst{23-22} = tsz8_64{3-2}; 2637 let Inst{21} = 0b1; 2638 let Inst{20-19} = tsz8_64{1-0}; 2639 let Inst{18-16} = imm{2-0}; // imm3 2640 let Inst{15-12} = 0b1001; 2641 let Inst{11-10} = opc; 2642 let Inst{9-5} = Zn; 2643 let Inst{4-0} = Zd; 2644 } 2645 2646 multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> { 2647 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; 2648 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { 2649 let Inst{19} = imm{3}; 2650 } 2651 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { 2652 let Inst{20-19} = imm{4-3}; 2653 } 2654 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { 2655 let Inst{22} = imm{5}; 2656 let Inst{20-19} = imm{4-3}; 2657 } 2658 } 2659 2660 multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> { 2661 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; 2662 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { 2663 let Inst{19} = imm{3}; 2664 } 2665 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { 2666 let Inst{20-19} = imm{4-3}; 2667 } 2668 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { 2669 let Inst{22} = imm{5}; 2670 let Inst{20-19} = imm{4-3}; 2671 } 2672 } 2673 //===----------------------------------------------------------------------===// 2674 // SVE Memory - Store Group 2675 //===----------------------------------------------------------------------===// 2676 2677 class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm, 2678 RegisterOperand VecList> 2679 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 2680 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 2681 "", 2682 []>, Sched<[]> { 2683 bits<3> Pg; 2684 bits<5> Rn; 2685 bits<5> Zt; 2686 bits<4> imm4; 2687 let Inst{31-25} = 0b1110010; 2688 let Inst{24-23} = msz; 2689 let Inst{22-21} = esz; 2690 let Inst{20} = 0; 2691 let Inst{19-16} = imm4; 2692 let Inst{15-13} = 0b111; 2693 let Inst{12-10} = Pg; 2694 let Inst{9-5} = Rn; 2695 let Inst{4-0} = Zt; 2696 2697 let mayStore = 1; 2698 } 2699 2700 multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm, 2701 RegisterOperand listty, ZPRRegOp zprty> 2702 { 2703 def NAME : sve_mem_cst_si<msz, esz, asm, listty>; 2704 2705 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 2706 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 2707 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 2708 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 2709 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 2710 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 2711 } 2712 2713 class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 2714 string asm, Operand immtype> 2715 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), 2716 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 2717 "", 2718 []>, Sched<[]> { 2719 bits<3> Pg; 2720 bits<5> Rn; 2721 bits<5> Zt; 2722 bits<4> imm4; 2723 let Inst{31-25} = 0b1110010; 2724 let Inst{24-23} = sz; 2725 let Inst{22-21} = nregs; 2726 let Inst{20} = 1; 2727 let Inst{19-16} = imm4; 2728 let Inst{15-13} = 0b111; 2729 let Inst{12-10} = Pg; 2730 let Inst{9-5} = Rn; 2731 let Inst{4-0} = Zt; 2732 2733 let mayStore = 1; 2734 } 2735 2736 multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 2737 string asm, Operand immtype> { 2738 def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>; 2739 2740 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 2741 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 2742 } 2743 2744 class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 2745 string asm, RegisterOperand gprty> 2746 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 2747 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 2748 "", 2749 []>, Sched<[]> { 2750 bits<3> Pg; 2751 bits<5> Rm; 2752 bits<5> Rn; 2753 bits<5> Zt; 2754 let Inst{31-25} = 0b1110010; 2755 let Inst{24-23} = sz; 2756 let Inst{22-21} = nregs; 2757 let Inst{20-16} = Rm; 2758 let Inst{15-13} = 0b011; 2759 let Inst{12-10} = Pg; 2760 let Inst{9-5} = Rn; 2761 let Inst{4-0} = Zt; 2762 2763 let mayStore = 1; 2764 } 2765 2766 class sve_mem_cst_ss_base<bits<4> dtype, string asm, 2767 RegisterOperand listty, RegisterOperand gprty> 2768 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 2769 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 2770 "", 2771 []>, Sched<[]> { 2772 bits<3> Pg; 2773 bits<5> Rm; 2774 bits<5> Rn; 2775 bits<5> Zt; 2776 let Inst{31-25} = 0b1110010; 2777 let Inst{24-21} = dtype; 2778 let Inst{20-16} = Rm; 2779 let Inst{15-13} = 0b010; 2780 let Inst{12-10} = Pg; 2781 let Inst{9-5} = Rn; 2782 let Inst{4-0} = Zt; 2783 2784 let mayStore = 1; 2785 } 2786 2787 multiclass sve_mem_cst_ss<bits<4> dtype, string asm, 2788 RegisterOperand listty, ZPRRegOp zprty, 2789 RegisterOperand gprty> { 2790 def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>; 2791 2792 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]", 2793 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 2794 } 2795 2796 class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList> 2797 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 2798 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 2799 "", 2800 []>, Sched<[]> { 2801 bits<3> Pg; 2802 bits<5> Rn; 2803 bits<5> Zt; 2804 bits<4> imm4; 2805 let Inst{31-25} = 0b1110010; 2806 let Inst{24-23} = msz; 2807 let Inst{22-20} = 0b001; 2808 let Inst{19-16} = imm4; 2809 let Inst{15-13} = 0b111; 2810 let Inst{12-10} = Pg; 2811 let Inst{9-5} = Rn; 2812 let Inst{4-0} = Zt; 2813 2814 let mayStore = 1; 2815 } 2816 2817 multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty, 2818 ZPRRegOp zprty> { 2819 def NAME : sve_mem_cstnt_si<msz, asm, listty>; 2820 2821 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 2822 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 2823 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 2824 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 2825 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 2826 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 2827 } 2828 2829 class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty, 2830 RegisterOperand gprty> 2831 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 2832 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 2833 "", 2834 []>, Sched<[]> { 2835 bits<3> Pg; 2836 bits<5> Rm; 2837 bits<5> Rn; 2838 bits<5> Zt; 2839 let Inst{31-25} = 0b1110010; 2840 let Inst{24-23} = msz; 2841 let Inst{22-21} = 0b00; 2842 let Inst{20-16} = Rm; 2843 let Inst{15-13} = 0b011; 2844 let Inst{12-10} = Pg; 2845 let Inst{9-5} = Rn; 2846 let Inst{4-0} = Zt; 2847 2848 let mayStore = 1; 2849 } 2850 2851 multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty, 2852 ZPRRegOp zprty, RegisterOperand gprty> { 2853 def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>; 2854 2855 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]", 2856 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 2857 } 2858 2859 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm, 2860 RegisterOperand VecList, RegisterOperand zprext> 2861 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 2862 asm, "\t$Zt, $Pg, [$Rn, $Zm]", 2863 "", 2864 []>, Sched<[]> { 2865 bits<3> Pg; 2866 bits<5> Rn; 2867 bits<5> Zm; 2868 bits<5> Zt; 2869 let Inst{31-25} = 0b1110010; 2870 let Inst{24-22} = opc; 2871 let Inst{21} = scaled; 2872 let Inst{20-16} = Zm; 2873 let Inst{15} = 0b1; 2874 let Inst{14} = xs; 2875 let Inst{13} = 0; 2876 let Inst{12-10} = Pg; 2877 let Inst{9-5} = Rn; 2878 let Inst{4-0} = Zt; 2879 2880 let mayStore = 1; 2881 } 2882 2883 multiclass sve_mem_sst_sv_32_scaled<bits<3> opc, string asm, 2884 RegisterOperand listty, 2885 ZPRRegOp zprty, 2886 RegisterOperand sxtw_opnd, 2887 RegisterOperand uxtw_opnd > { 2888 def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, listty, uxtw_opnd>; 2889 def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, listty, sxtw_opnd>; 2890 2891 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2892 (!cast<Instruction>(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 2893 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2894 (!cast<Instruction>(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 2895 } 2896 2897 multiclass sve_mem_sst_sv_32_unscaled<bits<3> opc, string asm, 2898 RegisterOperand listty, 2899 ZPRRegOp zprty, 2900 RegisterOperand sxtw_opnd, 2901 RegisterOperand uxtw_opnd> { 2902 def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, listty, uxtw_opnd>; 2903 def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, listty, sxtw_opnd>; 2904 2905 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2906 (!cast<Instruction>(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 2907 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2908 (!cast<Instruction>(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 2909 } 2910 2911 class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm, 2912 RegisterOperand zprext> 2913 : I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 2914 asm, "\t$Zt, $Pg, [$Rn, $Zm]", 2915 "", 2916 []>, Sched<[]> { 2917 bits<3> Pg; 2918 bits<5> Rn; 2919 bits<5> Zm; 2920 bits<5> Zt; 2921 let Inst{31-25} = 0b1110010; 2922 let Inst{24-23} = msz; 2923 let Inst{22} = 0b0; 2924 let Inst{21} = scaled; 2925 let Inst{20-16} = Zm; 2926 let Inst{15-13} = 0b101; 2927 let Inst{12-10} = Pg; 2928 let Inst{9-5} = Rn; 2929 let Inst{4-0} = Zt; 2930 2931 let mayStore = 1; 2932 } 2933 2934 multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm, 2935 RegisterOperand zprext> { 2936 def "" : sve_mem_sst_sv2<msz, 1, asm, zprext>; 2937 2938 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2939 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; 2940 2941 } 2942 2943 multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm> { 2944 def "" : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>; 2945 2946 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 2947 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; 2948 } 2949 2950 class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty, 2951 RegisterOperand VecList, Operand imm_ty> 2952 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 2953 asm, "\t$Zt, $Pg, [$Zn, $imm5]", 2954 "", 2955 []>, Sched<[]> { 2956 bits<3> Pg; 2957 bits<5> imm5; 2958 bits<5> Zn; 2959 bits<5> Zt; 2960 let Inst{31-25} = 0b1110010; 2961 let Inst{24-23} = opc{2-1}; 2962 let Inst{22} = 0b1; 2963 let Inst{21} = opc{0}; 2964 let Inst{20-16} = imm5; 2965 let Inst{15-13} = 0b101; 2966 let Inst{12-10} = Pg; 2967 let Inst{9-5} = Zn; 2968 let Inst{4-0} = Zt; 2969 2970 let mayStore = 1; 2971 } 2972 2973 multiclass sve_mem_sst_vi_ptrs<bits<3> opc, string asm, RegisterOperand listty, 2974 ZPRRegOp zprty, Operand imm_ty> { 2975 def _IMM : sve_mem_sst_vi<opc, asm, zprty, listty, imm_ty>; 2976 2977 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 2978 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>; 2979 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]", 2980 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>; 2981 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 2982 (!cast<Instruction>(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>; 2983 } 2984 2985 class sve_mem_z_spill<string asm> 2986 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9), 2987 asm, "\t$Zt, [$Rn, $imm9, mul vl]", 2988 "", 2989 []>, Sched<[]> { 2990 bits<5> Rn; 2991 bits<5> Zt; 2992 bits<9> imm9; 2993 let Inst{31-22} = 0b1110010110; 2994 let Inst{21-16} = imm9{8-3}; 2995 let Inst{15-13} = 0b010; 2996 let Inst{12-10} = imm9{2-0}; 2997 let Inst{9-5} = Rn; 2998 let Inst{4-0} = Zt; 2999 3000 let mayStore = 1; 3001 } 3002 3003 multiclass sve_mem_z_spill<string asm> { 3004 def NAME : sve_mem_z_spill<asm>; 3005 3006 def : InstAlias<asm # "\t$Zt, [$Rn]", 3007 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; 3008 } 3009 3010 class sve_mem_p_spill<string asm> 3011 : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 3012 asm, "\t$Pt, [$Rn, $imm9, mul vl]", 3013 "", 3014 []>, Sched<[]> { 3015 bits<4> Pt; 3016 bits<5> Rn; 3017 bits<9> imm9; 3018 let Inst{31-22} = 0b1110010110; 3019 let Inst{21-16} = imm9{8-3}; 3020 let Inst{15-13} = 0b000; 3021 let Inst{12-10} = imm9{2-0}; 3022 let Inst{9-5} = Rn; 3023 let Inst{4} = 0b0; 3024 let Inst{3-0} = Pt; 3025 3026 let mayStore = 1; 3027 } 3028 3029 multiclass sve_mem_p_spill<string asm> { 3030 def NAME : sve_mem_p_spill<asm>; 3031 3032 def : InstAlias<asm # "\t$Pt, [$Rn]", 3033 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; 3034 } 3035 3036 //===----------------------------------------------------------------------===// 3037 // SVE Permute - Predicates Group 3038 //===----------------------------------------------------------------------===// 3039 3040 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm, 3041 PPRRegOp pprty> 3042 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm), 3043 asm, "\t$Pd, $Pn, $Pm", 3044 "", 3045 []>, Sched<[]> { 3046 bits<4> Pd; 3047 bits<4> Pm; 3048 bits<4> Pn; 3049 let Inst{31-24} = 0b00000101; 3050 let Inst{23-22} = sz8_64; 3051 let Inst{21-20} = 0b10; 3052 let Inst{19-16} = Pm; 3053 let Inst{15-13} = 0b010; 3054 let Inst{12-10} = opc; 3055 let Inst{9} = 0b0; 3056 let Inst{8-5} = Pn; 3057 let Inst{4} = 0b0; 3058 let Inst{3-0} = Pd; 3059 } 3060 3061 multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> { 3062 def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>; 3063 def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>; 3064 def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>; 3065 def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>; 3066 } 3067 3068 class sve_int_perm_punpk<bit opc, string asm> 3069 : I<(outs PPR16:$Pd), (ins PPR8:$Pn), 3070 asm, "\t$Pd, $Pn", 3071 "", 3072 []>, Sched<[]> { 3073 bits<4> Pd; 3074 bits<4> Pn; 3075 let Inst{31-17} = 0b000001010011000; 3076 let Inst{16} = opc; 3077 let Inst{15-9} = 0b0100000; 3078 let Inst{8-5} = Pn; 3079 let Inst{4} = 0b0; 3080 let Inst{3-0} = Pd; 3081 } 3082 3083 class sve_int_rdffr_pred<bit s, string asm> 3084 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg), 3085 asm, "\t$Pd, $Pg/z", 3086 "", 3087 []>, Sched<[]> { 3088 bits<4> Pd; 3089 bits<4> Pg; 3090 let Inst{31-23} = 0b001001010; 3091 let Inst{22} = s; 3092 let Inst{21-9} = 0b0110001111000; 3093 let Inst{8-5} = Pg; 3094 let Inst{4} = 0; 3095 let Inst{3-0} = Pd; 3096 3097 let Defs = !if(!eq (s, 1), [NZCV], []); 3098 let Uses = [FFR]; 3099 } 3100 3101 class sve_int_rdffr_unpred<string asm> : I< 3102 (outs PPR8:$Pd), (ins), 3103 asm, "\t$Pd", 3104 "", 3105 []>, Sched<[]> { 3106 bits<4> Pd; 3107 let Inst{31-4} = 0b0010010100011001111100000000; 3108 let Inst{3-0} = Pd; 3109 3110 let Uses = [FFR]; 3111 } 3112 3113 class sve_int_wrffr<string asm> 3114 : I<(outs), (ins PPR8:$Pn), 3115 asm, "\t$Pn", 3116 "", 3117 []>, Sched<[]> { 3118 bits<4> Pn; 3119 let Inst{31-9} = 0b00100101001010001001000; 3120 let Inst{8-5} = Pn; 3121 let Inst{4-0} = 0b00000; 3122 3123 let hasSideEffects = 1; 3124 let Defs = [FFR]; 3125 } 3126 3127 class sve_int_setffr<string asm> 3128 : I<(outs), (ins), 3129 asm, "", 3130 "", 3131 []>, Sched<[]> { 3132 let Inst{31-0} = 0b00100101001011001001000000000000; 3133 3134 let hasSideEffects = 1; 3135 let Defs = [FFR]; 3136 } 3137 3138 //===----------------------------------------------------------------------===// 3139 // SVE Permute Vector - Predicated Group 3140 //===----------------------------------------------------------------------===// 3141 3142 class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm, 3143 ZPRRegOp zprty, RegisterClass rt> 3144 : I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm), 3145 asm, "\t$Rdn, $Pg, $_Rdn, $Zm", 3146 "", 3147 []>, Sched<[]> { 3148 bits<3> Pg; 3149 bits<5> Rdn; 3150 bits<5> Zm; 3151 let Inst{31-24} = 0b00000101; 3152 let Inst{23-22} = sz8_64; 3153 let Inst{21-17} = 0b11000; 3154 let Inst{16} = ab; 3155 let Inst{15-13} = 0b101; 3156 let Inst{12-10} = Pg; 3157 let Inst{9-5} = Zm; 3158 let Inst{4-0} = Rdn; 3159 3160 let Constraints = "$Rdn = $_Rdn"; 3161 } 3162 3163 multiclass sve_int_perm_clast_rz<bit ab, string asm> { 3164 def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>; 3165 def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>; 3166 def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>; 3167 def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>; 3168 } 3169 3170 class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm, 3171 ZPRRegOp zprty, RegisterClass rt> 3172 : I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm), 3173 asm, "\t$Vdn, $Pg, $_Vdn, $Zm", 3174 "", 3175 []>, Sched<[]> { 3176 bits<3> Pg; 3177 bits<5> Vdn; 3178 bits<5> Zm; 3179 let Inst{31-24} = 0b00000101; 3180 let Inst{23-22} = sz8_64; 3181 let Inst{21-17} = 0b10101; 3182 let Inst{16} = ab; 3183 let Inst{15-13} = 0b100; 3184 let Inst{12-10} = Pg; 3185 let Inst{9-5} = Zm; 3186 let Inst{4-0} = Vdn; 3187 3188 let Constraints = "$Vdn = $_Vdn"; 3189 } 3190 3191 multiclass sve_int_perm_clast_vz<bit ab, string asm> { 3192 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>; 3193 def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>; 3194 def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>; 3195 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>; 3196 } 3197 3198 class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm, 3199 ZPRRegOp zprty> 3200 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 3201 asm, "\t$Zdn, $Pg, $_Zdn, $Zm", 3202 "", 3203 []>, Sched<[]> { 3204 bits<3> Pg; 3205 bits<5> Zdn; 3206 bits<5> Zm; 3207 let Inst{31-24} = 0b00000101; 3208 let Inst{23-22} = sz8_64; 3209 let Inst{21-17} = 0b10100; 3210 let Inst{16} = ab; 3211 let Inst{15-13} = 0b100; 3212 let Inst{12-10} = Pg; 3213 let Inst{9-5} = Zm; 3214 let Inst{4-0} = Zdn; 3215 3216 let Constraints = "$Zdn = $_Zdn"; 3217 let DestructiveInstType = Destructive; 3218 let ElementSize = ElementSizeNone; 3219 } 3220 3221 multiclass sve_int_perm_clast_zz<bit ab, string asm> { 3222 def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>; 3223 def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>; 3224 def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>; 3225 def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>; 3226 } 3227 3228 class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm, 3229 ZPRRegOp zprty, RegisterClass resultRegType> 3230 : I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn), 3231 asm, "\t$Rd, $Pg, $Zn", 3232 "", 3233 []>, Sched<[]> { 3234 bits<3> Pg; 3235 bits<5> Rd; 3236 bits<5> Zn; 3237 let Inst{31-24} = 0b00000101; 3238 let Inst{23-22} = sz8_64; 3239 let Inst{21-17} = 0b10000; 3240 let Inst{16} = ab; 3241 let Inst{15-13} = 0b101; 3242 let Inst{12-10} = Pg; 3243 let Inst{9-5} = Zn; 3244 let Inst{4-0} = Rd; 3245 } 3246 3247 multiclass sve_int_perm_last_r<bit ab, string asm> { 3248 def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>; 3249 def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>; 3250 def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>; 3251 def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>; 3252 } 3253 3254 class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm, 3255 ZPRRegOp zprty, RegisterClass dstRegtype> 3256 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 3257 asm, "\t$Vd, $Pg, $Zn", 3258 "", 3259 []>, Sched<[]> { 3260 bits<3> Pg; 3261 bits<5> Vd; 3262 bits<5> Zn; 3263 let Inst{31-24} = 0b00000101; 3264 let Inst{23-22} = sz8_64; 3265 let Inst{21-17} = 0b10001; 3266 let Inst{16} = ab; 3267 let Inst{15-13} = 0b100; 3268 let Inst{12-10} = Pg; 3269 let Inst{9-5} = Zn; 3270 let Inst{4-0} = Vd; 3271 } 3272 3273 multiclass sve_int_perm_last_v<bit ab, string asm> { 3274 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>; 3275 def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>; 3276 def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>; 3277 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>; 3278 } 3279 3280 class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty> 3281 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 3282 asm, "\t$Zdn, $Pg, $_Zdn, $Zm", 3283 "", 3284 []>, Sched<[]> { 3285 bits<3> Pg; 3286 bits<5> Zdn; 3287 bits<5> Zm; 3288 let Inst{31-24} = 0b00000101; 3289 let Inst{23-22} = sz8_64; 3290 let Inst{21-13} = 0b101100100; 3291 let Inst{12-10} = Pg; 3292 let Inst{9-5} = Zm; 3293 let Inst{4-0} = Zdn; 3294 3295 let Constraints = "$Zdn = $_Zdn"; 3296 let DestructiveInstType = Destructive; 3297 let ElementSize = ElementSizeNone; 3298 } 3299 3300 multiclass sve_int_perm_splice<string asm> { 3301 def _B : sve_int_perm_splice<0b00, asm, ZPR8>; 3302 def _H : sve_int_perm_splice<0b01, asm, ZPR16>; 3303 def _S : sve_int_perm_splice<0b10, asm, ZPR32>; 3304 def _D : sve_int_perm_splice<0b11, asm, ZPR64>; 3305 } 3306 3307 class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm, 3308 ZPRRegOp zprty> 3309 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), 3310 asm, "\t$Zd, $Pg/m, $Zn", 3311 "", 3312 []>, Sched<[]> { 3313 bits<5> Zd; 3314 bits<3> Pg; 3315 bits<5> Zn; 3316 let Inst{31-24} = 0b00000101; 3317 let Inst{23-22} = sz8_64; 3318 let Inst{21-18} = 0b1001; 3319 let Inst{17-16} = opc; 3320 let Inst{15-13} = 0b100; 3321 let Inst{12-10} = Pg; 3322 let Inst{9-5} = Zn; 3323 let Inst{4-0} = Zd; 3324 3325 let Constraints = "$Zd = $_Zd"; 3326 let DestructiveInstType = Destructive; 3327 let ElementSize = zprty.ElementSize; 3328 } 3329 3330 multiclass sve_int_perm_rev_rbit<string asm> { 3331 def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>; 3332 def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>; 3333 def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>; 3334 def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>; 3335 } 3336 3337 multiclass sve_int_perm_rev_revb<string asm> { 3338 def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>; 3339 def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>; 3340 def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>; 3341 } 3342 3343 multiclass sve_int_perm_rev_revh<string asm> { 3344 def _S : sve_int_perm_rev<0b10, 0b01, asm, ZPR32>; 3345 def _D : sve_int_perm_rev<0b11, 0b01, asm, ZPR64>; 3346 } 3347 3348 multiclass sve_int_perm_rev_revw<string asm> { 3349 def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>; 3350 } 3351 3352 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3353 RegisterClass srcRegType> 3354 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn), 3355 asm, "\t$Zd, $Pg/m, $Rn", 3356 "", 3357 []>, Sched<[]> { 3358 bits<3> Pg; 3359 bits<5> Rn; 3360 bits<5> Zd; 3361 let Inst{31-24} = 0b00000101; 3362 let Inst{23-22} = sz8_64; 3363 let Inst{21-13} = 0b101000101; 3364 let Inst{12-10} = Pg; 3365 let Inst{9-5} = Rn; 3366 let Inst{4-0} = Zd; 3367 3368 let Constraints = "$Zd = $_Zd"; 3369 let DestructiveInstType = Destructive; 3370 let ElementSize = zprty.ElementSize; 3371 } 3372 3373 multiclass sve_int_perm_cpy_r<string asm> { 3374 def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>; 3375 def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>; 3376 def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>; 3377 def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>; 3378 3379 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 3380 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 3381 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 3382 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 3383 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 3384 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 3385 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 3386 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>; 3387 } 3388 3389 class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3390 RegisterClass srcRegtype> 3391 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn), 3392 asm, "\t$Zd, $Pg/m, $Vn", 3393 "", 3394 []>, Sched<[]> { 3395 bits<3> Pg; 3396 bits<5> Vn; 3397 bits<5> Zd; 3398 let Inst{31-24} = 0b00000101; 3399 let Inst{23-22} = sz8_64; 3400 let Inst{21-13} = 0b100000100; 3401 let Inst{12-10} = Pg; 3402 let Inst{9-5} = Vn; 3403 let Inst{4-0} = Zd; 3404 3405 let Constraints = "$Zd = $_Zd"; 3406 let DestructiveInstType = Destructive; 3407 let ElementSize = zprty.ElementSize; 3408 } 3409 3410 multiclass sve_int_perm_cpy_v<string asm> { 3411 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>; 3412 def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>; 3413 def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>; 3414 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>; 3415 3416 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 3417 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>; 3418 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 3419 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>; 3420 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 3421 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>; 3422 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 3423 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>; 3424 } 3425 3426 class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty> 3427 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), 3428 asm, "\t$Zd, $Pg, $Zn", 3429 "", 3430 []>, Sched<[]> { 3431 bits<3> Pg; 3432 bits<5> Zd; 3433 bits<5> Zn; 3434 let Inst{31-23} = 0b000001011; 3435 let Inst{22} = sz; 3436 let Inst{21-13} = 0b100001100; 3437 let Inst{12-10} = Pg; 3438 let Inst{9-5} = Zn; 3439 let Inst{4-0} = Zd; 3440 } 3441 3442 multiclass sve_int_perm_compact<string asm> { 3443 def _S : sve_int_perm_compact<0b0, asm, ZPR32>; 3444 def _D : sve_int_perm_compact<0b1, asm, ZPR64>; 3445 } 3446 3447 3448 //===----------------------------------------------------------------------===// 3449 // SVE Memory - Contiguous Load Group 3450 //===----------------------------------------------------------------------===// 3451 3452 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm, 3453 RegisterOperand VecList> 3454 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 3455 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 3456 "", 3457 []>, Sched<[]> { 3458 bits<3> Pg; 3459 bits<5> Rn; 3460 bits<5> Zt; 3461 bits<4> imm4; 3462 let Inst{31-25} = 0b1010010; 3463 let Inst{24-21} = dtype; 3464 let Inst{20} = nf; 3465 let Inst{19-16} = imm4; 3466 let Inst{15-13} = 0b101; 3467 let Inst{12-10} = Pg; 3468 let Inst{9-5} = Rn; 3469 let Inst{4-0} = Zt; 3470 3471 let mayLoad = 1; 3472 let Uses = !if(!eq(nf, 1), [FFR], []); 3473 let Defs = !if(!eq(nf, 1), [FFR], []); 3474 } 3475 3476 multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm, 3477 RegisterOperand listty, ZPRRegOp zprty> { 3478 def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>; 3479 3480 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3481 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3482 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 3483 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 3484 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3485 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3486 } 3487 3488 multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty, 3489 ZPRRegOp zprty> 3490 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>; 3491 3492 class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList> 3493 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 3494 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 3495 "", 3496 []>, Sched<[]> { 3497 bits<5> Zt; 3498 bits<3> Pg; 3499 bits<5> Rn; 3500 bits<4> imm4; 3501 let Inst{31-25} = 0b1010010; 3502 let Inst{24-23} = msz; 3503 let Inst{22-20} = 0b000; 3504 let Inst{19-16} = imm4; 3505 let Inst{15-13} = 0b111; 3506 let Inst{12-10} = Pg; 3507 let Inst{9-5} = Rn; 3508 let Inst{4-0} = Zt; 3509 3510 let mayLoad = 1; 3511 } 3512 3513 multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty, 3514 ZPRRegOp zprty> { 3515 def NAME : sve_mem_cldnt_si_base<msz, asm, listty>; 3516 3517 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3518 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3519 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 3520 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 3521 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3522 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3523 } 3524 3525 class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList, 3526 RegisterOperand gprty> 3527 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3528 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 3529 "", 3530 []>, Sched<[]> { 3531 bits<3> Pg; 3532 bits<5> Rm; 3533 bits<5> Rn; 3534 bits<5> Zt; 3535 let Inst{31-25} = 0b1010010; 3536 let Inst{24-23} = msz; 3537 let Inst{22-21} = 0b00; 3538 let Inst{20-16} = Rm; 3539 let Inst{15-13} = 0b110; 3540 let Inst{12-10} = Pg; 3541 let Inst{9-5} = Rn; 3542 let Inst{4-0} = Zt; 3543 3544 let mayLoad = 1; 3545 } 3546 3547 multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty, 3548 ZPRRegOp zprty, RegisterOperand gprty> { 3549 def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>; 3550 3551 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 3552 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 3553 } 3554 3555 class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList> 3556 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 3557 asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> { 3558 bits<5> Zt; 3559 bits<5> Rn; 3560 bits<3> Pg; 3561 bits<4> imm4; 3562 let Inst{31-25} = 0b1010010; 3563 let Inst{24-23} = sz; 3564 let Inst{22-20} = 0; 3565 let Inst{19-16} = imm4; 3566 let Inst{15-13} = 0b001; 3567 let Inst{12-10} = Pg; 3568 let Inst{9-5} = Rn; 3569 let Inst{4-0} = Zt; 3570 3571 let mayLoad = 1; 3572 } 3573 3574 multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty, 3575 ZPRRegOp zprty> { 3576 def NAME : sve_mem_ldqr_si<sz, asm, listty>; 3577 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3578 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3579 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3580 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3581 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]", 3582 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>; 3583 } 3584 3585 class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList, 3586 RegisterOperand gprty> 3587 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3588 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { 3589 bits<5> Zt; 3590 bits<3> Pg; 3591 bits<5> Rn; 3592 bits<5> Rm; 3593 let Inst{31-25} = 0b1010010; 3594 let Inst{24-23} = sz; 3595 let Inst{22-21} = 0; 3596 let Inst{20-16} = Rm; 3597 let Inst{15-13} = 0; 3598 let Inst{12-10} = Pg; 3599 let Inst{9-5} = Rn; 3600 let Inst{4-0} = Zt; 3601 3602 let mayLoad = 1; 3603 } 3604 3605 multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty, 3606 ZPRRegOp zprty, RegisterOperand gprty> { 3607 def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>; 3608 3609 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 3610 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 3611 } 3612 3613 class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm, 3614 RegisterOperand VecList, Operand immtype> 3615 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 3616 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]", 3617 "", 3618 []>, Sched<[]> { 3619 bits<3> Pg; 3620 bits<5> Rn; 3621 bits<5> Zt; 3622 bits<6> imm6; 3623 let Inst{31-25} = 0b1000010; 3624 let Inst{24-23} = dtypeh; 3625 let Inst{22} = 1; 3626 let Inst{21-16} = imm6; 3627 let Inst{15} = 0b1; 3628 let Inst{14-13} = dtypel; 3629 let Inst{12-10} = Pg; 3630 let Inst{9-5} = Rn; 3631 let Inst{4-0} = Zt; 3632 3633 let mayLoad = 1; 3634 } 3635 3636 multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm, 3637 RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> { 3638 def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>; 3639 3640 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3641 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3642 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]", 3643 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>; 3644 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3645 (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3646 } 3647 3648 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm, 3649 RegisterOperand VecList> 3650 : I<(outs VecList:$Zt), iops, 3651 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 3652 "", 3653 []>, Sched<[]> { 3654 bits<5> Zt; 3655 bits<3> Pg; 3656 bits<5> Rm; 3657 bits<5> Rn; 3658 let Inst{31-25} = 0b1010010; 3659 let Inst{24-21} = dtype; 3660 let Inst{20-16} = Rm; 3661 let Inst{15-14} = 0b01; 3662 let Inst{13} = ff; 3663 let Inst{12-10} = Pg; 3664 let Inst{9-5} = Rn; 3665 let Inst{4-0} = Zt; 3666 3667 let mayLoad = 1; 3668 let Uses = !if(!eq(ff, 1), [FFR], []); 3669 let Defs = !if(!eq(ff, 1), [FFR], []); 3670 } 3671 3672 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty, 3673 ZPRRegOp zprty, RegisterOperand gprty> { 3674 def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3675 asm, listty>; 3676 3677 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 3678 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 3679 } 3680 3681 multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty, 3682 ZPRRegOp zprty, RegisterOperand gprty> { 3683 def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3684 asm, listty>; 3685 3686 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 3687 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 3688 3689 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3690 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>; 3691 3692 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3693 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>; 3694 } 3695 3696 multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty, 3697 ZPRRegOp zprty> 3698 : sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>; 3699 3700 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3701 string asm, Operand immtype> 3702 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), 3703 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 3704 "", 3705 []>, Sched<[]> { 3706 bits<5> Zt; 3707 bits<3> Pg; 3708 bits<5> Rn; 3709 bits<4> imm4; 3710 let Inst{31-25} = 0b1010010; 3711 let Inst{24-23} = sz; 3712 let Inst{22-21} = nregs; 3713 let Inst{20} = 0; 3714 let Inst{19-16} = imm4; 3715 let Inst{15-13} = 0b111; 3716 let Inst{12-10} = Pg; 3717 let Inst{9-5} = Rn; 3718 let Inst{4-0} = Zt; 3719 3720 let mayLoad = 1; 3721 } 3722 3723 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3724 string asm, Operand immtype> { 3725 def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>; 3726 3727 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 3728 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3729 } 3730 3731 class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3732 string asm, RegisterOperand gprty> 3733 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3734 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 3735 "", 3736 []>, Sched<[]> { 3737 bits<3> Pg; 3738 bits<5> Rm; 3739 bits<5> Rn; 3740 bits<5> Zt; 3741 let Inst{31-25} = 0b1010010; 3742 let Inst{24-23} = sz; 3743 let Inst{22-21} = nregs; 3744 let Inst{20-16} = Rm; 3745 let Inst{15-13} = 0b110; 3746 let Inst{12-10} = Pg; 3747 let Inst{9-5} = Rn; 3748 let Inst{4-0} = Zt; 3749 3750 let mayLoad = 1; 3751 } 3752 3753 //===----------------------------------------------------------------------===// 3754 // SVE Memory - 32-bit Gather and Unsized Contiguous Group 3755 //===----------------------------------------------------------------------===// 3756 3757 // bit xs is '1' if offsets are signed 3758 // bit scaled is '1' if the offsets are scaled 3759 class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm, 3760 RegisterOperand zprext> 3761 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 3762 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", 3763 "", 3764 []>, Sched<[]> { 3765 bits<3> Pg; 3766 bits<5> Rn; 3767 bits<5> Zm; 3768 bits<5> Zt; 3769 let Inst{31-25} = 0b1000010; 3770 let Inst{24-23} = opc{3-2}; 3771 let Inst{22} = xs; 3772 let Inst{21} = scaled; 3773 let Inst{20-16} = Zm; 3774 let Inst{15} = 0b0; 3775 let Inst{14-13} = opc{1-0}; 3776 let Inst{12-10} = Pg; 3777 let Inst{9-5} = Rn; 3778 let Inst{4-0} = Zt; 3779 3780 let mayLoad = 1; 3781 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 3782 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 3783 } 3784 3785 multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm, 3786 RegisterOperand sxtw_opnd, 3787 RegisterOperand uxtw_opnd> { 3788 def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>; 3789 def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>; 3790 3791 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 3792 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 3793 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 3794 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 3795 } 3796 3797 multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm, 3798 RegisterOperand sxtw_opnd, 3799 RegisterOperand uxtw_opnd> { 3800 def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>; 3801 def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>; 3802 3803 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 3804 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 3805 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 3806 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 3807 } 3808 3809 3810 class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty> 3811 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 3812 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", 3813 "", 3814 []>, Sched<[]> { 3815 bits<3> Pg; 3816 bits<5> Zn; 3817 bits<5> Zt; 3818 bits<5> imm5; 3819 let Inst{31-25} = 0b1000010; 3820 let Inst{24-23} = opc{3-2}; 3821 let Inst{22-21} = 0b01; 3822 let Inst{20-16} = imm5; 3823 let Inst{15} = 0b1; 3824 let Inst{14-13} = opc{1-0}; 3825 let Inst{12-10} = Pg; 3826 let Inst{9-5} = Zn; 3827 let Inst{4-0} = Zt; 3828 3829 let mayLoad = 1; 3830 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 3831 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 3832 } 3833 3834 multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> { 3835 def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>; 3836 3837 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 3838 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>; 3839 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]", 3840 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>; 3841 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 3842 (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; 3843 } 3844 3845 class sve_mem_prfm_si<bits<2> msz, string asm> 3846 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6), 3847 asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]", 3848 "", 3849 []>, Sched<[]> { 3850 bits<5> Rn; 3851 bits<3> Pg; 3852 bits<6> imm6; 3853 bits<4> prfop; 3854 let Inst{31-22} = 0b1000010111; 3855 let Inst{21-16} = imm6; 3856 let Inst{15} = 0b0; 3857 let Inst{14-13} = msz; 3858 let Inst{12-10} = Pg; 3859 let Inst{9-5} = Rn; 3860 let Inst{4} = 0b0; 3861 let Inst{3-0} = prfop; 3862 3863 let hasSideEffects = 1; 3864 } 3865 3866 multiclass sve_mem_prfm_si<bits<2> msz, string asm> { 3867 def NAME : sve_mem_prfm_si<msz, asm>; 3868 3869 def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]", 3870 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3871 } 3872 3873 class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty> 3874 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3875 asm, "\t$prfop, $Pg, [$Rn, $Rm]", 3876 "", 3877 []>, Sched<[]> { 3878 bits<5> Rm; 3879 bits<5> Rn; 3880 bits<3> Pg; 3881 bits<4> prfop; 3882 let Inst{31-25} = 0b1000010; 3883 let Inst{24-23} = opc{2-1}; 3884 let Inst{22-21} = 0b00; 3885 let Inst{20-16} = Rm; 3886 let Inst{15} = 0b1; 3887 let Inst{14} = opc{0}; 3888 let Inst{13} = 0b0; 3889 let Inst{12-10} = Pg; 3890 let Inst{9-5} = Rn; 3891 let Inst{4} = 0b0; 3892 let Inst{3-0} = prfop; 3893 3894 let hasSideEffects = 1; 3895 } 3896 3897 class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm, 3898 RegisterOperand zprext> 3899 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 3900 asm, "\t$prfop, $Pg, [$Rn, $Zm]", 3901 "", 3902 []>, Sched<[]> { 3903 bits<3> Pg; 3904 bits<5> Rn; 3905 bits<5> Zm; 3906 bits<4> prfop; 3907 let Inst{31-23} = 0b100001000; 3908 let Inst{22} = xs; 3909 let Inst{21} = 0b1; 3910 let Inst{20-16} = Zm; 3911 let Inst{15} = 0b0; 3912 let Inst{14-13} = msz; 3913 let Inst{12-10} = Pg; 3914 let Inst{9-5} = Rn; 3915 let Inst{4} = 0b0; 3916 let Inst{3-0} = prfop; 3917 3918 let hasSideEffects = 1; 3919 } 3920 3921 multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm, 3922 RegisterOperand sxtw_opnd, 3923 RegisterOperand uxtw_opnd> { 3924 def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>; 3925 def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>; 3926 } 3927 3928 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> 3929 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 3930 asm, "\t$prfop, $Pg, [$Zn, $imm5]", 3931 "", 3932 []>, Sched<[]> { 3933 bits<3> Pg; 3934 bits<5> Zn; 3935 bits<5> imm5; 3936 bits<4> prfop; 3937 let Inst{31-25} = 0b1000010; 3938 let Inst{24-23} = msz; 3939 let Inst{22-21} = 0b00; 3940 let Inst{20-16} = imm5; 3941 let Inst{15-13} = 0b111; 3942 let Inst{12-10} = Pg; 3943 let Inst{9-5} = Zn; 3944 let Inst{4} = 0b0; 3945 let Inst{3-0} = prfop; 3946 } 3947 3948 multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> { 3949 def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>; 3950 3951 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]", 3952 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; 3953 } 3954 3955 class sve_mem_z_fill<string asm> 3956 : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9), 3957 asm, "\t$Zt, [$Rn, $imm9, mul vl]", 3958 "", 3959 []>, Sched<[]> { 3960 bits<5> Rn; 3961 bits<5> Zt; 3962 bits<9> imm9; 3963 let Inst{31-22} = 0b1000010110; 3964 let Inst{21-16} = imm9{8-3}; 3965 let Inst{15-13} = 0b010; 3966 let Inst{12-10} = imm9{2-0}; 3967 let Inst{9-5} = Rn; 3968 let Inst{4-0} = Zt; 3969 3970 let mayLoad = 1; 3971 } 3972 3973 multiclass sve_mem_z_fill<string asm> { 3974 def NAME : sve_mem_z_fill<asm>; 3975 3976 def : InstAlias<asm # "\t$Zt, [$Rn]", 3977 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; 3978 } 3979 3980 class sve_mem_p_fill<string asm> 3981 : I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), 3982 asm, "\t$Pt, [$Rn, $imm9, mul vl]", 3983 "", 3984 []>, Sched<[]> { 3985 bits<4> Pt; 3986 bits<5> Rn; 3987 bits<9> imm9; 3988 let Inst{31-22} = 0b1000010110; 3989 let Inst{21-16} = imm9{8-3}; 3990 let Inst{15-13} = 0b000; 3991 let Inst{12-10} = imm9{2-0}; 3992 let Inst{9-5} = Rn; 3993 let Inst{4} = 0b0; 3994 let Inst{3-0} = Pt; 3995 3996 let mayLoad = 1; 3997 } 3998 3999 multiclass sve_mem_p_fill<string asm> { 4000 def NAME : sve_mem_p_fill<asm>; 4001 4002 def : InstAlias<asm # "\t$Pt, [$Rn]", 4003 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; 4004 } 4005 4006 //===----------------------------------------------------------------------===// 4007 // SVE Memory - 64-bit Gather Group 4008 //===----------------------------------------------------------------------===// 4009 4010 // bit xs is '1' if offsets are signed 4011 // bit scaled is '1' if the offsets are scaled 4012 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) 4013 class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm, 4014 RegisterOperand zprext> 4015 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 4016 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", 4017 "", 4018 []>, Sched<[]> { 4019 bits<3> Pg; 4020 bits<5> Rn; 4021 bits<5> Zm; 4022 bits<5> Zt; 4023 let Inst{31-25} = 0b1100010; 4024 let Inst{24-23} = opc{3-2}; 4025 let Inst{22} = xs; 4026 let Inst{21} = scaled; 4027 let Inst{20-16} = Zm; 4028 let Inst{15} = lsl; 4029 let Inst{14-13} = opc{1-0}; 4030 let Inst{12-10} = Pg; 4031 let Inst{9-5} = Rn; 4032 let Inst{4-0} = Zt; 4033 4034 let mayLoad = 1; 4035 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 4036 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 4037 } 4038 4039 multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm, 4040 RegisterOperand sxtw_opnd, 4041 RegisterOperand uxtw_opnd> { 4042 def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>; 4043 def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>; 4044 4045 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4046 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 4047 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4048 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 4049 } 4050 4051 multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm, 4052 RegisterOperand sxtw_opnd, 4053 RegisterOperand uxtw_opnd> { 4054 def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>; 4055 def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>; 4056 4057 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4058 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 4059 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4060 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 4061 } 4062 4063 multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm, 4064 RegisterOperand zprext> { 4065 def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>; 4066 4067 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4068 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; 4069 } 4070 4071 multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> { 4072 def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>; 4073 4074 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 4075 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; 4076 } 4077 4078 class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty> 4079 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 4080 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", 4081 "", 4082 []>, Sched<[]> { 4083 bits<3> Pg; 4084 bits<5> Zn; 4085 bits<5> Zt; 4086 bits<5> imm5; 4087 let Inst{31-25} = 0b1100010; 4088 let Inst{24-23} = opc{3-2}; 4089 let Inst{22-21} = 0b01; 4090 let Inst{20-16} = imm5; 4091 let Inst{15} = 0b1; 4092 let Inst{14-13} = opc{1-0}; 4093 let Inst{12-10} = Pg; 4094 let Inst{9-5} = Zn; 4095 let Inst{4-0} = Zt; 4096 4097 let mayLoad = 1; 4098 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 4099 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 4100 } 4101 4102 multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> { 4103 def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>; 4104 4105 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 4106 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>; 4107 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]", 4108 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>; 4109 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 4110 (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; 4111 } 4112 4113 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) 4114 class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm, 4115 RegisterOperand zprext> 4116 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 4117 asm, "\t$prfop, $Pg, [$Rn, $Zm]", 4118 "", 4119 []>, Sched<[]> { 4120 bits<3> Pg; 4121 bits<5> Rn; 4122 bits<5> Zm; 4123 bits<4> prfop; 4124 let Inst{31-23} = 0b110001000; 4125 let Inst{22} = xs; 4126 let Inst{21} = 0b1; 4127 let Inst{20-16} = Zm; 4128 let Inst{15} = lsl; 4129 let Inst{14-13} = msz; 4130 let Inst{12-10} = Pg; 4131 let Inst{9-5} = Rn; 4132 let Inst{4} = 0b0; 4133 let Inst{3-0} = prfop; 4134 4135 let hasSideEffects = 1; 4136 } 4137 4138 multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm, 4139 RegisterOperand sxtw_opnd, 4140 RegisterOperand uxtw_opnd> { 4141 def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>; 4142 def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>; 4143 } 4144 4145 multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm, 4146 RegisterOperand zprext> { 4147 def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>; 4148 } 4149 4150 4151 class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> 4152 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 4153 asm, "\t$prfop, $Pg, [$Zn, $imm5]", 4154 "", 4155 []>, Sched<[]> { 4156 bits<3> Pg; 4157 bits<5> Zn; 4158 bits<5> imm5; 4159 bits<4> prfop; 4160 let Inst{31-25} = 0b1100010; 4161 let Inst{24-23} = msz; 4162 let Inst{22-21} = 0b00; 4163 let Inst{20-16} = imm5; 4164 let Inst{15-13} = 0b111; 4165 let Inst{12-10} = Pg; 4166 let Inst{9-5} = Zn; 4167 let Inst{4} = 0b0; 4168 let Inst{3-0} = prfop; 4169 4170 let hasSideEffects = 1; 4171 } 4172 4173 multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> { 4174 def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>; 4175 4176 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]", 4177 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; 4178 } 4179 4180 4181 //===----------------------------------------------------------------------===// 4182 // SVE Compute Vector Address Group 4183 //===----------------------------------------------------------------------===// 4184 4185 class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm, 4186 ZPRRegOp zprty, RegisterOperand zprext> 4187 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm), 4188 asm, "\t$Zd, [$Zn, $Zm]", 4189 "", 4190 []>, Sched<[]> { 4191 bits<5> Zd; 4192 bits<5> Zn; 4193 bits<5> Zm; 4194 let Inst{31-24} = 0b00000100; 4195 let Inst{23-22} = opc; 4196 let Inst{21} = 0b1; 4197 let Inst{20-16} = Zm; 4198 let Inst{15-12} = 0b1010; 4199 let Inst{11-10} = msz; 4200 let Inst{9-5} = Zn; 4201 let Inst{4-0} = Zd; 4202 } 4203 4204 multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> { 4205 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>; 4206 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>; 4207 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>; 4208 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>; 4209 } 4210 4211 multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> { 4212 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>; 4213 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>; 4214 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>; 4215 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>; 4216 } 4217 4218 multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> { 4219 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>; 4220 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>; 4221 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>; 4222 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>; 4223 } 4224 4225 multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> { 4226 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>; 4227 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>; 4228 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>; 4229 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>; 4230 } 4231 4232 4233 //===----------------------------------------------------------------------===// 4234 // SVE Integer Misc - Unpredicated Group 4235 //===----------------------------------------------------------------------===// 4236 4237 class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty> 4238 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 4239 asm, "\t$Zd, $Zn, $Zm", 4240 "", 4241 []>, Sched<[]> { 4242 bits<5> Zd; 4243 bits<5> Zm; 4244 bits<5> Zn; 4245 let Inst{31-24} = 0b00000100; 4246 let Inst{23-22} = sz; 4247 let Inst{21} = 0b1; 4248 let Inst{20-16} = Zm; 4249 let Inst{15-10} = 0b101100; 4250 let Inst{9-5} = Zn; 4251 let Inst{4-0} = Zd; 4252 } 4253 4254 multiclass sve_int_bin_cons_misc_0_b<string asm> { 4255 def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>; 4256 def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>; 4257 def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>; 4258 } 4259 4260 class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty> 4261 : I<(outs zprty:$Zd), (ins zprty:$Zn), 4262 asm, "\t$Zd, $Zn", 4263 "", 4264 []>, Sched<[]> { 4265 bits<5> Zd; 4266 bits<5> Zn; 4267 let Inst{31-24} = 0b00000100; 4268 let Inst{23-22} = opc{7-6}; 4269 let Inst{21} = 0b1; 4270 let Inst{20-16} = opc{5-1}; 4271 let Inst{15-11} = 0b10111; 4272 let Inst{10} = opc{0}; 4273 let Inst{9-5} = Zn; 4274 let Inst{4-0} = Zd; 4275 } 4276 4277 //===----------------------------------------------------------------------===// 4278 // SVE Integer Reduction Group 4279 //===----------------------------------------------------------------------===// 4280 4281 class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm, 4282 ZPRRegOp zprty, RegisterClass regtype> 4283 : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 4284 asm, "\t$Vd, $Pg, $Zn", 4285 "", 4286 []>, Sched<[]> { 4287 bits<3> Pg; 4288 bits<5> Vd; 4289 bits<5> Zn; 4290 let Inst{31-24} = 0b00000100; 4291 let Inst{23-22} = sz8_32; 4292 let Inst{21} = 0b0; 4293 let Inst{20-19} = fmt; 4294 let Inst{18-16} = opc; 4295 let Inst{15-13} = 0b001; 4296 let Inst{12-10} = Pg; 4297 let Inst{9-5} = Zn; 4298 let Inst{4-0} = Vd; 4299 } 4300 4301 multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm> { 4302 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; 4303 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; 4304 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; 4305 } 4306 4307 multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm> { 4308 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; 4309 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; 4310 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; 4311 def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>; 4312 } 4313 4314 multiclass sve_int_reduce_1<bits<3> opc, string asm> { 4315 def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>; 4316 def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>; 4317 def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>; 4318 def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>; 4319 } 4320 4321 multiclass sve_int_reduce_2<bits<3> opc, string asm> { 4322 def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>; 4323 def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>; 4324 def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>; 4325 def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>; 4326 } 4327 4328 class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm, 4329 ZPRRegOp zprty, string pg_suffix, dag iops> 4330 : I<(outs zprty:$Zd), iops, 4331 asm, "\t$Zd, $Pg"#pg_suffix#", $Zn", 4332 "", 4333 []>, Sched<[]> { 4334 bits<3> Pg; 4335 bits<5> Zd; 4336 bits<5> Zn; 4337 let Inst{31-24} = 0b00000100; 4338 let Inst{23-22} = sz8_32; 4339 let Inst{21-19} = 0b010; 4340 let Inst{18-16} = opc; 4341 let Inst{15-13} = 0b001; 4342 let Inst{12-10} = Pg; 4343 let Inst{9-5} = Zn; 4344 let Inst{4-0} = Zd; 4345 4346 let ElementSize = zprty.ElementSize; 4347 } 4348 4349 multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> { 4350 let Constraints = "$Zd = $_Zd" in { 4351 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m", 4352 (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>; 4353 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m", 4354 (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>; 4355 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m", 4356 (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>; 4357 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m", 4358 (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>; 4359 } 4360 } 4361 4362 multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> { 4363 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z", 4364 (ins PPR3bAny:$Pg, ZPR8:$Zn)>; 4365 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z", 4366 (ins PPR3bAny:$Pg, ZPR16:$Zn)>; 4367 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z", 4368 (ins PPR3bAny:$Pg, ZPR32:$Zn)>; 4369 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z", 4370 (ins PPR3bAny:$Pg, ZPR64:$Zn)>; 4371 } 4372 4373 //===----------------------------------------------------------------------===// 4374 // SVE Propagate Break Group 4375 //===----------------------------------------------------------------------===// 4376 4377 class sve_int_brkp<bits<2> opc, string asm> 4378 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), 4379 asm, "\t$Pd, $Pg/z, $Pn, $Pm", 4380 "", 4381 []>, Sched<[]> { 4382 bits<4> Pd; 4383 bits<4> Pg; 4384 bits<4> Pm; 4385 bits<4> Pn; 4386 let Inst{31-24} = 0b00100101; 4387 let Inst{23} = 0b0; 4388 let Inst{22} = opc{1}; 4389 let Inst{21-20} = 0b00; 4390 let Inst{19-16} = Pm; 4391 let Inst{15-14} = 0b11; 4392 let Inst{13-10} = Pg; 4393 let Inst{9} = 0b0; 4394 let Inst{8-5} = Pn; 4395 let Inst{4} = opc{0}; 4396 let Inst{3-0} = Pd; 4397 4398 let Defs = !if(!eq (opc{1}, 1), [NZCV], []); 4399 } 4400 4401 4402 //===----------------------------------------------------------------------===// 4403 // SVE Partition Break Group 4404 //===----------------------------------------------------------------------===// 4405 4406 class sve_int_brkn<bit S, string asm> 4407 : I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm), 4408 asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm", 4409 "", 4410 []>, Sched<[]> { 4411 bits<4> Pdm; 4412 bits<4> Pg; 4413 bits<4> Pn; 4414 let Inst{31-23} = 0b001001010; 4415 let Inst{22} = S; 4416 let Inst{21-14} = 0b01100001; 4417 let Inst{13-10} = Pg; 4418 let Inst{9} = 0b0; 4419 let Inst{8-5} = Pn; 4420 let Inst{4} = 0b0; 4421 let Inst{3-0} = Pdm; 4422 4423 let Constraints = "$Pdm = $_Pdm"; 4424 let Defs = !if(!eq (S, 0b1), [NZCV], []); 4425 } 4426 4427 class sve_int_break<bits<3> opc, string asm, string suffix, dag iops> 4428 : I<(outs PPR8:$Pd), iops, 4429 asm, "\t$Pd, $Pg"#suffix#", $Pn", 4430 "", 4431 []>, Sched<[]> { 4432 bits<4> Pd; 4433 bits<4> Pg; 4434 bits<4> Pn; 4435 let Inst{31-24} = 0b00100101; 4436 let Inst{23-22} = opc{2-1}; 4437 let Inst{21-14} = 0b01000001; 4438 let Inst{13-10} = Pg; 4439 let Inst{9} = 0b0; 4440 let Inst{8-5} = Pn; 4441 let Inst{4} = opc{0}; 4442 let Inst{3-0} = Pd; 4443 4444 let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", ""); 4445 let Defs = !if(!eq (opc{1}, 1), [NZCV], []); 4446 4447 } 4448 4449 multiclass sve_int_break_m<bits<3> opc, string asm> { 4450 def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>; 4451 } 4452 4453 multiclass sve_int_break_z<bits<3> opc, string asm> { 4454 def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>; 4455 } 4456 4457
