1 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> : 11 InstSI <outs, ins, "", pattern>, 12 SIMCInstr <opName, SIEncodingFamily.NONE> { 13 14 let SubtargetPredicate = isGCN; 15 16 let LGKM_CNT = 1; 17 let DS = 1; 18 let Size = 8; 19 let UseNamedOperandTable = 1; 20 21 // Most instruction load and store data, so set this as the default. 22 let mayLoad = 1; 23 let mayStore = 1; 24 25 let hasSideEffects = 0; 26 let SchedRW = [WriteLDS]; 27 28 let isPseudo = 1; 29 let isCodeGenOnly = 1; 30 31 let AsmMatchConverter = "cvtDS"; 32 33 string Mnemonic = opName; 34 string AsmOperands = asmOps; 35 36 // Well these bits a kind of hack because it would be more natural 37 // to test "outs" and "ins" dags for the presence of particular operands 38 bits<1> has_vdst = 1; 39 bits<1> has_addr = 1; 40 bits<1> has_data0 = 1; 41 bits<1> has_data1 = 1; 42 43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 44 bits<1> has_offset0 = 1; 45 bits<1> has_offset1 = 1; 46 47 bits<1> has_gds = 1; 48 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value 49 50 bits<1> has_m0_read = 1; 51 52 let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]); 53 } 54 55 class DS_Real <DS_Pseudo ds> : 56 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>, 57 Enc64 { 58 59 let isPseudo = 0; 60 let isCodeGenOnly = 0; 61 62 // copy relevant pseudo op flags 63 let SubtargetPredicate = ds.SubtargetPredicate; 64 let AsmMatchConverter = ds.AsmMatchConverter; 65 66 // encoding fields 67 bits<8> vdst; 68 bits<1> gds; 69 bits<8> addr; 70 bits<8> data0; 71 bits<8> data1; 72 bits<8> offset0; 73 bits<8> offset1; 74 75 bits<16> offset; 76 let offset0 = !if(ds.has_offset, offset{7-0}, ?); 77 let offset1 = !if(ds.has_offset, offset{15-8}, ?); 78 } 79 80 81 // DS Pseudo instructions 82 83 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32> 84 : DS_Pseudo<opName, 85 (outs), 86 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), 87 "$addr, $data0$offset$gds"> { 88 89 let has_data1 = 0; 90 let has_vdst = 0; 91 } 92 93 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> { 94 def "" : DS_1A1D_NORET<opName, rc>, 95 AtomicNoRet<opName, 0>; 96 97 let has_m0_read = 0 in { 98 def _gfx9 : DS_1A1D_NORET<opName, rc>, 99 AtomicNoRet<opName#"_gfx9", 0>; 100 } 101 } 102 103 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32> 104 : DS_Pseudo<opName, 105 (outs), 106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds), 107 "$addr, $data0, $data1"#"$offset"#"$gds"> { 108 109 let has_vdst = 0; 110 } 111 112 multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> { 113 def "" : DS_1A2D_NORET<opName, rc>, 114 AtomicNoRet<opName, 0>; 115 116 let has_m0_read = 0 in { 117 def _gfx9 : DS_1A2D_NORET<opName, rc>, 118 AtomicNoRet<opName#"_gfx9", 0>; 119 } 120 } 121 122 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32> 123 : DS_Pseudo<opName, 124 (outs), 125 (ins VGPR_32:$addr, rc:$data0, rc:$data1, 126 offset0:$offset0, offset1:$offset1, gds:$gds), 127 "$addr, $data0, $data1$offset0$offset1$gds"> { 128 129 let has_vdst = 0; 130 let has_offset = 0; 131 let AsmMatchConverter = "cvtDSOffset01"; 132 } 133 134 multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> { 135 def "" : DS_1A2D_Off8_NORET<opName, rc>; 136 137 let has_m0_read = 0 in { 138 def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>; 139 } 140 } 141 142 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32> 143 : DS_Pseudo<opName, 144 (outs rc:$vdst), 145 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), 146 "$vdst, $addr, $data0$offset$gds"> { 147 148 let hasPostISelHook = 1; 149 let has_data1 = 0; 150 } 151 152 multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32, 153 string NoRetOp = ""> { 154 def "" : DS_1A1D_RET<opName, rc>, 155 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>; 156 157 let has_m0_read = 0 in { 158 def _gfx9 : DS_1A1D_RET<opName, rc>, 159 AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"), 160 !if(!eq(NoRetOp, ""), 0, 1)>; 161 } 162 } 163 164 class DS_1A2D_RET<string opName, 165 RegisterClass rc = VGPR_32, 166 RegisterClass src = rc> 167 : DS_Pseudo<opName, 168 (outs rc:$vdst), 169 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds), 170 "$vdst, $addr, $data0, $data1$offset$gds"> { 171 172 let hasPostISelHook = 1; 173 } 174 175 multiclass DS_1A2D_RET_mc<string opName, 176 RegisterClass rc = VGPR_32, 177 string NoRetOp = "", 178 RegisterClass src = rc> { 179 def "" : DS_1A2D_RET<opName, rc, src>, 180 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>; 181 182 let has_m0_read = 0 in { 183 def _gfx9 : DS_1A2D_RET<opName, rc, src>, 184 AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>; 185 } 186 } 187 188 class DS_1A2D_Off8_RET<string opName, 189 RegisterClass rc = VGPR_32, 190 RegisterClass src = rc> 191 : DS_Pseudo<opName, 192 (outs rc:$vdst), 193 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds), 194 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> { 195 196 let has_offset = 0; 197 let AsmMatchConverter = "cvtDSOffset01"; 198 199 let hasPostISelHook = 1; 200 } 201 202 multiclass DS_1A2D_Off8_RET_mc<string opName, 203 RegisterClass rc = VGPR_32, 204 RegisterClass src = rc> { 205 def "" : DS_1A2D_Off8_RET<opName, rc, src>; 206 207 let has_m0_read = 0 in { 208 def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>; 209 } 210 } 211 212 213 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> 214 : DS_Pseudo<opName, 215 (outs rc:$vdst), 216 !if(HasTiedOutput, 217 (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in), 218 (ins VGPR_32:$addr, ofs:$offset, gds:$gds)), 219 "$vdst, $addr$offset$gds"> { 220 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", ""); 221 let DisableEncoding = !if(HasTiedOutput, "$vdst_in", ""); 222 let has_data0 = 0; 223 let has_data1 = 0; 224 } 225 226 multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> { 227 def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>; 228 229 let has_m0_read = 0 in { 230 def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>; 231 } 232 } 233 234 class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> : 235 DS_1A_RET<opName, rc, 1>; 236 237 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32> 238 : DS_Pseudo<opName, 239 (outs rc:$vdst), 240 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), 241 "$vdst, $addr$offset0$offset1$gds"> { 242 243 let has_offset = 0; 244 let has_data0 = 0; 245 let has_data1 = 0; 246 let AsmMatchConverter = "cvtDSOffset01"; 247 } 248 249 multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> { 250 def "" : DS_1A_Off8_RET<opName, rc>; 251 252 let has_m0_read = 0 in { 253 def _gfx9 : DS_1A_Off8_RET<opName, rc>; 254 } 255 } 256 257 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName, 258 (outs VGPR_32:$vdst), 259 (ins VGPR_32:$addr, offset:$offset), 260 "$vdst, $addr$offset gds"> { 261 262 let has_data0 = 0; 263 let has_data1 = 0; 264 let has_gds = 0; 265 let gdsValue = 1; 266 let AsmMatchConverter = "cvtDSGds"; 267 } 268 269 class DS_0A_RET <string opName> : DS_Pseudo<opName, 270 (outs VGPR_32:$vdst), 271 (ins offset:$offset, gds:$gds), 272 "$vdst$offset$gds"> { 273 274 let mayLoad = 1; 275 let mayStore = 1; 276 277 let has_addr = 0; 278 let has_data0 = 0; 279 let has_data1 = 0; 280 } 281 282 class DS_1A <string opName> : DS_Pseudo<opName, 283 (outs), 284 (ins VGPR_32:$addr, offset:$offset, gds:$gds), 285 "$addr$offset$gds"> { 286 287 let mayLoad = 1; 288 let mayStore = 1; 289 290 let has_vdst = 0; 291 let has_data0 = 0; 292 let has_data1 = 0; 293 } 294 295 multiclass DS_1A_mc <string opName> { 296 def "" : DS_1A<opName>; 297 298 let has_m0_read = 0 in { 299 def _gfx9 : DS_1A<opName>; 300 } 301 } 302 303 304 class DS_GWS <string opName, dag ins, string asmOps> 305 : DS_Pseudo<opName, (outs), ins, asmOps> { 306 307 let has_vdst = 0; 308 let has_addr = 0; 309 let has_data0 = 0; 310 let has_data1 = 0; 311 312 let has_gds = 0; 313 let gdsValue = 1; 314 let AsmMatchConverter = "cvtDSGds"; 315 } 316 317 class DS_GWS_0D <string opName> 318 : DS_GWS<opName, 319 (ins offset:$offset, gds:$gds), "$offset gds">; 320 321 class DS_GWS_1D <string opName> 322 : DS_GWS<opName, 323 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> { 324 325 let has_data0 = 1; 326 } 327 328 class DS_VOID <string opName> : DS_Pseudo<opName, 329 (outs), (ins), ""> { 330 let mayLoad = 0; 331 let mayStore = 0; 332 let hasSideEffects = 1; 333 let UseNamedOperandTable = 0; 334 let AsmMatchConverter = ""; 335 336 let has_vdst = 0; 337 let has_addr = 0; 338 let has_data0 = 0; 339 let has_data1 = 0; 340 let has_offset = 0; 341 let has_offset0 = 0; 342 let has_offset1 = 0; 343 let has_gds = 0; 344 } 345 346 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag> 347 : DS_Pseudo<opName, 348 (outs VGPR_32:$vdst), 349 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset), 350 "$vdst, $addr, $data0$offset", 351 [(set i32:$vdst, 352 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > { 353 354 let mayLoad = 0; 355 let mayStore = 0; 356 let isConvergent = 1; 357 358 let has_data1 = 0; 359 let has_gds = 0; 360 } 361 362 defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">; 363 defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">; 364 defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">; 365 defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">; 366 defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">; 367 defm DS_MIN_I32 : DS_1A1D_NORET_mc<"ds_min_i32">; 368 defm DS_MAX_I32 : DS_1A1D_NORET_mc<"ds_max_i32">; 369 defm DS_MIN_U32 : DS_1A1D_NORET_mc<"ds_min_u32">; 370 defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">; 371 defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">; 372 defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">; 373 defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">; 374 defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">; 375 defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">; 376 defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">; 377 378 let mayLoad = 0 in { 379 defm DS_WRITE_B8 : DS_1A1D_NORET_mc<"ds_write_b8">; 380 defm DS_WRITE_B16 : DS_1A1D_NORET_mc<"ds_write_b16">; 381 defm DS_WRITE_B32 : DS_1A1D_NORET_mc<"ds_write_b32">; 382 defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">; 383 defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">; 384 385 386 let has_m0_read = 0 in { 387 388 let SubtargetPredicate = HasD16LoadStore in { 389 def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">; 390 def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">; 391 } 392 393 let SubtargetPredicate = HasDSAddTid in { 394 def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">; 395 } 396 397 } // End has_m0_read = 0 398 } // End mayLoad = 0 399 400 defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">; 401 defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">; 402 defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">; 403 404 defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>; 405 defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>; 406 defm DS_RSUB_U64 : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>; 407 defm DS_INC_U64 : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>; 408 defm DS_DEC_U64 : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>; 409 defm DS_MIN_I64 : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>; 410 defm DS_MAX_I64 : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>; 411 defm DS_MIN_U64 : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>; 412 defm DS_MAX_U64 : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>; 413 defm DS_AND_B64 : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>; 414 defm DS_OR_B64 : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>; 415 defm DS_XOR_B64 : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>; 416 defm DS_MSKOR_B64 : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>; 417 let mayLoad = 0 in { 418 defm DS_WRITE_B64 : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>; 419 defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>; 420 defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>; 421 } 422 defm DS_CMPST_B64 : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>; 423 defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>; 424 defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>; 425 defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>; 426 427 defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">; 428 defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">; 429 defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; 430 defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; 431 defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; 432 defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; 433 defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">; 434 defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">; 435 defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">; 436 defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">; 437 defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">; 438 defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">; 439 defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; 440 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; 441 defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; 442 defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; 443 defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">; 444 defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">; 445 446 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">; 447 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>; 448 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>; 449 450 defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">; 451 defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; 452 defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; 453 defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; 454 defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; 455 defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">; 456 defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">; 457 defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">; 458 defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">; 459 defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">; 460 defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">; 461 defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; 462 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; 463 defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; 464 defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; 465 defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">; 466 defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">; 467 468 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>; 469 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>; 470 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>; 471 472 def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">; 473 def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">; 474 def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">; 475 def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">; 476 def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">; 477 478 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">; 479 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">; 480 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">; 481 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">; 482 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">; 483 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">; 484 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">; 485 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">; 486 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">; 487 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">; 488 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">; 489 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">; 490 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">; 491 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">; 492 493 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">; 494 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">; 495 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">; 496 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">; 497 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">; 498 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">; 499 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">; 500 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">; 501 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">; 502 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">; 503 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">; 504 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">; 505 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">; 506 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">; 507 508 def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">; 509 def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">; 510 511 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in { 512 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>; 513 } 514 515 let mayStore = 0 in { 516 defm DS_READ_I8 : DS_1A_RET_mc<"ds_read_i8">; 517 defm DS_READ_U8 : DS_1A_RET_mc<"ds_read_u8">; 518 defm DS_READ_I16 : DS_1A_RET_mc<"ds_read_i16">; 519 defm DS_READ_U16 : DS_1A_RET_mc<"ds_read_u16">; 520 defm DS_READ_B32 : DS_1A_RET_mc<"ds_read_b32">; 521 defm DS_READ_B64 : DS_1A_RET_mc<"ds_read_b64", VReg_64>; 522 523 defm DS_READ2_B32 : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>; 524 defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>; 525 526 defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>; 527 defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>; 528 529 let has_m0_read = 0 in { 530 let SubtargetPredicate = HasD16LoadStore in { 531 def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">; 532 def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">; 533 def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">; 534 def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">; 535 def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">; 536 def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">; 537 } 538 539 let SubtargetPredicate = HasDSAddTid in { 540 def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">; 541 } 542 } // End has_m0_read = 0 543 } 544 545 def DS_CONSUME : DS_0A_RET<"ds_consume">; 546 def DS_APPEND : DS_0A_RET<"ds_append">; 547 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; 548 549 //===----------------------------------------------------------------------===// 550 // Instruction definitions for CI and newer. 551 //===----------------------------------------------------------------------===// 552 553 let SubtargetPredicate = isCIVI in { 554 555 defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>; 556 defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>; 557 558 def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; 559 560 let mayStore = 0 in { 561 defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>; 562 defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>; 563 } // End mayStore = 0 564 565 let mayLoad = 0 in { 566 defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>; 567 defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>; 568 } // End mayLoad = 0 569 570 def DS_NOP : DS_VOID<"ds_nop">; 571 572 } // let SubtargetPredicate = isCIVI 573 574 //===----------------------------------------------------------------------===// 575 // Instruction definitions for VI and newer. 576 //===----------------------------------------------------------------------===// 577 578 let SubtargetPredicate = isVI in { 579 580 let Uses = [EXEC] in { 581 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32", 582 int_amdgcn_ds_permute>; 583 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32", 584 int_amdgcn_ds_bpermute>; 585 } 586 587 def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">; 588 589 } // let SubtargetPredicate = isVI 590 591 //===----------------------------------------------------------------------===// 592 // DS Patterns 593 //===----------------------------------------------------------------------===// 594 595 def : GCNPat < 596 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16), 597 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0)) 598 >; 599 600 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat < 601 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), 602 (inst $ptr, (as_i16imm $offset), (i1 0)) 603 >; 604 605 multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> { 606 607 let OtherPredicates = [LDSRequiresM0Init] in { 608 def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>; 609 } 610 611 let OtherPredicates = [NotLDSRequiresM0Init] in { 612 def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; 613 } 614 } 615 616 617 multiclass DSReadPat_Hi16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> { 618 def : GCNPat < 619 (build_vector vt:$lo, (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))), 620 (v2i16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo)) 621 >; 622 623 def : GCNPat < 624 (build_vector f16:$lo, (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))))), 625 (v2f16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo)) 626 >; 627 } 628 629 multiclass DSReadPat_Lo16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> { 630 def : GCNPat < 631 (build_vector (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), (vt (Hi16Elt vt:$hi))), 632 (v2i16 (inst $ptr, (as_i16imm $offset), 0, $hi)) 633 >; 634 635 def : GCNPat < 636 (build_vector (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))))), (f16 (Hi16Elt f16:$hi))), 637 (v2f16 (inst $ptr, (as_i16imm $offset), 0, $hi)) 638 >; 639 } 640 641 defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">; 642 defm : DSReadPat_mc <DS_READ_U8, i32, "az_extloadi8_local">; 643 defm : DSReadPat_mc <DS_READ_I8, i16, "sextloadi8_local">; 644 defm : DSReadPat_mc <DS_READ_U8, i16, "az_extloadi8_local">; 645 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">; 646 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">; 647 defm : DSReadPat_mc <DS_READ_U16, i32, "az_extloadi16_local">; 648 defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">; 649 defm : DSReadPat_mc <DS_READ_B32, i32, "load_local">; 650 defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">; 651 defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">; 652 653 let AddedComplexity = 100 in { 654 655 defm : DSReadPat_mc <DS_READ_B64, v2i32, "load_align8_local">; 656 defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">; 657 658 } // End AddedComplexity = 100 659 660 let OtherPredicates = [D16PreservesUnusedBits] in { 661 let AddedComplexity = 100 in { 662 defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>; 663 defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>; 664 defm : DSReadPat_Hi16<DS_READ_I8_D16_HI, sextloadi8_local>; 665 666 defm : DSReadPat_Lo16<DS_READ_U16_D16, load_local>; 667 defm : DSReadPat_Lo16<DS_READ_U8_D16, az_extloadi8_local>; 668 defm : DSReadPat_Lo16<DS_READ_I8_D16, sextloadi8_local>; 669 670 } 671 } 672 673 class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat < 674 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), 675 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 676 >; 677 678 multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> { 679 let OtherPredicates = [LDSRequiresM0Init] in { 680 def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>; 681 } 682 683 let OtherPredicates = [NotLDSRequiresM0Init] in { 684 def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; 685 } 686 } 687 688 // Irritatingly, atomic_store reverses the order of operands from a 689 // normal store. 690 class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat < 691 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 692 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 693 >; 694 695 multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> { 696 let OtherPredicates = [LDSRequiresM0Init] in { 697 def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>; 698 } 699 700 let OtherPredicates = [NotLDSRequiresM0Init] in { 701 def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; 702 } 703 } 704 705 defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">; 706 defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">; 707 defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">; 708 defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">; 709 defm : DSWritePat_mc <DS_WRITE_B32, i32, "store_local">; 710 defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local">; 711 defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local">; 712 713 let OtherPredicates = [D16PreservesUnusedBits] in { 714 def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>; 715 def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>; 716 } 717 718 719 class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, PatFrag frag> : GCNPat < 720 (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))), 721 (inst $ptr, $offset0, $offset1, (i1 0)) 722 >; 723 724 class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat< 725 (frag v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)), 726 (inst $ptr, (i32 (EXTRACT_SUBREG $value, sub0)), 727 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1, 728 (i1 0)) 729 >; 730 731 let OtherPredicates = [LDSRequiresM0Init] in { 732 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>; 733 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>; 734 } 735 736 let OtherPredicates = [NotLDSRequiresM0Init] in { 737 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, load_local>; 738 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>; 739 } 740 741 742 let AddedComplexity = 100 in { 743 744 defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">; 745 defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">; 746 747 } // End AddedComplexity = 100 748 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat < 749 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 750 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 751 >; 752 753 multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> { 754 let OtherPredicates = [LDSRequiresM0Init] in { 755 def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_m0")>; 756 } 757 758 let OtherPredicates = [NotLDSRequiresM0Init] in { 759 def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, 760 !cast<PatFrag>(frag)>; 761 } 762 } 763 764 765 766 class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat < 767 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), 768 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) 769 >; 770 771 multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> { 772 let OtherPredicates = [LDSRequiresM0Init] in { 773 def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_m0")>; 774 } 775 776 let OtherPredicates = [NotLDSRequiresM0Init] in { 777 def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, 778 !cast<PatFrag>(frag)>; 779 } 780 } 781 782 783 784 // 32-bit atomics. 785 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap_local">; 786 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add_local">; 787 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub_local">; 788 defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc_local">; 789 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec_local">; 790 defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and_local">; 791 defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or_local">; 792 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor_local">; 793 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min_local">; 794 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max_local">; 795 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin_local">; 796 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax_local">; 797 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap_local">; 798 defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin_local">; 799 defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax_local">; 800 defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd_local">; 801 802 // 64-bit atomics. 803 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap_local">; 804 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add_local">; 805 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub_local">; 806 defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc_local">; 807 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec_local">; 808 defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and_local">; 809 defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or_local">; 810 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor_local">; 811 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min_local">; 812 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max_local">; 813 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin_local">; 814 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax_local">; 815 816 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap_local">; 817 818 //===----------------------------------------------------------------------===// 819 // Real instructions 820 //===----------------------------------------------------------------------===// 821 822 //===----------------------------------------------------------------------===// 823 // SIInstructions.td 824 //===----------------------------------------------------------------------===// 825 826 class DS_Real_si <bits<8> op, DS_Pseudo ds> : 827 DS_Real <ds>, 828 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> { 829 let AssemblerPredicates=[isSICI]; 830 let DecoderNamespace="SICI"; 831 832 // encoding 833 let Inst{7-0} = !if(ds.has_offset0, offset0, 0); 834 let Inst{15-8} = !if(ds.has_offset1, offset1, 0); 835 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue); 836 let Inst{25-18} = op; 837 let Inst{31-26} = 0x36; // ds prefix 838 let Inst{39-32} = !if(ds.has_addr, addr, 0); 839 let Inst{47-40} = !if(ds.has_data0, data0, 0); 840 let Inst{55-48} = !if(ds.has_data1, data1, 0); 841 let Inst{63-56} = !if(ds.has_vdst, vdst, 0); 842 } 843 844 def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>; 845 def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>; 846 def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>; 847 def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>; 848 def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>; 849 def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>; 850 def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>; 851 def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>; 852 def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>; 853 def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>; 854 def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>; 855 def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>; 856 def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>; 857 def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>; 858 def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>; 859 def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>; 860 def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>; 861 def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>; 862 def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>; 863 def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>; 864 def DS_NOP_si : DS_Real_si<0x14, DS_NOP>; 865 def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>; 866 def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>; 867 def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>; 868 def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>; 869 def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>; 870 def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>; 871 def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>; 872 def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>; 873 def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>; 874 def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>; 875 def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>; 876 def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>; 877 def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>; 878 def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>; 879 def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>; 880 def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>; 881 def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>; 882 def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>; 883 def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>; 884 def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>; 885 def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>; 886 def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>; 887 def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>; 888 def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>; 889 def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>; 890 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>; 891 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>; 892 893 // These instruction are CI/VI only 894 def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>; 895 def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>; 896 def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>; 897 898 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>; 899 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>; 900 def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>; 901 def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>; 902 def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>; 903 def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>; 904 def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>; 905 def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>; 906 def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>; 907 def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>; 908 def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>; 909 def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>; 910 def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>; 911 def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>; 912 def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>; 913 def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>; 914 def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>; 915 def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>; 916 def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>; 917 def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>; 918 def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>; 919 def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>; 920 def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>; 921 def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>; 922 def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>; 923 def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>; 924 def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>; 925 def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>; 926 def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>; 927 def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>; 928 def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>; 929 930 def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>; 931 def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>; 932 def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>; 933 def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>; 934 def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>; 935 def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>; 936 def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>; 937 def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>; 938 def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>; 939 def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>; 940 def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>; 941 def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>; 942 def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>; 943 def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>; 944 def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>; 945 def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>; 946 def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>; 947 def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>; 948 def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>; 949 def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>; 950 951 def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>; 952 def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>; 953 def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>; 954 955 def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>; 956 def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>; 957 def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>; 958 def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>; 959 def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>; 960 def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>; 961 def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>; 962 def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>; 963 def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>; 964 def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>; 965 def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>; 966 def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>; 967 def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>; 968 969 def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>; 970 def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>; 971 972 def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>; 973 def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>; 974 def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>; 975 def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>; 976 def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>; 977 def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>; 978 def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>; 979 def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>; 980 def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>; 981 def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>; 982 def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>; 983 def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>; 984 def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>; 985 986 def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>; 987 def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>; 988 def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>; 989 def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>; 990 def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>; 991 def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>; 992 993 //===----------------------------------------------------------------------===// 994 // VIInstructions.td 995 //===----------------------------------------------------------------------===// 996 997 class DS_Real_vi <bits<8> op, DS_Pseudo ds> : 998 DS_Real <ds>, 999 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> { 1000 let AssemblerPredicates = [isVI]; 1001 let DecoderNamespace="VI"; 1002 1003 // encoding 1004 let Inst{7-0} = !if(ds.has_offset0, offset0, 0); 1005 let Inst{15-8} = !if(ds.has_offset1, offset1, 0); 1006 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue); 1007 let Inst{24-17} = op; 1008 let Inst{31-26} = 0x36; // ds prefix 1009 let Inst{39-32} = !if(ds.has_addr, addr, 0); 1010 let Inst{47-40} = !if(ds.has_data0, data0, 0); 1011 let Inst{55-48} = !if(ds.has_data1, data1, 0); 1012 let Inst{63-56} = !if(ds.has_vdst, vdst, 0); 1013 } 1014 1015 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>; 1016 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>; 1017 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>; 1018 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>; 1019 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>; 1020 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>; 1021 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>; 1022 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>; 1023 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>; 1024 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>; 1025 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>; 1026 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>; 1027 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>; 1028 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>; 1029 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>; 1030 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>; 1031 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>; 1032 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>; 1033 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>; 1034 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>; 1035 def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>; 1036 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>; 1037 def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>; 1038 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>; 1039 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>; 1040 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>; 1041 def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>; 1042 def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>; 1043 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; 1044 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; 1045 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; 1046 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>; 1047 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>; 1048 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>; 1049 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>; 1050 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>; 1051 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>; 1052 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>; 1053 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>; 1054 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>; 1055 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>; 1056 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>; 1057 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>; 1058 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>; 1059 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>; 1060 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>; 1061 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>; 1062 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>; 1063 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>; 1064 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>; 1065 def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>; 1066 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>; 1067 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>; 1068 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>; 1069 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>; 1070 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>; 1071 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; 1072 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; 1073 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; 1074 def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>; 1075 def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>; 1076 def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>; 1077 def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>; 1078 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>; 1079 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>; 1080 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>; 1081 1082 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>; 1083 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>; 1084 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>; 1085 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>; 1086 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>; 1087 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>; 1088 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>; 1089 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>; 1090 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>; 1091 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>; 1092 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>; 1093 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>; 1094 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>; 1095 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>; 1096 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>; 1097 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>; 1098 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>; 1099 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>; 1100 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>; 1101 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>; 1102 1103 def DS_WRITE_B8_D16_HI_vi : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>; 1104 def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>; 1105 1106 def DS_READ_U8_D16_vi : DS_Real_vi<0x56, DS_READ_U8_D16>; 1107 def DS_READ_U8_D16_HI_vi : DS_Real_vi<0x57, DS_READ_U8_D16_HI>; 1108 def DS_READ_I8_D16_vi : DS_Real_vi<0x58, DS_READ_I8_D16>; 1109 def DS_READ_I8_D16_HI_vi : DS_Real_vi<0x59, DS_READ_I8_D16_HI>; 1110 def DS_READ_U16_D16_vi : DS_Real_vi<0x5a, DS_READ_U16_D16>; 1111 def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>; 1112 1113 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>; 1114 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>; 1115 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>; 1116 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>; 1117 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>; 1118 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>; 1119 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>; 1120 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>; 1121 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>; 1122 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>; 1123 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>; 1124 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>; 1125 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>; 1126 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>; 1127 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>; 1128 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>; 1129 def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>; 1130 def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>; 1131 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>; 1132 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>; 1133 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>; 1134 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>; 1135 1136 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>; 1137 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>; 1138 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>; 1139 1140 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>; 1141 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>; 1142 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>; 1143 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>; 1144 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>; 1145 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>; 1146 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>; 1147 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>; 1148 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>; 1149 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>; 1150 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>; 1151 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>; 1152 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>; 1153 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>; 1154 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>; 1155 def DS_ADD_SRC2_F32_vi : DS_Real_vi<0x95, DS_ADD_SRC2_F32>; 1156 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>; 1157 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>; 1158 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>; 1159 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>; 1160 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>; 1161 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>; 1162 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>; 1163 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>; 1164 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>; 1165 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>; 1166 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>; 1167 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>; 1168 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>; 1169 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>; 1170 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>; 1171 def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>; 1172 def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>; 1173 def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>; 1174 def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>; 1175
