1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// Add implicit use of exec to vector register copies. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "AMDGPU.h" 16 #include "AMDGPUSubtarget.h" 17 #include "SIInstrInfo.h" 18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 19 #include "llvm/CodeGen/MachineFunctionPass.h" 20 21 using namespace llvm; 22 23 #define DEBUG_TYPE "si-fix-vgpr-copies" 24 25 namespace { 26 27 class SIFixVGPRCopies : public MachineFunctionPass { 28 public: 29 static char ID; 30 31 public: 32 SIFixVGPRCopies() : MachineFunctionPass(ID) { 33 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry()); 34 } 35 36 bool runOnMachineFunction(MachineFunction &MF) override; 37 38 StringRef getPassName() const override { return "SI Fix VGPR copies"; } 39 }; 40 41 } // End anonymous namespace. 42 43 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false) 44 45 char SIFixVGPRCopies::ID = 0; 46 47 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID; 48 49 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) { 50 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); 51 const SIRegisterInfo *TRI = ST.getRegisterInfo(); 52 const SIInstrInfo *TII = ST.getInstrInfo(); 53 bool Changed = false; 54 55 for (MachineBasicBlock &MBB : MF) { 56 for (MachineInstr &MI : MBB) { 57 switch (MI.getOpcode()) { 58 case AMDGPU::COPY: 59 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { 60 MI.addOperand(MF, 61 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); 62 LLVM_DEBUG(dbgs() << "Add exec use to " << MI); 63 Changed = true; 64 } 65 break; 66 default: 67 break; 68 } 69 } 70 } 71 72 return Changed; 73 } 74
