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      1 //===- HexagonDepInstrInfo.td ---------------------------------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 // Automatically generated file, please consult code owner before editing.
     10 //===----------------------------------------------------------------------===//
     11 
     12 
     13 def A2_abs : HInst<
     14 (outs IntRegs:$Rd32),
     15 (ins IntRegs:$Rs32),
     16 "$Rd32 = abs($Rs32)",
     17 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
     18 let Inst{13-5} = 0b000000100;
     19 let Inst{31-21} = 0b10001100100;
     20 let hasNewValue = 1;
     21 let opNewValue = 0;
     22 let prefersSlot3 = 1;
     23 }
     24 def A2_absp : HInst<
     25 (outs DoubleRegs:$Rdd32),
     26 (ins DoubleRegs:$Rss32),
     27 "$Rdd32 = abs($Rss32)",
     28 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
     29 let Inst{13-5} = 0b000000110;
     30 let Inst{31-21} = 0b10000000100;
     31 let prefersSlot3 = 1;
     32 }
     33 def A2_abssat : HInst<
     34 (outs IntRegs:$Rd32),
     35 (ins IntRegs:$Rs32),
     36 "$Rd32 = abs($Rs32):sat",
     37 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
     38 let Inst{13-5} = 0b000000101;
     39 let Inst{31-21} = 0b10001100100;
     40 let hasNewValue = 1;
     41 let opNewValue = 0;
     42 let prefersSlot3 = 1;
     43 let Defs = [USR_OVF];
     44 }
     45 def A2_add : HInst<
     46 (outs IntRegs:$Rd32),
     47 (ins IntRegs:$Rs32, IntRegs:$Rt32),
     48 "$Rd32 = add($Rs32,$Rt32)",
     49 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
     50 let Inst{7-5} = 0b000;
     51 let Inst{13-13} = 0b0;
     52 let Inst{31-21} = 0b11110011000;
     53 let hasNewValue = 1;
     54 let opNewValue = 0;
     55 let CextOpcode = "A2_add";
     56 let InputType = "reg";
     57 let BaseOpcode = "A2_add";
     58 let isCommutable = 1;
     59 let isPredicable = 1;
     60 }
     61 def A2_addh_h16_hh : HInst<
     62 (outs IntRegs:$Rd32),
     63 (ins IntRegs:$Rt32, IntRegs:$Rs32),
     64 "$Rd32 = add($Rt32.h,$Rs32.h):<<16",
     65 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
     66 let Inst{7-5} = 0b011;
     67 let Inst{13-13} = 0b0;
     68 let Inst{31-21} = 0b11010101010;
     69 let hasNewValue = 1;
     70 let opNewValue = 0;
     71 let prefersSlot3 = 1;
     72 }
     73 def A2_addh_h16_hl : HInst<
     74 (outs IntRegs:$Rd32),
     75 (ins IntRegs:$Rt32, IntRegs:$Rs32),
     76 "$Rd32 = add($Rt32.h,$Rs32.l):<<16",
     77 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
     78 let Inst{7-5} = 0b010;
     79 let Inst{13-13} = 0b0;
     80 let Inst{31-21} = 0b11010101010;
     81 let hasNewValue = 1;
     82 let opNewValue = 0;
     83 let prefersSlot3 = 1;
     84 }
     85 def A2_addh_h16_lh : HInst<
     86 (outs IntRegs:$Rd32),
     87 (ins IntRegs:$Rt32, IntRegs:$Rs32),
     88 "$Rd32 = add($Rt32.l,$Rs32.h):<<16",
     89 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
     90 let Inst{7-5} = 0b001;
     91 let Inst{13-13} = 0b0;
     92 let Inst{31-21} = 0b11010101010;
     93 let hasNewValue = 1;
     94 let opNewValue = 0;
     95 let prefersSlot3 = 1;
     96 }
     97 def A2_addh_h16_ll : HInst<
     98 (outs IntRegs:$Rd32),
     99 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    100 "$Rd32 = add($Rt32.l,$Rs32.l):<<16",
    101 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
    102 let Inst{7-5} = 0b000;
    103 let Inst{13-13} = 0b0;
    104 let Inst{31-21} = 0b11010101010;
    105 let hasNewValue = 1;
    106 let opNewValue = 0;
    107 let prefersSlot3 = 1;
    108 }
    109 def A2_addh_h16_sat_hh : HInst<
    110 (outs IntRegs:$Rd32),
    111 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    112 "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
    113 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    114 let Inst{7-5} = 0b111;
    115 let Inst{13-13} = 0b0;
    116 let Inst{31-21} = 0b11010101010;
    117 let hasNewValue = 1;
    118 let opNewValue = 0;
    119 let prefersSlot3 = 1;
    120 let Defs = [USR_OVF];
    121 }
    122 def A2_addh_h16_sat_hl : HInst<
    123 (outs IntRegs:$Rd32),
    124 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    125 "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
    126 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    127 let Inst{7-5} = 0b110;
    128 let Inst{13-13} = 0b0;
    129 let Inst{31-21} = 0b11010101010;
    130 let hasNewValue = 1;
    131 let opNewValue = 0;
    132 let prefersSlot3 = 1;
    133 let Defs = [USR_OVF];
    134 }
    135 def A2_addh_h16_sat_lh : HInst<
    136 (outs IntRegs:$Rd32),
    137 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    138 "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
    139 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    140 let Inst{7-5} = 0b101;
    141 let Inst{13-13} = 0b0;
    142 let Inst{31-21} = 0b11010101010;
    143 let hasNewValue = 1;
    144 let opNewValue = 0;
    145 let prefersSlot3 = 1;
    146 let Defs = [USR_OVF];
    147 }
    148 def A2_addh_h16_sat_ll : HInst<
    149 (outs IntRegs:$Rd32),
    150 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    151 "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
    152 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    153 let Inst{7-5} = 0b100;
    154 let Inst{13-13} = 0b0;
    155 let Inst{31-21} = 0b11010101010;
    156 let hasNewValue = 1;
    157 let opNewValue = 0;
    158 let prefersSlot3 = 1;
    159 let Defs = [USR_OVF];
    160 }
    161 def A2_addh_l16_hl : HInst<
    162 (outs IntRegs:$Rd32),
    163 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    164 "$Rd32 = add($Rt32.l,$Rs32.h)",
    165 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
    166 let Inst{7-5} = 0b010;
    167 let Inst{13-13} = 0b0;
    168 let Inst{31-21} = 0b11010101000;
    169 let hasNewValue = 1;
    170 let opNewValue = 0;
    171 let prefersSlot3 = 1;
    172 }
    173 def A2_addh_l16_ll : HInst<
    174 (outs IntRegs:$Rd32),
    175 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    176 "$Rd32 = add($Rt32.l,$Rs32.l)",
    177 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
    178 let Inst{7-5} = 0b000;
    179 let Inst{13-13} = 0b0;
    180 let Inst{31-21} = 0b11010101000;
    181 let hasNewValue = 1;
    182 let opNewValue = 0;
    183 let prefersSlot3 = 1;
    184 }
    185 def A2_addh_l16_sat_hl : HInst<
    186 (outs IntRegs:$Rd32),
    187 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    188 "$Rd32 = add($Rt32.l,$Rs32.h):sat",
    189 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    190 let Inst{7-5} = 0b110;
    191 let Inst{13-13} = 0b0;
    192 let Inst{31-21} = 0b11010101000;
    193 let hasNewValue = 1;
    194 let opNewValue = 0;
    195 let prefersSlot3 = 1;
    196 let Defs = [USR_OVF];
    197 }
    198 def A2_addh_l16_sat_ll : HInst<
    199 (outs IntRegs:$Rd32),
    200 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    201 "$Rd32 = add($Rt32.l,$Rs32.l):sat",
    202 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    203 let Inst{7-5} = 0b100;
    204 let Inst{13-13} = 0b0;
    205 let Inst{31-21} = 0b11010101000;
    206 let hasNewValue = 1;
    207 let opNewValue = 0;
    208 let prefersSlot3 = 1;
    209 let Defs = [USR_OVF];
    210 }
    211 def A2_addi : HInst<
    212 (outs IntRegs:$Rd32),
    213 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
    214 "$Rd32 = add($Rs32,#$Ii)",
    215 tc_b9488031, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
    216 let Inst{31-28} = 0b1011;
    217 let hasNewValue = 1;
    218 let opNewValue = 0;
    219 let CextOpcode = "A2_add";
    220 let InputType = "imm";
    221 let BaseOpcode = "A2_addi";
    222 let isPredicable = 1;
    223 let isAdd = 1;
    224 let isExtendable = 1;
    225 let opExtendable = 2;
    226 let isExtentSigned = 1;
    227 let opExtentBits = 16;
    228 let opExtentAlign = 0;
    229 }
    230 def A2_addp : HInst<
    231 (outs DoubleRegs:$Rdd32),
    232 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    233 "$Rdd32 = add($Rss32,$Rtt32)",
    234 tc_540fdfbc, TypeALU64>, Enc_a56825 {
    235 let Inst{7-5} = 0b111;
    236 let Inst{13-13} = 0b0;
    237 let Inst{31-21} = 0b11010011000;
    238 let isCommutable = 1;
    239 let isAdd = 1;
    240 }
    241 def A2_addpsat : HInst<
    242 (outs DoubleRegs:$Rdd32),
    243 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    244 "$Rdd32 = add($Rss32,$Rtt32):sat",
    245 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
    246 let Inst{7-5} = 0b101;
    247 let Inst{13-13} = 0b0;
    248 let Inst{31-21} = 0b11010011011;
    249 let prefersSlot3 = 1;
    250 let Defs = [USR_OVF];
    251 let isCommutable = 1;
    252 }
    253 def A2_addsat : HInst<
    254 (outs IntRegs:$Rd32),
    255 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    256 "$Rd32 = add($Rs32,$Rt32):sat",
    257 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
    258 let Inst{7-5} = 0b000;
    259 let Inst{13-13} = 0b0;
    260 let Inst{31-21} = 0b11110110010;
    261 let hasNewValue = 1;
    262 let opNewValue = 0;
    263 let prefersSlot3 = 1;
    264 let Defs = [USR_OVF];
    265 let InputType = "reg";
    266 let isCommutable = 1;
    267 }
    268 def A2_addsp : HInst<
    269 (outs DoubleRegs:$Rdd32),
    270 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
    271 "$Rdd32 = add($Rs32,$Rtt32)",
    272 tc_897d1a9d, TypeALU64> {
    273 let isPseudo = 1;
    274 }
    275 def A2_addsph : HInst<
    276 (outs DoubleRegs:$Rdd32),
    277 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    278 "$Rdd32 = add($Rss32,$Rtt32):raw:hi",
    279 tc_897d1a9d, TypeALU64>, Enc_a56825 {
    280 let Inst{7-5} = 0b111;
    281 let Inst{13-13} = 0b0;
    282 let Inst{31-21} = 0b11010011011;
    283 let prefersSlot3 = 1;
    284 }
    285 def A2_addspl : HInst<
    286 (outs DoubleRegs:$Rdd32),
    287 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    288 "$Rdd32 = add($Rss32,$Rtt32):raw:lo",
    289 tc_897d1a9d, TypeALU64>, Enc_a56825 {
    290 let Inst{7-5} = 0b110;
    291 let Inst{13-13} = 0b0;
    292 let Inst{31-21} = 0b11010011011;
    293 let prefersSlot3 = 1;
    294 }
    295 def A2_and : HInst<
    296 (outs IntRegs:$Rd32),
    297 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    298 "$Rd32 = and($Rs32,$Rt32)",
    299 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
    300 let Inst{7-5} = 0b000;
    301 let Inst{13-13} = 0b0;
    302 let Inst{31-21} = 0b11110001000;
    303 let hasNewValue = 1;
    304 let opNewValue = 0;
    305 let CextOpcode = "A2_and";
    306 let InputType = "reg";
    307 let BaseOpcode = "A2_and";
    308 let isCommutable = 1;
    309 let isPredicable = 1;
    310 }
    311 def A2_andir : HInst<
    312 (outs IntRegs:$Rd32),
    313 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
    314 "$Rd32 = and($Rs32,#$Ii)",
    315 tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
    316 let Inst{31-22} = 0b0111011000;
    317 let hasNewValue = 1;
    318 let opNewValue = 0;
    319 let CextOpcode = "A2_and";
    320 let InputType = "imm";
    321 let isExtendable = 1;
    322 let opExtendable = 2;
    323 let isExtentSigned = 1;
    324 let opExtentBits = 10;
    325 let opExtentAlign = 0;
    326 }
    327 def A2_andp : HInst<
    328 (outs DoubleRegs:$Rdd32),
    329 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    330 "$Rdd32 = and($Rss32,$Rtt32)",
    331 tc_540fdfbc, TypeALU64>, Enc_a56825 {
    332 let Inst{7-5} = 0b000;
    333 let Inst{13-13} = 0b0;
    334 let Inst{31-21} = 0b11010011111;
    335 let isCommutable = 1;
    336 }
    337 def A2_aslh : HInst<
    338 (outs IntRegs:$Rd32),
    339 (ins IntRegs:$Rs32),
    340 "$Rd32 = aslh($Rs32)",
    341 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
    342 let Inst{13-5} = 0b000000000;
    343 let Inst{31-21} = 0b01110000000;
    344 let hasNewValue = 1;
    345 let opNewValue = 0;
    346 let BaseOpcode = "A2_aslh";
    347 let isPredicable = 1;
    348 }
    349 def A2_asrh : HInst<
    350 (outs IntRegs:$Rd32),
    351 (ins IntRegs:$Rs32),
    352 "$Rd32 = asrh($Rs32)",
    353 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
    354 let Inst{13-5} = 0b000000000;
    355 let Inst{31-21} = 0b01110000001;
    356 let hasNewValue = 1;
    357 let opNewValue = 0;
    358 let BaseOpcode = "A2_asrh";
    359 let isPredicable = 1;
    360 }
    361 def A2_combine_hh : HInst<
    362 (outs IntRegs:$Rd32),
    363 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    364 "$Rd32 = combine($Rt32.h,$Rs32.h)",
    365 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
    366 let Inst{7-5} = 0b000;
    367 let Inst{13-13} = 0b0;
    368 let Inst{31-21} = 0b11110011100;
    369 let hasNewValue = 1;
    370 let opNewValue = 0;
    371 let InputType = "reg";
    372 }
    373 def A2_combine_hl : HInst<
    374 (outs IntRegs:$Rd32),
    375 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    376 "$Rd32 = combine($Rt32.h,$Rs32.l)",
    377 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
    378 let Inst{7-5} = 0b000;
    379 let Inst{13-13} = 0b0;
    380 let Inst{31-21} = 0b11110011101;
    381 let hasNewValue = 1;
    382 let opNewValue = 0;
    383 let InputType = "reg";
    384 }
    385 def A2_combine_lh : HInst<
    386 (outs IntRegs:$Rd32),
    387 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    388 "$Rd32 = combine($Rt32.l,$Rs32.h)",
    389 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
    390 let Inst{7-5} = 0b000;
    391 let Inst{13-13} = 0b0;
    392 let Inst{31-21} = 0b11110011110;
    393 let hasNewValue = 1;
    394 let opNewValue = 0;
    395 let InputType = "reg";
    396 }
    397 def A2_combine_ll : HInst<
    398 (outs IntRegs:$Rd32),
    399 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    400 "$Rd32 = combine($Rt32.l,$Rs32.l)",
    401 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
    402 let Inst{7-5} = 0b000;
    403 let Inst{13-13} = 0b0;
    404 let Inst{31-21} = 0b11110011111;
    405 let hasNewValue = 1;
    406 let opNewValue = 0;
    407 let InputType = "reg";
    408 }
    409 def A2_combineii : HInst<
    410 (outs DoubleRegs:$Rdd32),
    411 (ins s32_0Imm:$Ii, s8_0Imm:$II),
    412 "$Rdd32 = combine(#$Ii,#$II)",
    413 tc_b9488031, TypeALU32_2op>, Enc_18c338 {
    414 let Inst{31-23} = 0b011111000;
    415 let isReMaterializable = 1;
    416 let isAsCheapAsAMove = 1;
    417 let isMoveImm = 1;
    418 let isExtendable = 1;
    419 let opExtendable = 1;
    420 let isExtentSigned = 1;
    421 let opExtentBits = 8;
    422 let opExtentAlign = 0;
    423 }
    424 def A2_combinew : HInst<
    425 (outs DoubleRegs:$Rdd32),
    426 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    427 "$Rdd32 = combine($Rs32,$Rt32)",
    428 tc_b9488031, TypeALU32_3op>, Enc_be32a5, PredNewRel {
    429 let Inst{7-5} = 0b000;
    430 let Inst{13-13} = 0b0;
    431 let Inst{31-21} = 0b11110101000;
    432 let InputType = "reg";
    433 let BaseOpcode = "A2_combinew";
    434 let isPredicable = 1;
    435 }
    436 def A2_max : HInst<
    437 (outs IntRegs:$Rd32),
    438 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    439 "$Rd32 = max($Rs32,$Rt32)",
    440 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
    441 let Inst{7-5} = 0b000;
    442 let Inst{13-13} = 0b0;
    443 let Inst{31-21} = 0b11010101110;
    444 let hasNewValue = 1;
    445 let opNewValue = 0;
    446 let prefersSlot3 = 1;
    447 }
    448 def A2_maxp : HInst<
    449 (outs DoubleRegs:$Rdd32),
    450 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    451 "$Rdd32 = max($Rss32,$Rtt32)",
    452 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
    453 let Inst{7-5} = 0b100;
    454 let Inst{13-13} = 0b0;
    455 let Inst{31-21} = 0b11010011110;
    456 let prefersSlot3 = 1;
    457 }
    458 def A2_maxu : HInst<
    459 (outs IntRegs:$Rd32),
    460 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    461 "$Rd32 = maxu($Rs32,$Rt32)",
    462 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
    463 let Inst{7-5} = 0b100;
    464 let Inst{13-13} = 0b0;
    465 let Inst{31-21} = 0b11010101110;
    466 let hasNewValue = 1;
    467 let opNewValue = 0;
    468 let prefersSlot3 = 1;
    469 }
    470 def A2_maxup : HInst<
    471 (outs DoubleRegs:$Rdd32),
    472 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    473 "$Rdd32 = maxu($Rss32,$Rtt32)",
    474 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
    475 let Inst{7-5} = 0b101;
    476 let Inst{13-13} = 0b0;
    477 let Inst{31-21} = 0b11010011110;
    478 let prefersSlot3 = 1;
    479 }
    480 def A2_min : HInst<
    481 (outs IntRegs:$Rd32),
    482 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    483 "$Rd32 = min($Rt32,$Rs32)",
    484 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    485 let Inst{7-5} = 0b000;
    486 let Inst{13-13} = 0b0;
    487 let Inst{31-21} = 0b11010101101;
    488 let hasNewValue = 1;
    489 let opNewValue = 0;
    490 let prefersSlot3 = 1;
    491 }
    492 def A2_minp : HInst<
    493 (outs DoubleRegs:$Rdd32),
    494 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
    495 "$Rdd32 = min($Rtt32,$Rss32)",
    496 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
    497 let Inst{7-5} = 0b110;
    498 let Inst{13-13} = 0b0;
    499 let Inst{31-21} = 0b11010011101;
    500 let prefersSlot3 = 1;
    501 }
    502 def A2_minu : HInst<
    503 (outs IntRegs:$Rd32),
    504 (ins IntRegs:$Rt32, IntRegs:$Rs32),
    505 "$Rd32 = minu($Rt32,$Rs32)",
    506 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
    507 let Inst{7-5} = 0b100;
    508 let Inst{13-13} = 0b0;
    509 let Inst{31-21} = 0b11010101101;
    510 let hasNewValue = 1;
    511 let opNewValue = 0;
    512 let prefersSlot3 = 1;
    513 }
    514 def A2_minup : HInst<
    515 (outs DoubleRegs:$Rdd32),
    516 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
    517 "$Rdd32 = minu($Rtt32,$Rss32)",
    518 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
    519 let Inst{7-5} = 0b111;
    520 let Inst{13-13} = 0b0;
    521 let Inst{31-21} = 0b11010011101;
    522 let prefersSlot3 = 1;
    523 }
    524 def A2_neg : HInst<
    525 (outs IntRegs:$Rd32),
    526 (ins IntRegs:$Rs32),
    527 "$Rd32 = neg($Rs32)",
    528 tc_68cb12ce, TypeALU32_2op> {
    529 let hasNewValue = 1;
    530 let opNewValue = 0;
    531 let isPseudo = 1;
    532 let isCodeGenOnly = 1;
    533 }
    534 def A2_negp : HInst<
    535 (outs DoubleRegs:$Rdd32),
    536 (ins DoubleRegs:$Rss32),
    537 "$Rdd32 = neg($Rss32)",
    538 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
    539 let Inst{13-5} = 0b000000101;
    540 let Inst{31-21} = 0b10000000100;
    541 }
    542 def A2_negsat : HInst<
    543 (outs IntRegs:$Rd32),
    544 (ins IntRegs:$Rs32),
    545 "$Rd32 = neg($Rs32):sat",
    546 tc_c2f7d806, TypeS_2op>, Enc_5e2823 {
    547 let Inst{13-5} = 0b000000110;
    548 let Inst{31-21} = 0b10001100100;
    549 let hasNewValue = 1;
    550 let opNewValue = 0;
    551 let prefersSlot3 = 1;
    552 let Defs = [USR_OVF];
    553 }
    554 def A2_nop : HInst<
    555 (outs),
    556 (ins),
    557 "nop",
    558 tc_6efc556e, TypeALU32_2op>, Enc_e3b0c4 {
    559 let Inst{13-0} = 0b00000000000000;
    560 let Inst{31-16} = 0b0111111100000000;
    561 }
    562 def A2_not : HInst<
    563 (outs IntRegs:$Rd32),
    564 (ins IntRegs:$Rs32),
    565 "$Rd32 = not($Rs32)",
    566 tc_68cb12ce, TypeALU32_2op> {
    567 let hasNewValue = 1;
    568 let opNewValue = 0;
    569 let isPseudo = 1;
    570 let isCodeGenOnly = 1;
    571 }
    572 def A2_notp : HInst<
    573 (outs DoubleRegs:$Rdd32),
    574 (ins DoubleRegs:$Rss32),
    575 "$Rdd32 = not($Rss32)",
    576 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
    577 let Inst{13-5} = 0b000000100;
    578 let Inst{31-21} = 0b10000000100;
    579 }
    580 def A2_or : HInst<
    581 (outs IntRegs:$Rd32),
    582 (ins IntRegs:$Rs32, IntRegs:$Rt32),
    583 "$Rd32 = or($Rs32,$Rt32)",
    584 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
    585 let Inst{7-5} = 0b000;
    586 let Inst{13-13} = 0b0;
    587 let Inst{31-21} = 0b11110001001;
    588 let hasNewValue = 1;
    589 let opNewValue = 0;
    590 let CextOpcode = "A2_or";
    591 let InputType = "reg";
    592 let BaseOpcode = "A2_or";
    593 let isCommutable = 1;
    594 let isPredicable = 1;
    595 }
    596 def A2_orir : HInst<
    597 (outs IntRegs:$Rd32),
    598 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
    599 "$Rd32 = or($Rs32,#$Ii)",
    600 tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel {
    601 let Inst{31-22} = 0b0111011010;
    602 let hasNewValue = 1;
    603 let opNewValue = 0;
    604 let CextOpcode = "A2_or";
    605 let InputType = "imm";
    606 let isExtendable = 1;
    607 let opExtendable = 2;
    608 let isExtentSigned = 1;
    609 let opExtentBits = 10;
    610 let opExtentAlign = 0;
    611 }
    612 def A2_orp : HInst<
    613 (outs DoubleRegs:$Rdd32),
    614 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
    615 "$Rdd32 = or($Rss32,$Rtt32)",
    616 tc_540fdfbc, TypeALU64>, Enc_a56825 {
    617 let Inst{7-5} = 0b010;
    618 let Inst{13-13} = 0b0;
    619 let Inst{31-21} = 0b11010011111;
    620 let isCommutable = 1;
    621 }
    622 def A2_paddf : HInst<
    623 (outs IntRegs:$Rd32),
    624 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    625 "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
    626 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
    627 let Inst{7-7} = 0b1;
    628 let Inst{13-13} = 0b0;
    629 let Inst{31-21} = 0b11111011000;
    630 let isPredicated = 1;
    631 let isPredicatedFalse = 1;
    632 let hasNewValue = 1;
    633 let opNewValue = 0;
    634 let CextOpcode = "A2_add";
    635 let InputType = "reg";
    636 let BaseOpcode = "A2_add";
    637 }
    638 def A2_paddfnew : HInst<
    639 (outs IntRegs:$Rd32),
    640 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    641 "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
    642 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
    643 let Inst{7-7} = 0b1;
    644 let Inst{13-13} = 0b1;
    645 let Inst{31-21} = 0b11111011000;
    646 let isPredicated = 1;
    647 let isPredicatedFalse = 1;
    648 let hasNewValue = 1;
    649 let opNewValue = 0;
    650 let isPredicatedNew = 1;
    651 let CextOpcode = "A2_add";
    652 let InputType = "reg";
    653 let BaseOpcode = "A2_add";
    654 }
    655 def A2_paddif : HInst<
    656 (outs IntRegs:$Rd32),
    657 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
    658 "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
    659 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
    660 let Inst{13-13} = 0b0;
    661 let Inst{31-23} = 0b011101001;
    662 let isPredicated = 1;
    663 let isPredicatedFalse = 1;
    664 let hasNewValue = 1;
    665 let opNewValue = 0;
    666 let CextOpcode = "A2_add";
    667 let InputType = "imm";
    668 let BaseOpcode = "A2_addi";
    669 let isExtendable = 1;
    670 let opExtendable = 3;
    671 let isExtentSigned = 1;
    672 let opExtentBits = 8;
    673 let opExtentAlign = 0;
    674 }
    675 def A2_paddifnew : HInst<
    676 (outs IntRegs:$Rd32),
    677 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
    678 "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
    679 tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
    680 let Inst{13-13} = 0b1;
    681 let Inst{31-23} = 0b011101001;
    682 let isPredicated = 1;
    683 let isPredicatedFalse = 1;
    684 let hasNewValue = 1;
    685 let opNewValue = 0;
    686 let isPredicatedNew = 1;
    687 let CextOpcode = "A2_add";
    688 let InputType = "imm";
    689 let BaseOpcode = "A2_addi";
    690 let isExtendable = 1;
    691 let opExtendable = 3;
    692 let isExtentSigned = 1;
    693 let opExtentBits = 8;
    694 let opExtentAlign = 0;
    695 }
    696 def A2_paddit : HInst<
    697 (outs IntRegs:$Rd32),
    698 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
    699 "if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
    700 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
    701 let Inst{13-13} = 0b0;
    702 let Inst{31-23} = 0b011101000;
    703 let isPredicated = 1;
    704 let hasNewValue = 1;
    705 let opNewValue = 0;
    706 let CextOpcode = "A2_add";
    707 let InputType = "imm";
    708 let BaseOpcode = "A2_addi";
    709 let isExtendable = 1;
    710 let opExtendable = 3;
    711 let isExtentSigned = 1;
    712 let opExtentBits = 8;
    713 let opExtentAlign = 0;
    714 }
    715 def A2_padditnew : HInst<
    716 (outs IntRegs:$Rd32),
    717 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
    718 "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
    719 tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
    720 let Inst{13-13} = 0b1;
    721 let Inst{31-23} = 0b011101000;
    722 let isPredicated = 1;
    723 let hasNewValue = 1;
    724 let opNewValue = 0;
    725 let isPredicatedNew = 1;
    726 let CextOpcode = "A2_add";
    727 let InputType = "imm";
    728 let BaseOpcode = "A2_addi";
    729 let isExtendable = 1;
    730 let opExtendable = 3;
    731 let isExtentSigned = 1;
    732 let opExtentBits = 8;
    733 let opExtentAlign = 0;
    734 }
    735 def A2_paddt : HInst<
    736 (outs IntRegs:$Rd32),
    737 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    738 "if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
    739 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
    740 let Inst{7-7} = 0b0;
    741 let Inst{13-13} = 0b0;
    742 let Inst{31-21} = 0b11111011000;
    743 let isPredicated = 1;
    744 let hasNewValue = 1;
    745 let opNewValue = 0;
    746 let CextOpcode = "A2_add";
    747 let InputType = "reg";
    748 let BaseOpcode = "A2_add";
    749 }
    750 def A2_paddtnew : HInst<
    751 (outs IntRegs:$Rd32),
    752 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    753 "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
    754 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
    755 let Inst{7-7} = 0b0;
    756 let Inst{13-13} = 0b1;
    757 let Inst{31-21} = 0b11111011000;
    758 let isPredicated = 1;
    759 let hasNewValue = 1;
    760 let opNewValue = 0;
    761 let isPredicatedNew = 1;
    762 let CextOpcode = "A2_add";
    763 let InputType = "reg";
    764 let BaseOpcode = "A2_add";
    765 }
    766 def A2_pandf : HInst<
    767 (outs IntRegs:$Rd32),
    768 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    769 "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
    770 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    771 let Inst{7-7} = 0b1;
    772 let Inst{13-13} = 0b0;
    773 let Inst{31-21} = 0b11111001000;
    774 let isPredicated = 1;
    775 let isPredicatedFalse = 1;
    776 let hasNewValue = 1;
    777 let opNewValue = 0;
    778 let BaseOpcode = "A2_and";
    779 }
    780 def A2_pandfnew : HInst<
    781 (outs IntRegs:$Rd32),
    782 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    783 "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
    784 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    785 let Inst{7-7} = 0b1;
    786 let Inst{13-13} = 0b1;
    787 let Inst{31-21} = 0b11111001000;
    788 let isPredicated = 1;
    789 let isPredicatedFalse = 1;
    790 let hasNewValue = 1;
    791 let opNewValue = 0;
    792 let isPredicatedNew = 1;
    793 let BaseOpcode = "A2_and";
    794 }
    795 def A2_pandt : HInst<
    796 (outs IntRegs:$Rd32),
    797 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    798 "if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
    799 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    800 let Inst{7-7} = 0b0;
    801 let Inst{13-13} = 0b0;
    802 let Inst{31-21} = 0b11111001000;
    803 let isPredicated = 1;
    804 let hasNewValue = 1;
    805 let opNewValue = 0;
    806 let BaseOpcode = "A2_and";
    807 }
    808 def A2_pandtnew : HInst<
    809 (outs IntRegs:$Rd32),
    810 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    811 "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
    812 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    813 let Inst{7-7} = 0b0;
    814 let Inst{13-13} = 0b1;
    815 let Inst{31-21} = 0b11111001000;
    816 let isPredicated = 1;
    817 let hasNewValue = 1;
    818 let opNewValue = 0;
    819 let isPredicatedNew = 1;
    820 let BaseOpcode = "A2_and";
    821 }
    822 def A2_porf : HInst<
    823 (outs IntRegs:$Rd32),
    824 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    825 "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
    826 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    827 let Inst{7-7} = 0b1;
    828 let Inst{13-13} = 0b0;
    829 let Inst{31-21} = 0b11111001001;
    830 let isPredicated = 1;
    831 let isPredicatedFalse = 1;
    832 let hasNewValue = 1;
    833 let opNewValue = 0;
    834 let BaseOpcode = "A2_or";
    835 }
    836 def A2_porfnew : HInst<
    837 (outs IntRegs:$Rd32),
    838 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    839 "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
    840 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    841 let Inst{7-7} = 0b1;
    842 let Inst{13-13} = 0b1;
    843 let Inst{31-21} = 0b11111001001;
    844 let isPredicated = 1;
    845 let isPredicatedFalse = 1;
    846 let hasNewValue = 1;
    847 let opNewValue = 0;
    848 let isPredicatedNew = 1;
    849 let BaseOpcode = "A2_or";
    850 }
    851 def A2_port : HInst<
    852 (outs IntRegs:$Rd32),
    853 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    854 "if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
    855 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    856 let Inst{7-7} = 0b0;
    857 let Inst{13-13} = 0b0;
    858 let Inst{31-21} = 0b11111001001;
    859 let isPredicated = 1;
    860 let hasNewValue = 1;
    861 let opNewValue = 0;
    862 let BaseOpcode = "A2_or";
    863 }
    864 def A2_portnew : HInst<
    865 (outs IntRegs:$Rd32),
    866 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    867 "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
    868 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    869 let Inst{7-7} = 0b0;
    870 let Inst{13-13} = 0b1;
    871 let Inst{31-21} = 0b11111001001;
    872 let isPredicated = 1;
    873 let hasNewValue = 1;
    874 let opNewValue = 0;
    875 let isPredicatedNew = 1;
    876 let BaseOpcode = "A2_or";
    877 }
    878 def A2_psubf : HInst<
    879 (outs IntRegs:$Rd32),
    880 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
    881 "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
    882 tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
    883 let Inst{7-7} = 0b1;
    884 let Inst{13-13} = 0b0;
    885 let Inst{31-21} = 0b11111011001;
    886 let isPredicated = 1;
    887 let isPredicatedFalse = 1;
    888 let hasNewValue = 1;
    889 let opNewValue = 0;
    890 let BaseOpcode = "A2_sub";
    891 }
    892 def A2_psubfnew : HInst<
    893 (outs IntRegs:$Rd32),
    894 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
    895 "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
    896 tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
    897 let Inst{7-7} = 0b1;
    898 let Inst{13-13} = 0b1;
    899 let Inst{31-21} = 0b11111011001;
    900 let isPredicated = 1;
    901 let isPredicatedFalse = 1;
    902 let hasNewValue = 1;
    903 let opNewValue = 0;
    904 let isPredicatedNew = 1;
    905 let BaseOpcode = "A2_sub";
    906 }
    907 def A2_psubt : HInst<
    908 (outs IntRegs:$Rd32),
    909 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
    910 "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
    911 tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
    912 let Inst{7-7} = 0b0;
    913 let Inst{13-13} = 0b0;
    914 let Inst{31-21} = 0b11111011001;
    915 let isPredicated = 1;
    916 let hasNewValue = 1;
    917 let opNewValue = 0;
    918 let BaseOpcode = "A2_sub";
    919 }
    920 def A2_psubtnew : HInst<
    921 (outs IntRegs:$Rd32),
    922 (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
    923 "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
    924 tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
    925 let Inst{7-7} = 0b0;
    926 let Inst{13-13} = 0b1;
    927 let Inst{31-21} = 0b11111011001;
    928 let isPredicated = 1;
    929 let hasNewValue = 1;
    930 let opNewValue = 0;
    931 let isPredicatedNew = 1;
    932 let BaseOpcode = "A2_sub";
    933 }
    934 def A2_pxorf : HInst<
    935 (outs IntRegs:$Rd32),
    936 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    937 "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
    938 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    939 let Inst{7-7} = 0b1;
    940 let Inst{13-13} = 0b0;
    941 let Inst{31-21} = 0b11111001011;
    942 let isPredicated = 1;
    943 let isPredicatedFalse = 1;
    944 let hasNewValue = 1;
    945 let opNewValue = 0;
    946 let BaseOpcode = "A2_xor";
    947 }
    948 def A2_pxorfnew : HInst<
    949 (outs IntRegs:$Rd32),
    950 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    951 "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
    952 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    953 let Inst{7-7} = 0b1;
    954 let Inst{13-13} = 0b1;
    955 let Inst{31-21} = 0b11111001011;
    956 let isPredicated = 1;
    957 let isPredicatedFalse = 1;
    958 let hasNewValue = 1;
    959 let opNewValue = 0;
    960 let isPredicatedNew = 1;
    961 let BaseOpcode = "A2_xor";
    962 }
    963 def A2_pxort : HInst<
    964 (outs IntRegs:$Rd32),
    965 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    966 "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
    967 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    968 let Inst{7-7} = 0b0;
    969 let Inst{13-13} = 0b0;
    970 let Inst{31-21} = 0b11111001011;
    971 let isPredicated = 1;
    972 let hasNewValue = 1;
    973 let opNewValue = 0;
    974 let BaseOpcode = "A2_xor";
    975 }
    976 def A2_pxortnew : HInst<
    977 (outs IntRegs:$Rd32),
    978 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
    979 "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
    980 tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
    981 let Inst{7-7} = 0b0;
    982 let Inst{13-13} = 0b1;
    983 let Inst{31-21} = 0b11111001011;
    984 let isPredicated = 1;
    985 let hasNewValue = 1;
    986 let opNewValue = 0;
    987 let isPredicatedNew = 1;
    988 let BaseOpcode = "A2_xor";
    989 }
    990 def A2_roundsat : HInst<
    991 (outs IntRegs:$Rd32),
    992 (ins DoubleRegs:$Rss32),
    993 "$Rd32 = round($Rss32):sat",
    994 tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
    995 let Inst{13-5} = 0b000000001;
    996 let Inst{31-21} = 0b10001000110;
    997 let hasNewValue = 1;
    998 let opNewValue = 0;
    999 let prefersSlot3 = 1;
   1000 let Defs = [USR_OVF];
   1001 }
   1002 def A2_sat : HInst<
   1003 (outs IntRegs:$Rd32),
   1004 (ins DoubleRegs:$Rss32),
   1005 "$Rd32 = sat($Rss32)",
   1006 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   1007 let Inst{13-5} = 0b000000000;
   1008 let Inst{31-21} = 0b10001000110;
   1009 let hasNewValue = 1;
   1010 let opNewValue = 0;
   1011 let Defs = [USR_OVF];
   1012 }
   1013 def A2_satb : HInst<
   1014 (outs IntRegs:$Rd32),
   1015 (ins IntRegs:$Rs32),
   1016 "$Rd32 = satb($Rs32)",
   1017 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   1018 let Inst{13-5} = 0b000000111;
   1019 let Inst{31-21} = 0b10001100110;
   1020 let hasNewValue = 1;
   1021 let opNewValue = 0;
   1022 let Defs = [USR_OVF];
   1023 }
   1024 def A2_sath : HInst<
   1025 (outs IntRegs:$Rd32),
   1026 (ins IntRegs:$Rs32),
   1027 "$Rd32 = sath($Rs32)",
   1028 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   1029 let Inst{13-5} = 0b000000100;
   1030 let Inst{31-21} = 0b10001100110;
   1031 let hasNewValue = 1;
   1032 let opNewValue = 0;
   1033 let Defs = [USR_OVF];
   1034 }
   1035 def A2_satub : HInst<
   1036 (outs IntRegs:$Rd32),
   1037 (ins IntRegs:$Rs32),
   1038 "$Rd32 = satub($Rs32)",
   1039 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   1040 let Inst{13-5} = 0b000000110;
   1041 let Inst{31-21} = 0b10001100110;
   1042 let hasNewValue = 1;
   1043 let opNewValue = 0;
   1044 let Defs = [USR_OVF];
   1045 }
   1046 def A2_satuh : HInst<
   1047 (outs IntRegs:$Rd32),
   1048 (ins IntRegs:$Rs32),
   1049 "$Rd32 = satuh($Rs32)",
   1050 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   1051 let Inst{13-5} = 0b000000101;
   1052 let Inst{31-21} = 0b10001100110;
   1053 let hasNewValue = 1;
   1054 let opNewValue = 0;
   1055 let Defs = [USR_OVF];
   1056 }
   1057 def A2_sub : HInst<
   1058 (outs IntRegs:$Rd32),
   1059 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1060 "$Rd32 = sub($Rt32,$Rs32)",
   1061 tc_b9488031, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
   1062 let Inst{7-5} = 0b000;
   1063 let Inst{13-13} = 0b0;
   1064 let Inst{31-21} = 0b11110011001;
   1065 let hasNewValue = 1;
   1066 let opNewValue = 0;
   1067 let CextOpcode = "A2_sub";
   1068 let InputType = "reg";
   1069 let BaseOpcode = "A2_sub";
   1070 let isPredicable = 1;
   1071 }
   1072 def A2_subh_h16_hh : HInst<
   1073 (outs IntRegs:$Rd32),
   1074 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1075 "$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
   1076 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
   1077 let Inst{7-5} = 0b011;
   1078 let Inst{13-13} = 0b0;
   1079 let Inst{31-21} = 0b11010101011;
   1080 let hasNewValue = 1;
   1081 let opNewValue = 0;
   1082 let prefersSlot3 = 1;
   1083 }
   1084 def A2_subh_h16_hl : HInst<
   1085 (outs IntRegs:$Rd32),
   1086 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1087 "$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
   1088 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
   1089 let Inst{7-5} = 0b010;
   1090 let Inst{13-13} = 0b0;
   1091 let Inst{31-21} = 0b11010101011;
   1092 let hasNewValue = 1;
   1093 let opNewValue = 0;
   1094 let prefersSlot3 = 1;
   1095 }
   1096 def A2_subh_h16_lh : HInst<
   1097 (outs IntRegs:$Rd32),
   1098 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1099 "$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
   1100 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
   1101 let Inst{7-5} = 0b001;
   1102 let Inst{13-13} = 0b0;
   1103 let Inst{31-21} = 0b11010101011;
   1104 let hasNewValue = 1;
   1105 let opNewValue = 0;
   1106 let prefersSlot3 = 1;
   1107 }
   1108 def A2_subh_h16_ll : HInst<
   1109 (outs IntRegs:$Rd32),
   1110 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1111 "$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
   1112 tc_897d1a9d, TypeALU64>, Enc_bd6011 {
   1113 let Inst{7-5} = 0b000;
   1114 let Inst{13-13} = 0b0;
   1115 let Inst{31-21} = 0b11010101011;
   1116 let hasNewValue = 1;
   1117 let opNewValue = 0;
   1118 let prefersSlot3 = 1;
   1119 }
   1120 def A2_subh_h16_sat_hh : HInst<
   1121 (outs IntRegs:$Rd32),
   1122 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1123 "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
   1124 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1125 let Inst{7-5} = 0b111;
   1126 let Inst{13-13} = 0b0;
   1127 let Inst{31-21} = 0b11010101011;
   1128 let hasNewValue = 1;
   1129 let opNewValue = 0;
   1130 let prefersSlot3 = 1;
   1131 let Defs = [USR_OVF];
   1132 }
   1133 def A2_subh_h16_sat_hl : HInst<
   1134 (outs IntRegs:$Rd32),
   1135 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1136 "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
   1137 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1138 let Inst{7-5} = 0b110;
   1139 let Inst{13-13} = 0b0;
   1140 let Inst{31-21} = 0b11010101011;
   1141 let hasNewValue = 1;
   1142 let opNewValue = 0;
   1143 let prefersSlot3 = 1;
   1144 let Defs = [USR_OVF];
   1145 }
   1146 def A2_subh_h16_sat_lh : HInst<
   1147 (outs IntRegs:$Rd32),
   1148 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1149 "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
   1150 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1151 let Inst{7-5} = 0b101;
   1152 let Inst{13-13} = 0b0;
   1153 let Inst{31-21} = 0b11010101011;
   1154 let hasNewValue = 1;
   1155 let opNewValue = 0;
   1156 let prefersSlot3 = 1;
   1157 let Defs = [USR_OVF];
   1158 }
   1159 def A2_subh_h16_sat_ll : HInst<
   1160 (outs IntRegs:$Rd32),
   1161 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1162 "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
   1163 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1164 let Inst{7-5} = 0b100;
   1165 let Inst{13-13} = 0b0;
   1166 let Inst{31-21} = 0b11010101011;
   1167 let hasNewValue = 1;
   1168 let opNewValue = 0;
   1169 let prefersSlot3 = 1;
   1170 let Defs = [USR_OVF];
   1171 }
   1172 def A2_subh_l16_hl : HInst<
   1173 (outs IntRegs:$Rd32),
   1174 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1175 "$Rd32 = sub($Rt32.l,$Rs32.h)",
   1176 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
   1177 let Inst{7-5} = 0b010;
   1178 let Inst{13-13} = 0b0;
   1179 let Inst{31-21} = 0b11010101001;
   1180 let hasNewValue = 1;
   1181 let opNewValue = 0;
   1182 let prefersSlot3 = 1;
   1183 }
   1184 def A2_subh_l16_ll : HInst<
   1185 (outs IntRegs:$Rd32),
   1186 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1187 "$Rd32 = sub($Rt32.l,$Rs32.l)",
   1188 tc_1b9c9ee5, TypeALU64>, Enc_bd6011 {
   1189 let Inst{7-5} = 0b000;
   1190 let Inst{13-13} = 0b0;
   1191 let Inst{31-21} = 0b11010101001;
   1192 let hasNewValue = 1;
   1193 let opNewValue = 0;
   1194 let prefersSlot3 = 1;
   1195 }
   1196 def A2_subh_l16_sat_hl : HInst<
   1197 (outs IntRegs:$Rd32),
   1198 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1199 "$Rd32 = sub($Rt32.l,$Rs32.h):sat",
   1200 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1201 let Inst{7-5} = 0b110;
   1202 let Inst{13-13} = 0b0;
   1203 let Inst{31-21} = 0b11010101001;
   1204 let hasNewValue = 1;
   1205 let opNewValue = 0;
   1206 let prefersSlot3 = 1;
   1207 let Defs = [USR_OVF];
   1208 }
   1209 def A2_subh_l16_sat_ll : HInst<
   1210 (outs IntRegs:$Rd32),
   1211 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1212 "$Rd32 = sub($Rt32.l,$Rs32.l):sat",
   1213 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   1214 let Inst{7-5} = 0b100;
   1215 let Inst{13-13} = 0b0;
   1216 let Inst{31-21} = 0b11010101001;
   1217 let hasNewValue = 1;
   1218 let opNewValue = 0;
   1219 let prefersSlot3 = 1;
   1220 let Defs = [USR_OVF];
   1221 }
   1222 def A2_subp : HInst<
   1223 (outs DoubleRegs:$Rdd32),
   1224 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1225 "$Rdd32 = sub($Rtt32,$Rss32)",
   1226 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   1227 let Inst{7-5} = 0b111;
   1228 let Inst{13-13} = 0b0;
   1229 let Inst{31-21} = 0b11010011001;
   1230 }
   1231 def A2_subri : HInst<
   1232 (outs IntRegs:$Rd32),
   1233 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
   1234 "$Rd32 = sub(#$Ii,$Rs32)",
   1235 tc_b9488031, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
   1236 let Inst{31-22} = 0b0111011001;
   1237 let hasNewValue = 1;
   1238 let opNewValue = 0;
   1239 let CextOpcode = "A2_sub";
   1240 let InputType = "imm";
   1241 let isExtendable = 1;
   1242 let opExtendable = 1;
   1243 let isExtentSigned = 1;
   1244 let opExtentBits = 10;
   1245 let opExtentAlign = 0;
   1246 }
   1247 def A2_subsat : HInst<
   1248 (outs IntRegs:$Rd32),
   1249 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1250 "$Rd32 = sub($Rt32,$Rs32):sat",
   1251 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
   1252 let Inst{7-5} = 0b000;
   1253 let Inst{13-13} = 0b0;
   1254 let Inst{31-21} = 0b11110110110;
   1255 let hasNewValue = 1;
   1256 let opNewValue = 0;
   1257 let prefersSlot3 = 1;
   1258 let Defs = [USR_OVF];
   1259 let InputType = "reg";
   1260 }
   1261 def A2_svaddh : HInst<
   1262 (outs IntRegs:$Rd32),
   1263 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   1264 "$Rd32 = vaddh($Rs32,$Rt32)",
   1265 tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
   1266 let Inst{7-5} = 0b000;
   1267 let Inst{13-13} = 0b0;
   1268 let Inst{31-21} = 0b11110110000;
   1269 let hasNewValue = 1;
   1270 let opNewValue = 0;
   1271 let InputType = "reg";
   1272 let isCommutable = 1;
   1273 }
   1274 def A2_svaddhs : HInst<
   1275 (outs IntRegs:$Rd32),
   1276 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   1277 "$Rd32 = vaddh($Rs32,$Rt32):sat",
   1278 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
   1279 let Inst{7-5} = 0b000;
   1280 let Inst{13-13} = 0b0;
   1281 let Inst{31-21} = 0b11110110001;
   1282 let hasNewValue = 1;
   1283 let opNewValue = 0;
   1284 let prefersSlot3 = 1;
   1285 let Defs = [USR_OVF];
   1286 let InputType = "reg";
   1287 let isCommutable = 1;
   1288 }
   1289 def A2_svadduhs : HInst<
   1290 (outs IntRegs:$Rd32),
   1291 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   1292 "$Rd32 = vadduh($Rs32,$Rt32):sat",
   1293 tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be {
   1294 let Inst{7-5} = 0b000;
   1295 let Inst{13-13} = 0b0;
   1296 let Inst{31-21} = 0b11110110011;
   1297 let hasNewValue = 1;
   1298 let opNewValue = 0;
   1299 let prefersSlot3 = 1;
   1300 let Defs = [USR_OVF];
   1301 let InputType = "reg";
   1302 let isCommutable = 1;
   1303 }
   1304 def A2_svavgh : HInst<
   1305 (outs IntRegs:$Rd32),
   1306 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   1307 "$Rd32 = vavgh($Rs32,$Rt32)",
   1308 tc_b9488031, TypeALU32_3op>, Enc_5ab2be {
   1309 let Inst{7-5} = 0b000;
   1310 let Inst{13-13} = 0b0;
   1311 let Inst{31-21} = 0b11110111000;
   1312 let hasNewValue = 1;
   1313 let opNewValue = 0;
   1314 let InputType = "reg";
   1315 let isCommutable = 1;
   1316 }
   1317 def A2_svavghs : HInst<
   1318 (outs IntRegs:$Rd32),
   1319 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   1320 "$Rd32 = vavgh($Rs32,$Rt32):rnd",
   1321 tc_8fe6b782, TypeALU32_3op>, Enc_5ab2be {
   1322 let Inst{7-5} = 0b000;
   1323 let Inst{13-13} = 0b0;
   1324 let Inst{31-21} = 0b11110111001;
   1325 let hasNewValue = 1;
   1326 let opNewValue = 0;
   1327 let InputType = "reg";
   1328 let isCommutable = 1;
   1329 }
   1330 def A2_svnavgh : HInst<
   1331 (outs IntRegs:$Rd32),
   1332 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1333 "$Rd32 = vnavgh($Rt32,$Rs32)",
   1334 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
   1335 let Inst{7-5} = 0b000;
   1336 let Inst{13-13} = 0b0;
   1337 let Inst{31-21} = 0b11110111011;
   1338 let hasNewValue = 1;
   1339 let opNewValue = 0;
   1340 let InputType = "reg";
   1341 }
   1342 def A2_svsubh : HInst<
   1343 (outs IntRegs:$Rd32),
   1344 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1345 "$Rd32 = vsubh($Rt32,$Rs32)",
   1346 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
   1347 let Inst{7-5} = 0b000;
   1348 let Inst{13-13} = 0b0;
   1349 let Inst{31-21} = 0b11110110100;
   1350 let hasNewValue = 1;
   1351 let opNewValue = 0;
   1352 let InputType = "reg";
   1353 }
   1354 def A2_svsubhs : HInst<
   1355 (outs IntRegs:$Rd32),
   1356 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1357 "$Rd32 = vsubh($Rt32,$Rs32):sat",
   1358 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
   1359 let Inst{7-5} = 0b000;
   1360 let Inst{13-13} = 0b0;
   1361 let Inst{31-21} = 0b11110110101;
   1362 let hasNewValue = 1;
   1363 let opNewValue = 0;
   1364 let prefersSlot3 = 1;
   1365 let Defs = [USR_OVF];
   1366 let InputType = "reg";
   1367 }
   1368 def A2_svsubuhs : HInst<
   1369 (outs IntRegs:$Rd32),
   1370 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   1371 "$Rd32 = vsubuh($Rt32,$Rs32):sat",
   1372 tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 {
   1373 let Inst{7-5} = 0b000;
   1374 let Inst{13-13} = 0b0;
   1375 let Inst{31-21} = 0b11110110111;
   1376 let hasNewValue = 1;
   1377 let opNewValue = 0;
   1378 let prefersSlot3 = 1;
   1379 let Defs = [USR_OVF];
   1380 let InputType = "reg";
   1381 }
   1382 def A2_swiz : HInst<
   1383 (outs IntRegs:$Rd32),
   1384 (ins IntRegs:$Rs32),
   1385 "$Rd32 = swiz($Rs32)",
   1386 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   1387 let Inst{13-5} = 0b000000111;
   1388 let Inst{31-21} = 0b10001100100;
   1389 let hasNewValue = 1;
   1390 let opNewValue = 0;
   1391 }
   1392 def A2_sxtb : HInst<
   1393 (outs IntRegs:$Rd32),
   1394 (ins IntRegs:$Rs32),
   1395 "$Rd32 = sxtb($Rs32)",
   1396 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
   1397 let Inst{13-5} = 0b000000000;
   1398 let Inst{31-21} = 0b01110000101;
   1399 let hasNewValue = 1;
   1400 let opNewValue = 0;
   1401 let BaseOpcode = "A2_sxtb";
   1402 let isPredicable = 1;
   1403 }
   1404 def A2_sxth : HInst<
   1405 (outs IntRegs:$Rd32),
   1406 (ins IntRegs:$Rs32),
   1407 "$Rd32 = sxth($Rs32)",
   1408 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
   1409 let Inst{13-5} = 0b000000000;
   1410 let Inst{31-21} = 0b01110000111;
   1411 let hasNewValue = 1;
   1412 let opNewValue = 0;
   1413 let BaseOpcode = "A2_sxth";
   1414 let isPredicable = 1;
   1415 }
   1416 def A2_sxtw : HInst<
   1417 (outs DoubleRegs:$Rdd32),
   1418 (ins IntRegs:$Rs32),
   1419 "$Rdd32 = sxtw($Rs32)",
   1420 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   1421 let Inst{13-5} = 0b000000000;
   1422 let Inst{31-21} = 0b10000100010;
   1423 }
   1424 def A2_tfr : HInst<
   1425 (outs IntRegs:$Rd32),
   1426 (ins IntRegs:$Rs32),
   1427 "$Rd32 = $Rs32",
   1428 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
   1429 let Inst{13-5} = 0b000000000;
   1430 let Inst{31-21} = 0b01110000011;
   1431 let hasNewValue = 1;
   1432 let opNewValue = 0;
   1433 let InputType = "reg";
   1434 let BaseOpcode = "A2_tfr";
   1435 let isPredicable = 1;
   1436 }
   1437 def A2_tfrcrr : HInst<
   1438 (outs IntRegs:$Rd32),
   1439 (ins CtrRegs:$Cs32),
   1440 "$Rd32 = $Cs32",
   1441 tc_29175780, TypeCR>, Enc_0cb018 {
   1442 let Inst{13-5} = 0b000000000;
   1443 let Inst{31-21} = 0b01101010000;
   1444 let hasNewValue = 1;
   1445 let opNewValue = 0;
   1446 }
   1447 def A2_tfrf : HInst<
   1448 (outs IntRegs:$Rd32),
   1449 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   1450 "if (!$Pu4) $Rd32 = $Rs32",
   1451 tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
   1452 let isPredicated = 1;
   1453 let isPredicatedFalse = 1;
   1454 let hasNewValue = 1;
   1455 let opNewValue = 0;
   1456 let CextOpcode = "A2_tfr";
   1457 let InputType = "reg";
   1458 let BaseOpcode = "A2_tfr";
   1459 let isPseudo = 1;
   1460 let isCodeGenOnly = 1;
   1461 }
   1462 def A2_tfrfnew : HInst<
   1463 (outs IntRegs:$Rd32),
   1464 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   1465 "if (!$Pu4.new) $Rd32 = $Rs32",
   1466 tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
   1467 let isPredicated = 1;
   1468 let isPredicatedFalse = 1;
   1469 let hasNewValue = 1;
   1470 let opNewValue = 0;
   1471 let isPredicatedNew = 1;
   1472 let CextOpcode = "A2_tfr";
   1473 let InputType = "reg";
   1474 let BaseOpcode = "A2_tfr";
   1475 let isPseudo = 1;
   1476 let isCodeGenOnly = 1;
   1477 }
   1478 def A2_tfrih : HInst<
   1479 (outs IntRegs:$Rx32),
   1480 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
   1481 "$Rx32.h = #$Ii",
   1482 tc_b9488031, TypeALU32_2op>, Enc_51436c {
   1483 let Inst{21-21} = 0b1;
   1484 let Inst{31-24} = 0b01110010;
   1485 let hasNewValue = 1;
   1486 let opNewValue = 0;
   1487 let Constraints = "$Rx32 = $Rx32in";
   1488 }
   1489 def A2_tfril : HInst<
   1490 (outs IntRegs:$Rx32),
   1491 (ins IntRegs:$Rx32in, u16_0Imm:$Ii),
   1492 "$Rx32.l = #$Ii",
   1493 tc_b9488031, TypeALU32_2op>, Enc_51436c {
   1494 let Inst{21-21} = 0b1;
   1495 let Inst{31-24} = 0b01110001;
   1496 let hasNewValue = 1;
   1497 let opNewValue = 0;
   1498 let Constraints = "$Rx32 = $Rx32in";
   1499 }
   1500 def A2_tfrp : HInst<
   1501 (outs DoubleRegs:$Rdd32),
   1502 (ins DoubleRegs:$Rss32),
   1503 "$Rdd32 = $Rss32",
   1504 tc_b9488031, TypeALU32_2op>, PredNewRel {
   1505 let BaseOpcode = "A2_tfrp";
   1506 let isPredicable = 1;
   1507 let isPseudo = 1;
   1508 }
   1509 def A2_tfrpf : HInst<
   1510 (outs DoubleRegs:$Rdd32),
   1511 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
   1512 "if (!$Pu4) $Rdd32 = $Rss32",
   1513 tc_b9488031, TypeALU32_2op>, PredNewRel {
   1514 let isPredicated = 1;
   1515 let isPredicatedFalse = 1;
   1516 let BaseOpcode = "A2_tfrp";
   1517 let isPseudo = 1;
   1518 }
   1519 def A2_tfrpfnew : HInst<
   1520 (outs DoubleRegs:$Rdd32),
   1521 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
   1522 "if (!$Pu4.new) $Rdd32 = $Rss32",
   1523 tc_5f6847a1, TypeALU32_2op>, PredNewRel {
   1524 let isPredicated = 1;
   1525 let isPredicatedFalse = 1;
   1526 let isPredicatedNew = 1;
   1527 let BaseOpcode = "A2_tfrp";
   1528 let isPseudo = 1;
   1529 }
   1530 def A2_tfrpi : HInst<
   1531 (outs DoubleRegs:$Rdd32),
   1532 (ins s8_0Imm:$Ii),
   1533 "$Rdd32 = #$Ii",
   1534 tc_b9488031, TypeALU64> {
   1535 let isReMaterializable = 1;
   1536 let isAsCheapAsAMove = 1;
   1537 let isMoveImm = 1;
   1538 let isPseudo = 1;
   1539 }
   1540 def A2_tfrpt : HInst<
   1541 (outs DoubleRegs:$Rdd32),
   1542 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
   1543 "if ($Pu4) $Rdd32 = $Rss32",
   1544 tc_b9488031, TypeALU32_2op>, PredNewRel {
   1545 let isPredicated = 1;
   1546 let BaseOpcode = "A2_tfrp";
   1547 let isPseudo = 1;
   1548 }
   1549 def A2_tfrptnew : HInst<
   1550 (outs DoubleRegs:$Rdd32),
   1551 (ins PredRegs:$Pu4, DoubleRegs:$Rss32),
   1552 "if ($Pu4.new) $Rdd32 = $Rss32",
   1553 tc_5f6847a1, TypeALU32_2op>, PredNewRel {
   1554 let isPredicated = 1;
   1555 let isPredicatedNew = 1;
   1556 let BaseOpcode = "A2_tfrp";
   1557 let isPseudo = 1;
   1558 }
   1559 def A2_tfrrcr : HInst<
   1560 (outs CtrRegs:$Cd32),
   1561 (ins IntRegs:$Rs32),
   1562 "$Cd32 = $Rs32",
   1563 tc_a21dc435, TypeCR>, Enc_bd811a {
   1564 let Inst{13-5} = 0b000000000;
   1565 let Inst{31-21} = 0b01100010001;
   1566 let hasNewValue = 1;
   1567 let opNewValue = 0;
   1568 }
   1569 def A2_tfrsi : HInst<
   1570 (outs IntRegs:$Rd32),
   1571 (ins s32_0Imm:$Ii),
   1572 "$Rd32 = #$Ii",
   1573 tc_68cb12ce, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
   1574 let Inst{21-21} = 0b0;
   1575 let Inst{31-24} = 0b01111000;
   1576 let hasNewValue = 1;
   1577 let opNewValue = 0;
   1578 let CextOpcode = "A2_tfr";
   1579 let InputType = "imm";
   1580 let BaseOpcode = "A2_tfrsi";
   1581 let isPredicable = 1;
   1582 let isReMaterializable = 1;
   1583 let isAsCheapAsAMove = 1;
   1584 let isMoveImm = 1;
   1585 let isExtendable = 1;
   1586 let opExtendable = 1;
   1587 let isExtentSigned = 1;
   1588 let opExtentBits = 16;
   1589 let opExtentAlign = 0;
   1590 }
   1591 def A2_tfrt : HInst<
   1592 (outs IntRegs:$Rd32),
   1593 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   1594 "if ($Pu4) $Rd32 = $Rs32",
   1595 tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel {
   1596 let isPredicated = 1;
   1597 let hasNewValue = 1;
   1598 let opNewValue = 0;
   1599 let CextOpcode = "A2_tfr";
   1600 let InputType = "reg";
   1601 let BaseOpcode = "A2_tfr";
   1602 let isPseudo = 1;
   1603 let isCodeGenOnly = 1;
   1604 }
   1605 def A2_tfrtnew : HInst<
   1606 (outs IntRegs:$Rd32),
   1607 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   1608 "if ($Pu4.new) $Rd32 = $Rs32",
   1609 tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel {
   1610 let isPredicated = 1;
   1611 let hasNewValue = 1;
   1612 let opNewValue = 0;
   1613 let isPredicatedNew = 1;
   1614 let CextOpcode = "A2_tfr";
   1615 let InputType = "reg";
   1616 let BaseOpcode = "A2_tfr";
   1617 let isPseudo = 1;
   1618 let isCodeGenOnly = 1;
   1619 }
   1620 def A2_vabsh : HInst<
   1621 (outs DoubleRegs:$Rdd32),
   1622 (ins DoubleRegs:$Rss32),
   1623 "$Rdd32 = vabsh($Rss32)",
   1624 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
   1625 let Inst{13-5} = 0b000000100;
   1626 let Inst{31-21} = 0b10000000010;
   1627 let prefersSlot3 = 1;
   1628 }
   1629 def A2_vabshsat : HInst<
   1630 (outs DoubleRegs:$Rdd32),
   1631 (ins DoubleRegs:$Rss32),
   1632 "$Rdd32 = vabsh($Rss32):sat",
   1633 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
   1634 let Inst{13-5} = 0b000000101;
   1635 let Inst{31-21} = 0b10000000010;
   1636 let prefersSlot3 = 1;
   1637 let Defs = [USR_OVF];
   1638 }
   1639 def A2_vabsw : HInst<
   1640 (outs DoubleRegs:$Rdd32),
   1641 (ins DoubleRegs:$Rss32),
   1642 "$Rdd32 = vabsw($Rss32)",
   1643 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
   1644 let Inst{13-5} = 0b000000110;
   1645 let Inst{31-21} = 0b10000000010;
   1646 let prefersSlot3 = 1;
   1647 }
   1648 def A2_vabswsat : HInst<
   1649 (outs DoubleRegs:$Rdd32),
   1650 (ins DoubleRegs:$Rss32),
   1651 "$Rdd32 = vabsw($Rss32):sat",
   1652 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
   1653 let Inst{13-5} = 0b000000111;
   1654 let Inst{31-21} = 0b10000000010;
   1655 let prefersSlot3 = 1;
   1656 let Defs = [USR_OVF];
   1657 }
   1658 def A2_vaddb_map : HInst<
   1659 (outs DoubleRegs:$Rdd32),
   1660 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1661 "$Rdd32 = vaddb($Rss32,$Rtt32)",
   1662 tc_540fdfbc, TypeMAPPING> {
   1663 let isPseudo = 1;
   1664 let isCodeGenOnly = 1;
   1665 }
   1666 def A2_vaddh : HInst<
   1667 (outs DoubleRegs:$Rdd32),
   1668 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1669 "$Rdd32 = vaddh($Rss32,$Rtt32)",
   1670 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1671 let Inst{7-5} = 0b010;
   1672 let Inst{13-13} = 0b0;
   1673 let Inst{31-21} = 0b11010011000;
   1674 }
   1675 def A2_vaddhs : HInst<
   1676 (outs DoubleRegs:$Rdd32),
   1677 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1678 "$Rdd32 = vaddh($Rss32,$Rtt32):sat",
   1679 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
   1680 let Inst{7-5} = 0b011;
   1681 let Inst{13-13} = 0b0;
   1682 let Inst{31-21} = 0b11010011000;
   1683 let prefersSlot3 = 1;
   1684 let Defs = [USR_OVF];
   1685 }
   1686 def A2_vaddub : HInst<
   1687 (outs DoubleRegs:$Rdd32),
   1688 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1689 "$Rdd32 = vaddub($Rss32,$Rtt32)",
   1690 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1691 let Inst{7-5} = 0b000;
   1692 let Inst{13-13} = 0b0;
   1693 let Inst{31-21} = 0b11010011000;
   1694 }
   1695 def A2_vaddubs : HInst<
   1696 (outs DoubleRegs:$Rdd32),
   1697 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1698 "$Rdd32 = vaddub($Rss32,$Rtt32):sat",
   1699 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
   1700 let Inst{7-5} = 0b001;
   1701 let Inst{13-13} = 0b0;
   1702 let Inst{31-21} = 0b11010011000;
   1703 let prefersSlot3 = 1;
   1704 let Defs = [USR_OVF];
   1705 }
   1706 def A2_vadduhs : HInst<
   1707 (outs DoubleRegs:$Rdd32),
   1708 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1709 "$Rdd32 = vadduh($Rss32,$Rtt32):sat",
   1710 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
   1711 let Inst{7-5} = 0b100;
   1712 let Inst{13-13} = 0b0;
   1713 let Inst{31-21} = 0b11010011000;
   1714 let prefersSlot3 = 1;
   1715 let Defs = [USR_OVF];
   1716 }
   1717 def A2_vaddw : HInst<
   1718 (outs DoubleRegs:$Rdd32),
   1719 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1720 "$Rdd32 = vaddw($Rss32,$Rtt32)",
   1721 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1722 let Inst{7-5} = 0b101;
   1723 let Inst{13-13} = 0b0;
   1724 let Inst{31-21} = 0b11010011000;
   1725 }
   1726 def A2_vaddws : HInst<
   1727 (outs DoubleRegs:$Rdd32),
   1728 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1729 "$Rdd32 = vaddw($Rss32,$Rtt32):sat",
   1730 tc_b44c6e2a, TypeALU64>, Enc_a56825 {
   1731 let Inst{7-5} = 0b110;
   1732 let Inst{13-13} = 0b0;
   1733 let Inst{31-21} = 0b11010011000;
   1734 let prefersSlot3 = 1;
   1735 let Defs = [USR_OVF];
   1736 }
   1737 def A2_vavgh : HInst<
   1738 (outs DoubleRegs:$Rdd32),
   1739 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1740 "$Rdd32 = vavgh($Rss32,$Rtt32)",
   1741 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1742 let Inst{7-5} = 0b010;
   1743 let Inst{13-13} = 0b0;
   1744 let Inst{31-21} = 0b11010011010;
   1745 }
   1746 def A2_vavghcr : HInst<
   1747 (outs DoubleRegs:$Rdd32),
   1748 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1749 "$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
   1750 tc_2b6f77c6, TypeALU64>, Enc_a56825 {
   1751 let Inst{7-5} = 0b100;
   1752 let Inst{13-13} = 0b0;
   1753 let Inst{31-21} = 0b11010011010;
   1754 let prefersSlot3 = 1;
   1755 }
   1756 def A2_vavghr : HInst<
   1757 (outs DoubleRegs:$Rdd32),
   1758 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1759 "$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
   1760 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
   1761 let Inst{7-5} = 0b011;
   1762 let Inst{13-13} = 0b0;
   1763 let Inst{31-21} = 0b11010011010;
   1764 }
   1765 def A2_vavgub : HInst<
   1766 (outs DoubleRegs:$Rdd32),
   1767 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1768 "$Rdd32 = vavgub($Rss32,$Rtt32)",
   1769 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1770 let Inst{7-5} = 0b000;
   1771 let Inst{13-13} = 0b0;
   1772 let Inst{31-21} = 0b11010011010;
   1773 }
   1774 def A2_vavgubr : HInst<
   1775 (outs DoubleRegs:$Rdd32),
   1776 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1777 "$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
   1778 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
   1779 let Inst{7-5} = 0b001;
   1780 let Inst{13-13} = 0b0;
   1781 let Inst{31-21} = 0b11010011010;
   1782 }
   1783 def A2_vavguh : HInst<
   1784 (outs DoubleRegs:$Rdd32),
   1785 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1786 "$Rdd32 = vavguh($Rss32,$Rtt32)",
   1787 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1788 let Inst{7-5} = 0b101;
   1789 let Inst{13-13} = 0b0;
   1790 let Inst{31-21} = 0b11010011010;
   1791 }
   1792 def A2_vavguhr : HInst<
   1793 (outs DoubleRegs:$Rdd32),
   1794 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1795 "$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
   1796 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
   1797 let Inst{7-5} = 0b110;
   1798 let Inst{13-13} = 0b0;
   1799 let Inst{31-21} = 0b11010011010;
   1800 }
   1801 def A2_vavguw : HInst<
   1802 (outs DoubleRegs:$Rdd32),
   1803 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1804 "$Rdd32 = vavguw($Rss32,$Rtt32)",
   1805 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1806 let Inst{7-5} = 0b011;
   1807 let Inst{13-13} = 0b0;
   1808 let Inst{31-21} = 0b11010011011;
   1809 }
   1810 def A2_vavguwr : HInst<
   1811 (outs DoubleRegs:$Rdd32),
   1812 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1813 "$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
   1814 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
   1815 let Inst{7-5} = 0b100;
   1816 let Inst{13-13} = 0b0;
   1817 let Inst{31-21} = 0b11010011011;
   1818 }
   1819 def A2_vavgw : HInst<
   1820 (outs DoubleRegs:$Rdd32),
   1821 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1822 "$Rdd32 = vavgw($Rss32,$Rtt32)",
   1823 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   1824 let Inst{7-5} = 0b000;
   1825 let Inst{13-13} = 0b0;
   1826 let Inst{31-21} = 0b11010011011;
   1827 }
   1828 def A2_vavgwcr : HInst<
   1829 (outs DoubleRegs:$Rdd32),
   1830 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1831 "$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
   1832 tc_2b6f77c6, TypeALU64>, Enc_a56825 {
   1833 let Inst{7-5} = 0b010;
   1834 let Inst{13-13} = 0b0;
   1835 let Inst{31-21} = 0b11010011011;
   1836 let prefersSlot3 = 1;
   1837 }
   1838 def A2_vavgwr : HInst<
   1839 (outs DoubleRegs:$Rdd32),
   1840 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1841 "$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
   1842 tc_dbdffe3d, TypeALU64>, Enc_a56825 {
   1843 let Inst{7-5} = 0b001;
   1844 let Inst{13-13} = 0b0;
   1845 let Inst{31-21} = 0b11010011011;
   1846 }
   1847 def A2_vcmpbeq : HInst<
   1848 (outs PredRegs:$Pd4),
   1849 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1850 "$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
   1851 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1852 let Inst{7-2} = 0b110000;
   1853 let Inst{13-13} = 0b0;
   1854 let Inst{31-21} = 0b11010010000;
   1855 }
   1856 def A2_vcmpbgtu : HInst<
   1857 (outs PredRegs:$Pd4),
   1858 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1859 "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
   1860 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1861 let Inst{7-2} = 0b111000;
   1862 let Inst{13-13} = 0b0;
   1863 let Inst{31-21} = 0b11010010000;
   1864 }
   1865 def A2_vcmpheq : HInst<
   1866 (outs PredRegs:$Pd4),
   1867 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1868 "$Pd4 = vcmph.eq($Rss32,$Rtt32)",
   1869 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1870 let Inst{7-2} = 0b011000;
   1871 let Inst{13-13} = 0b0;
   1872 let Inst{31-21} = 0b11010010000;
   1873 }
   1874 def A2_vcmphgt : HInst<
   1875 (outs PredRegs:$Pd4),
   1876 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1877 "$Pd4 = vcmph.gt($Rss32,$Rtt32)",
   1878 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1879 let Inst{7-2} = 0b100000;
   1880 let Inst{13-13} = 0b0;
   1881 let Inst{31-21} = 0b11010010000;
   1882 }
   1883 def A2_vcmphgtu : HInst<
   1884 (outs PredRegs:$Pd4),
   1885 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1886 "$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
   1887 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1888 let Inst{7-2} = 0b101000;
   1889 let Inst{13-13} = 0b0;
   1890 let Inst{31-21} = 0b11010010000;
   1891 }
   1892 def A2_vcmpweq : HInst<
   1893 (outs PredRegs:$Pd4),
   1894 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1895 "$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
   1896 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1897 let Inst{7-2} = 0b000000;
   1898 let Inst{13-13} = 0b0;
   1899 let Inst{31-21} = 0b11010010000;
   1900 }
   1901 def A2_vcmpwgt : HInst<
   1902 (outs PredRegs:$Pd4),
   1903 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1904 "$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
   1905 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1906 let Inst{7-2} = 0b001000;
   1907 let Inst{13-13} = 0b0;
   1908 let Inst{31-21} = 0b11010010000;
   1909 }
   1910 def A2_vcmpwgtu : HInst<
   1911 (outs PredRegs:$Pd4),
   1912 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   1913 "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
   1914 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   1915 let Inst{7-2} = 0b010000;
   1916 let Inst{13-13} = 0b0;
   1917 let Inst{31-21} = 0b11010010000;
   1918 }
   1919 def A2_vconj : HInst<
   1920 (outs DoubleRegs:$Rdd32),
   1921 (ins DoubleRegs:$Rss32),
   1922 "$Rdd32 = vconj($Rss32):sat",
   1923 tc_c2f7d806, TypeS_2op>, Enc_b9c5fb {
   1924 let Inst{13-5} = 0b000000111;
   1925 let Inst{31-21} = 0b10000000100;
   1926 let prefersSlot3 = 1;
   1927 let Defs = [USR_OVF];
   1928 }
   1929 def A2_vmaxb : HInst<
   1930 (outs DoubleRegs:$Rdd32),
   1931 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1932 "$Rdd32 = vmaxb($Rtt32,$Rss32)",
   1933 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1934 let Inst{7-5} = 0b110;
   1935 let Inst{13-13} = 0b0;
   1936 let Inst{31-21} = 0b11010011110;
   1937 let prefersSlot3 = 1;
   1938 }
   1939 def A2_vmaxh : HInst<
   1940 (outs DoubleRegs:$Rdd32),
   1941 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1942 "$Rdd32 = vmaxh($Rtt32,$Rss32)",
   1943 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1944 let Inst{7-5} = 0b001;
   1945 let Inst{13-13} = 0b0;
   1946 let Inst{31-21} = 0b11010011110;
   1947 let prefersSlot3 = 1;
   1948 }
   1949 def A2_vmaxub : HInst<
   1950 (outs DoubleRegs:$Rdd32),
   1951 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1952 "$Rdd32 = vmaxub($Rtt32,$Rss32)",
   1953 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1954 let Inst{7-5} = 0b000;
   1955 let Inst{13-13} = 0b0;
   1956 let Inst{31-21} = 0b11010011110;
   1957 let prefersSlot3 = 1;
   1958 }
   1959 def A2_vmaxuh : HInst<
   1960 (outs DoubleRegs:$Rdd32),
   1961 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1962 "$Rdd32 = vmaxuh($Rtt32,$Rss32)",
   1963 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1964 let Inst{7-5} = 0b010;
   1965 let Inst{13-13} = 0b0;
   1966 let Inst{31-21} = 0b11010011110;
   1967 let prefersSlot3 = 1;
   1968 }
   1969 def A2_vmaxuw : HInst<
   1970 (outs DoubleRegs:$Rdd32),
   1971 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1972 "$Rdd32 = vmaxuw($Rtt32,$Rss32)",
   1973 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1974 let Inst{7-5} = 0b101;
   1975 let Inst{13-13} = 0b0;
   1976 let Inst{31-21} = 0b11010011101;
   1977 let prefersSlot3 = 1;
   1978 }
   1979 def A2_vmaxw : HInst<
   1980 (outs DoubleRegs:$Rdd32),
   1981 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1982 "$Rdd32 = vmaxw($Rtt32,$Rss32)",
   1983 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1984 let Inst{7-5} = 0b011;
   1985 let Inst{13-13} = 0b0;
   1986 let Inst{31-21} = 0b11010011110;
   1987 let prefersSlot3 = 1;
   1988 }
   1989 def A2_vminb : HInst<
   1990 (outs DoubleRegs:$Rdd32),
   1991 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   1992 "$Rdd32 = vminb($Rtt32,$Rss32)",
   1993 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   1994 let Inst{7-5} = 0b111;
   1995 let Inst{13-13} = 0b0;
   1996 let Inst{31-21} = 0b11010011110;
   1997 let prefersSlot3 = 1;
   1998 }
   1999 def A2_vminh : HInst<
   2000 (outs DoubleRegs:$Rdd32),
   2001 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2002 "$Rdd32 = vminh($Rtt32,$Rss32)",
   2003 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2004 let Inst{7-5} = 0b001;
   2005 let Inst{13-13} = 0b0;
   2006 let Inst{31-21} = 0b11010011101;
   2007 let prefersSlot3 = 1;
   2008 }
   2009 def A2_vminub : HInst<
   2010 (outs DoubleRegs:$Rdd32),
   2011 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2012 "$Rdd32 = vminub($Rtt32,$Rss32)",
   2013 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2014 let Inst{7-5} = 0b000;
   2015 let Inst{13-13} = 0b0;
   2016 let Inst{31-21} = 0b11010011101;
   2017 let prefersSlot3 = 1;
   2018 }
   2019 def A2_vminuh : HInst<
   2020 (outs DoubleRegs:$Rdd32),
   2021 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2022 "$Rdd32 = vminuh($Rtt32,$Rss32)",
   2023 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2024 let Inst{7-5} = 0b010;
   2025 let Inst{13-13} = 0b0;
   2026 let Inst{31-21} = 0b11010011101;
   2027 let prefersSlot3 = 1;
   2028 }
   2029 def A2_vminuw : HInst<
   2030 (outs DoubleRegs:$Rdd32),
   2031 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2032 "$Rdd32 = vminuw($Rtt32,$Rss32)",
   2033 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2034 let Inst{7-5} = 0b100;
   2035 let Inst{13-13} = 0b0;
   2036 let Inst{31-21} = 0b11010011101;
   2037 let prefersSlot3 = 1;
   2038 }
   2039 def A2_vminw : HInst<
   2040 (outs DoubleRegs:$Rdd32),
   2041 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2042 "$Rdd32 = vminw($Rtt32,$Rss32)",
   2043 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2044 let Inst{7-5} = 0b011;
   2045 let Inst{13-13} = 0b0;
   2046 let Inst{31-21} = 0b11010011101;
   2047 let prefersSlot3 = 1;
   2048 }
   2049 def A2_vnavgh : HInst<
   2050 (outs DoubleRegs:$Rdd32),
   2051 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2052 "$Rdd32 = vnavgh($Rtt32,$Rss32)",
   2053 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2054 let Inst{7-5} = 0b000;
   2055 let Inst{13-13} = 0b0;
   2056 let Inst{31-21} = 0b11010011100;
   2057 }
   2058 def A2_vnavghcr : HInst<
   2059 (outs DoubleRegs:$Rdd32),
   2060 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2061 "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
   2062 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
   2063 let Inst{7-5} = 0b010;
   2064 let Inst{13-13} = 0b0;
   2065 let Inst{31-21} = 0b11010011100;
   2066 let prefersSlot3 = 1;
   2067 let Defs = [USR_OVF];
   2068 }
   2069 def A2_vnavghr : HInst<
   2070 (outs DoubleRegs:$Rdd32),
   2071 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2072 "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
   2073 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
   2074 let Inst{7-5} = 0b001;
   2075 let Inst{13-13} = 0b0;
   2076 let Inst{31-21} = 0b11010011100;
   2077 let prefersSlot3 = 1;
   2078 let Defs = [USR_OVF];
   2079 }
   2080 def A2_vnavgw : HInst<
   2081 (outs DoubleRegs:$Rdd32),
   2082 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2083 "$Rdd32 = vnavgw($Rtt32,$Rss32)",
   2084 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2085 let Inst{7-5} = 0b011;
   2086 let Inst{13-13} = 0b0;
   2087 let Inst{31-21} = 0b11010011100;
   2088 }
   2089 def A2_vnavgwcr : HInst<
   2090 (outs DoubleRegs:$Rdd32),
   2091 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2092 "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
   2093 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
   2094 let Inst{7-5} = 0b110;
   2095 let Inst{13-13} = 0b0;
   2096 let Inst{31-21} = 0b11010011100;
   2097 let prefersSlot3 = 1;
   2098 let Defs = [USR_OVF];
   2099 }
   2100 def A2_vnavgwr : HInst<
   2101 (outs DoubleRegs:$Rdd32),
   2102 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2103 "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
   2104 tc_2b6f77c6, TypeALU64>, Enc_ea23e4 {
   2105 let Inst{7-5} = 0b100;
   2106 let Inst{13-13} = 0b0;
   2107 let Inst{31-21} = 0b11010011100;
   2108 let prefersSlot3 = 1;
   2109 let Defs = [USR_OVF];
   2110 }
   2111 def A2_vraddub : HInst<
   2112 (outs DoubleRegs:$Rdd32),
   2113 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2114 "$Rdd32 = vraddub($Rss32,$Rtt32)",
   2115 tc_8fd5f294, TypeM>, Enc_a56825 {
   2116 let Inst{7-5} = 0b001;
   2117 let Inst{13-13} = 0b0;
   2118 let Inst{31-21} = 0b11101000010;
   2119 let prefersSlot3 = 1;
   2120 }
   2121 def A2_vraddub_acc : HInst<
   2122 (outs DoubleRegs:$Rxx32),
   2123 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2124 "$Rxx32 += vraddub($Rss32,$Rtt32)",
   2125 tc_e913dc32, TypeM>, Enc_88c16c {
   2126 let Inst{7-5} = 0b001;
   2127 let Inst{13-13} = 0b0;
   2128 let Inst{31-21} = 0b11101010010;
   2129 let prefersSlot3 = 1;
   2130 let Constraints = "$Rxx32 = $Rxx32in";
   2131 }
   2132 def A2_vrsadub : HInst<
   2133 (outs DoubleRegs:$Rdd32),
   2134 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2135 "$Rdd32 = vrsadub($Rss32,$Rtt32)",
   2136 tc_8fd5f294, TypeM>, Enc_a56825 {
   2137 let Inst{7-5} = 0b010;
   2138 let Inst{13-13} = 0b0;
   2139 let Inst{31-21} = 0b11101000010;
   2140 let prefersSlot3 = 1;
   2141 }
   2142 def A2_vrsadub_acc : HInst<
   2143 (outs DoubleRegs:$Rxx32),
   2144 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2145 "$Rxx32 += vrsadub($Rss32,$Rtt32)",
   2146 tc_e913dc32, TypeM>, Enc_88c16c {
   2147 let Inst{7-5} = 0b010;
   2148 let Inst{13-13} = 0b0;
   2149 let Inst{31-21} = 0b11101010010;
   2150 let prefersSlot3 = 1;
   2151 let Constraints = "$Rxx32 = $Rxx32in";
   2152 }
   2153 def A2_vsubb_map : HInst<
   2154 (outs DoubleRegs:$Rdd32),
   2155 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2156 "$Rdd32 = vsubb($Rss32,$Rtt32)",
   2157 tc_540fdfbc, TypeMAPPING> {
   2158 let isPseudo = 1;
   2159 let isCodeGenOnly = 1;
   2160 }
   2161 def A2_vsubh : HInst<
   2162 (outs DoubleRegs:$Rdd32),
   2163 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2164 "$Rdd32 = vsubh($Rtt32,$Rss32)",
   2165 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2166 let Inst{7-5} = 0b010;
   2167 let Inst{13-13} = 0b0;
   2168 let Inst{31-21} = 0b11010011001;
   2169 }
   2170 def A2_vsubhs : HInst<
   2171 (outs DoubleRegs:$Rdd32),
   2172 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2173 "$Rdd32 = vsubh($Rtt32,$Rss32):sat",
   2174 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2175 let Inst{7-5} = 0b011;
   2176 let Inst{13-13} = 0b0;
   2177 let Inst{31-21} = 0b11010011001;
   2178 let prefersSlot3 = 1;
   2179 let Defs = [USR_OVF];
   2180 }
   2181 def A2_vsubub : HInst<
   2182 (outs DoubleRegs:$Rdd32),
   2183 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2184 "$Rdd32 = vsubub($Rtt32,$Rss32)",
   2185 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2186 let Inst{7-5} = 0b000;
   2187 let Inst{13-13} = 0b0;
   2188 let Inst{31-21} = 0b11010011001;
   2189 }
   2190 def A2_vsububs : HInst<
   2191 (outs DoubleRegs:$Rdd32),
   2192 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2193 "$Rdd32 = vsubub($Rtt32,$Rss32):sat",
   2194 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2195 let Inst{7-5} = 0b001;
   2196 let Inst{13-13} = 0b0;
   2197 let Inst{31-21} = 0b11010011001;
   2198 let prefersSlot3 = 1;
   2199 let Defs = [USR_OVF];
   2200 }
   2201 def A2_vsubuhs : HInst<
   2202 (outs DoubleRegs:$Rdd32),
   2203 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2204 "$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
   2205 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2206 let Inst{7-5} = 0b100;
   2207 let Inst{13-13} = 0b0;
   2208 let Inst{31-21} = 0b11010011001;
   2209 let prefersSlot3 = 1;
   2210 let Defs = [USR_OVF];
   2211 }
   2212 def A2_vsubw : HInst<
   2213 (outs DoubleRegs:$Rdd32),
   2214 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2215 "$Rdd32 = vsubw($Rtt32,$Rss32)",
   2216 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2217 let Inst{7-5} = 0b101;
   2218 let Inst{13-13} = 0b0;
   2219 let Inst{31-21} = 0b11010011001;
   2220 }
   2221 def A2_vsubws : HInst<
   2222 (outs DoubleRegs:$Rdd32),
   2223 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2224 "$Rdd32 = vsubw($Rtt32,$Rss32):sat",
   2225 tc_b44c6e2a, TypeALU64>, Enc_ea23e4 {
   2226 let Inst{7-5} = 0b110;
   2227 let Inst{13-13} = 0b0;
   2228 let Inst{31-21} = 0b11010011001;
   2229 let prefersSlot3 = 1;
   2230 let Defs = [USR_OVF];
   2231 }
   2232 def A2_xor : HInst<
   2233 (outs IntRegs:$Rd32),
   2234 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2235 "$Rd32 = xor($Rs32,$Rt32)",
   2236 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
   2237 let Inst{7-5} = 0b000;
   2238 let Inst{13-13} = 0b0;
   2239 let Inst{31-21} = 0b11110001011;
   2240 let hasNewValue = 1;
   2241 let opNewValue = 0;
   2242 let InputType = "reg";
   2243 let BaseOpcode = "A2_xor";
   2244 let isCommutable = 1;
   2245 let isPredicable = 1;
   2246 }
   2247 def A2_xorp : HInst<
   2248 (outs DoubleRegs:$Rdd32),
   2249 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2250 "$Rdd32 = xor($Rss32,$Rtt32)",
   2251 tc_540fdfbc, TypeALU64>, Enc_a56825 {
   2252 let Inst{7-5} = 0b100;
   2253 let Inst{13-13} = 0b0;
   2254 let Inst{31-21} = 0b11010011111;
   2255 let isCommutable = 1;
   2256 }
   2257 def A2_zxtb : HInst<
   2258 (outs IntRegs:$Rd32),
   2259 (ins IntRegs:$Rs32),
   2260 "$Rd32 = zxtb($Rs32)",
   2261 tc_b9488031, TypeALU32_2op>, PredNewRel {
   2262 let hasNewValue = 1;
   2263 let opNewValue = 0;
   2264 let BaseOpcode = "A2_zxtb";
   2265 let isPredicable = 1;
   2266 let isPseudo = 1;
   2267 let isCodeGenOnly = 1;
   2268 }
   2269 def A2_zxth : HInst<
   2270 (outs IntRegs:$Rd32),
   2271 (ins IntRegs:$Rs32),
   2272 "$Rd32 = zxth($Rs32)",
   2273 tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel {
   2274 let Inst{13-5} = 0b000000000;
   2275 let Inst{31-21} = 0b01110000110;
   2276 let hasNewValue = 1;
   2277 let opNewValue = 0;
   2278 let BaseOpcode = "A2_zxth";
   2279 let isPredicable = 1;
   2280 }
   2281 def A4_addp_c : HInst<
   2282 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
   2283 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
   2284 "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
   2285 tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
   2286 let Inst{7-7} = 0b0;
   2287 let Inst{13-13} = 0b0;
   2288 let Inst{31-21} = 0b11000010110;
   2289 let isPredicateLate = 1;
   2290 let Constraints = "$Px4 = $Px4in";
   2291 }
   2292 def A4_andn : HInst<
   2293 (outs IntRegs:$Rd32),
   2294 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   2295 "$Rd32 = and($Rt32,~$Rs32)",
   2296 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
   2297 let Inst{7-5} = 0b000;
   2298 let Inst{13-13} = 0b0;
   2299 let Inst{31-21} = 0b11110001100;
   2300 let hasNewValue = 1;
   2301 let opNewValue = 0;
   2302 let InputType = "reg";
   2303 }
   2304 def A4_andnp : HInst<
   2305 (outs DoubleRegs:$Rdd32),
   2306 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2307 "$Rdd32 = and($Rtt32,~$Rss32)",
   2308 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2309 let Inst{7-5} = 0b001;
   2310 let Inst{13-13} = 0b0;
   2311 let Inst{31-21} = 0b11010011111;
   2312 }
   2313 def A4_bitsplit : HInst<
   2314 (outs DoubleRegs:$Rdd32),
   2315 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2316 "$Rdd32 = bitsplit($Rs32,$Rt32)",
   2317 tc_1b9c9ee5, TypeALU64>, Enc_be32a5 {
   2318 let Inst{7-5} = 0b000;
   2319 let Inst{13-13} = 0b0;
   2320 let Inst{31-21} = 0b11010100001;
   2321 let prefersSlot3 = 1;
   2322 }
   2323 def A4_bitspliti : HInst<
   2324 (outs DoubleRegs:$Rdd32),
   2325 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   2326 "$Rdd32 = bitsplit($Rs32,#$Ii)",
   2327 tc_1b9c9ee5, TypeS_2op>, Enc_311abd {
   2328 let Inst{7-5} = 0b100;
   2329 let Inst{13-13} = 0b0;
   2330 let Inst{31-21} = 0b10001000110;
   2331 let prefersSlot3 = 1;
   2332 }
   2333 def A4_boundscheck : HInst<
   2334 (outs PredRegs:$Pd4),
   2335 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   2336 "$Pd4 = boundscheck($Rs32,$Rtt32)",
   2337 tc_1e856f58, TypeALU64> {
   2338 let isPseudo = 1;
   2339 }
   2340 def A4_boundscheck_hi : HInst<
   2341 (outs PredRegs:$Pd4),
   2342 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2343 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
   2344 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   2345 let Inst{7-2} = 0b101000;
   2346 let Inst{13-13} = 0b1;
   2347 let Inst{31-21} = 0b11010010000;
   2348 }
   2349 def A4_boundscheck_lo : HInst<
   2350 (outs PredRegs:$Pd4),
   2351 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   2352 "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
   2353 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   2354 let Inst{7-2} = 0b100000;
   2355 let Inst{13-13} = 0b1;
   2356 let Inst{31-21} = 0b11010010000;
   2357 }
   2358 def A4_cmpbeq : HInst<
   2359 (outs PredRegs:$Pd4),
   2360 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2361 "$Pd4 = cmpb.eq($Rs32,$Rt32)",
   2362 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2363 let Inst{7-2} = 0b110000;
   2364 let Inst{13-13} = 0b0;
   2365 let Inst{31-21} = 0b11000111110;
   2366 let CextOpcode = "A4_cmpbeq";
   2367 let InputType = "reg";
   2368 let isCommutable = 1;
   2369 let isCompare = 1;
   2370 }
   2371 def A4_cmpbeqi : HInst<
   2372 (outs PredRegs:$Pd4),
   2373 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
   2374 "$Pd4 = cmpb.eq($Rs32,#$Ii)",
   2375 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
   2376 let Inst{4-2} = 0b000;
   2377 let Inst{13-13} = 0b0;
   2378 let Inst{31-21} = 0b11011101000;
   2379 let CextOpcode = "A4_cmpbeq";
   2380 let InputType = "imm";
   2381 let isCommutable = 1;
   2382 let isCompare = 1;
   2383 }
   2384 def A4_cmpbgt : HInst<
   2385 (outs PredRegs:$Pd4),
   2386 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2387 "$Pd4 = cmpb.gt($Rs32,$Rt32)",
   2388 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2389 let Inst{7-2} = 0b010000;
   2390 let Inst{13-13} = 0b0;
   2391 let Inst{31-21} = 0b11000111110;
   2392 let CextOpcode = "A4_cmpbgt";
   2393 let InputType = "reg";
   2394 let isCompare = 1;
   2395 }
   2396 def A4_cmpbgti : HInst<
   2397 (outs PredRegs:$Pd4),
   2398 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
   2399 "$Pd4 = cmpb.gt($Rs32,#$Ii)",
   2400 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
   2401 let Inst{4-2} = 0b000;
   2402 let Inst{13-13} = 0b0;
   2403 let Inst{31-21} = 0b11011101001;
   2404 let CextOpcode = "A4_cmpbgt";
   2405 let InputType = "imm";
   2406 let isCompare = 1;
   2407 }
   2408 def A4_cmpbgtu : HInst<
   2409 (outs PredRegs:$Pd4),
   2410 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2411 "$Pd4 = cmpb.gtu($Rs32,$Rt32)",
   2412 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2413 let Inst{7-2} = 0b111000;
   2414 let Inst{13-13} = 0b0;
   2415 let Inst{31-21} = 0b11000111110;
   2416 let CextOpcode = "A4_cmpbgtu";
   2417 let InputType = "reg";
   2418 let isCompare = 1;
   2419 }
   2420 def A4_cmpbgtui : HInst<
   2421 (outs PredRegs:$Pd4),
   2422 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
   2423 "$Pd4 = cmpb.gtu($Rs32,#$Ii)",
   2424 tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
   2425 let Inst{4-2} = 0b000;
   2426 let Inst{13-12} = 0b00;
   2427 let Inst{31-21} = 0b11011101010;
   2428 let CextOpcode = "A4_cmpbgtu";
   2429 let InputType = "imm";
   2430 let isCompare = 1;
   2431 let isExtendable = 1;
   2432 let opExtendable = 2;
   2433 let isExtentSigned = 0;
   2434 let opExtentBits = 7;
   2435 let opExtentAlign = 0;
   2436 }
   2437 def A4_cmpheq : HInst<
   2438 (outs PredRegs:$Pd4),
   2439 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2440 "$Pd4 = cmph.eq($Rs32,$Rt32)",
   2441 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2442 let Inst{7-2} = 0b011000;
   2443 let Inst{13-13} = 0b0;
   2444 let Inst{31-21} = 0b11000111110;
   2445 let CextOpcode = "A4_cmpheq";
   2446 let InputType = "reg";
   2447 let isCommutable = 1;
   2448 let isCompare = 1;
   2449 }
   2450 def A4_cmpheqi : HInst<
   2451 (outs PredRegs:$Pd4),
   2452 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   2453 "$Pd4 = cmph.eq($Rs32,#$Ii)",
   2454 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
   2455 let Inst{4-2} = 0b010;
   2456 let Inst{13-13} = 0b0;
   2457 let Inst{31-21} = 0b11011101000;
   2458 let CextOpcode = "A4_cmpheq";
   2459 let InputType = "imm";
   2460 let isCommutable = 1;
   2461 let isCompare = 1;
   2462 let isExtendable = 1;
   2463 let opExtendable = 2;
   2464 let isExtentSigned = 1;
   2465 let opExtentBits = 8;
   2466 let opExtentAlign = 0;
   2467 }
   2468 def A4_cmphgt : HInst<
   2469 (outs PredRegs:$Pd4),
   2470 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2471 "$Pd4 = cmph.gt($Rs32,$Rt32)",
   2472 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2473 let Inst{7-2} = 0b100000;
   2474 let Inst{13-13} = 0b0;
   2475 let Inst{31-21} = 0b11000111110;
   2476 let CextOpcode = "A4_cmphgt";
   2477 let InputType = "reg";
   2478 let isCompare = 1;
   2479 }
   2480 def A4_cmphgti : HInst<
   2481 (outs PredRegs:$Pd4),
   2482 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   2483 "$Pd4 = cmph.gt($Rs32,#$Ii)",
   2484 tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel {
   2485 let Inst{4-2} = 0b010;
   2486 let Inst{13-13} = 0b0;
   2487 let Inst{31-21} = 0b11011101001;
   2488 let CextOpcode = "A4_cmphgt";
   2489 let InputType = "imm";
   2490 let isCompare = 1;
   2491 let isExtendable = 1;
   2492 let opExtendable = 2;
   2493 let isExtentSigned = 1;
   2494 let opExtentBits = 8;
   2495 let opExtentAlign = 0;
   2496 }
   2497 def A4_cmphgtu : HInst<
   2498 (outs PredRegs:$Pd4),
   2499 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2500 "$Pd4 = cmph.gtu($Rs32,$Rt32)",
   2501 tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel {
   2502 let Inst{7-2} = 0b101000;
   2503 let Inst{13-13} = 0b0;
   2504 let Inst{31-21} = 0b11000111110;
   2505 let CextOpcode = "A4_cmphgtu";
   2506 let InputType = "reg";
   2507 let isCompare = 1;
   2508 }
   2509 def A4_cmphgtui : HInst<
   2510 (outs PredRegs:$Pd4),
   2511 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
   2512 "$Pd4 = cmph.gtu($Rs32,#$Ii)",
   2513 tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel {
   2514 let Inst{4-2} = 0b010;
   2515 let Inst{13-12} = 0b00;
   2516 let Inst{31-21} = 0b11011101010;
   2517 let CextOpcode = "A4_cmphgtu";
   2518 let InputType = "imm";
   2519 let isCompare = 1;
   2520 let isExtendable = 1;
   2521 let opExtendable = 2;
   2522 let isExtentSigned = 0;
   2523 let opExtentBits = 7;
   2524 let opExtentAlign = 0;
   2525 }
   2526 def A4_combineii : HInst<
   2527 (outs DoubleRegs:$Rdd32),
   2528 (ins s8_0Imm:$Ii, u32_0Imm:$II),
   2529 "$Rdd32 = combine(#$Ii,#$II)",
   2530 tc_b9488031, TypeALU32_2op>, Enc_f0cca7 {
   2531 let Inst{31-21} = 0b01111100100;
   2532 let isExtendable = 1;
   2533 let opExtendable = 2;
   2534 let isExtentSigned = 0;
   2535 let opExtentBits = 6;
   2536 let opExtentAlign = 0;
   2537 }
   2538 def A4_combineir : HInst<
   2539 (outs DoubleRegs:$Rdd32),
   2540 (ins s32_0Imm:$Ii, IntRegs:$Rs32),
   2541 "$Rdd32 = combine(#$Ii,$Rs32)",
   2542 tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
   2543 let Inst{13-13} = 0b1;
   2544 let Inst{31-21} = 0b01110011001;
   2545 let isExtendable = 1;
   2546 let opExtendable = 1;
   2547 let isExtentSigned = 1;
   2548 let opExtentBits = 8;
   2549 let opExtentAlign = 0;
   2550 }
   2551 def A4_combineri : HInst<
   2552 (outs DoubleRegs:$Rdd32),
   2553 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   2554 "$Rdd32 = combine($Rs32,#$Ii)",
   2555 tc_b9488031, TypeALU32_2op>, Enc_9cdba7 {
   2556 let Inst{13-13} = 0b1;
   2557 let Inst{31-21} = 0b01110011000;
   2558 let isExtendable = 1;
   2559 let opExtendable = 2;
   2560 let isExtentSigned = 1;
   2561 let opExtentBits = 8;
   2562 let opExtentAlign = 0;
   2563 }
   2564 def A4_cround_ri : HInst<
   2565 (outs IntRegs:$Rd32),
   2566 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   2567 "$Rd32 = cround($Rs32,#$Ii)",
   2568 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
   2569 let Inst{7-5} = 0b000;
   2570 let Inst{13-13} = 0b0;
   2571 let Inst{31-21} = 0b10001100111;
   2572 let hasNewValue = 1;
   2573 let opNewValue = 0;
   2574 let prefersSlot3 = 1;
   2575 }
   2576 def A4_cround_rr : HInst<
   2577 (outs IntRegs:$Rd32),
   2578 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2579 "$Rd32 = cround($Rs32,$Rt32)",
   2580 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
   2581 let Inst{7-5} = 0b000;
   2582 let Inst{13-13} = 0b0;
   2583 let Inst{31-21} = 0b11000110110;
   2584 let hasNewValue = 1;
   2585 let opNewValue = 0;
   2586 let prefersSlot3 = 1;
   2587 }
   2588 def A4_ext : HInst<
   2589 (outs),
   2590 (ins u26_6Imm:$Ii),
   2591 "immext(#$Ii)",
   2592 tc_452f85af, TypeEXTENDER>, Enc_2b518f {
   2593 let Inst{31-28} = 0b0000;
   2594 }
   2595 def A4_modwrapu : HInst<
   2596 (outs IntRegs:$Rd32),
   2597 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2598 "$Rd32 = modwrap($Rs32,$Rt32)",
   2599 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
   2600 let Inst{7-5} = 0b111;
   2601 let Inst{13-13} = 0b0;
   2602 let Inst{31-21} = 0b11010011111;
   2603 let hasNewValue = 1;
   2604 let opNewValue = 0;
   2605 let prefersSlot3 = 1;
   2606 }
   2607 def A4_orn : HInst<
   2608 (outs IntRegs:$Rd32),
   2609 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   2610 "$Rd32 = or($Rt32,~$Rs32)",
   2611 tc_b9488031, TypeALU32_3op>, Enc_bd6011 {
   2612 let Inst{7-5} = 0b000;
   2613 let Inst{13-13} = 0b0;
   2614 let Inst{31-21} = 0b11110001101;
   2615 let hasNewValue = 1;
   2616 let opNewValue = 0;
   2617 let InputType = "reg";
   2618 }
   2619 def A4_ornp : HInst<
   2620 (outs DoubleRegs:$Rdd32),
   2621 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   2622 "$Rdd32 = or($Rtt32,~$Rss32)",
   2623 tc_540fdfbc, TypeALU64>, Enc_ea23e4 {
   2624 let Inst{7-5} = 0b011;
   2625 let Inst{13-13} = 0b0;
   2626 let Inst{31-21} = 0b11010011111;
   2627 }
   2628 def A4_paslhf : HInst<
   2629 (outs IntRegs:$Rd32),
   2630 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2631 "if (!$Pu4) $Rd32 = aslh($Rs32)",
   2632 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2633 let Inst{7-5} = 0b000;
   2634 let Inst{13-10} = 0b1010;
   2635 let Inst{31-21} = 0b01110000000;
   2636 let isPredicated = 1;
   2637 let isPredicatedFalse = 1;
   2638 let hasNewValue = 1;
   2639 let opNewValue = 0;
   2640 let BaseOpcode = "A2_aslh";
   2641 }
   2642 def A4_paslhfnew : HInst<
   2643 (outs IntRegs:$Rd32),
   2644 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2645 "if (!$Pu4.new) $Rd32 = aslh($Rs32)",
   2646 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2647 let Inst{7-5} = 0b000;
   2648 let Inst{13-10} = 0b1011;
   2649 let Inst{31-21} = 0b01110000000;
   2650 let isPredicated = 1;
   2651 let isPredicatedFalse = 1;
   2652 let hasNewValue = 1;
   2653 let opNewValue = 0;
   2654 let isPredicatedNew = 1;
   2655 let BaseOpcode = "A2_aslh";
   2656 }
   2657 def A4_paslht : HInst<
   2658 (outs IntRegs:$Rd32),
   2659 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2660 "if ($Pu4) $Rd32 = aslh($Rs32)",
   2661 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2662 let Inst{7-5} = 0b000;
   2663 let Inst{13-10} = 0b1000;
   2664 let Inst{31-21} = 0b01110000000;
   2665 let isPredicated = 1;
   2666 let hasNewValue = 1;
   2667 let opNewValue = 0;
   2668 let BaseOpcode = "A2_aslh";
   2669 }
   2670 def A4_paslhtnew : HInst<
   2671 (outs IntRegs:$Rd32),
   2672 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2673 "if ($Pu4.new) $Rd32 = aslh($Rs32)",
   2674 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2675 let Inst{7-5} = 0b000;
   2676 let Inst{13-10} = 0b1001;
   2677 let Inst{31-21} = 0b01110000000;
   2678 let isPredicated = 1;
   2679 let hasNewValue = 1;
   2680 let opNewValue = 0;
   2681 let isPredicatedNew = 1;
   2682 let BaseOpcode = "A2_aslh";
   2683 }
   2684 def A4_pasrhf : HInst<
   2685 (outs IntRegs:$Rd32),
   2686 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2687 "if (!$Pu4) $Rd32 = asrh($Rs32)",
   2688 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2689 let Inst{7-5} = 0b000;
   2690 let Inst{13-10} = 0b1010;
   2691 let Inst{31-21} = 0b01110000001;
   2692 let isPredicated = 1;
   2693 let isPredicatedFalse = 1;
   2694 let hasNewValue = 1;
   2695 let opNewValue = 0;
   2696 let BaseOpcode = "A2_asrh";
   2697 }
   2698 def A4_pasrhfnew : HInst<
   2699 (outs IntRegs:$Rd32),
   2700 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2701 "if (!$Pu4.new) $Rd32 = asrh($Rs32)",
   2702 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2703 let Inst{7-5} = 0b000;
   2704 let Inst{13-10} = 0b1011;
   2705 let Inst{31-21} = 0b01110000001;
   2706 let isPredicated = 1;
   2707 let isPredicatedFalse = 1;
   2708 let hasNewValue = 1;
   2709 let opNewValue = 0;
   2710 let isPredicatedNew = 1;
   2711 let BaseOpcode = "A2_asrh";
   2712 }
   2713 def A4_pasrht : HInst<
   2714 (outs IntRegs:$Rd32),
   2715 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2716 "if ($Pu4) $Rd32 = asrh($Rs32)",
   2717 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2718 let Inst{7-5} = 0b000;
   2719 let Inst{13-10} = 0b1000;
   2720 let Inst{31-21} = 0b01110000001;
   2721 let isPredicated = 1;
   2722 let hasNewValue = 1;
   2723 let opNewValue = 0;
   2724 let BaseOpcode = "A2_asrh";
   2725 }
   2726 def A4_pasrhtnew : HInst<
   2727 (outs IntRegs:$Rd32),
   2728 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2729 "if ($Pu4.new) $Rd32 = asrh($Rs32)",
   2730 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2731 let Inst{7-5} = 0b000;
   2732 let Inst{13-10} = 0b1001;
   2733 let Inst{31-21} = 0b01110000001;
   2734 let isPredicated = 1;
   2735 let hasNewValue = 1;
   2736 let opNewValue = 0;
   2737 let isPredicatedNew = 1;
   2738 let BaseOpcode = "A2_asrh";
   2739 }
   2740 def A4_psxtbf : HInst<
   2741 (outs IntRegs:$Rd32),
   2742 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2743 "if (!$Pu4) $Rd32 = sxtb($Rs32)",
   2744 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2745 let Inst{7-5} = 0b000;
   2746 let Inst{13-10} = 0b1010;
   2747 let Inst{31-21} = 0b01110000101;
   2748 let isPredicated = 1;
   2749 let isPredicatedFalse = 1;
   2750 let hasNewValue = 1;
   2751 let opNewValue = 0;
   2752 let BaseOpcode = "A2_sxtb";
   2753 }
   2754 def A4_psxtbfnew : HInst<
   2755 (outs IntRegs:$Rd32),
   2756 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2757 "if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
   2758 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2759 let Inst{7-5} = 0b000;
   2760 let Inst{13-10} = 0b1011;
   2761 let Inst{31-21} = 0b01110000101;
   2762 let isPredicated = 1;
   2763 let isPredicatedFalse = 1;
   2764 let hasNewValue = 1;
   2765 let opNewValue = 0;
   2766 let isPredicatedNew = 1;
   2767 let BaseOpcode = "A2_sxtb";
   2768 }
   2769 def A4_psxtbt : HInst<
   2770 (outs IntRegs:$Rd32),
   2771 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2772 "if ($Pu4) $Rd32 = sxtb($Rs32)",
   2773 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2774 let Inst{7-5} = 0b000;
   2775 let Inst{13-10} = 0b1000;
   2776 let Inst{31-21} = 0b01110000101;
   2777 let isPredicated = 1;
   2778 let hasNewValue = 1;
   2779 let opNewValue = 0;
   2780 let BaseOpcode = "A2_sxtb";
   2781 }
   2782 def A4_psxtbtnew : HInst<
   2783 (outs IntRegs:$Rd32),
   2784 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2785 "if ($Pu4.new) $Rd32 = sxtb($Rs32)",
   2786 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2787 let Inst{7-5} = 0b000;
   2788 let Inst{13-10} = 0b1001;
   2789 let Inst{31-21} = 0b01110000101;
   2790 let isPredicated = 1;
   2791 let hasNewValue = 1;
   2792 let opNewValue = 0;
   2793 let isPredicatedNew = 1;
   2794 let BaseOpcode = "A2_sxtb";
   2795 }
   2796 def A4_psxthf : HInst<
   2797 (outs IntRegs:$Rd32),
   2798 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2799 "if (!$Pu4) $Rd32 = sxth($Rs32)",
   2800 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2801 let Inst{7-5} = 0b000;
   2802 let Inst{13-10} = 0b1010;
   2803 let Inst{31-21} = 0b01110000111;
   2804 let isPredicated = 1;
   2805 let isPredicatedFalse = 1;
   2806 let hasNewValue = 1;
   2807 let opNewValue = 0;
   2808 let BaseOpcode = "A2_sxth";
   2809 }
   2810 def A4_psxthfnew : HInst<
   2811 (outs IntRegs:$Rd32),
   2812 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2813 "if (!$Pu4.new) $Rd32 = sxth($Rs32)",
   2814 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2815 let Inst{7-5} = 0b000;
   2816 let Inst{13-10} = 0b1011;
   2817 let Inst{31-21} = 0b01110000111;
   2818 let isPredicated = 1;
   2819 let isPredicatedFalse = 1;
   2820 let hasNewValue = 1;
   2821 let opNewValue = 0;
   2822 let isPredicatedNew = 1;
   2823 let BaseOpcode = "A2_sxth";
   2824 }
   2825 def A4_psxtht : HInst<
   2826 (outs IntRegs:$Rd32),
   2827 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2828 "if ($Pu4) $Rd32 = sxth($Rs32)",
   2829 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2830 let Inst{7-5} = 0b000;
   2831 let Inst{13-10} = 0b1000;
   2832 let Inst{31-21} = 0b01110000111;
   2833 let isPredicated = 1;
   2834 let hasNewValue = 1;
   2835 let opNewValue = 0;
   2836 let BaseOpcode = "A2_sxth";
   2837 }
   2838 def A4_psxthtnew : HInst<
   2839 (outs IntRegs:$Rd32),
   2840 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2841 "if ($Pu4.new) $Rd32 = sxth($Rs32)",
   2842 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2843 let Inst{7-5} = 0b000;
   2844 let Inst{13-10} = 0b1001;
   2845 let Inst{31-21} = 0b01110000111;
   2846 let isPredicated = 1;
   2847 let hasNewValue = 1;
   2848 let opNewValue = 0;
   2849 let isPredicatedNew = 1;
   2850 let BaseOpcode = "A2_sxth";
   2851 }
   2852 def A4_pzxtbf : HInst<
   2853 (outs IntRegs:$Rd32),
   2854 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2855 "if (!$Pu4) $Rd32 = zxtb($Rs32)",
   2856 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2857 let Inst{7-5} = 0b000;
   2858 let Inst{13-10} = 0b1010;
   2859 let Inst{31-21} = 0b01110000100;
   2860 let isPredicated = 1;
   2861 let isPredicatedFalse = 1;
   2862 let hasNewValue = 1;
   2863 let opNewValue = 0;
   2864 let BaseOpcode = "A2_zxtb";
   2865 }
   2866 def A4_pzxtbfnew : HInst<
   2867 (outs IntRegs:$Rd32),
   2868 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2869 "if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
   2870 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2871 let Inst{7-5} = 0b000;
   2872 let Inst{13-10} = 0b1011;
   2873 let Inst{31-21} = 0b01110000100;
   2874 let isPredicated = 1;
   2875 let isPredicatedFalse = 1;
   2876 let hasNewValue = 1;
   2877 let opNewValue = 0;
   2878 let isPredicatedNew = 1;
   2879 let BaseOpcode = "A2_zxtb";
   2880 }
   2881 def A4_pzxtbt : HInst<
   2882 (outs IntRegs:$Rd32),
   2883 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2884 "if ($Pu4) $Rd32 = zxtb($Rs32)",
   2885 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2886 let Inst{7-5} = 0b000;
   2887 let Inst{13-10} = 0b1000;
   2888 let Inst{31-21} = 0b01110000100;
   2889 let isPredicated = 1;
   2890 let hasNewValue = 1;
   2891 let opNewValue = 0;
   2892 let BaseOpcode = "A2_zxtb";
   2893 }
   2894 def A4_pzxtbtnew : HInst<
   2895 (outs IntRegs:$Rd32),
   2896 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2897 "if ($Pu4.new) $Rd32 = zxtb($Rs32)",
   2898 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2899 let Inst{7-5} = 0b000;
   2900 let Inst{13-10} = 0b1001;
   2901 let Inst{31-21} = 0b01110000100;
   2902 let isPredicated = 1;
   2903 let hasNewValue = 1;
   2904 let opNewValue = 0;
   2905 let isPredicatedNew = 1;
   2906 let BaseOpcode = "A2_zxtb";
   2907 }
   2908 def A4_pzxthf : HInst<
   2909 (outs IntRegs:$Rd32),
   2910 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2911 "if (!$Pu4) $Rd32 = zxth($Rs32)",
   2912 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2913 let Inst{7-5} = 0b000;
   2914 let Inst{13-10} = 0b1010;
   2915 let Inst{31-21} = 0b01110000110;
   2916 let isPredicated = 1;
   2917 let isPredicatedFalse = 1;
   2918 let hasNewValue = 1;
   2919 let opNewValue = 0;
   2920 let BaseOpcode = "A2_zxth";
   2921 }
   2922 def A4_pzxthfnew : HInst<
   2923 (outs IntRegs:$Rd32),
   2924 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2925 "if (!$Pu4.new) $Rd32 = zxth($Rs32)",
   2926 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2927 let Inst{7-5} = 0b000;
   2928 let Inst{13-10} = 0b1011;
   2929 let Inst{31-21} = 0b01110000110;
   2930 let isPredicated = 1;
   2931 let isPredicatedFalse = 1;
   2932 let hasNewValue = 1;
   2933 let opNewValue = 0;
   2934 let isPredicatedNew = 1;
   2935 let BaseOpcode = "A2_zxth";
   2936 }
   2937 def A4_pzxtht : HInst<
   2938 (outs IntRegs:$Rd32),
   2939 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2940 "if ($Pu4) $Rd32 = zxth($Rs32)",
   2941 tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2942 let Inst{7-5} = 0b000;
   2943 let Inst{13-10} = 0b1000;
   2944 let Inst{31-21} = 0b01110000110;
   2945 let isPredicated = 1;
   2946 let hasNewValue = 1;
   2947 let opNewValue = 0;
   2948 let BaseOpcode = "A2_zxth";
   2949 }
   2950 def A4_pzxthtnew : HInst<
   2951 (outs IntRegs:$Rd32),
   2952 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   2953 "if ($Pu4.new) $Rd32 = zxth($Rs32)",
   2954 tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel {
   2955 let Inst{7-5} = 0b000;
   2956 let Inst{13-10} = 0b1001;
   2957 let Inst{31-21} = 0b01110000110;
   2958 let isPredicated = 1;
   2959 let hasNewValue = 1;
   2960 let opNewValue = 0;
   2961 let isPredicatedNew = 1;
   2962 let BaseOpcode = "A2_zxth";
   2963 }
   2964 def A4_rcmpeq : HInst<
   2965 (outs IntRegs:$Rd32),
   2966 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2967 "$Rd32 = cmp.eq($Rs32,$Rt32)",
   2968 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
   2969 let Inst{7-5} = 0b000;
   2970 let Inst{13-13} = 0b0;
   2971 let Inst{31-21} = 0b11110011010;
   2972 let hasNewValue = 1;
   2973 let opNewValue = 0;
   2974 let CextOpcode = "A4_rcmpeq";
   2975 let InputType = "reg";
   2976 let isCommutable = 1;
   2977 }
   2978 def A4_rcmpeqi : HInst<
   2979 (outs IntRegs:$Rd32),
   2980 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   2981 "$Rd32 = cmp.eq($Rs32,#$Ii)",
   2982 tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
   2983 let Inst{13-13} = 0b1;
   2984 let Inst{31-21} = 0b01110011010;
   2985 let hasNewValue = 1;
   2986 let opNewValue = 0;
   2987 let CextOpcode = "A4_rcmpeqi";
   2988 let InputType = "imm";
   2989 let isExtendable = 1;
   2990 let opExtendable = 2;
   2991 let isExtentSigned = 1;
   2992 let opExtentBits = 8;
   2993 let opExtentAlign = 0;
   2994 }
   2995 def A4_rcmpneq : HInst<
   2996 (outs IntRegs:$Rd32),
   2997 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   2998 "$Rd32 = !cmp.eq($Rs32,$Rt32)",
   2999 tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
   3000 let Inst{7-5} = 0b000;
   3001 let Inst{13-13} = 0b0;
   3002 let Inst{31-21} = 0b11110011011;
   3003 let hasNewValue = 1;
   3004 let opNewValue = 0;
   3005 let CextOpcode = "A4_rcmpneq";
   3006 let InputType = "reg";
   3007 let isCommutable = 1;
   3008 }
   3009 def A4_rcmpneqi : HInst<
   3010 (outs IntRegs:$Rd32),
   3011 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   3012 "$Rd32 = !cmp.eq($Rs32,#$Ii)",
   3013 tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
   3014 let Inst{13-13} = 0b1;
   3015 let Inst{31-21} = 0b01110011011;
   3016 let hasNewValue = 1;
   3017 let opNewValue = 0;
   3018 let CextOpcode = "A4_rcmpeqi";
   3019 let InputType = "imm";
   3020 let isExtendable = 1;
   3021 let opExtendable = 2;
   3022 let isExtentSigned = 1;
   3023 let opExtentBits = 8;
   3024 let opExtentAlign = 0;
   3025 }
   3026 def A4_round_ri : HInst<
   3027 (outs IntRegs:$Rd32),
   3028 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   3029 "$Rd32 = round($Rs32,#$Ii)",
   3030 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
   3031 let Inst{7-5} = 0b100;
   3032 let Inst{13-13} = 0b0;
   3033 let Inst{31-21} = 0b10001100111;
   3034 let hasNewValue = 1;
   3035 let opNewValue = 0;
   3036 let prefersSlot3 = 1;
   3037 }
   3038 def A4_round_ri_sat : HInst<
   3039 (outs IntRegs:$Rd32),
   3040 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   3041 "$Rd32 = round($Rs32,#$Ii):sat",
   3042 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
   3043 let Inst{7-5} = 0b110;
   3044 let Inst{13-13} = 0b0;
   3045 let Inst{31-21} = 0b10001100111;
   3046 let hasNewValue = 1;
   3047 let opNewValue = 0;
   3048 let prefersSlot3 = 1;
   3049 let Defs = [USR_OVF];
   3050 }
   3051 def A4_round_rr : HInst<
   3052 (outs IntRegs:$Rd32),
   3053 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3054 "$Rd32 = round($Rs32,$Rt32)",
   3055 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
   3056 let Inst{7-5} = 0b100;
   3057 let Inst{13-13} = 0b0;
   3058 let Inst{31-21} = 0b11000110110;
   3059 let hasNewValue = 1;
   3060 let opNewValue = 0;
   3061 let prefersSlot3 = 1;
   3062 }
   3063 def A4_round_rr_sat : HInst<
   3064 (outs IntRegs:$Rd32),
   3065 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3066 "$Rd32 = round($Rs32,$Rt32):sat",
   3067 tc_2b6f77c6, TypeS_3op>, Enc_5ab2be {
   3068 let Inst{7-5} = 0b110;
   3069 let Inst{13-13} = 0b0;
   3070 let Inst{31-21} = 0b11000110110;
   3071 let hasNewValue = 1;
   3072 let opNewValue = 0;
   3073 let prefersSlot3 = 1;
   3074 let Defs = [USR_OVF];
   3075 }
   3076 def A4_subp_c : HInst<
   3077 (outs DoubleRegs:$Rdd32, PredRegs:$Px4),
   3078 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
   3079 "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
   3080 tc_523fcf30, TypeS_3op>, Enc_2b3f60 {
   3081 let Inst{7-7} = 0b0;
   3082 let Inst{13-13} = 0b0;
   3083 let Inst{31-21} = 0b11000010111;
   3084 let isPredicateLate = 1;
   3085 let Constraints = "$Px4 = $Px4in";
   3086 }
   3087 def A4_tfrcpp : HInst<
   3088 (outs DoubleRegs:$Rdd32),
   3089 (ins CtrRegs64:$Css32),
   3090 "$Rdd32 = $Css32",
   3091 tc_29175780, TypeCR>, Enc_667b39 {
   3092 let Inst{13-5} = 0b000000000;
   3093 let Inst{31-21} = 0b01101000000;
   3094 }
   3095 def A4_tfrpcp : HInst<
   3096 (outs CtrRegs64:$Cdd32),
   3097 (ins DoubleRegs:$Rss32),
   3098 "$Cdd32 = $Rss32",
   3099 tc_a21dc435, TypeCR>, Enc_0ed752 {
   3100 let Inst{13-5} = 0b000000000;
   3101 let Inst{31-21} = 0b01100011001;
   3102 }
   3103 def A4_tlbmatch : HInst<
   3104 (outs PredRegs:$Pd4),
   3105 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   3106 "$Pd4 = tlbmatch($Rss32,$Rt32)",
   3107 tc_04c9decc, TypeALU64>, Enc_03833b {
   3108 let Inst{7-2} = 0b011000;
   3109 let Inst{13-13} = 0b1;
   3110 let Inst{31-21} = 0b11010010000;
   3111 let isPredicateLate = 1;
   3112 }
   3113 def A4_vcmpbeq_any : HInst<
   3114 (outs PredRegs:$Pd4),
   3115 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3116 "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
   3117 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   3118 let Inst{7-2} = 0b000000;
   3119 let Inst{13-13} = 0b1;
   3120 let Inst{31-21} = 0b11010010000;
   3121 }
   3122 def A4_vcmpbeqi : HInst<
   3123 (outs PredRegs:$Pd4),
   3124 (ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
   3125 "$Pd4 = vcmpb.eq($Rss32,#$Ii)",
   3126 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3127 let Inst{4-2} = 0b000;
   3128 let Inst{13-13} = 0b0;
   3129 let Inst{31-21} = 0b11011100000;
   3130 }
   3131 def A4_vcmpbgt : HInst<
   3132 (outs PredRegs:$Pd4),
   3133 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3134 "$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
   3135 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   3136 let Inst{7-2} = 0b010000;
   3137 let Inst{13-13} = 0b1;
   3138 let Inst{31-21} = 0b11010010000;
   3139 }
   3140 def A4_vcmpbgti : HInst<
   3141 (outs PredRegs:$Pd4),
   3142 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
   3143 "$Pd4 = vcmpb.gt($Rss32,#$Ii)",
   3144 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3145 let Inst{4-2} = 0b000;
   3146 let Inst{13-13} = 0b0;
   3147 let Inst{31-21} = 0b11011100001;
   3148 }
   3149 def A4_vcmpbgtui : HInst<
   3150 (outs PredRegs:$Pd4),
   3151 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
   3152 "$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
   3153 tc_7a830544, TypeALU64>, Enc_3680c2 {
   3154 let Inst{4-2} = 0b000;
   3155 let Inst{13-12} = 0b00;
   3156 let Inst{31-21} = 0b11011100010;
   3157 }
   3158 def A4_vcmpheqi : HInst<
   3159 (outs PredRegs:$Pd4),
   3160 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
   3161 "$Pd4 = vcmph.eq($Rss32,#$Ii)",
   3162 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3163 let Inst{4-2} = 0b010;
   3164 let Inst{13-13} = 0b0;
   3165 let Inst{31-21} = 0b11011100000;
   3166 }
   3167 def A4_vcmphgti : HInst<
   3168 (outs PredRegs:$Pd4),
   3169 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
   3170 "$Pd4 = vcmph.gt($Rss32,#$Ii)",
   3171 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3172 let Inst{4-2} = 0b010;
   3173 let Inst{13-13} = 0b0;
   3174 let Inst{31-21} = 0b11011100001;
   3175 }
   3176 def A4_vcmphgtui : HInst<
   3177 (outs PredRegs:$Pd4),
   3178 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
   3179 "$Pd4 = vcmph.gtu($Rss32,#$Ii)",
   3180 tc_7a830544, TypeALU64>, Enc_3680c2 {
   3181 let Inst{4-2} = 0b010;
   3182 let Inst{13-12} = 0b00;
   3183 let Inst{31-21} = 0b11011100010;
   3184 }
   3185 def A4_vcmpweqi : HInst<
   3186 (outs PredRegs:$Pd4),
   3187 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
   3188 "$Pd4 = vcmpw.eq($Rss32,#$Ii)",
   3189 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3190 let Inst{4-2} = 0b100;
   3191 let Inst{13-13} = 0b0;
   3192 let Inst{31-21} = 0b11011100000;
   3193 }
   3194 def A4_vcmpwgti : HInst<
   3195 (outs PredRegs:$Pd4),
   3196 (ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
   3197 "$Pd4 = vcmpw.gt($Rss32,#$Ii)",
   3198 tc_7a830544, TypeALU64>, Enc_0d8adb {
   3199 let Inst{4-2} = 0b100;
   3200 let Inst{13-13} = 0b0;
   3201 let Inst{31-21} = 0b11011100001;
   3202 }
   3203 def A4_vcmpwgtui : HInst<
   3204 (outs PredRegs:$Pd4),
   3205 (ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
   3206 "$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
   3207 tc_7a830544, TypeALU64>, Enc_3680c2 {
   3208 let Inst{4-2} = 0b100;
   3209 let Inst{13-12} = 0b00;
   3210 let Inst{31-21} = 0b11011100010;
   3211 }
   3212 def A4_vrmaxh : HInst<
   3213 (outs DoubleRegs:$Rxx32),
   3214 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3215 "$Rxx32 = vrmaxh($Rss32,$Ru32)",
   3216 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3217 let Inst{7-5} = 0b001;
   3218 let Inst{13-13} = 0b0;
   3219 let Inst{31-21} = 0b11001011001;
   3220 let prefersSlot3 = 1;
   3221 let Constraints = "$Rxx32 = $Rxx32in";
   3222 }
   3223 def A4_vrmaxuh : HInst<
   3224 (outs DoubleRegs:$Rxx32),
   3225 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3226 "$Rxx32 = vrmaxuh($Rss32,$Ru32)",
   3227 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3228 let Inst{7-5} = 0b001;
   3229 let Inst{13-13} = 0b1;
   3230 let Inst{31-21} = 0b11001011001;
   3231 let prefersSlot3 = 1;
   3232 let Constraints = "$Rxx32 = $Rxx32in";
   3233 }
   3234 def A4_vrmaxuw : HInst<
   3235 (outs DoubleRegs:$Rxx32),
   3236 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3237 "$Rxx32 = vrmaxuw($Rss32,$Ru32)",
   3238 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3239 let Inst{7-5} = 0b010;
   3240 let Inst{13-13} = 0b1;
   3241 let Inst{31-21} = 0b11001011001;
   3242 let prefersSlot3 = 1;
   3243 let Constraints = "$Rxx32 = $Rxx32in";
   3244 }
   3245 def A4_vrmaxw : HInst<
   3246 (outs DoubleRegs:$Rxx32),
   3247 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3248 "$Rxx32 = vrmaxw($Rss32,$Ru32)",
   3249 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3250 let Inst{7-5} = 0b010;
   3251 let Inst{13-13} = 0b0;
   3252 let Inst{31-21} = 0b11001011001;
   3253 let prefersSlot3 = 1;
   3254 let Constraints = "$Rxx32 = $Rxx32in";
   3255 }
   3256 def A4_vrminh : HInst<
   3257 (outs DoubleRegs:$Rxx32),
   3258 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3259 "$Rxx32 = vrminh($Rss32,$Ru32)",
   3260 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3261 let Inst{7-5} = 0b101;
   3262 let Inst{13-13} = 0b0;
   3263 let Inst{31-21} = 0b11001011001;
   3264 let prefersSlot3 = 1;
   3265 let Constraints = "$Rxx32 = $Rxx32in";
   3266 }
   3267 def A4_vrminuh : HInst<
   3268 (outs DoubleRegs:$Rxx32),
   3269 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3270 "$Rxx32 = vrminuh($Rss32,$Ru32)",
   3271 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3272 let Inst{7-5} = 0b101;
   3273 let Inst{13-13} = 0b1;
   3274 let Inst{31-21} = 0b11001011001;
   3275 let prefersSlot3 = 1;
   3276 let Constraints = "$Rxx32 = $Rxx32in";
   3277 }
   3278 def A4_vrminuw : HInst<
   3279 (outs DoubleRegs:$Rxx32),
   3280 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3281 "$Rxx32 = vrminuw($Rss32,$Ru32)",
   3282 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3283 let Inst{7-5} = 0b110;
   3284 let Inst{13-13} = 0b1;
   3285 let Inst{31-21} = 0b11001011001;
   3286 let prefersSlot3 = 1;
   3287 let Constraints = "$Rxx32 = $Rxx32in";
   3288 }
   3289 def A4_vrminw : HInst<
   3290 (outs DoubleRegs:$Rxx32),
   3291 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
   3292 "$Rxx32 = vrminw($Rss32,$Ru32)",
   3293 tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 {
   3294 let Inst{7-5} = 0b110;
   3295 let Inst{13-13} = 0b0;
   3296 let Inst{31-21} = 0b11001011001;
   3297 let prefersSlot3 = 1;
   3298 let Constraints = "$Rxx32 = $Rxx32in";
   3299 }
   3300 def A5_ACS : HInst<
   3301 (outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
   3302 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3303 "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
   3304 tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55]> {
   3305 let Inst{7-7} = 0b0;
   3306 let Inst{13-13} = 0b0;
   3307 let Inst{31-21} = 0b11101010101;
   3308 let isPredicateLate = 1;
   3309 let prefersSlot3 = 1;
   3310 let Defs = [USR_OVF];
   3311 let Constraints = "$Rxx32 = $Rxx32in";
   3312 }
   3313 def A5_vaddhubs : HInst<
   3314 (outs IntRegs:$Rd32),
   3315 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3316 "$Rd32 = vaddhub($Rss32,$Rtt32):sat",
   3317 tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5]> {
   3318 let Inst{7-5} = 0b001;
   3319 let Inst{13-13} = 0b0;
   3320 let Inst{31-21} = 0b11000001010;
   3321 let hasNewValue = 1;
   3322 let opNewValue = 0;
   3323 let prefersSlot3 = 1;
   3324 let Defs = [USR_OVF];
   3325 }
   3326 def A6_vcmpbeq_notany : HInst<
   3327 (outs PredRegs:$Pd4),
   3328 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3329 "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
   3330 tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
   3331 let Inst{7-2} = 0b001000;
   3332 let Inst{13-13} = 0b1;
   3333 let Inst{31-21} = 0b11010010000;
   3334 }
   3335 def A6_vminub_RdP : HInst<
   3336 (outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
   3337 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   3338 "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
   3339 tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
   3340 let Inst{7-7} = 0b0;
   3341 let Inst{13-13} = 0b0;
   3342 let Inst{31-21} = 0b11101010111;
   3343 let isPredicateLate = 1;
   3344 let prefersSlot3 = 1;
   3345 }
   3346 def C2_all8 : HInst<
   3347 (outs PredRegs:$Pd4),
   3348 (ins PredRegs:$Ps4),
   3349 "$Pd4 = all8($Ps4)",
   3350 tc_f2704b9a, TypeCR>, Enc_65d691 {
   3351 let Inst{13-2} = 0b000000000000;
   3352 let Inst{31-18} = 0b01101011101000;
   3353 }
   3354 def C2_and : HInst<
   3355 (outs PredRegs:$Pd4),
   3356 (ins PredRegs:$Pt4, PredRegs:$Ps4),
   3357 "$Pd4 = and($Pt4,$Ps4)",
   3358 tc_53bc8a6a, TypeCR>, Enc_454a26 {
   3359 let Inst{7-2} = 0b000000;
   3360 let Inst{13-10} = 0b0000;
   3361 let Inst{31-18} = 0b01101011000000;
   3362 }
   3363 def C2_andn : HInst<
   3364 (outs PredRegs:$Pd4),
   3365 (ins PredRegs:$Pt4, PredRegs:$Ps4),
   3366 "$Pd4 = and($Pt4,!$Ps4)",
   3367 tc_53bc8a6a, TypeCR>, Enc_454a26 {
   3368 let Inst{7-2} = 0b000000;
   3369 let Inst{13-10} = 0b0000;
   3370 let Inst{31-18} = 0b01101011011000;
   3371 }
   3372 def C2_any8 : HInst<
   3373 (outs PredRegs:$Pd4),
   3374 (ins PredRegs:$Ps4),
   3375 "$Pd4 = any8($Ps4)",
   3376 tc_f2704b9a, TypeCR>, Enc_65d691 {
   3377 let Inst{13-2} = 0b000000000000;
   3378 let Inst{31-18} = 0b01101011100000;
   3379 }
   3380 def C2_bitsclr : HInst<
   3381 (outs PredRegs:$Pd4),
   3382 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3383 "$Pd4 = bitsclr($Rs32,$Rt32)",
   3384 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   3385 let Inst{7-2} = 0b000000;
   3386 let Inst{13-13} = 0b0;
   3387 let Inst{31-21} = 0b11000111100;
   3388 }
   3389 def C2_bitsclri : HInst<
   3390 (outs PredRegs:$Pd4),
   3391 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
   3392 "$Pd4 = bitsclr($Rs32,#$Ii)",
   3393 tc_7a830544, TypeS_2op>, Enc_5d6c34 {
   3394 let Inst{7-2} = 0b000000;
   3395 let Inst{31-21} = 0b10000101100;
   3396 }
   3397 def C2_bitsset : HInst<
   3398 (outs PredRegs:$Pd4),
   3399 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3400 "$Pd4 = bitsset($Rs32,$Rt32)",
   3401 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   3402 let Inst{7-2} = 0b000000;
   3403 let Inst{13-13} = 0b0;
   3404 let Inst{31-21} = 0b11000111010;
   3405 }
   3406 def C2_ccombinewf : HInst<
   3407 (outs DoubleRegs:$Rdd32),
   3408 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
   3409 "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
   3410 tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
   3411 let Inst{7-7} = 0b1;
   3412 let Inst{13-13} = 0b0;
   3413 let Inst{31-21} = 0b11111101000;
   3414 let isPredicated = 1;
   3415 let isPredicatedFalse = 1;
   3416 let BaseOpcode = "A2_combinew";
   3417 }
   3418 def C2_ccombinewnewf : HInst<
   3419 (outs DoubleRegs:$Rdd32),
   3420 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
   3421 "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
   3422 tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
   3423 let Inst{7-7} = 0b1;
   3424 let Inst{13-13} = 0b1;
   3425 let Inst{31-21} = 0b11111101000;
   3426 let isPredicated = 1;
   3427 let isPredicatedFalse = 1;
   3428 let isPredicatedNew = 1;
   3429 let BaseOpcode = "A2_combinew";
   3430 }
   3431 def C2_ccombinewnewt : HInst<
   3432 (outs DoubleRegs:$Rdd32),
   3433 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
   3434 "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
   3435 tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
   3436 let Inst{7-7} = 0b0;
   3437 let Inst{13-13} = 0b1;
   3438 let Inst{31-21} = 0b11111101000;
   3439 let isPredicated = 1;
   3440 let isPredicatedNew = 1;
   3441 let BaseOpcode = "A2_combinew";
   3442 }
   3443 def C2_ccombinewt : HInst<
   3444 (outs DoubleRegs:$Rdd32),
   3445 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
   3446 "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
   3447 tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
   3448 let Inst{7-7} = 0b0;
   3449 let Inst{13-13} = 0b0;
   3450 let Inst{31-21} = 0b11111101000;
   3451 let isPredicated = 1;
   3452 let BaseOpcode = "A2_combinew";
   3453 }
   3454 def C2_cmoveif : HInst<
   3455 (outs IntRegs:$Rd32),
   3456 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
   3457 "if (!$Pu4) $Rd32 = #$Ii",
   3458 tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
   3459 let Inst{13-13} = 0b0;
   3460 let Inst{20-20} = 0b0;
   3461 let Inst{31-23} = 0b011111101;
   3462 let isPredicated = 1;
   3463 let isPredicatedFalse = 1;
   3464 let hasNewValue = 1;
   3465 let opNewValue = 0;
   3466 let CextOpcode = "A2_tfr";
   3467 let InputType = "imm";
   3468 let BaseOpcode = "A2_tfrsi";
   3469 let isMoveImm = 1;
   3470 let isExtendable = 1;
   3471 let opExtendable = 2;
   3472 let isExtentSigned = 1;
   3473 let opExtentBits = 12;
   3474 let opExtentAlign = 0;
   3475 }
   3476 def C2_cmoveit : HInst<
   3477 (outs IntRegs:$Rd32),
   3478 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
   3479 "if ($Pu4) $Rd32 = #$Ii",
   3480 tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
   3481 let Inst{13-13} = 0b0;
   3482 let Inst{20-20} = 0b0;
   3483 let Inst{31-23} = 0b011111100;
   3484 let isPredicated = 1;
   3485 let hasNewValue = 1;
   3486 let opNewValue = 0;
   3487 let CextOpcode = "A2_tfr";
   3488 let InputType = "imm";
   3489 let BaseOpcode = "A2_tfrsi";
   3490 let isMoveImm = 1;
   3491 let isExtendable = 1;
   3492 let opExtendable = 2;
   3493 let isExtentSigned = 1;
   3494 let opExtentBits = 12;
   3495 let opExtentAlign = 0;
   3496 }
   3497 def C2_cmovenewif : HInst<
   3498 (outs IntRegs:$Rd32),
   3499 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
   3500 "if (!$Pu4.new) $Rd32 = #$Ii",
   3501 tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
   3502 let Inst{13-13} = 0b1;
   3503 let Inst{20-20} = 0b0;
   3504 let Inst{31-23} = 0b011111101;
   3505 let isPredicated = 1;
   3506 let isPredicatedFalse = 1;
   3507 let hasNewValue = 1;
   3508 let opNewValue = 0;
   3509 let isPredicatedNew = 1;
   3510 let CextOpcode = "A2_tfr";
   3511 let InputType = "imm";
   3512 let BaseOpcode = "A2_tfrsi";
   3513 let isMoveImm = 1;
   3514 let isExtendable = 1;
   3515 let opExtendable = 2;
   3516 let isExtentSigned = 1;
   3517 let opExtentBits = 12;
   3518 let opExtentAlign = 0;
   3519 }
   3520 def C2_cmovenewit : HInst<
   3521 (outs IntRegs:$Rd32),
   3522 (ins PredRegs:$Pu4, s32_0Imm:$Ii),
   3523 "if ($Pu4.new) $Rd32 = #$Ii",
   3524 tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
   3525 let Inst{13-13} = 0b1;
   3526 let Inst{20-20} = 0b0;
   3527 let Inst{31-23} = 0b011111100;
   3528 let isPredicated = 1;
   3529 let hasNewValue = 1;
   3530 let opNewValue = 0;
   3531 let isPredicatedNew = 1;
   3532 let CextOpcode = "A2_tfr";
   3533 let InputType = "imm";
   3534 let BaseOpcode = "A2_tfrsi";
   3535 let isMoveImm = 1;
   3536 let isExtendable = 1;
   3537 let opExtendable = 2;
   3538 let isExtentSigned = 1;
   3539 let opExtentBits = 12;
   3540 let opExtentAlign = 0;
   3541 }
   3542 def C2_cmpeq : HInst<
   3543 (outs PredRegs:$Pd4),
   3544 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3545 "$Pd4 = cmp.eq($Rs32,$Rt32)",
   3546 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3547 let Inst{7-2} = 0b000000;
   3548 let Inst{13-13} = 0b0;
   3549 let Inst{31-21} = 0b11110010000;
   3550 let CextOpcode = "C2_cmpeq";
   3551 let InputType = "reg";
   3552 let isCommutable = 1;
   3553 let isCompare = 1;
   3554 }
   3555 def C2_cmpeqi : HInst<
   3556 (outs PredRegs:$Pd4),
   3557 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   3558 "$Pd4 = cmp.eq($Rs32,#$Ii)",
   3559 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
   3560 let Inst{4-2} = 0b000;
   3561 let Inst{31-22} = 0b0111010100;
   3562 let CextOpcode = "C2_cmpeq";
   3563 let InputType = "imm";
   3564 let isCompare = 1;
   3565 let isExtendable = 1;
   3566 let opExtendable = 2;
   3567 let isExtentSigned = 1;
   3568 let opExtentBits = 10;
   3569 let opExtentAlign = 0;
   3570 }
   3571 def C2_cmpeqp : HInst<
   3572 (outs PredRegs:$Pd4),
   3573 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3574 "$Pd4 = cmp.eq($Rss32,$Rtt32)",
   3575 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   3576 let Inst{7-2} = 0b000000;
   3577 let Inst{13-13} = 0b0;
   3578 let Inst{31-21} = 0b11010010100;
   3579 let isCommutable = 1;
   3580 let isCompare = 1;
   3581 }
   3582 def C2_cmpgei : HInst<
   3583 (outs PredRegs:$Pd4),
   3584 (ins IntRegs:$Rs32, s8_0Imm:$Ii),
   3585 "$Pd4 = cmp.ge($Rs32,#$Ii)",
   3586 tc_6ebb4a12, TypeALU32_2op> {
   3587 let isCompare = 1;
   3588 let isPseudo = 1;
   3589 }
   3590 def C2_cmpgeui : HInst<
   3591 (outs PredRegs:$Pd4),
   3592 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
   3593 "$Pd4 = cmp.geu($Rs32,#$Ii)",
   3594 tc_6ebb4a12, TypeALU32_2op> {
   3595 let isCompare = 1;
   3596 let isPseudo = 1;
   3597 }
   3598 def C2_cmpgt : HInst<
   3599 (outs PredRegs:$Pd4),
   3600 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3601 "$Pd4 = cmp.gt($Rs32,$Rt32)",
   3602 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3603 let Inst{7-2} = 0b000000;
   3604 let Inst{13-13} = 0b0;
   3605 let Inst{31-21} = 0b11110010010;
   3606 let CextOpcode = "C2_cmpgt";
   3607 let InputType = "reg";
   3608 let isCompare = 1;
   3609 }
   3610 def C2_cmpgti : HInst<
   3611 (outs PredRegs:$Pd4),
   3612 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   3613 "$Pd4 = cmp.gt($Rs32,#$Ii)",
   3614 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
   3615 let Inst{4-2} = 0b000;
   3616 let Inst{31-22} = 0b0111010101;
   3617 let CextOpcode = "C2_cmpgt";
   3618 let InputType = "imm";
   3619 let isCompare = 1;
   3620 let isExtendable = 1;
   3621 let opExtendable = 2;
   3622 let isExtentSigned = 1;
   3623 let opExtentBits = 10;
   3624 let opExtentAlign = 0;
   3625 }
   3626 def C2_cmpgtp : HInst<
   3627 (outs PredRegs:$Pd4),
   3628 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3629 "$Pd4 = cmp.gt($Rss32,$Rtt32)",
   3630 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   3631 let Inst{7-2} = 0b010000;
   3632 let Inst{13-13} = 0b0;
   3633 let Inst{31-21} = 0b11010010100;
   3634 let isCompare = 1;
   3635 }
   3636 def C2_cmpgtu : HInst<
   3637 (outs PredRegs:$Pd4),
   3638 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3639 "$Pd4 = cmp.gtu($Rs32,$Rt32)",
   3640 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3641 let Inst{7-2} = 0b000000;
   3642 let Inst{13-13} = 0b0;
   3643 let Inst{31-21} = 0b11110010011;
   3644 let CextOpcode = "C2_cmpgtu";
   3645 let InputType = "reg";
   3646 let isCompare = 1;
   3647 }
   3648 def C2_cmpgtui : HInst<
   3649 (outs PredRegs:$Pd4),
   3650 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
   3651 "$Pd4 = cmp.gtu($Rs32,#$Ii)",
   3652 tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
   3653 let Inst{4-2} = 0b000;
   3654 let Inst{31-21} = 0b01110101100;
   3655 let CextOpcode = "C2_cmpgtu";
   3656 let InputType = "imm";
   3657 let isCompare = 1;
   3658 let isExtendable = 1;
   3659 let opExtendable = 2;
   3660 let isExtentSigned = 0;
   3661 let opExtentBits = 9;
   3662 let opExtentAlign = 0;
   3663 }
   3664 def C2_cmpgtup : HInst<
   3665 (outs PredRegs:$Pd4),
   3666 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3667 "$Pd4 = cmp.gtu($Rss32,$Rtt32)",
   3668 tc_1e856f58, TypeALU64>, Enc_fcf7a7 {
   3669 let Inst{7-2} = 0b100000;
   3670 let Inst{13-13} = 0b0;
   3671 let Inst{31-21} = 0b11010010100;
   3672 let isCompare = 1;
   3673 }
   3674 def C2_cmplt : HInst<
   3675 (outs PredRegs:$Pd4),
   3676 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3677 "$Pd4 = cmp.lt($Rs32,$Rt32)",
   3678 tc_6ebb4a12, TypeALU32_3op> {
   3679 let isCompare = 1;
   3680 let isPseudo = 1;
   3681 let isCodeGenOnly = 1;
   3682 }
   3683 def C2_cmpltu : HInst<
   3684 (outs PredRegs:$Pd4),
   3685 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3686 "$Pd4 = cmp.ltu($Rs32,$Rt32)",
   3687 tc_6ebb4a12, TypeALU32_3op> {
   3688 let isCompare = 1;
   3689 let isPseudo = 1;
   3690 let isCodeGenOnly = 1;
   3691 }
   3692 def C2_mask : HInst<
   3693 (outs DoubleRegs:$Rdd32),
   3694 (ins PredRegs:$Pt4),
   3695 "$Rdd32 = mask($Pt4)",
   3696 tc_cde8b071, TypeS_2op>, Enc_78e566 {
   3697 let Inst{7-5} = 0b000;
   3698 let Inst{13-10} = 0b0000;
   3699 let Inst{31-16} = 0b1000011000000000;
   3700 }
   3701 def C2_mux : HInst<
   3702 (outs IntRegs:$Rd32),
   3703 (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
   3704 "$Rd32 = mux($Pu4,$Rs32,$Rt32)",
   3705 tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54 {
   3706 let Inst{7-7} = 0b0;
   3707 let Inst{13-13} = 0b0;
   3708 let Inst{31-21} = 0b11110100000;
   3709 let hasNewValue = 1;
   3710 let opNewValue = 0;
   3711 let InputType = "reg";
   3712 }
   3713 def C2_muxii : HInst<
   3714 (outs IntRegs:$Rd32),
   3715 (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
   3716 "$Rd32 = mux($Pu4,#$Ii,#$II)",
   3717 tc_d6bf0472, TypeALU32_2op>, Enc_830e5d {
   3718 let Inst{31-25} = 0b0111101;
   3719 let hasNewValue = 1;
   3720 let opNewValue = 0;
   3721 let isExtendable = 1;
   3722 let opExtendable = 2;
   3723 let isExtentSigned = 1;
   3724 let opExtentBits = 8;
   3725 let opExtentAlign = 0;
   3726 }
   3727 def C2_muxir : HInst<
   3728 (outs IntRegs:$Rd32),
   3729 (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
   3730 "$Rd32 = mux($Pu4,$Rs32,#$Ii)",
   3731 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
   3732 let Inst{13-13} = 0b0;
   3733 let Inst{31-23} = 0b011100110;
   3734 let hasNewValue = 1;
   3735 let opNewValue = 0;
   3736 let InputType = "imm";
   3737 let isExtendable = 1;
   3738 let opExtendable = 3;
   3739 let isExtentSigned = 1;
   3740 let opExtentBits = 8;
   3741 let opExtentAlign = 0;
   3742 }
   3743 def C2_muxri : HInst<
   3744 (outs IntRegs:$Rd32),
   3745 (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
   3746 "$Rd32 = mux($Pu4,#$Ii,$Rs32)",
   3747 tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f {
   3748 let Inst{13-13} = 0b0;
   3749 let Inst{31-23} = 0b011100111;
   3750 let hasNewValue = 1;
   3751 let opNewValue = 0;
   3752 let InputType = "imm";
   3753 let isExtendable = 1;
   3754 let opExtendable = 2;
   3755 let isExtentSigned = 1;
   3756 let opExtentBits = 8;
   3757 let opExtentAlign = 0;
   3758 }
   3759 def C2_not : HInst<
   3760 (outs PredRegs:$Pd4),
   3761 (ins PredRegs:$Ps4),
   3762 "$Pd4 = not($Ps4)",
   3763 tc_f2704b9a, TypeCR>, Enc_65d691 {
   3764 let Inst{13-2} = 0b000000000000;
   3765 let Inst{31-18} = 0b01101011110000;
   3766 }
   3767 def C2_or : HInst<
   3768 (outs PredRegs:$Pd4),
   3769 (ins PredRegs:$Pt4, PredRegs:$Ps4),
   3770 "$Pd4 = or($Pt4,$Ps4)",
   3771 tc_53bc8a6a, TypeCR>, Enc_454a26 {
   3772 let Inst{7-2} = 0b000000;
   3773 let Inst{13-10} = 0b0000;
   3774 let Inst{31-18} = 0b01101011001000;
   3775 }
   3776 def C2_orn : HInst<
   3777 (outs PredRegs:$Pd4),
   3778 (ins PredRegs:$Pt4, PredRegs:$Ps4),
   3779 "$Pd4 = or($Pt4,!$Ps4)",
   3780 tc_53bc8a6a, TypeCR>, Enc_454a26 {
   3781 let Inst{7-2} = 0b000000;
   3782 let Inst{13-10} = 0b0000;
   3783 let Inst{31-18} = 0b01101011111000;
   3784 }
   3785 def C2_pxfer_map : HInst<
   3786 (outs PredRegs:$Pd4),
   3787 (ins PredRegs:$Ps4),
   3788 "$Pd4 = $Ps4",
   3789 tc_53bc8a6a, TypeMAPPING> {
   3790 let isPseudo = 1;
   3791 let isCodeGenOnly = 1;
   3792 }
   3793 def C2_tfrpr : HInst<
   3794 (outs IntRegs:$Rd32),
   3795 (ins PredRegs:$Ps4),
   3796 "$Rd32 = $Ps4",
   3797 tc_cde8b071, TypeS_2op>, Enc_f5e933 {
   3798 let Inst{13-5} = 0b000000000;
   3799 let Inst{31-18} = 0b10001001010000;
   3800 let hasNewValue = 1;
   3801 let opNewValue = 0;
   3802 }
   3803 def C2_tfrrp : HInst<
   3804 (outs PredRegs:$Pd4),
   3805 (ins IntRegs:$Rs32),
   3806 "$Pd4 = $Rs32",
   3807 tc_351fed2d, TypeS_2op>, Enc_48b75f {
   3808 let Inst{13-2} = 0b000000000000;
   3809 let Inst{31-21} = 0b10000101010;
   3810 }
   3811 def C2_vitpack : HInst<
   3812 (outs IntRegs:$Rd32),
   3813 (ins PredRegs:$Ps4, PredRegs:$Pt4),
   3814 "$Rd32 = vitpack($Ps4,$Pt4)",
   3815 tc_1b9c9ee5, TypeS_2op>, Enc_527412 {
   3816 let Inst{7-5} = 0b000;
   3817 let Inst{13-10} = 0b0000;
   3818 let Inst{31-18} = 0b10001001000000;
   3819 let hasNewValue = 1;
   3820 let opNewValue = 0;
   3821 let prefersSlot3 = 1;
   3822 }
   3823 def C2_vmux : HInst<
   3824 (outs DoubleRegs:$Rdd32),
   3825 (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   3826 "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
   3827 tc_f8eeed7a, TypeALU64>, Enc_329361 {
   3828 let Inst{7-7} = 0b0;
   3829 let Inst{13-13} = 0b0;
   3830 let Inst{31-21} = 0b11010001000;
   3831 }
   3832 def C2_xor : HInst<
   3833 (outs PredRegs:$Pd4),
   3834 (ins PredRegs:$Ps4, PredRegs:$Pt4),
   3835 "$Pd4 = xor($Ps4,$Pt4)",
   3836 tc_53bc8a6a, TypeCR>, Enc_284ebb {
   3837 let Inst{7-2} = 0b000000;
   3838 let Inst{13-10} = 0b0000;
   3839 let Inst{31-18} = 0b01101011010000;
   3840 }
   3841 def C4_addipc : HInst<
   3842 (outs IntRegs:$Rd32),
   3843 (ins u32_0Imm:$Ii),
   3844 "$Rd32 = add(pc,#$Ii)",
   3845 tc_b9c4623f, TypeCR>, Enc_607661 {
   3846 let Inst{6-5} = 0b00;
   3847 let Inst{13-13} = 0b0;
   3848 let Inst{31-16} = 0b0110101001001001;
   3849 let hasNewValue = 1;
   3850 let opNewValue = 0;
   3851 let isExtendable = 1;
   3852 let opExtendable = 1;
   3853 let isExtentSigned = 0;
   3854 let opExtentBits = 6;
   3855 let opExtentAlign = 0;
   3856 }
   3857 def C4_and_and : HInst<
   3858 (outs PredRegs:$Pd4),
   3859 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   3860 "$Pd4 = and($Ps4,and($Pt4,$Pu4))",
   3861 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   3862 let Inst{5-2} = 0b0000;
   3863 let Inst{13-10} = 0b0000;
   3864 let Inst{31-18} = 0b01101011000100;
   3865 }
   3866 def C4_and_andn : HInst<
   3867 (outs PredRegs:$Pd4),
   3868 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   3869 "$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
   3870 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   3871 let Inst{5-2} = 0b0000;
   3872 let Inst{13-10} = 0b0000;
   3873 let Inst{31-18} = 0b01101011100100;
   3874 }
   3875 def C4_and_or : HInst<
   3876 (outs PredRegs:$Pd4),
   3877 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   3878 "$Pd4 = and($Ps4,or($Pt4,$Pu4))",
   3879 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   3880 let Inst{5-2} = 0b0000;
   3881 let Inst{13-10} = 0b0000;
   3882 let Inst{31-18} = 0b01101011001100;
   3883 }
   3884 def C4_and_orn : HInst<
   3885 (outs PredRegs:$Pd4),
   3886 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   3887 "$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
   3888 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   3889 let Inst{5-2} = 0b0000;
   3890 let Inst{13-10} = 0b0000;
   3891 let Inst{31-18} = 0b01101011101100;
   3892 }
   3893 def C4_cmplte : HInst<
   3894 (outs PredRegs:$Pd4),
   3895 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3896 "$Pd4 = !cmp.gt($Rs32,$Rt32)",
   3897 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3898 let Inst{7-2} = 0b000100;
   3899 let Inst{13-13} = 0b0;
   3900 let Inst{31-21} = 0b11110010010;
   3901 let CextOpcode = "C4_cmplte";
   3902 let InputType = "reg";
   3903 let isCompare = 1;
   3904 }
   3905 def C4_cmpltei : HInst<
   3906 (outs PredRegs:$Pd4),
   3907 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   3908 "$Pd4 = !cmp.gt($Rs32,#$Ii)",
   3909 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
   3910 let Inst{4-2} = 0b100;
   3911 let Inst{31-22} = 0b0111010101;
   3912 let CextOpcode = "C4_cmplte";
   3913 let InputType = "imm";
   3914 let isCompare = 1;
   3915 let isExtendable = 1;
   3916 let opExtendable = 2;
   3917 let isExtentSigned = 1;
   3918 let opExtentBits = 10;
   3919 let opExtentAlign = 0;
   3920 }
   3921 def C4_cmplteu : HInst<
   3922 (outs PredRegs:$Pd4),
   3923 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3924 "$Pd4 = !cmp.gtu($Rs32,$Rt32)",
   3925 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3926 let Inst{7-2} = 0b000100;
   3927 let Inst{13-13} = 0b0;
   3928 let Inst{31-21} = 0b11110010011;
   3929 let CextOpcode = "C4_cmplteu";
   3930 let InputType = "reg";
   3931 let isCompare = 1;
   3932 }
   3933 def C4_cmplteui : HInst<
   3934 (outs PredRegs:$Pd4),
   3935 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
   3936 "$Pd4 = !cmp.gtu($Rs32,#$Ii)",
   3937 tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
   3938 let Inst{4-2} = 0b100;
   3939 let Inst{31-21} = 0b01110101100;
   3940 let CextOpcode = "C4_cmplteu";
   3941 let InputType = "imm";
   3942 let isCompare = 1;
   3943 let isExtendable = 1;
   3944 let opExtendable = 2;
   3945 let isExtentSigned = 0;
   3946 let opExtentBits = 9;
   3947 let opExtentAlign = 0;
   3948 }
   3949 def C4_cmpneq : HInst<
   3950 (outs PredRegs:$Pd4),
   3951 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3952 "$Pd4 = !cmp.eq($Rs32,$Rt32)",
   3953 tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
   3954 let Inst{7-2} = 0b000100;
   3955 let Inst{13-13} = 0b0;
   3956 let Inst{31-21} = 0b11110010000;
   3957 let CextOpcode = "C4_cmpneq";
   3958 let InputType = "reg";
   3959 let isCommutable = 1;
   3960 let isCompare = 1;
   3961 }
   3962 def C4_cmpneqi : HInst<
   3963 (outs PredRegs:$Pd4),
   3964 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   3965 "$Pd4 = !cmp.eq($Rs32,#$Ii)",
   3966 tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
   3967 let Inst{4-2} = 0b100;
   3968 let Inst{31-22} = 0b0111010100;
   3969 let CextOpcode = "C4_cmpneq";
   3970 let InputType = "imm";
   3971 let isCompare = 1;
   3972 let isExtendable = 1;
   3973 let opExtendable = 2;
   3974 let isExtentSigned = 1;
   3975 let opExtentBits = 10;
   3976 let opExtentAlign = 0;
   3977 }
   3978 def C4_fastcorner9 : HInst<
   3979 (outs PredRegs:$Pd4),
   3980 (ins PredRegs:$Ps4, PredRegs:$Pt4),
   3981 "$Pd4 = fastcorner9($Ps4,$Pt4)",
   3982 tc_53bc8a6a, TypeCR>, Enc_284ebb {
   3983 let Inst{7-2} = 0b100100;
   3984 let Inst{13-10} = 0b1000;
   3985 let Inst{31-18} = 0b01101011000000;
   3986 }
   3987 def C4_fastcorner9_not : HInst<
   3988 (outs PredRegs:$Pd4),
   3989 (ins PredRegs:$Ps4, PredRegs:$Pt4),
   3990 "$Pd4 = !fastcorner9($Ps4,$Pt4)",
   3991 tc_53bc8a6a, TypeCR>, Enc_284ebb {
   3992 let Inst{7-2} = 0b100100;
   3993 let Inst{13-10} = 0b1000;
   3994 let Inst{31-18} = 0b01101011000100;
   3995 }
   3996 def C4_nbitsclr : HInst<
   3997 (outs PredRegs:$Pd4),
   3998 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   3999 "$Pd4 = !bitsclr($Rs32,$Rt32)",
   4000 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   4001 let Inst{7-2} = 0b000000;
   4002 let Inst{13-13} = 0b0;
   4003 let Inst{31-21} = 0b11000111101;
   4004 }
   4005 def C4_nbitsclri : HInst<
   4006 (outs PredRegs:$Pd4),
   4007 (ins IntRegs:$Rs32, u6_0Imm:$Ii),
   4008 "$Pd4 = !bitsclr($Rs32,#$Ii)",
   4009 tc_7a830544, TypeS_2op>, Enc_5d6c34 {
   4010 let Inst{7-2} = 0b000000;
   4011 let Inst{31-21} = 0b10000101101;
   4012 }
   4013 def C4_nbitsset : HInst<
   4014 (outs PredRegs:$Pd4),
   4015 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4016 "$Pd4 = !bitsset($Rs32,$Rt32)",
   4017 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   4018 let Inst{7-2} = 0b000000;
   4019 let Inst{13-13} = 0b0;
   4020 let Inst{31-21} = 0b11000111011;
   4021 }
   4022 def C4_or_and : HInst<
   4023 (outs PredRegs:$Pd4),
   4024 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   4025 "$Pd4 = or($Ps4,and($Pt4,$Pu4))",
   4026 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   4027 let Inst{5-2} = 0b0000;
   4028 let Inst{13-10} = 0b0000;
   4029 let Inst{31-18} = 0b01101011010100;
   4030 }
   4031 def C4_or_andn : HInst<
   4032 (outs PredRegs:$Pd4),
   4033 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   4034 "$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
   4035 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   4036 let Inst{5-2} = 0b0000;
   4037 let Inst{13-10} = 0b0000;
   4038 let Inst{31-18} = 0b01101011110100;
   4039 }
   4040 def C4_or_or : HInst<
   4041 (outs PredRegs:$Pd4),
   4042 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   4043 "$Pd4 = or($Ps4,or($Pt4,$Pu4))",
   4044 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   4045 let Inst{5-2} = 0b0000;
   4046 let Inst{13-10} = 0b0000;
   4047 let Inst{31-18} = 0b01101011011100;
   4048 }
   4049 def C4_or_orn : HInst<
   4050 (outs PredRegs:$Pd4),
   4051 (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
   4052 "$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
   4053 tc_481e5e5c, TypeCR>, Enc_9ac432 {
   4054 let Inst{5-2} = 0b0000;
   4055 let Inst{13-10} = 0b0000;
   4056 let Inst{31-18} = 0b01101011111100;
   4057 }
   4058 def F2_conv_d2df : HInst<
   4059 (outs DoubleRegs:$Rdd32),
   4060 (ins DoubleRegs:$Rss32),
   4061 "$Rdd32 = convert_d2df($Rss32)",
   4062 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4063 let Inst{13-5} = 0b000000011;
   4064 let Inst{31-21} = 0b10000000111;
   4065 let isFP = 1;
   4066 let Uses = [USR];
   4067 }
   4068 def F2_conv_d2sf : HInst<
   4069 (outs IntRegs:$Rd32),
   4070 (ins DoubleRegs:$Rss32),
   4071 "$Rd32 = convert_d2sf($Rss32)",
   4072 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4073 let Inst{13-5} = 0b000000001;
   4074 let Inst{31-21} = 0b10001000010;
   4075 let hasNewValue = 1;
   4076 let opNewValue = 0;
   4077 let isFP = 1;
   4078 let Uses = [USR];
   4079 }
   4080 def F2_conv_df2d : HInst<
   4081 (outs DoubleRegs:$Rdd32),
   4082 (ins DoubleRegs:$Rss32),
   4083 "$Rdd32 = convert_df2d($Rss32)",
   4084 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4085 let Inst{13-5} = 0b000000000;
   4086 let Inst{31-21} = 0b10000000111;
   4087 let isFP = 1;
   4088 let Uses = [USR];
   4089 }
   4090 def F2_conv_df2d_chop : HInst<
   4091 (outs DoubleRegs:$Rdd32),
   4092 (ins DoubleRegs:$Rss32),
   4093 "$Rdd32 = convert_df2d($Rss32):chop",
   4094 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4095 let Inst{13-5} = 0b000000110;
   4096 let Inst{31-21} = 0b10000000111;
   4097 let isFP = 1;
   4098 let Uses = [USR];
   4099 }
   4100 def F2_conv_df2sf : HInst<
   4101 (outs IntRegs:$Rd32),
   4102 (ins DoubleRegs:$Rss32),
   4103 "$Rd32 = convert_df2sf($Rss32)",
   4104 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4105 let Inst{13-5} = 0b000000001;
   4106 let Inst{31-21} = 0b10001000000;
   4107 let hasNewValue = 1;
   4108 let opNewValue = 0;
   4109 let isFP = 1;
   4110 let Uses = [USR];
   4111 }
   4112 def F2_conv_df2ud : HInst<
   4113 (outs DoubleRegs:$Rdd32),
   4114 (ins DoubleRegs:$Rss32),
   4115 "$Rdd32 = convert_df2ud($Rss32)",
   4116 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4117 let Inst{13-5} = 0b000000001;
   4118 let Inst{31-21} = 0b10000000111;
   4119 let isFP = 1;
   4120 let Uses = [USR];
   4121 }
   4122 def F2_conv_df2ud_chop : HInst<
   4123 (outs DoubleRegs:$Rdd32),
   4124 (ins DoubleRegs:$Rss32),
   4125 "$Rdd32 = convert_df2ud($Rss32):chop",
   4126 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4127 let Inst{13-5} = 0b000000111;
   4128 let Inst{31-21} = 0b10000000111;
   4129 let isFP = 1;
   4130 let Uses = [USR];
   4131 }
   4132 def F2_conv_df2uw : HInst<
   4133 (outs IntRegs:$Rd32),
   4134 (ins DoubleRegs:$Rss32),
   4135 "$Rd32 = convert_df2uw($Rss32)",
   4136 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4137 let Inst{13-5} = 0b000000001;
   4138 let Inst{31-21} = 0b10001000011;
   4139 let hasNewValue = 1;
   4140 let opNewValue = 0;
   4141 let isFP = 1;
   4142 let Uses = [USR];
   4143 }
   4144 def F2_conv_df2uw_chop : HInst<
   4145 (outs IntRegs:$Rd32),
   4146 (ins DoubleRegs:$Rss32),
   4147 "$Rd32 = convert_df2uw($Rss32):chop",
   4148 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4149 let Inst{13-5} = 0b000000001;
   4150 let Inst{31-21} = 0b10001000101;
   4151 let hasNewValue = 1;
   4152 let opNewValue = 0;
   4153 let isFP = 1;
   4154 let Uses = [USR];
   4155 }
   4156 def F2_conv_df2w : HInst<
   4157 (outs IntRegs:$Rd32),
   4158 (ins DoubleRegs:$Rss32),
   4159 "$Rd32 = convert_df2w($Rss32)",
   4160 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4161 let Inst{13-5} = 0b000000001;
   4162 let Inst{31-21} = 0b10001000100;
   4163 let hasNewValue = 1;
   4164 let opNewValue = 0;
   4165 let isFP = 1;
   4166 let Uses = [USR];
   4167 }
   4168 def F2_conv_df2w_chop : HInst<
   4169 (outs IntRegs:$Rd32),
   4170 (ins DoubleRegs:$Rss32),
   4171 "$Rd32 = convert_df2w($Rss32):chop",
   4172 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4173 let Inst{13-5} = 0b000000001;
   4174 let Inst{31-21} = 0b10001000111;
   4175 let hasNewValue = 1;
   4176 let opNewValue = 0;
   4177 let isFP = 1;
   4178 let Uses = [USR];
   4179 }
   4180 def F2_conv_sf2d : HInst<
   4181 (outs DoubleRegs:$Rdd32),
   4182 (ins IntRegs:$Rs32),
   4183 "$Rdd32 = convert_sf2d($Rs32)",
   4184 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4185 let Inst{13-5} = 0b000000100;
   4186 let Inst{31-21} = 0b10000100100;
   4187 let isFP = 1;
   4188 let Uses = [USR];
   4189 }
   4190 def F2_conv_sf2d_chop : HInst<
   4191 (outs DoubleRegs:$Rdd32),
   4192 (ins IntRegs:$Rs32),
   4193 "$Rdd32 = convert_sf2d($Rs32):chop",
   4194 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4195 let Inst{13-5} = 0b000000110;
   4196 let Inst{31-21} = 0b10000100100;
   4197 let isFP = 1;
   4198 let Uses = [USR];
   4199 }
   4200 def F2_conv_sf2df : HInst<
   4201 (outs DoubleRegs:$Rdd32),
   4202 (ins IntRegs:$Rs32),
   4203 "$Rdd32 = convert_sf2df($Rs32)",
   4204 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4205 let Inst{13-5} = 0b000000000;
   4206 let Inst{31-21} = 0b10000100100;
   4207 let isFP = 1;
   4208 let Uses = [USR];
   4209 }
   4210 def F2_conv_sf2ud : HInst<
   4211 (outs DoubleRegs:$Rdd32),
   4212 (ins IntRegs:$Rs32),
   4213 "$Rdd32 = convert_sf2ud($Rs32)",
   4214 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4215 let Inst{13-5} = 0b000000011;
   4216 let Inst{31-21} = 0b10000100100;
   4217 let isFP = 1;
   4218 let Uses = [USR];
   4219 }
   4220 def F2_conv_sf2ud_chop : HInst<
   4221 (outs DoubleRegs:$Rdd32),
   4222 (ins IntRegs:$Rs32),
   4223 "$Rdd32 = convert_sf2ud($Rs32):chop",
   4224 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4225 let Inst{13-5} = 0b000000101;
   4226 let Inst{31-21} = 0b10000100100;
   4227 let isFP = 1;
   4228 let Uses = [USR];
   4229 }
   4230 def F2_conv_sf2uw : HInst<
   4231 (outs IntRegs:$Rd32),
   4232 (ins IntRegs:$Rs32),
   4233 "$Rd32 = convert_sf2uw($Rs32)",
   4234 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4235 let Inst{13-5} = 0b000000000;
   4236 let Inst{31-21} = 0b10001011011;
   4237 let hasNewValue = 1;
   4238 let opNewValue = 0;
   4239 let isFP = 1;
   4240 let Uses = [USR];
   4241 }
   4242 def F2_conv_sf2uw_chop : HInst<
   4243 (outs IntRegs:$Rd32),
   4244 (ins IntRegs:$Rs32),
   4245 "$Rd32 = convert_sf2uw($Rs32):chop",
   4246 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4247 let Inst{13-5} = 0b000000001;
   4248 let Inst{31-21} = 0b10001011011;
   4249 let hasNewValue = 1;
   4250 let opNewValue = 0;
   4251 let isFP = 1;
   4252 let Uses = [USR];
   4253 }
   4254 def F2_conv_sf2w : HInst<
   4255 (outs IntRegs:$Rd32),
   4256 (ins IntRegs:$Rs32),
   4257 "$Rd32 = convert_sf2w($Rs32)",
   4258 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4259 let Inst{13-5} = 0b000000000;
   4260 let Inst{31-21} = 0b10001011100;
   4261 let hasNewValue = 1;
   4262 let opNewValue = 0;
   4263 let isFP = 1;
   4264 let Uses = [USR];
   4265 }
   4266 def F2_conv_sf2w_chop : HInst<
   4267 (outs IntRegs:$Rd32),
   4268 (ins IntRegs:$Rs32),
   4269 "$Rd32 = convert_sf2w($Rs32):chop",
   4270 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4271 let Inst{13-5} = 0b000000001;
   4272 let Inst{31-21} = 0b10001011100;
   4273 let hasNewValue = 1;
   4274 let opNewValue = 0;
   4275 let isFP = 1;
   4276 let Uses = [USR];
   4277 }
   4278 def F2_conv_ud2df : HInst<
   4279 (outs DoubleRegs:$Rdd32),
   4280 (ins DoubleRegs:$Rss32),
   4281 "$Rdd32 = convert_ud2df($Rss32)",
   4282 tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> {
   4283 let Inst{13-5} = 0b000000010;
   4284 let Inst{31-21} = 0b10000000111;
   4285 let isFP = 1;
   4286 let Uses = [USR];
   4287 }
   4288 def F2_conv_ud2sf : HInst<
   4289 (outs IntRegs:$Rd32),
   4290 (ins DoubleRegs:$Rss32),
   4291 "$Rd32 = convert_ud2sf($Rss32)",
   4292 tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   4293 let Inst{13-5} = 0b000000001;
   4294 let Inst{31-21} = 0b10001000001;
   4295 let hasNewValue = 1;
   4296 let opNewValue = 0;
   4297 let isFP = 1;
   4298 let Uses = [USR];
   4299 }
   4300 def F2_conv_uw2df : HInst<
   4301 (outs DoubleRegs:$Rdd32),
   4302 (ins IntRegs:$Rs32),
   4303 "$Rdd32 = convert_uw2df($Rs32)",
   4304 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4305 let Inst{13-5} = 0b000000001;
   4306 let Inst{31-21} = 0b10000100100;
   4307 let isFP = 1;
   4308 let Uses = [USR];
   4309 }
   4310 def F2_conv_uw2sf : HInst<
   4311 (outs IntRegs:$Rd32),
   4312 (ins IntRegs:$Rs32),
   4313 "$Rd32 = convert_uw2sf($Rs32)",
   4314 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4315 let Inst{13-5} = 0b000000000;
   4316 let Inst{31-21} = 0b10001011001;
   4317 let hasNewValue = 1;
   4318 let opNewValue = 0;
   4319 let isFP = 1;
   4320 let Uses = [USR];
   4321 }
   4322 def F2_conv_w2df : HInst<
   4323 (outs DoubleRegs:$Rdd32),
   4324 (ins IntRegs:$Rs32),
   4325 "$Rdd32 = convert_w2df($Rs32)",
   4326 tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> {
   4327 let Inst{13-5} = 0b000000010;
   4328 let Inst{31-21} = 0b10000100100;
   4329 let isFP = 1;
   4330 let Uses = [USR];
   4331 }
   4332 def F2_conv_w2sf : HInst<
   4333 (outs IntRegs:$Rd32),
   4334 (ins IntRegs:$Rs32),
   4335 "$Rd32 = convert_w2sf($Rs32)",
   4336 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4337 let Inst{13-5} = 0b000000000;
   4338 let Inst{31-21} = 0b10001011010;
   4339 let hasNewValue = 1;
   4340 let opNewValue = 0;
   4341 let isFP = 1;
   4342 let Uses = [USR];
   4343 }
   4344 def F2_dfclass : HInst<
   4345 (outs PredRegs:$Pd4),
   4346 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
   4347 "$Pd4 = dfclass($Rss32,#$Ii)",
   4348 tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5]> {
   4349 let Inst{4-2} = 0b100;
   4350 let Inst{13-10} = 0b0000;
   4351 let Inst{31-21} = 0b11011100100;
   4352 let isFP = 1;
   4353 let Uses = [USR];
   4354 }
   4355 def F2_dfcmpeq : HInst<
   4356 (outs PredRegs:$Pd4),
   4357 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   4358 "$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
   4359 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> {
   4360 let Inst{7-2} = 0b000000;
   4361 let Inst{13-13} = 0b0;
   4362 let Inst{31-21} = 0b11010010111;
   4363 let isFP = 1;
   4364 let Uses = [USR];
   4365 let isCompare = 1;
   4366 }
   4367 def F2_dfcmpge : HInst<
   4368 (outs PredRegs:$Pd4),
   4369 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   4370 "$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
   4371 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> {
   4372 let Inst{7-2} = 0b010000;
   4373 let Inst{13-13} = 0b0;
   4374 let Inst{31-21} = 0b11010010111;
   4375 let isFP = 1;
   4376 let Uses = [USR];
   4377 let isCompare = 1;
   4378 }
   4379 def F2_dfcmpgt : HInst<
   4380 (outs PredRegs:$Pd4),
   4381 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   4382 "$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
   4383 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> {
   4384 let Inst{7-2} = 0b001000;
   4385 let Inst{13-13} = 0b0;
   4386 let Inst{31-21} = 0b11010010111;
   4387 let isFP = 1;
   4388 let Uses = [USR];
   4389 let isCompare = 1;
   4390 }
   4391 def F2_dfcmpuo : HInst<
   4392 (outs PredRegs:$Pd4),
   4393 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   4394 "$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
   4395 tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> {
   4396 let Inst{7-2} = 0b011000;
   4397 let Inst{13-13} = 0b0;
   4398 let Inst{31-21} = 0b11010010111;
   4399 let isFP = 1;
   4400 let Uses = [USR];
   4401 let isCompare = 1;
   4402 }
   4403 def F2_dfimm_n : HInst<
   4404 (outs DoubleRegs:$Rdd32),
   4405 (ins u10_0Imm:$Ii),
   4406 "$Rdd32 = dfmake(#$Ii):neg",
   4407 tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> {
   4408 let Inst{20-16} = 0b00000;
   4409 let Inst{31-22} = 0b1101100101;
   4410 let prefersSlot3 = 1;
   4411 }
   4412 def F2_dfimm_p : HInst<
   4413 (outs DoubleRegs:$Rdd32),
   4414 (ins u10_0Imm:$Ii),
   4415 "$Rdd32 = dfmake(#$Ii):pos",
   4416 tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> {
   4417 let Inst{20-16} = 0b00000;
   4418 let Inst{31-22} = 0b1101100100;
   4419 let prefersSlot3 = 1;
   4420 }
   4421 def F2_sfadd : HInst<
   4422 (outs IntRegs:$Rd32),
   4423 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4424 "$Rd32 = sfadd($Rs32,$Rt32)",
   4425 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4426 let Inst{7-5} = 0b000;
   4427 let Inst{13-13} = 0b0;
   4428 let Inst{31-21} = 0b11101011000;
   4429 let hasNewValue = 1;
   4430 let opNewValue = 0;
   4431 let isFP = 1;
   4432 let Uses = [USR];
   4433 let isCommutable = 1;
   4434 }
   4435 def F2_sfclass : HInst<
   4436 (outs PredRegs:$Pd4),
   4437 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   4438 "$Pd4 = sfclass($Rs32,#$Ii)",
   4439 tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5]> {
   4440 let Inst{7-2} = 0b000000;
   4441 let Inst{13-13} = 0b0;
   4442 let Inst{31-21} = 0b10000101111;
   4443 let isFP = 1;
   4444 let Uses = [USR];
   4445 }
   4446 def F2_sfcmpeq : HInst<
   4447 (outs PredRegs:$Pd4),
   4448 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4449 "$Pd4 = sfcmp.eq($Rs32,$Rt32)",
   4450 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> {
   4451 let Inst{7-2} = 0b011000;
   4452 let Inst{13-13} = 0b0;
   4453 let Inst{31-21} = 0b11000111111;
   4454 let isFP = 1;
   4455 let Uses = [USR];
   4456 let isCompare = 1;
   4457 }
   4458 def F2_sfcmpge : HInst<
   4459 (outs PredRegs:$Pd4),
   4460 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4461 "$Pd4 = sfcmp.ge($Rs32,$Rt32)",
   4462 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> {
   4463 let Inst{7-2} = 0b000000;
   4464 let Inst{13-13} = 0b0;
   4465 let Inst{31-21} = 0b11000111111;
   4466 let isFP = 1;
   4467 let Uses = [USR];
   4468 let isCompare = 1;
   4469 }
   4470 def F2_sfcmpgt : HInst<
   4471 (outs PredRegs:$Pd4),
   4472 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4473 "$Pd4 = sfcmp.gt($Rs32,$Rt32)",
   4474 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> {
   4475 let Inst{7-2} = 0b100000;
   4476 let Inst{13-13} = 0b0;
   4477 let Inst{31-21} = 0b11000111111;
   4478 let isFP = 1;
   4479 let Uses = [USR];
   4480 let isCompare = 1;
   4481 }
   4482 def F2_sfcmpuo : HInst<
   4483 (outs PredRegs:$Pd4),
   4484 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4485 "$Pd4 = sfcmp.uo($Rs32,$Rt32)",
   4486 tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> {
   4487 let Inst{7-2} = 0b001000;
   4488 let Inst{13-13} = 0b0;
   4489 let Inst{31-21} = 0b11000111111;
   4490 let isFP = 1;
   4491 let Uses = [USR];
   4492 let isCompare = 1;
   4493 }
   4494 def F2_sffixupd : HInst<
   4495 (outs IntRegs:$Rd32),
   4496 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4497 "$Rd32 = sffixupd($Rs32,$Rt32)",
   4498 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4499 let Inst{7-5} = 0b001;
   4500 let Inst{13-13} = 0b0;
   4501 let Inst{31-21} = 0b11101011110;
   4502 let hasNewValue = 1;
   4503 let opNewValue = 0;
   4504 let isFP = 1;
   4505 }
   4506 def F2_sffixupn : HInst<
   4507 (outs IntRegs:$Rd32),
   4508 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4509 "$Rd32 = sffixupn($Rs32,$Rt32)",
   4510 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4511 let Inst{7-5} = 0b000;
   4512 let Inst{13-13} = 0b0;
   4513 let Inst{31-21} = 0b11101011110;
   4514 let hasNewValue = 1;
   4515 let opNewValue = 0;
   4516 let isFP = 1;
   4517 }
   4518 def F2_sffixupr : HInst<
   4519 (outs IntRegs:$Rd32),
   4520 (ins IntRegs:$Rs32),
   4521 "$Rd32 = sffixupr($Rs32)",
   4522 tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> {
   4523 let Inst{13-5} = 0b000000000;
   4524 let Inst{31-21} = 0b10001011101;
   4525 let hasNewValue = 1;
   4526 let opNewValue = 0;
   4527 let isFP = 1;
   4528 }
   4529 def F2_sffma : HInst<
   4530 (outs IntRegs:$Rx32),
   4531 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   4532 "$Rx32 += sfmpy($Rs32,$Rt32)",
   4533 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> {
   4534 let Inst{7-5} = 0b100;
   4535 let Inst{13-13} = 0b0;
   4536 let Inst{31-21} = 0b11101111000;
   4537 let hasNewValue = 1;
   4538 let opNewValue = 0;
   4539 let isFP = 1;
   4540 let Uses = [USR];
   4541 let Constraints = "$Rx32 = $Rx32in";
   4542 }
   4543 def F2_sffma_lib : HInst<
   4544 (outs IntRegs:$Rx32),
   4545 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   4546 "$Rx32 += sfmpy($Rs32,$Rt32):lib",
   4547 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> {
   4548 let Inst{7-5} = 0b110;
   4549 let Inst{13-13} = 0b0;
   4550 let Inst{31-21} = 0b11101111000;
   4551 let hasNewValue = 1;
   4552 let opNewValue = 0;
   4553 let isFP = 1;
   4554 let Uses = [USR];
   4555 let Constraints = "$Rx32 = $Rx32in";
   4556 }
   4557 def F2_sffma_sc : HInst<
   4558 (outs IntRegs:$Rx32),
   4559 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
   4560 "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
   4561 tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5]> {
   4562 let Inst{7-7} = 0b1;
   4563 let Inst{13-13} = 0b0;
   4564 let Inst{31-21} = 0b11101111011;
   4565 let hasNewValue = 1;
   4566 let opNewValue = 0;
   4567 let isFP = 1;
   4568 let Uses = [USR];
   4569 let Constraints = "$Rx32 = $Rx32in";
   4570 }
   4571 def F2_sffms : HInst<
   4572 (outs IntRegs:$Rx32),
   4573 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   4574 "$Rx32 -= sfmpy($Rs32,$Rt32)",
   4575 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> {
   4576 let Inst{7-5} = 0b101;
   4577 let Inst{13-13} = 0b0;
   4578 let Inst{31-21} = 0b11101111000;
   4579 let hasNewValue = 1;
   4580 let opNewValue = 0;
   4581 let isFP = 1;
   4582 let Uses = [USR];
   4583 let Constraints = "$Rx32 = $Rx32in";
   4584 }
   4585 def F2_sffms_lib : HInst<
   4586 (outs IntRegs:$Rx32),
   4587 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   4588 "$Rx32 -= sfmpy($Rs32,$Rt32):lib",
   4589 tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> {
   4590 let Inst{7-5} = 0b111;
   4591 let Inst{13-13} = 0b0;
   4592 let Inst{31-21} = 0b11101111000;
   4593 let hasNewValue = 1;
   4594 let opNewValue = 0;
   4595 let isFP = 1;
   4596 let Uses = [USR];
   4597 let Constraints = "$Rx32 = $Rx32in";
   4598 }
   4599 def F2_sfimm_n : HInst<
   4600 (outs IntRegs:$Rd32),
   4601 (ins u10_0Imm:$Ii),
   4602 "$Rd32 = sfmake(#$Ii):neg",
   4603 tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> {
   4604 let Inst{20-16} = 0b00000;
   4605 let Inst{31-22} = 0b1101011001;
   4606 let hasNewValue = 1;
   4607 let opNewValue = 0;
   4608 let prefersSlot3 = 1;
   4609 }
   4610 def F2_sfimm_p : HInst<
   4611 (outs IntRegs:$Rd32),
   4612 (ins u10_0Imm:$Ii),
   4613 "$Rd32 = sfmake(#$Ii):pos",
   4614 tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> {
   4615 let Inst{20-16} = 0b00000;
   4616 let Inst{31-22} = 0b1101011000;
   4617 let hasNewValue = 1;
   4618 let opNewValue = 0;
   4619 let prefersSlot3 = 1;
   4620 }
   4621 def F2_sfinvsqrta : HInst<
   4622 (outs IntRegs:$Rd32, PredRegs:$Pe4),
   4623 (ins IntRegs:$Rs32),
   4624 "$Rd32,$Pe4 = sfinvsqrta($Rs32)",
   4625 tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5]> {
   4626 let Inst{13-7} = 0b0000000;
   4627 let Inst{31-21} = 0b10001011111;
   4628 let hasNewValue = 1;
   4629 let opNewValue = 0;
   4630 let isFP = 1;
   4631 let isPredicateLate = 1;
   4632 }
   4633 def F2_sfmax : HInst<
   4634 (outs IntRegs:$Rd32),
   4635 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4636 "$Rd32 = sfmax($Rs32,$Rt32)",
   4637 tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4638 let Inst{7-5} = 0b000;
   4639 let Inst{13-13} = 0b0;
   4640 let Inst{31-21} = 0b11101011100;
   4641 let hasNewValue = 1;
   4642 let opNewValue = 0;
   4643 let isFP = 1;
   4644 let prefersSlot3 = 1;
   4645 let Uses = [USR];
   4646 }
   4647 def F2_sfmin : HInst<
   4648 (outs IntRegs:$Rd32),
   4649 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4650 "$Rd32 = sfmin($Rs32,$Rt32)",
   4651 tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4652 let Inst{7-5} = 0b001;
   4653 let Inst{13-13} = 0b0;
   4654 let Inst{31-21} = 0b11101011100;
   4655 let hasNewValue = 1;
   4656 let opNewValue = 0;
   4657 let isFP = 1;
   4658 let prefersSlot3 = 1;
   4659 let Uses = [USR];
   4660 }
   4661 def F2_sfmpy : HInst<
   4662 (outs IntRegs:$Rd32),
   4663 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4664 "$Rd32 = sfmpy($Rs32,$Rt32)",
   4665 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4666 let Inst{7-5} = 0b000;
   4667 let Inst{13-13} = 0b0;
   4668 let Inst{31-21} = 0b11101011010;
   4669 let hasNewValue = 1;
   4670 let opNewValue = 0;
   4671 let isFP = 1;
   4672 let Uses = [USR];
   4673 let isCommutable = 1;
   4674 }
   4675 def F2_sfrecipa : HInst<
   4676 (outs IntRegs:$Rd32, PredRegs:$Pe4),
   4677 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4678 "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
   4679 tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5]> {
   4680 let Inst{7-7} = 0b1;
   4681 let Inst{13-13} = 0b0;
   4682 let Inst{31-21} = 0b11101011111;
   4683 let hasNewValue = 1;
   4684 let opNewValue = 0;
   4685 let isFP = 1;
   4686 let isPredicateLate = 1;
   4687 }
   4688 def F2_sfsub : HInst<
   4689 (outs IntRegs:$Rd32),
   4690 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   4691 "$Rd32 = sfsub($Rs32,$Rt32)",
   4692 tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> {
   4693 let Inst{7-5} = 0b001;
   4694 let Inst{13-13} = 0b0;
   4695 let Inst{31-21} = 0b11101011000;
   4696 let hasNewValue = 1;
   4697 let opNewValue = 0;
   4698 let isFP = 1;
   4699 let Uses = [USR];
   4700 }
   4701 def G4_tfrgcpp : HInst<
   4702 (outs DoubleRegs:$Rdd32),
   4703 (ins GuestRegs64:$Gss32),
   4704 "$Rdd32 = $Gss32",
   4705 tc_6fa4db47, TypeCR>, Enc_0aa344 {
   4706 let Inst{13-5} = 0b000000000;
   4707 let Inst{31-21} = 0b01101000001;
   4708 }
   4709 def G4_tfrgcrr : HInst<
   4710 (outs IntRegs:$Rd32),
   4711 (ins GuestRegs:$Gs32),
   4712 "$Rd32 = $Gs32",
   4713 tc_6fa4db47, TypeCR>, Enc_44271f {
   4714 let Inst{13-5} = 0b000000000;
   4715 let Inst{31-21} = 0b01101010001;
   4716 let hasNewValue = 1;
   4717 let opNewValue = 0;
   4718 }
   4719 def G4_tfrgpcp : HInst<
   4720 (outs GuestRegs64:$Gdd32),
   4721 (ins DoubleRegs:$Rss32),
   4722 "$Gdd32 = $Rss32",
   4723 tc_994333cd, TypeCR>, Enc_ed5027 {
   4724 let Inst{13-5} = 0b000000000;
   4725 let Inst{31-21} = 0b01100011000;
   4726 let hasNewValue = 1;
   4727 let opNewValue = 0;
   4728 }
   4729 def G4_tfrgrcr : HInst<
   4730 (outs GuestRegs:$Gd32),
   4731 (ins IntRegs:$Rs32),
   4732 "$Gd32 = $Rs32",
   4733 tc_994333cd, TypeCR>, Enc_621fba {
   4734 let Inst{13-5} = 0b000000000;
   4735 let Inst{31-21} = 0b01100010000;
   4736 let hasNewValue = 1;
   4737 let opNewValue = 0;
   4738 }
   4739 def J2_call : HInst<
   4740 (outs),
   4741 (ins a30_2Imm:$Ii),
   4742 "call $Ii",
   4743 tc_a27582fa, TypeJ>, Enc_81ac1d, PredRel {
   4744 let Inst{0-0} = 0b0;
   4745 let Inst{31-25} = 0b0101101;
   4746 let isCall = 1;
   4747 let prefersSlot3 = 1;
   4748 let cofRelax2 = 1;
   4749 let cofMax1 = 1;
   4750 let Uses = [R29];
   4751 let Defs = [PC, R31];
   4752 let BaseOpcode = "J2_call";
   4753 let isPredicable = 1;
   4754 let hasSideEffects = 1;
   4755 let isExtendable = 1;
   4756 let opExtendable = 0;
   4757 let isExtentSigned = 1;
   4758 let opExtentBits = 24;
   4759 let opExtentAlign = 2;
   4760 }
   4761 def J2_callf : HInst<
   4762 (outs),
   4763 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
   4764 "if (!$Pu4) call $Ii",
   4765 tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
   4766 let Inst{0-0} = 0b0;
   4767 let Inst{12-10} = 0b000;
   4768 let Inst{21-21} = 0b1;
   4769 let Inst{31-24} = 0b01011101;
   4770 let isPredicated = 1;
   4771 let isPredicatedFalse = 1;
   4772 let isCall = 1;
   4773 let prefersSlot3 = 1;
   4774 let cofRelax1 = 1;
   4775 let cofRelax2 = 1;
   4776 let cofMax1 = 1;
   4777 let Uses = [R29];
   4778 let Defs = [PC, R31];
   4779 let BaseOpcode = "J2_call";
   4780 let hasSideEffects = 1;
   4781 let isTaken = Inst{12};
   4782 let isExtendable = 1;
   4783 let opExtendable = 1;
   4784 let isExtentSigned = 1;
   4785 let opExtentBits = 17;
   4786 let opExtentAlign = 2;
   4787 }
   4788 def J2_callr : HInst<
   4789 (outs),
   4790 (ins IntRegs:$Rs32),
   4791 "callr $Rs32",
   4792 tc_15411484, TypeJ>, Enc_ecbcc8 {
   4793 let Inst{13-0} = 0b00000000000000;
   4794 let Inst{31-21} = 0b01010000101;
   4795 let isCall = 1;
   4796 let prefersSlot3 = 1;
   4797 let cofMax1 = 1;
   4798 let Uses = [R29];
   4799 let Defs = [PC, R31];
   4800 let hasSideEffects = 1;
   4801 }
   4802 def J2_callrf : HInst<
   4803 (outs),
   4804 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   4805 "if (!$Pu4) callr $Rs32",
   4806 tc_10b97e27, TypeJ>, Enc_88d4d9 {
   4807 let Inst{7-0} = 0b00000000;
   4808 let Inst{13-10} = 0b0000;
   4809 let Inst{31-21} = 0b01010001001;
   4810 let isPredicated = 1;
   4811 let isPredicatedFalse = 1;
   4812 let isCall = 1;
   4813 let prefersSlot3 = 1;
   4814 let cofMax1 = 1;
   4815 let Uses = [R29];
   4816 let Defs = [PC, R31];
   4817 let hasSideEffects = 1;
   4818 let isTaken = Inst{12};
   4819 }
   4820 def J2_callrt : HInst<
   4821 (outs),
   4822 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   4823 "if ($Pu4) callr $Rs32",
   4824 tc_10b97e27, TypeJ>, Enc_88d4d9 {
   4825 let Inst{7-0} = 0b00000000;
   4826 let Inst{13-10} = 0b0000;
   4827 let Inst{31-21} = 0b01010001000;
   4828 let isPredicated = 1;
   4829 let isCall = 1;
   4830 let prefersSlot3 = 1;
   4831 let cofMax1 = 1;
   4832 let Uses = [R29];
   4833 let Defs = [PC, R31];
   4834 let hasSideEffects = 1;
   4835 let isTaken = Inst{12};
   4836 }
   4837 def J2_callt : HInst<
   4838 (outs),
   4839 (ins PredRegs:$Pu4, a30_2Imm:$Ii),
   4840 "if ($Pu4) call $Ii",
   4841 tc_2f185f5c, TypeJ>, Enc_daea09, PredRel {
   4842 let Inst{0-0} = 0b0;
   4843 let Inst{12-10} = 0b000;
   4844 let Inst{21-21} = 0b0;
   4845 let Inst{31-24} = 0b01011101;
   4846 let isPredicated = 1;
   4847 let isCall = 1;
   4848 let prefersSlot3 = 1;
   4849 let cofRelax1 = 1;
   4850 let cofRelax2 = 1;
   4851 let cofMax1 = 1;
   4852 let Uses = [R29];
   4853 let Defs = [PC, R31];
   4854 let BaseOpcode = "J2_call";
   4855 let hasSideEffects = 1;
   4856 let isTaken = Inst{12};
   4857 let isExtendable = 1;
   4858 let opExtendable = 1;
   4859 let isExtentSigned = 1;
   4860 let opExtentBits = 17;
   4861 let opExtentAlign = 2;
   4862 }
   4863 def J2_endloop0 : HInst<
   4864 (outs),
   4865 (ins),
   4866 "endloop0",
   4867 tc_52d7bbea, TypeJ> {
   4868 let Uses = [LC0, SA0];
   4869 let Defs = [LC0, P3, PC, USR];
   4870 let isBranch = 1;
   4871 let isTerminator = 1;
   4872 let isPseudo = 1;
   4873 }
   4874 def J2_endloop01 : HInst<
   4875 (outs),
   4876 (ins),
   4877 "endloop01",
   4878 tc_52d7bbea, TypeJ> {
   4879 let Uses = [LC0, LC1, SA0, SA1];
   4880 let Defs = [LC0, LC1, P3, PC, USR];
   4881 let isPseudo = 1;
   4882 }
   4883 def J2_endloop1 : HInst<
   4884 (outs),
   4885 (ins),
   4886 "endloop1",
   4887 tc_52d7bbea, TypeJ> {
   4888 let Uses = [LC1, SA1];
   4889 let Defs = [LC1, PC];
   4890 let isBranch = 1;
   4891 let isTerminator = 1;
   4892 let isPseudo = 1;
   4893 }
   4894 def J2_jump : HInst<
   4895 (outs),
   4896 (ins b30_2Imm:$Ii),
   4897 "jump $Ii",
   4898 tc_3669266a, TypeJ>, Enc_81ac1d, PredNewRel {
   4899 let Inst{0-0} = 0b0;
   4900 let Inst{31-25} = 0b0101100;
   4901 let isTerminator = 1;
   4902 let isBranch = 1;
   4903 let cofRelax2 = 1;
   4904 let cofMax1 = 1;
   4905 let Defs = [PC];
   4906 let InputType = "imm";
   4907 let BaseOpcode = "J2_jump";
   4908 let isBarrier = 1;
   4909 let isPredicable = 1;
   4910 let isExtendable = 1;
   4911 let opExtendable = 0;
   4912 let isExtentSigned = 1;
   4913 let opExtentBits = 24;
   4914 let opExtentAlign = 2;
   4915 }
   4916 def J2_jumpf : HInst<
   4917 (outs),
   4918 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   4919 "if (!$Pu4) jump:nt $Ii",
   4920 tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
   4921 let Inst{0-0} = 0b0;
   4922 let Inst{12-10} = 0b000;
   4923 let Inst{21-21} = 0b1;
   4924 let Inst{31-24} = 0b01011100;
   4925 let isPredicated = 1;
   4926 let isPredicatedFalse = 1;
   4927 let isTerminator = 1;
   4928 let isBranch = 1;
   4929 let cofRelax1 = 1;
   4930 let cofRelax2 = 1;
   4931 let cofMax1 = 1;
   4932 let Defs = [PC];
   4933 let InputType = "imm";
   4934 let BaseOpcode = "J2_jump";
   4935 let isTaken = Inst{12};
   4936 let isExtendable = 1;
   4937 let opExtendable = 1;
   4938 let isExtentSigned = 1;
   4939 let opExtentBits = 17;
   4940 let opExtentAlign = 2;
   4941 }
   4942 def J2_jumpf_nopred_map : HInst<
   4943 (outs),
   4944 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
   4945 "if (!$Pu4) jump $Ii",
   4946 tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60]> {
   4947 let isPseudo = 1;
   4948 let isCodeGenOnly = 1;
   4949 }
   4950 def J2_jumpfnew : HInst<
   4951 (outs),
   4952 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   4953 "if (!$Pu4.new) jump:nt $Ii",
   4954 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
   4955 let Inst{0-0} = 0b0;
   4956 let Inst{12-10} = 0b010;
   4957 let Inst{21-21} = 0b1;
   4958 let Inst{31-24} = 0b01011100;
   4959 let isPredicated = 1;
   4960 let isPredicatedFalse = 1;
   4961 let isTerminator = 1;
   4962 let isBranch = 1;
   4963 let isPredicatedNew = 1;
   4964 let cofRelax1 = 1;
   4965 let cofRelax2 = 1;
   4966 let cofMax1 = 1;
   4967 let Defs = [PC];
   4968 let InputType = "imm";
   4969 let BaseOpcode = "J2_jump";
   4970 let isTaken = Inst{12};
   4971 let isExtendable = 1;
   4972 let opExtendable = 1;
   4973 let isExtentSigned = 1;
   4974 let opExtentBits = 17;
   4975 let opExtentAlign = 2;
   4976 }
   4977 def J2_jumpfnewpt : HInst<
   4978 (outs),
   4979 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   4980 "if (!$Pu4.new) jump:t $Ii",
   4981 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
   4982 let Inst{0-0} = 0b0;
   4983 let Inst{12-10} = 0b110;
   4984 let Inst{21-21} = 0b1;
   4985 let Inst{31-24} = 0b01011100;
   4986 let isPredicated = 1;
   4987 let isPredicatedFalse = 1;
   4988 let isTerminator = 1;
   4989 let isBranch = 1;
   4990 let isPredicatedNew = 1;
   4991 let cofRelax1 = 1;
   4992 let cofRelax2 = 1;
   4993 let cofMax1 = 1;
   4994 let Defs = [PC];
   4995 let InputType = "imm";
   4996 let BaseOpcode = "J2_jump";
   4997 let isTaken = Inst{12};
   4998 let isExtendable = 1;
   4999 let opExtendable = 1;
   5000 let isExtentSigned = 1;
   5001 let opExtentBits = 17;
   5002 let opExtentAlign = 2;
   5003 }
   5004 def J2_jumpfpt : HInst<
   5005 (outs),
   5006 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   5007 "if (!$Pu4) jump:t $Ii",
   5008 tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
   5009 let Inst{0-0} = 0b0;
   5010 let Inst{12-10} = 0b100;
   5011 let Inst{21-21} = 0b1;
   5012 let Inst{31-24} = 0b01011100;
   5013 let isPredicated = 1;
   5014 let isPredicatedFalse = 1;
   5015 let isTerminator = 1;
   5016 let isBranch = 1;
   5017 let cofRelax1 = 1;
   5018 let cofRelax2 = 1;
   5019 let cofMax1 = 1;
   5020 let Defs = [PC];
   5021 let InputType = "imm";
   5022 let BaseOpcode = "J2_jump";
   5023 let isTaken = Inst{12};
   5024 let isExtendable = 1;
   5025 let opExtendable = 1;
   5026 let isExtentSigned = 1;
   5027 let opExtentBits = 17;
   5028 let opExtentAlign = 2;
   5029 }
   5030 def J2_jumpr : HInst<
   5031 (outs),
   5032 (ins IntRegs:$Rs32),
   5033 "jumpr $Rs32",
   5034 tc_9faf76ae, TypeJ>, Enc_ecbcc8, PredNewRel {
   5035 let Inst{13-0} = 0b00000000000000;
   5036 let Inst{31-21} = 0b01010010100;
   5037 let isTerminator = 1;
   5038 let isIndirectBranch = 1;
   5039 let isBranch = 1;
   5040 let cofMax1 = 1;
   5041 let Defs = [PC];
   5042 let InputType = "reg";
   5043 let BaseOpcode = "J2_jumpr";
   5044 let isBarrier = 1;
   5045 let isPredicable = 1;
   5046 }
   5047 def J2_jumprf : HInst<
   5048 (outs),
   5049 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5050 "if (!$Pu4) jumpr:nt $Rs32",
   5051 tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
   5052 let Inst{7-0} = 0b00000000;
   5053 let Inst{13-10} = 0b0000;
   5054 let Inst{31-21} = 0b01010011011;
   5055 let isPredicated = 1;
   5056 let isPredicatedFalse = 1;
   5057 let isTerminator = 1;
   5058 let isIndirectBranch = 1;
   5059 let isBranch = 1;
   5060 let cofMax1 = 1;
   5061 let Defs = [PC];
   5062 let InputType = "reg";
   5063 let BaseOpcode = "J2_jumpr";
   5064 let isTaken = Inst{12};
   5065 }
   5066 def J2_jumprf_nopred_map : HInst<
   5067 (outs),
   5068 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5069 "if (!$Pu4) jumpr $Rs32",
   5070 tc_e0739b8c, TypeMAPPING>, Requires<[HasV60]> {
   5071 let isPseudo = 1;
   5072 let isCodeGenOnly = 1;
   5073 }
   5074 def J2_jumprfnew : HInst<
   5075 (outs),
   5076 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5077 "if (!$Pu4.new) jumpr:nt $Rs32",
   5078 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
   5079 let Inst{7-0} = 0b00000000;
   5080 let Inst{13-10} = 0b0010;
   5081 let Inst{31-21} = 0b01010011011;
   5082 let isPredicated = 1;
   5083 let isPredicatedFalse = 1;
   5084 let isTerminator = 1;
   5085 let isIndirectBranch = 1;
   5086 let isBranch = 1;
   5087 let isPredicatedNew = 1;
   5088 let cofMax1 = 1;
   5089 let Defs = [PC];
   5090 let InputType = "reg";
   5091 let BaseOpcode = "J2_jumpr";
   5092 let isTaken = Inst{12};
   5093 }
   5094 def J2_jumprfnewpt : HInst<
   5095 (outs),
   5096 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5097 "if (!$Pu4.new) jumpr:t $Rs32",
   5098 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
   5099 let Inst{7-0} = 0b00000000;
   5100 let Inst{13-10} = 0b0110;
   5101 let Inst{31-21} = 0b01010011011;
   5102 let isPredicated = 1;
   5103 let isPredicatedFalse = 1;
   5104 let isTerminator = 1;
   5105 let isIndirectBranch = 1;
   5106 let isBranch = 1;
   5107 let isPredicatedNew = 1;
   5108 let cofMax1 = 1;
   5109 let Defs = [PC];
   5110 let InputType = "reg";
   5111 let BaseOpcode = "J2_jumpr";
   5112 let isTaken = Inst{12};
   5113 }
   5114 def J2_jumprfpt : HInst<
   5115 (outs),
   5116 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5117 "if (!$Pu4) jumpr:t $Rs32",
   5118 tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
   5119 let Inst{7-0} = 0b00000000;
   5120 let Inst{13-10} = 0b0100;
   5121 let Inst{31-21} = 0b01010011011;
   5122 let isPredicated = 1;
   5123 let isPredicatedFalse = 1;
   5124 let isTerminator = 1;
   5125 let isIndirectBranch = 1;
   5126 let isBranch = 1;
   5127 let cofMax1 = 1;
   5128 let Defs = [PC];
   5129 let InputType = "reg";
   5130 let BaseOpcode = "J2_jumpr";
   5131 let isTaken = Inst{12};
   5132 }
   5133 def J2_jumprgtez : HInst<
   5134 (outs),
   5135 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5136 "if ($Rs32>=#0) jump:nt $Ii",
   5137 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5138 let Inst{0-0} = 0b0;
   5139 let Inst{12-12} = 0b0;
   5140 let Inst{31-22} = 0b0110000101;
   5141 let isPredicated = 1;
   5142 let isTerminator = 1;
   5143 let isBranch = 1;
   5144 let isPredicatedNew = 1;
   5145 let cofRelax1 = 1;
   5146 let cofRelax2 = 1;
   5147 let cofMax1 = 1;
   5148 let Defs = [PC];
   5149 let isTaken = Inst{12};
   5150 }
   5151 def J2_jumprgtezpt : HInst<
   5152 (outs),
   5153 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5154 "if ($Rs32>=#0) jump:t $Ii",
   5155 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5156 let Inst{0-0} = 0b0;
   5157 let Inst{12-12} = 0b1;
   5158 let Inst{31-22} = 0b0110000101;
   5159 let isPredicated = 1;
   5160 let isTerminator = 1;
   5161 let isBranch = 1;
   5162 let isPredicatedNew = 1;
   5163 let cofRelax1 = 1;
   5164 let cofRelax2 = 1;
   5165 let cofMax1 = 1;
   5166 let Defs = [PC];
   5167 let isTaken = Inst{12};
   5168 }
   5169 def J2_jumprltez : HInst<
   5170 (outs),
   5171 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5172 "if ($Rs32<=#0) jump:nt $Ii",
   5173 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5174 let Inst{0-0} = 0b0;
   5175 let Inst{12-12} = 0b0;
   5176 let Inst{31-22} = 0b0110000111;
   5177 let isPredicated = 1;
   5178 let isTerminator = 1;
   5179 let isBranch = 1;
   5180 let isPredicatedNew = 1;
   5181 let cofRelax1 = 1;
   5182 let cofRelax2 = 1;
   5183 let cofMax1 = 1;
   5184 let Defs = [PC];
   5185 let isTaken = Inst{12};
   5186 }
   5187 def J2_jumprltezpt : HInst<
   5188 (outs),
   5189 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5190 "if ($Rs32<=#0) jump:t $Ii",
   5191 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5192 let Inst{0-0} = 0b0;
   5193 let Inst{12-12} = 0b1;
   5194 let Inst{31-22} = 0b0110000111;
   5195 let isPredicated = 1;
   5196 let isTerminator = 1;
   5197 let isBranch = 1;
   5198 let isPredicatedNew = 1;
   5199 let cofRelax1 = 1;
   5200 let cofRelax2 = 1;
   5201 let cofMax1 = 1;
   5202 let Defs = [PC];
   5203 let isTaken = Inst{12};
   5204 }
   5205 def J2_jumprnz : HInst<
   5206 (outs),
   5207 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5208 "if ($Rs32==#0) jump:nt $Ii",
   5209 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5210 let Inst{0-0} = 0b0;
   5211 let Inst{12-12} = 0b0;
   5212 let Inst{31-22} = 0b0110000110;
   5213 let isPredicated = 1;
   5214 let isTerminator = 1;
   5215 let isBranch = 1;
   5216 let isPredicatedNew = 1;
   5217 let cofRelax1 = 1;
   5218 let cofRelax2 = 1;
   5219 let cofMax1 = 1;
   5220 let Defs = [PC];
   5221 let isTaken = Inst{12};
   5222 }
   5223 def J2_jumprnzpt : HInst<
   5224 (outs),
   5225 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5226 "if ($Rs32==#0) jump:t $Ii",
   5227 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5228 let Inst{0-0} = 0b0;
   5229 let Inst{12-12} = 0b1;
   5230 let Inst{31-22} = 0b0110000110;
   5231 let isPredicated = 1;
   5232 let isTerminator = 1;
   5233 let isBranch = 1;
   5234 let isPredicatedNew = 1;
   5235 let cofRelax1 = 1;
   5236 let cofRelax2 = 1;
   5237 let cofMax1 = 1;
   5238 let Defs = [PC];
   5239 let isTaken = Inst{12};
   5240 }
   5241 def J2_jumprt : HInst<
   5242 (outs),
   5243 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5244 "if ($Pu4) jumpr:nt $Rs32",
   5245 tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel {
   5246 let Inst{7-0} = 0b00000000;
   5247 let Inst{13-10} = 0b0000;
   5248 let Inst{31-21} = 0b01010011010;
   5249 let isPredicated = 1;
   5250 let isTerminator = 1;
   5251 let isIndirectBranch = 1;
   5252 let isBranch = 1;
   5253 let cofMax1 = 1;
   5254 let Defs = [PC];
   5255 let InputType = "reg";
   5256 let BaseOpcode = "J2_jumpr";
   5257 let isTaken = Inst{12};
   5258 }
   5259 def J2_jumprt_nopred_map : HInst<
   5260 (outs),
   5261 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5262 "if ($Pu4) jumpr $Rs32",
   5263 tc_e0739b8c, TypeMAPPING>, Requires<[HasV60]> {
   5264 let isPseudo = 1;
   5265 let isCodeGenOnly = 1;
   5266 }
   5267 def J2_jumprtnew : HInst<
   5268 (outs),
   5269 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5270 "if ($Pu4.new) jumpr:nt $Rs32",
   5271 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
   5272 let Inst{7-0} = 0b00000000;
   5273 let Inst{13-10} = 0b0010;
   5274 let Inst{31-21} = 0b01010011010;
   5275 let isPredicated = 1;
   5276 let isTerminator = 1;
   5277 let isIndirectBranch = 1;
   5278 let isBranch = 1;
   5279 let isPredicatedNew = 1;
   5280 let cofMax1 = 1;
   5281 let Defs = [PC];
   5282 let InputType = "reg";
   5283 let BaseOpcode = "J2_jumpr";
   5284 let isTaken = Inst{12};
   5285 }
   5286 def J2_jumprtnewpt : HInst<
   5287 (outs),
   5288 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5289 "if ($Pu4.new) jumpr:t $Rs32",
   5290 tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel {
   5291 let Inst{7-0} = 0b00000000;
   5292 let Inst{13-10} = 0b0110;
   5293 let Inst{31-21} = 0b01010011010;
   5294 let isPredicated = 1;
   5295 let isTerminator = 1;
   5296 let isIndirectBranch = 1;
   5297 let isBranch = 1;
   5298 let isPredicatedNew = 1;
   5299 let cofMax1 = 1;
   5300 let Defs = [PC];
   5301 let InputType = "reg";
   5302 let BaseOpcode = "J2_jumpr";
   5303 let isTaken = Inst{12};
   5304 }
   5305 def J2_jumprtpt : HInst<
   5306 (outs),
   5307 (ins PredRegs:$Pu4, IntRegs:$Rs32),
   5308 "if ($Pu4) jumpr:t $Rs32",
   5309 tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
   5310 let Inst{7-0} = 0b00000000;
   5311 let Inst{13-10} = 0b0100;
   5312 let Inst{31-21} = 0b01010011010;
   5313 let isPredicated = 1;
   5314 let isTerminator = 1;
   5315 let isIndirectBranch = 1;
   5316 let isBranch = 1;
   5317 let cofMax1 = 1;
   5318 let Defs = [PC];
   5319 let InputType = "reg";
   5320 let BaseOpcode = "J2_jumpr";
   5321 let isTaken = Inst{12};
   5322 }
   5323 def J2_jumprz : HInst<
   5324 (outs),
   5325 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5326 "if ($Rs32!=#0) jump:nt $Ii",
   5327 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5328 let Inst{0-0} = 0b0;
   5329 let Inst{12-12} = 0b0;
   5330 let Inst{31-22} = 0b0110000100;
   5331 let isPredicated = 1;
   5332 let isTerminator = 1;
   5333 let isBranch = 1;
   5334 let isPredicatedNew = 1;
   5335 let cofRelax1 = 1;
   5336 let cofRelax2 = 1;
   5337 let cofMax1 = 1;
   5338 let Defs = [PC];
   5339 let isTaken = Inst{12};
   5340 }
   5341 def J2_jumprzpt : HInst<
   5342 (outs),
   5343 (ins IntRegs:$Rs32, b13_2Imm:$Ii),
   5344 "if ($Rs32!=#0) jump:t $Ii",
   5345 tc_73043bf4, TypeCR>, Enc_0fa531 {
   5346 let Inst{0-0} = 0b0;
   5347 let Inst{12-12} = 0b1;
   5348 let Inst{31-22} = 0b0110000100;
   5349 let isPredicated = 1;
   5350 let isTerminator = 1;
   5351 let isBranch = 1;
   5352 let isPredicatedNew = 1;
   5353 let cofRelax1 = 1;
   5354 let cofRelax2 = 1;
   5355 let cofMax1 = 1;
   5356 let Defs = [PC];
   5357 let isTaken = Inst{12};
   5358 }
   5359 def J2_jumpt : HInst<
   5360 (outs),
   5361 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   5362 "if ($Pu4) jump:nt $Ii",
   5363 tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel {
   5364 let Inst{0-0} = 0b0;
   5365 let Inst{12-10} = 0b000;
   5366 let Inst{21-21} = 0b0;
   5367 let Inst{31-24} = 0b01011100;
   5368 let isPredicated = 1;
   5369 let isTerminator = 1;
   5370 let isBranch = 1;
   5371 let cofRelax1 = 1;
   5372 let cofRelax2 = 1;
   5373 let cofMax1 = 1;
   5374 let Defs = [PC];
   5375 let InputType = "imm";
   5376 let BaseOpcode = "J2_jump";
   5377 let isTaken = Inst{12};
   5378 let isExtendable = 1;
   5379 let opExtendable = 1;
   5380 let isExtentSigned = 1;
   5381 let opExtentBits = 17;
   5382 let opExtentAlign = 2;
   5383 }
   5384 def J2_jumpt_nopred_map : HInst<
   5385 (outs),
   5386 (ins PredRegs:$Pu4, b15_2Imm:$Ii),
   5387 "if ($Pu4) jump $Ii",
   5388 tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60]> {
   5389 let isPseudo = 1;
   5390 let isCodeGenOnly = 1;
   5391 }
   5392 def J2_jumptnew : HInst<
   5393 (outs),
   5394 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   5395 "if ($Pu4.new) jump:nt $Ii",
   5396 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
   5397 let Inst{0-0} = 0b0;
   5398 let Inst{12-10} = 0b010;
   5399 let Inst{21-21} = 0b0;
   5400 let Inst{31-24} = 0b01011100;
   5401 let isPredicated = 1;
   5402 let isTerminator = 1;
   5403 let isBranch = 1;
   5404 let isPredicatedNew = 1;
   5405 let cofRelax1 = 1;
   5406 let cofRelax2 = 1;
   5407 let cofMax1 = 1;
   5408 let Defs = [PC];
   5409 let InputType = "imm";
   5410 let BaseOpcode = "J2_jump";
   5411 let isTaken = Inst{12};
   5412 let isExtendable = 1;
   5413 let opExtendable = 1;
   5414 let isExtentSigned = 1;
   5415 let opExtentBits = 17;
   5416 let opExtentAlign = 2;
   5417 }
   5418 def J2_jumptnewpt : HInst<
   5419 (outs),
   5420 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   5421 "if ($Pu4.new) jump:t $Ii",
   5422 tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel {
   5423 let Inst{0-0} = 0b0;
   5424 let Inst{12-10} = 0b110;
   5425 let Inst{21-21} = 0b0;
   5426 let Inst{31-24} = 0b01011100;
   5427 let isPredicated = 1;
   5428 let isTerminator = 1;
   5429 let isBranch = 1;
   5430 let isPredicatedNew = 1;
   5431 let cofRelax1 = 1;
   5432 let cofRelax2 = 1;
   5433 let cofMax1 = 1;
   5434 let Defs = [PC];
   5435 let InputType = "imm";
   5436 let BaseOpcode = "J2_jump";
   5437 let isTaken = Inst{12};
   5438 let isExtendable = 1;
   5439 let opExtendable = 1;
   5440 let isExtentSigned = 1;
   5441 let opExtentBits = 17;
   5442 let opExtentAlign = 2;
   5443 }
   5444 def J2_jumptpt : HInst<
   5445 (outs),
   5446 (ins PredRegs:$Pu4, b30_2Imm:$Ii),
   5447 "if ($Pu4) jump:t $Ii",
   5448 tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
   5449 let Inst{0-0} = 0b0;
   5450 let Inst{12-10} = 0b100;
   5451 let Inst{21-21} = 0b0;
   5452 let Inst{31-24} = 0b01011100;
   5453 let isPredicated = 1;
   5454 let isTerminator = 1;
   5455 let isBranch = 1;
   5456 let cofRelax1 = 1;
   5457 let cofRelax2 = 1;
   5458 let cofMax1 = 1;
   5459 let Defs = [PC];
   5460 let InputType = "imm";
   5461 let BaseOpcode = "J2_jump";
   5462 let isTaken = Inst{12};
   5463 let isExtendable = 1;
   5464 let opExtendable = 1;
   5465 let isExtentSigned = 1;
   5466 let opExtentBits = 17;
   5467 let opExtentAlign = 2;
   5468 }
   5469 def J2_loop0i : HInst<
   5470 (outs),
   5471 (ins b30_2Imm:$Ii, u10_0Imm:$II),
   5472 "loop0($Ii,#$II)",
   5473 tc_cf59f215, TypeCR>, Enc_4dc228 {
   5474 let Inst{2-2} = 0b0;
   5475 let Inst{13-13} = 0b0;
   5476 let Inst{31-21} = 0b01101001000;
   5477 let cofRelax1 = 1;
   5478 let cofRelax2 = 1;
   5479 let Defs = [LC0, SA0, USR];
   5480 let isExtendable = 1;
   5481 let opExtendable = 0;
   5482 let isExtentSigned = 1;
   5483 let opExtentBits = 9;
   5484 let opExtentAlign = 2;
   5485 }
   5486 def J2_loop0r : HInst<
   5487 (outs),
   5488 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
   5489 "loop0($Ii,$Rs32)",
   5490 tc_7934b9df, TypeCR>, Enc_864a5a {
   5491 let Inst{2-0} = 0b000;
   5492 let Inst{7-5} = 0b000;
   5493 let Inst{13-13} = 0b0;
   5494 let Inst{31-21} = 0b01100000000;
   5495 let cofRelax1 = 1;
   5496 let cofRelax2 = 1;
   5497 let Defs = [LC0, SA0, USR];
   5498 let isExtendable = 1;
   5499 let opExtendable = 0;
   5500 let isExtentSigned = 1;
   5501 let opExtentBits = 9;
   5502 let opExtentAlign = 2;
   5503 }
   5504 def J2_loop1i : HInst<
   5505 (outs),
   5506 (ins b30_2Imm:$Ii, u10_0Imm:$II),
   5507 "loop1($Ii,#$II)",
   5508 tc_cf59f215, TypeCR>, Enc_4dc228 {
   5509 let Inst{2-2} = 0b0;
   5510 let Inst{13-13} = 0b0;
   5511 let Inst{31-21} = 0b01101001001;
   5512 let cofRelax1 = 1;
   5513 let cofRelax2 = 1;
   5514 let Defs = [LC1, SA1];
   5515 let isExtendable = 1;
   5516 let opExtendable = 0;
   5517 let isExtentSigned = 1;
   5518 let opExtentBits = 9;
   5519 let opExtentAlign = 2;
   5520 }
   5521 def J2_loop1r : HInst<
   5522 (outs),
   5523 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
   5524 "loop1($Ii,$Rs32)",
   5525 tc_7934b9df, TypeCR>, Enc_864a5a {
   5526 let Inst{2-0} = 0b000;
   5527 let Inst{7-5} = 0b000;
   5528 let Inst{13-13} = 0b0;
   5529 let Inst{31-21} = 0b01100000001;
   5530 let cofRelax1 = 1;
   5531 let cofRelax2 = 1;
   5532 let Defs = [LC1, SA1];
   5533 let isExtendable = 1;
   5534 let opExtendable = 0;
   5535 let isExtentSigned = 1;
   5536 let opExtentBits = 9;
   5537 let opExtentAlign = 2;
   5538 }
   5539 def J2_pause : HInst<
   5540 (outs),
   5541 (ins u8_0Imm:$Ii),
   5542 "pause(#$Ii)",
   5543 tc_681a2300, TypeJ>, Enc_a51a9a {
   5544 let Inst{1-0} = 0b00;
   5545 let Inst{7-5} = 0b000;
   5546 let Inst{13-13} = 0b0;
   5547 let Inst{31-16} = 0b0101010001000000;
   5548 let isSolo = 1;
   5549 }
   5550 def J2_ploop1si : HInst<
   5551 (outs),
   5552 (ins b30_2Imm:$Ii, u10_0Imm:$II),
   5553 "p3 = sp1loop0($Ii,#$II)",
   5554 tc_c5e2426d, TypeCR>, Enc_4dc228 {
   5555 let Inst{2-2} = 0b0;
   5556 let Inst{13-13} = 0b0;
   5557 let Inst{31-21} = 0b01101001101;
   5558 let isPredicateLate = 1;
   5559 let cofRelax1 = 1;
   5560 let cofRelax2 = 1;
   5561 let Defs = [LC0, P3, SA0, USR];
   5562 let isExtendable = 1;
   5563 let opExtendable = 0;
   5564 let isExtentSigned = 1;
   5565 let opExtentBits = 9;
   5566 let opExtentAlign = 2;
   5567 }
   5568 def J2_ploop1sr : HInst<
   5569 (outs),
   5570 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
   5571 "p3 = sp1loop0($Ii,$Rs32)",
   5572 tc_4f7cd700, TypeCR>, Enc_864a5a {
   5573 let Inst{2-0} = 0b000;
   5574 let Inst{7-5} = 0b000;
   5575 let Inst{13-13} = 0b0;
   5576 let Inst{31-21} = 0b01100000101;
   5577 let isPredicateLate = 1;
   5578 let cofRelax1 = 1;
   5579 let cofRelax2 = 1;
   5580 let Defs = [LC0, P3, SA0, USR];
   5581 let isExtendable = 1;
   5582 let opExtendable = 0;
   5583 let isExtentSigned = 1;
   5584 let opExtentBits = 9;
   5585 let opExtentAlign = 2;
   5586 }
   5587 def J2_ploop2si : HInst<
   5588 (outs),
   5589 (ins b30_2Imm:$Ii, u10_0Imm:$II),
   5590 "p3 = sp2loop0($Ii,#$II)",
   5591 tc_c5e2426d, TypeCR>, Enc_4dc228 {
   5592 let Inst{2-2} = 0b0;
   5593 let Inst{13-13} = 0b0;
   5594 let Inst{31-21} = 0b01101001110;
   5595 let isPredicateLate = 1;
   5596 let cofRelax1 = 1;
   5597 let cofRelax2 = 1;
   5598 let Defs = [LC0, P3, SA0, USR];
   5599 let isExtendable = 1;
   5600 let opExtendable = 0;
   5601 let isExtentSigned = 1;
   5602 let opExtentBits = 9;
   5603 let opExtentAlign = 2;
   5604 }
   5605 def J2_ploop2sr : HInst<
   5606 (outs),
   5607 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
   5608 "p3 = sp2loop0($Ii,$Rs32)",
   5609 tc_4f7cd700, TypeCR>, Enc_864a5a {
   5610 let Inst{2-0} = 0b000;
   5611 let Inst{7-5} = 0b000;
   5612 let Inst{13-13} = 0b0;
   5613 let Inst{31-21} = 0b01100000110;
   5614 let isPredicateLate = 1;
   5615 let cofRelax1 = 1;
   5616 let cofRelax2 = 1;
   5617 let Defs = [LC0, P3, SA0, USR];
   5618 let isExtendable = 1;
   5619 let opExtendable = 0;
   5620 let isExtentSigned = 1;
   5621 let opExtentBits = 9;
   5622 let opExtentAlign = 2;
   5623 }
   5624 def J2_ploop3si : HInst<
   5625 (outs),
   5626 (ins b30_2Imm:$Ii, u10_0Imm:$II),
   5627 "p3 = sp3loop0($Ii,#$II)",
   5628 tc_c5e2426d, TypeCR>, Enc_4dc228 {
   5629 let Inst{2-2} = 0b0;
   5630 let Inst{13-13} = 0b0;
   5631 let Inst{31-21} = 0b01101001111;
   5632 let isPredicateLate = 1;
   5633 let cofRelax1 = 1;
   5634 let cofRelax2 = 1;
   5635 let Defs = [LC0, P3, SA0, USR];
   5636 let isExtendable = 1;
   5637 let opExtendable = 0;
   5638 let isExtentSigned = 1;
   5639 let opExtentBits = 9;
   5640 let opExtentAlign = 2;
   5641 }
   5642 def J2_ploop3sr : HInst<
   5643 (outs),
   5644 (ins b30_2Imm:$Ii, IntRegs:$Rs32),
   5645 "p3 = sp3loop0($Ii,$Rs32)",
   5646 tc_4f7cd700, TypeCR>, Enc_864a5a {
   5647 let Inst{2-0} = 0b000;
   5648 let Inst{7-5} = 0b000;
   5649 let Inst{13-13} = 0b0;
   5650 let Inst{31-21} = 0b01100000111;
   5651 let isPredicateLate = 1;
   5652 let cofRelax1 = 1;
   5653 let cofRelax2 = 1;
   5654 let Defs = [LC0, P3, SA0, USR];
   5655 let isExtendable = 1;
   5656 let opExtendable = 0;
   5657 let isExtentSigned = 1;
   5658 let opExtentBits = 9;
   5659 let opExtentAlign = 2;
   5660 }
   5661 def J2_trap0 : HInst<
   5662 (outs),
   5663 (ins u8_0Imm:$Ii),
   5664 "trap0(#$Ii)",
   5665 tc_14cd4cfa, TypeJ>, Enc_a51a9a {
   5666 let Inst{1-0} = 0b00;
   5667 let Inst{7-5} = 0b000;
   5668 let Inst{13-13} = 0b0;
   5669 let Inst{31-16} = 0b0101010000000000;
   5670 let isSolo = 1;
   5671 }
   5672 def J2_trap1 : HInst<
   5673 (outs IntRegs:$Rx32),
   5674 (ins IntRegs:$Rx32in, u8_0Imm:$Ii),
   5675 "trap1($Rx32,#$Ii)",
   5676 tc_59a01ead, TypeJ>, Enc_33f8ba {
   5677 let Inst{1-0} = 0b00;
   5678 let Inst{7-5} = 0b000;
   5679 let Inst{13-13} = 0b0;
   5680 let Inst{31-21} = 0b01010100100;
   5681 let hasNewValue = 1;
   5682 let opNewValue = 0;
   5683 let isSolo = 1;
   5684 let Uses = [GOSP];
   5685 let Defs = [GOSP, PC];
   5686 let Constraints = "$Rx32 = $Rx32in";
   5687 }
   5688 def J2_trap1_noregmap : HInst<
   5689 (outs),
   5690 (ins u8_0Imm:$Ii),
   5691 "trap1(#$Ii)",
   5692 tc_59a01ead, TypeMAPPING> {
   5693 let isPseudo = 1;
   5694 let isCodeGenOnly = 1;
   5695 }
   5696 def J4_cmpeq_f_jumpnv_nt : HInst<
   5697 (outs),
   5698 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   5699 "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
   5700 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   5701 let Inst{0-0} = 0b0;
   5702 let Inst{13-13} = 0b0;
   5703 let Inst{19-19} = 0b0;
   5704 let Inst{31-22} = 0b0010000001;
   5705 let isPredicated = 1;
   5706 let isPredicatedFalse = 1;
   5707 let isTerminator = 1;
   5708 let isBranch = 1;
   5709 let isNewValue = 1;
   5710 let cofMax1 = 1;
   5711 let isRestrictNoSlot1Store = 1;
   5712 let Defs = [PC];
   5713 let BaseOpcode = "J4_cmpeqr";
   5714 let isTaken = Inst{13};
   5715 let isExtendable = 1;
   5716 let opExtendable = 2;
   5717 let isExtentSigned = 1;
   5718 let opExtentBits = 11;
   5719 let opExtentAlign = 2;
   5720 let opNewValue = 0;
   5721 }
   5722 def J4_cmpeq_f_jumpnv_t : HInst<
   5723 (outs),
   5724 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   5725 "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
   5726 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   5727 let Inst{0-0} = 0b0;
   5728 let Inst{13-13} = 0b1;
   5729 let Inst{19-19} = 0b0;
   5730 let Inst{31-22} = 0b0010000001;
   5731 let isPredicated = 1;
   5732 let isPredicatedFalse = 1;
   5733 let isTerminator = 1;
   5734 let isBranch = 1;
   5735 let isNewValue = 1;
   5736 let cofMax1 = 1;
   5737 let isRestrictNoSlot1Store = 1;
   5738 let Defs = [PC];
   5739 let BaseOpcode = "J4_cmpeqr";
   5740 let isTaken = Inst{13};
   5741 let isExtendable = 1;
   5742 let opExtendable = 2;
   5743 let isExtentSigned = 1;
   5744 let opExtentBits = 11;
   5745 let opExtentAlign = 2;
   5746 let opNewValue = 0;
   5747 }
   5748 def J4_cmpeq_fp0_jump_nt : HInst<
   5749 (outs),
   5750 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5751 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
   5752 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5753 let Inst{0-0} = 0b0;
   5754 let Inst{13-12} = 0b00;
   5755 let Inst{31-22} = 0b0001010001;
   5756 let isPredicated = 1;
   5757 let isPredicatedFalse = 1;
   5758 let isTerminator = 1;
   5759 let isBranch = 1;
   5760 let isPredicatedNew = 1;
   5761 let cofRelax1 = 1;
   5762 let cofRelax2 = 1;
   5763 let cofMax1 = 1;
   5764 let Uses = [P0];
   5765 let Defs = [P0, PC];
   5766 let BaseOpcode = "J4_cmpeqp0";
   5767 let isTaken = Inst{13};
   5768 let isExtendable = 1;
   5769 let opExtendable = 2;
   5770 let isExtentSigned = 1;
   5771 let opExtentBits = 11;
   5772 let opExtentAlign = 2;
   5773 }
   5774 def J4_cmpeq_fp0_jump_t : HInst<
   5775 (outs),
   5776 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5777 "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
   5778 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5779 let Inst{0-0} = 0b0;
   5780 let Inst{13-12} = 0b10;
   5781 let Inst{31-22} = 0b0001010001;
   5782 let isPredicated = 1;
   5783 let isPredicatedFalse = 1;
   5784 let isTerminator = 1;
   5785 let isBranch = 1;
   5786 let isPredicatedNew = 1;
   5787 let cofRelax1 = 1;
   5788 let cofRelax2 = 1;
   5789 let cofMax1 = 1;
   5790 let Uses = [P0];
   5791 let Defs = [P0, PC];
   5792 let BaseOpcode = "J4_cmpeqp0";
   5793 let isTaken = Inst{13};
   5794 let isExtendable = 1;
   5795 let opExtendable = 2;
   5796 let isExtentSigned = 1;
   5797 let opExtentBits = 11;
   5798 let opExtentAlign = 2;
   5799 }
   5800 def J4_cmpeq_fp1_jump_nt : HInst<
   5801 (outs),
   5802 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5803 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
   5804 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5805 let Inst{0-0} = 0b0;
   5806 let Inst{13-12} = 0b01;
   5807 let Inst{31-22} = 0b0001010001;
   5808 let isPredicated = 1;
   5809 let isPredicatedFalse = 1;
   5810 let isTerminator = 1;
   5811 let isBranch = 1;
   5812 let isPredicatedNew = 1;
   5813 let cofRelax1 = 1;
   5814 let cofRelax2 = 1;
   5815 let cofMax1 = 1;
   5816 let Uses = [P1];
   5817 let Defs = [P1, PC];
   5818 let BaseOpcode = "J4_cmpeqp1";
   5819 let isTaken = Inst{13};
   5820 let isExtendable = 1;
   5821 let opExtendable = 2;
   5822 let isExtentSigned = 1;
   5823 let opExtentBits = 11;
   5824 let opExtentAlign = 2;
   5825 }
   5826 def J4_cmpeq_fp1_jump_t : HInst<
   5827 (outs),
   5828 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5829 "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
   5830 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5831 let Inst{0-0} = 0b0;
   5832 let Inst{13-12} = 0b11;
   5833 let Inst{31-22} = 0b0001010001;
   5834 let isPredicated = 1;
   5835 let isPredicatedFalse = 1;
   5836 let isTerminator = 1;
   5837 let isBranch = 1;
   5838 let isPredicatedNew = 1;
   5839 let cofRelax1 = 1;
   5840 let cofRelax2 = 1;
   5841 let cofMax1 = 1;
   5842 let Uses = [P1];
   5843 let Defs = [P1, PC];
   5844 let BaseOpcode = "J4_cmpeqp1";
   5845 let isTaken = Inst{13};
   5846 let isExtendable = 1;
   5847 let opExtendable = 2;
   5848 let isExtentSigned = 1;
   5849 let opExtentBits = 11;
   5850 let opExtentAlign = 2;
   5851 }
   5852 def J4_cmpeq_t_jumpnv_nt : HInst<
   5853 (outs),
   5854 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   5855 "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
   5856 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   5857 let Inst{0-0} = 0b0;
   5858 let Inst{13-13} = 0b0;
   5859 let Inst{19-19} = 0b0;
   5860 let Inst{31-22} = 0b0010000000;
   5861 let isPredicated = 1;
   5862 let isTerminator = 1;
   5863 let isBranch = 1;
   5864 let isNewValue = 1;
   5865 let cofMax1 = 1;
   5866 let isRestrictNoSlot1Store = 1;
   5867 let Defs = [PC];
   5868 let BaseOpcode = "J4_cmpeqr";
   5869 let isTaken = Inst{13};
   5870 let isExtendable = 1;
   5871 let opExtendable = 2;
   5872 let isExtentSigned = 1;
   5873 let opExtentBits = 11;
   5874 let opExtentAlign = 2;
   5875 let opNewValue = 0;
   5876 }
   5877 def J4_cmpeq_t_jumpnv_t : HInst<
   5878 (outs),
   5879 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   5880 "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
   5881 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   5882 let Inst{0-0} = 0b0;
   5883 let Inst{13-13} = 0b1;
   5884 let Inst{19-19} = 0b0;
   5885 let Inst{31-22} = 0b0010000000;
   5886 let isPredicated = 1;
   5887 let isTerminator = 1;
   5888 let isBranch = 1;
   5889 let isNewValue = 1;
   5890 let cofMax1 = 1;
   5891 let isRestrictNoSlot1Store = 1;
   5892 let Defs = [PC];
   5893 let BaseOpcode = "J4_cmpeqr";
   5894 let isTaken = Inst{13};
   5895 let isExtendable = 1;
   5896 let opExtendable = 2;
   5897 let isExtentSigned = 1;
   5898 let opExtentBits = 11;
   5899 let opExtentAlign = 2;
   5900 let opNewValue = 0;
   5901 }
   5902 def J4_cmpeq_tp0_jump_nt : HInst<
   5903 (outs),
   5904 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5905 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
   5906 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5907 let Inst{0-0} = 0b0;
   5908 let Inst{13-12} = 0b00;
   5909 let Inst{31-22} = 0b0001010000;
   5910 let isPredicated = 1;
   5911 let isTerminator = 1;
   5912 let isBranch = 1;
   5913 let isPredicatedNew = 1;
   5914 let cofRelax1 = 1;
   5915 let cofRelax2 = 1;
   5916 let cofMax1 = 1;
   5917 let Uses = [P0];
   5918 let Defs = [P0, PC];
   5919 let BaseOpcode = "J4_cmpeqp0";
   5920 let isTaken = Inst{13};
   5921 let isExtendable = 1;
   5922 let opExtendable = 2;
   5923 let isExtentSigned = 1;
   5924 let opExtentBits = 11;
   5925 let opExtentAlign = 2;
   5926 }
   5927 def J4_cmpeq_tp0_jump_t : HInst<
   5928 (outs),
   5929 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5930 "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
   5931 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5932 let Inst{0-0} = 0b0;
   5933 let Inst{13-12} = 0b10;
   5934 let Inst{31-22} = 0b0001010000;
   5935 let isPredicated = 1;
   5936 let isTerminator = 1;
   5937 let isBranch = 1;
   5938 let isPredicatedNew = 1;
   5939 let cofRelax1 = 1;
   5940 let cofRelax2 = 1;
   5941 let cofMax1 = 1;
   5942 let Uses = [P0];
   5943 let Defs = [P0, PC];
   5944 let BaseOpcode = "J4_cmpeqp0";
   5945 let isTaken = Inst{13};
   5946 let isExtendable = 1;
   5947 let opExtendable = 2;
   5948 let isExtentSigned = 1;
   5949 let opExtentBits = 11;
   5950 let opExtentAlign = 2;
   5951 }
   5952 def J4_cmpeq_tp1_jump_nt : HInst<
   5953 (outs),
   5954 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5955 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
   5956 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5957 let Inst{0-0} = 0b0;
   5958 let Inst{13-12} = 0b01;
   5959 let Inst{31-22} = 0b0001010000;
   5960 let isPredicated = 1;
   5961 let isTerminator = 1;
   5962 let isBranch = 1;
   5963 let isPredicatedNew = 1;
   5964 let cofRelax1 = 1;
   5965 let cofRelax2 = 1;
   5966 let cofMax1 = 1;
   5967 let Uses = [P1];
   5968 let Defs = [P1, PC];
   5969 let BaseOpcode = "J4_cmpeqp1";
   5970 let isTaken = Inst{13};
   5971 let isExtendable = 1;
   5972 let opExtendable = 2;
   5973 let isExtentSigned = 1;
   5974 let opExtentBits = 11;
   5975 let opExtentAlign = 2;
   5976 }
   5977 def J4_cmpeq_tp1_jump_t : HInst<
   5978 (outs),
   5979 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   5980 "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
   5981 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   5982 let Inst{0-0} = 0b0;
   5983 let Inst{13-12} = 0b11;
   5984 let Inst{31-22} = 0b0001010000;
   5985 let isPredicated = 1;
   5986 let isTerminator = 1;
   5987 let isBranch = 1;
   5988 let isPredicatedNew = 1;
   5989 let cofRelax1 = 1;
   5990 let cofRelax2 = 1;
   5991 let cofMax1 = 1;
   5992 let Uses = [P1];
   5993 let Defs = [P1, PC];
   5994 let BaseOpcode = "J4_cmpeqp1";
   5995 let isTaken = Inst{13};
   5996 let isExtendable = 1;
   5997 let opExtendable = 2;
   5998 let isExtentSigned = 1;
   5999 let opExtentBits = 11;
   6000 let opExtentAlign = 2;
   6001 }
   6002 def J4_cmpeqi_f_jumpnv_nt : HInst<
   6003 (outs),
   6004 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6005 "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
   6006 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6007 let Inst{0-0} = 0b0;
   6008 let Inst{13-13} = 0b0;
   6009 let Inst{19-19} = 0b0;
   6010 let Inst{31-22} = 0b0010010001;
   6011 let isPredicated = 1;
   6012 let isPredicatedFalse = 1;
   6013 let isTerminator = 1;
   6014 let isBranch = 1;
   6015 let isNewValue = 1;
   6016 let cofMax1 = 1;
   6017 let isRestrictNoSlot1Store = 1;
   6018 let Defs = [PC];
   6019 let BaseOpcode = "J4_cmpeqi";
   6020 let isTaken = Inst{13};
   6021 let isExtendable = 1;
   6022 let opExtendable = 2;
   6023 let isExtentSigned = 1;
   6024 let opExtentBits = 11;
   6025 let opExtentAlign = 2;
   6026 let opNewValue = 0;
   6027 }
   6028 def J4_cmpeqi_f_jumpnv_t : HInst<
   6029 (outs),
   6030 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6031 "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
   6032 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6033 let Inst{0-0} = 0b0;
   6034 let Inst{13-13} = 0b1;
   6035 let Inst{19-19} = 0b0;
   6036 let Inst{31-22} = 0b0010010001;
   6037 let isPredicated = 1;
   6038 let isPredicatedFalse = 1;
   6039 let isTerminator = 1;
   6040 let isBranch = 1;
   6041 let isNewValue = 1;
   6042 let cofMax1 = 1;
   6043 let isRestrictNoSlot1Store = 1;
   6044 let Defs = [PC];
   6045 let BaseOpcode = "J4_cmpeqi";
   6046 let isTaken = Inst{13};
   6047 let isExtendable = 1;
   6048 let opExtendable = 2;
   6049 let isExtentSigned = 1;
   6050 let opExtentBits = 11;
   6051 let opExtentAlign = 2;
   6052 let opNewValue = 0;
   6053 }
   6054 def J4_cmpeqi_fp0_jump_nt : HInst<
   6055 (outs),
   6056 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6057 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
   6058 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6059 let Inst{0-0} = 0b0;
   6060 let Inst{13-13} = 0b0;
   6061 let Inst{31-22} = 0b0001000001;
   6062 let isPredicated = 1;
   6063 let isPredicatedFalse = 1;
   6064 let isTerminator = 1;
   6065 let isBranch = 1;
   6066 let isPredicatedNew = 1;
   6067 let cofRelax1 = 1;
   6068 let cofRelax2 = 1;
   6069 let cofMax1 = 1;
   6070 let Uses = [P0];
   6071 let Defs = [P0, PC];
   6072 let BaseOpcode = "J4_cmpeqip0";
   6073 let isTaken = Inst{13};
   6074 let isExtendable = 1;
   6075 let opExtendable = 2;
   6076 let isExtentSigned = 1;
   6077 let opExtentBits = 11;
   6078 let opExtentAlign = 2;
   6079 }
   6080 def J4_cmpeqi_fp0_jump_t : HInst<
   6081 (outs),
   6082 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6083 "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
   6084 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6085 let Inst{0-0} = 0b0;
   6086 let Inst{13-13} = 0b1;
   6087 let Inst{31-22} = 0b0001000001;
   6088 let isPredicated = 1;
   6089 let isPredicatedFalse = 1;
   6090 let isTerminator = 1;
   6091 let isBranch = 1;
   6092 let isPredicatedNew = 1;
   6093 let cofRelax1 = 1;
   6094 let cofRelax2 = 1;
   6095 let cofMax1 = 1;
   6096 let Uses = [P0];
   6097 let Defs = [P0, PC];
   6098 let BaseOpcode = "J4_cmpeqip0";
   6099 let isTaken = Inst{13};
   6100 let isExtendable = 1;
   6101 let opExtendable = 2;
   6102 let isExtentSigned = 1;
   6103 let opExtentBits = 11;
   6104 let opExtentAlign = 2;
   6105 }
   6106 def J4_cmpeqi_fp1_jump_nt : HInst<
   6107 (outs),
   6108 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6109 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
   6110 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6111 let Inst{0-0} = 0b0;
   6112 let Inst{13-13} = 0b0;
   6113 let Inst{31-22} = 0b0001001001;
   6114 let isPredicated = 1;
   6115 let isPredicatedFalse = 1;
   6116 let isTerminator = 1;
   6117 let isBranch = 1;
   6118 let isPredicatedNew = 1;
   6119 let cofRelax1 = 1;
   6120 let cofRelax2 = 1;
   6121 let cofMax1 = 1;
   6122 let Uses = [P1];
   6123 let Defs = [P1, PC];
   6124 let BaseOpcode = "J4_cmpeqip1";
   6125 let isTaken = Inst{13};
   6126 let isExtendable = 1;
   6127 let opExtendable = 2;
   6128 let isExtentSigned = 1;
   6129 let opExtentBits = 11;
   6130 let opExtentAlign = 2;
   6131 }
   6132 def J4_cmpeqi_fp1_jump_t : HInst<
   6133 (outs),
   6134 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6135 "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
   6136 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6137 let Inst{0-0} = 0b0;
   6138 let Inst{13-13} = 0b1;
   6139 let Inst{31-22} = 0b0001001001;
   6140 let isPredicated = 1;
   6141 let isPredicatedFalse = 1;
   6142 let isTerminator = 1;
   6143 let isBranch = 1;
   6144 let isPredicatedNew = 1;
   6145 let cofRelax1 = 1;
   6146 let cofRelax2 = 1;
   6147 let cofMax1 = 1;
   6148 let Uses = [P1];
   6149 let Defs = [P1, PC];
   6150 let BaseOpcode = "J4_cmpeqip1";
   6151 let isTaken = Inst{13};
   6152 let isExtendable = 1;
   6153 let opExtendable = 2;
   6154 let isExtentSigned = 1;
   6155 let opExtentBits = 11;
   6156 let opExtentAlign = 2;
   6157 }
   6158 def J4_cmpeqi_t_jumpnv_nt : HInst<
   6159 (outs),
   6160 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6161 "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
   6162 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6163 let Inst{0-0} = 0b0;
   6164 let Inst{13-13} = 0b0;
   6165 let Inst{19-19} = 0b0;
   6166 let Inst{31-22} = 0b0010010000;
   6167 let isPredicated = 1;
   6168 let isTerminator = 1;
   6169 let isBranch = 1;
   6170 let isNewValue = 1;
   6171 let cofMax1 = 1;
   6172 let isRestrictNoSlot1Store = 1;
   6173 let Defs = [PC];
   6174 let BaseOpcode = "J4_cmpeqi";
   6175 let isTaken = Inst{13};
   6176 let isExtendable = 1;
   6177 let opExtendable = 2;
   6178 let isExtentSigned = 1;
   6179 let opExtentBits = 11;
   6180 let opExtentAlign = 2;
   6181 let opNewValue = 0;
   6182 }
   6183 def J4_cmpeqi_t_jumpnv_t : HInst<
   6184 (outs),
   6185 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6186 "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
   6187 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6188 let Inst{0-0} = 0b0;
   6189 let Inst{13-13} = 0b1;
   6190 let Inst{19-19} = 0b0;
   6191 let Inst{31-22} = 0b0010010000;
   6192 let isPredicated = 1;
   6193 let isTerminator = 1;
   6194 let isBranch = 1;
   6195 let isNewValue = 1;
   6196 let cofMax1 = 1;
   6197 let isRestrictNoSlot1Store = 1;
   6198 let Defs = [PC];
   6199 let BaseOpcode = "J4_cmpeqi";
   6200 let isTaken = Inst{13};
   6201 let isExtendable = 1;
   6202 let opExtendable = 2;
   6203 let isExtentSigned = 1;
   6204 let opExtentBits = 11;
   6205 let opExtentAlign = 2;
   6206 let opNewValue = 0;
   6207 }
   6208 def J4_cmpeqi_tp0_jump_nt : HInst<
   6209 (outs),
   6210 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6211 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
   6212 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6213 let Inst{0-0} = 0b0;
   6214 let Inst{13-13} = 0b0;
   6215 let Inst{31-22} = 0b0001000000;
   6216 let isPredicated = 1;
   6217 let isTerminator = 1;
   6218 let isBranch = 1;
   6219 let isPredicatedNew = 1;
   6220 let cofRelax1 = 1;
   6221 let cofRelax2 = 1;
   6222 let cofMax1 = 1;
   6223 let Uses = [P0];
   6224 let Defs = [P0, PC];
   6225 let BaseOpcode = "J4_cmpeqip0";
   6226 let isTaken = Inst{13};
   6227 let isExtendable = 1;
   6228 let opExtendable = 2;
   6229 let isExtentSigned = 1;
   6230 let opExtentBits = 11;
   6231 let opExtentAlign = 2;
   6232 }
   6233 def J4_cmpeqi_tp0_jump_t : HInst<
   6234 (outs),
   6235 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6236 "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
   6237 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6238 let Inst{0-0} = 0b0;
   6239 let Inst{13-13} = 0b1;
   6240 let Inst{31-22} = 0b0001000000;
   6241 let isPredicated = 1;
   6242 let isTerminator = 1;
   6243 let isBranch = 1;
   6244 let isPredicatedNew = 1;
   6245 let cofRelax1 = 1;
   6246 let cofRelax2 = 1;
   6247 let cofMax1 = 1;
   6248 let Uses = [P0];
   6249 let Defs = [P0, PC];
   6250 let BaseOpcode = "J4_cmpeqip0";
   6251 let isTaken = Inst{13};
   6252 let isExtendable = 1;
   6253 let opExtendable = 2;
   6254 let isExtentSigned = 1;
   6255 let opExtentBits = 11;
   6256 let opExtentAlign = 2;
   6257 }
   6258 def J4_cmpeqi_tp1_jump_nt : HInst<
   6259 (outs),
   6260 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6261 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
   6262 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6263 let Inst{0-0} = 0b0;
   6264 let Inst{13-13} = 0b0;
   6265 let Inst{31-22} = 0b0001001000;
   6266 let isPredicated = 1;
   6267 let isTerminator = 1;
   6268 let isBranch = 1;
   6269 let isPredicatedNew = 1;
   6270 let cofRelax1 = 1;
   6271 let cofRelax2 = 1;
   6272 let cofMax1 = 1;
   6273 let Uses = [P1];
   6274 let Defs = [P1, PC];
   6275 let BaseOpcode = "J4_cmpeqip1";
   6276 let isTaken = Inst{13};
   6277 let isExtendable = 1;
   6278 let opExtendable = 2;
   6279 let isExtentSigned = 1;
   6280 let opExtentBits = 11;
   6281 let opExtentAlign = 2;
   6282 }
   6283 def J4_cmpeqi_tp1_jump_t : HInst<
   6284 (outs),
   6285 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6286 "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
   6287 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6288 let Inst{0-0} = 0b0;
   6289 let Inst{13-13} = 0b1;
   6290 let Inst{31-22} = 0b0001001000;
   6291 let isPredicated = 1;
   6292 let isTerminator = 1;
   6293 let isBranch = 1;
   6294 let isPredicatedNew = 1;
   6295 let cofRelax1 = 1;
   6296 let cofRelax2 = 1;
   6297 let cofMax1 = 1;
   6298 let Uses = [P1];
   6299 let Defs = [P1, PC];
   6300 let BaseOpcode = "J4_cmpeqip1";
   6301 let isTaken = Inst{13};
   6302 let isExtendable = 1;
   6303 let opExtendable = 2;
   6304 let isExtentSigned = 1;
   6305 let opExtentBits = 11;
   6306 let opExtentAlign = 2;
   6307 }
   6308 def J4_cmpeqn1_f_jumpnv_nt : HInst<
   6309 (outs),
   6310 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   6311 "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
   6312 tc_bde7aaf4, TypeNCJ>, Enc_e90a15, PredRel {
   6313 let Inst{0-0} = 0b0;
   6314 let Inst{13-8} = 0b000000;
   6315 let Inst{19-19} = 0b0;
   6316 let Inst{31-22} = 0b0010011001;
   6317 let isPredicated = 1;
   6318 let isPredicatedFalse = 1;
   6319 let isTerminator = 1;
   6320 let isBranch = 1;
   6321 let isNewValue = 1;
   6322 let cofMax1 = 1;
   6323 let isRestrictNoSlot1Store = 1;
   6324 let Defs = [PC];
   6325 let BaseOpcode = "J4_cmpeqn1r";
   6326 let isTaken = Inst{13};
   6327 let isExtendable = 1;
   6328 let opExtendable = 2;
   6329 let isExtentSigned = 1;
   6330 let opExtentBits = 11;
   6331 let opExtentAlign = 2;
   6332 let opNewValue = 0;
   6333 }
   6334 def J4_cmpeqn1_f_jumpnv_t : HInst<
   6335 (outs),
   6336 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   6337 "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
   6338 tc_bde7aaf4, TypeNCJ>, Enc_5a18b3, PredRel {
   6339 let Inst{0-0} = 0b0;
   6340 let Inst{13-8} = 0b100000;
   6341 let Inst{19-19} = 0b0;
   6342 let Inst{31-22} = 0b0010011001;
   6343 let isPredicated = 1;
   6344 let isPredicatedFalse = 1;
   6345 let isTerminator = 1;
   6346 let isBranch = 1;
   6347 let isNewValue = 1;
   6348 let cofMax1 = 1;
   6349 let isRestrictNoSlot1Store = 1;
   6350 let Defs = [PC];
   6351 let BaseOpcode = "J4_cmpeqn1r";
   6352 let isTaken = Inst{13};
   6353 let isExtendable = 1;
   6354 let opExtendable = 2;
   6355 let isExtentSigned = 1;
   6356 let opExtentBits = 11;
   6357 let opExtentAlign = 2;
   6358 let opNewValue = 0;
   6359 }
   6360 def J4_cmpeqn1_fp0_jump_nt : HInst<
   6361 (outs),
   6362 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6363 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
   6364 tc_99be14ca, TypeCJ>, Enc_1de724, PredRel {
   6365 let Inst{0-0} = 0b0;
   6366 let Inst{13-8} = 0b000000;
   6367 let Inst{31-22} = 0b0001000111;
   6368 let isPredicated = 1;
   6369 let isPredicatedFalse = 1;
   6370 let isTerminator = 1;
   6371 let isBranch = 1;
   6372 let isPredicatedNew = 1;
   6373 let cofRelax1 = 1;
   6374 let cofRelax2 = 1;
   6375 let cofMax1 = 1;
   6376 let Uses = [P0];
   6377 let Defs = [P0, PC];
   6378 let BaseOpcode = "J4_cmpeqn1p0";
   6379 let isTaken = Inst{13};
   6380 let isExtendable = 1;
   6381 let opExtendable = 2;
   6382 let isExtentSigned = 1;
   6383 let opExtentBits = 11;
   6384 let opExtentAlign = 2;
   6385 }
   6386 def J4_cmpeqn1_fp0_jump_t : HInst<
   6387 (outs),
   6388 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6389 "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
   6390 tc_99be14ca, TypeCJ>, Enc_14640c, PredRel {
   6391 let Inst{0-0} = 0b0;
   6392 let Inst{13-8} = 0b100000;
   6393 let Inst{31-22} = 0b0001000111;
   6394 let isPredicated = 1;
   6395 let isPredicatedFalse = 1;
   6396 let isTerminator = 1;
   6397 let isBranch = 1;
   6398 let isPredicatedNew = 1;
   6399 let cofRelax1 = 1;
   6400 let cofRelax2 = 1;
   6401 let cofMax1 = 1;
   6402 let Uses = [P0];
   6403 let Defs = [P0, PC];
   6404 let BaseOpcode = "J4_cmpeqn1p0";
   6405 let isTaken = Inst{13};
   6406 let isExtendable = 1;
   6407 let opExtendable = 2;
   6408 let isExtentSigned = 1;
   6409 let opExtentBits = 11;
   6410 let opExtentAlign = 2;
   6411 }
   6412 def J4_cmpeqn1_fp1_jump_nt : HInst<
   6413 (outs),
   6414 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6415 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
   6416 tc_99be14ca, TypeCJ>, Enc_668704, PredRel {
   6417 let Inst{0-0} = 0b0;
   6418 let Inst{13-8} = 0b000000;
   6419 let Inst{31-22} = 0b0001001111;
   6420 let isPredicated = 1;
   6421 let isPredicatedFalse = 1;
   6422 let isTerminator = 1;
   6423 let isBranch = 1;
   6424 let isPredicatedNew = 1;
   6425 let cofRelax1 = 1;
   6426 let cofRelax2 = 1;
   6427 let cofMax1 = 1;
   6428 let Uses = [P1];
   6429 let Defs = [P1, PC];
   6430 let BaseOpcode = "J4_cmpeqn1p1";
   6431 let isTaken = Inst{13};
   6432 let isExtendable = 1;
   6433 let opExtendable = 2;
   6434 let isExtentSigned = 1;
   6435 let opExtentBits = 11;
   6436 let opExtentAlign = 2;
   6437 }
   6438 def J4_cmpeqn1_fp1_jump_t : HInst<
   6439 (outs),
   6440 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6441 "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
   6442 tc_99be14ca, TypeCJ>, Enc_800e04, PredRel {
   6443 let Inst{0-0} = 0b0;
   6444 let Inst{13-8} = 0b100000;
   6445 let Inst{31-22} = 0b0001001111;
   6446 let isPredicated = 1;
   6447 let isPredicatedFalse = 1;
   6448 let isTerminator = 1;
   6449 let isBranch = 1;
   6450 let isPredicatedNew = 1;
   6451 let cofRelax1 = 1;
   6452 let cofRelax2 = 1;
   6453 let cofMax1 = 1;
   6454 let Uses = [P1];
   6455 let Defs = [P1, PC];
   6456 let BaseOpcode = "J4_cmpeqn1p1";
   6457 let isTaken = Inst{13};
   6458 let isExtendable = 1;
   6459 let opExtendable = 2;
   6460 let isExtentSigned = 1;
   6461 let opExtentBits = 11;
   6462 let opExtentAlign = 2;
   6463 }
   6464 def J4_cmpeqn1_t_jumpnv_nt : HInst<
   6465 (outs),
   6466 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   6467 "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
   6468 tc_bde7aaf4, TypeNCJ>, Enc_4aca3a, PredRel {
   6469 let Inst{0-0} = 0b0;
   6470 let Inst{13-8} = 0b000000;
   6471 let Inst{19-19} = 0b0;
   6472 let Inst{31-22} = 0b0010011000;
   6473 let isPredicated = 1;
   6474 let isTerminator = 1;
   6475 let isBranch = 1;
   6476 let isNewValue = 1;
   6477 let cofMax1 = 1;
   6478 let isRestrictNoSlot1Store = 1;
   6479 let Defs = [PC];
   6480 let BaseOpcode = "J4_cmpeqn1r";
   6481 let isTaken = Inst{13};
   6482 let isExtendable = 1;
   6483 let opExtendable = 2;
   6484 let isExtentSigned = 1;
   6485 let opExtentBits = 11;
   6486 let opExtentAlign = 2;
   6487 let opNewValue = 0;
   6488 }
   6489 def J4_cmpeqn1_t_jumpnv_t : HInst<
   6490 (outs),
   6491 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   6492 "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
   6493 tc_bde7aaf4, TypeNCJ>, Enc_f7ea77, PredRel {
   6494 let Inst{0-0} = 0b0;
   6495 let Inst{13-8} = 0b100000;
   6496 let Inst{19-19} = 0b0;
   6497 let Inst{31-22} = 0b0010011000;
   6498 let isPredicated = 1;
   6499 let isTerminator = 1;
   6500 let isBranch = 1;
   6501 let isNewValue = 1;
   6502 let cofMax1 = 1;
   6503 let isRestrictNoSlot1Store = 1;
   6504 let Defs = [PC];
   6505 let BaseOpcode = "J4_cmpeqn1r";
   6506 let isTaken = Inst{13};
   6507 let isExtendable = 1;
   6508 let opExtendable = 2;
   6509 let isExtentSigned = 1;
   6510 let opExtentBits = 11;
   6511 let opExtentAlign = 2;
   6512 let opNewValue = 0;
   6513 }
   6514 def J4_cmpeqn1_tp0_jump_nt : HInst<
   6515 (outs),
   6516 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6517 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
   6518 tc_99be14ca, TypeCJ>, Enc_405228, PredRel {
   6519 let Inst{0-0} = 0b0;
   6520 let Inst{13-8} = 0b000000;
   6521 let Inst{31-22} = 0b0001000110;
   6522 let isPredicated = 1;
   6523 let isTerminator = 1;
   6524 let isBranch = 1;
   6525 let isPredicatedNew = 1;
   6526 let cofRelax1 = 1;
   6527 let cofRelax2 = 1;
   6528 let cofMax1 = 1;
   6529 let Uses = [P0];
   6530 let Defs = [P0, PC];
   6531 let BaseOpcode = "J4_cmpeqn1p0";
   6532 let isTaken = Inst{13};
   6533 let isExtendable = 1;
   6534 let opExtendable = 2;
   6535 let isExtentSigned = 1;
   6536 let opExtentBits = 11;
   6537 let opExtentAlign = 2;
   6538 }
   6539 def J4_cmpeqn1_tp0_jump_t : HInst<
   6540 (outs),
   6541 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6542 "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
   6543 tc_99be14ca, TypeCJ>, Enc_3a2484, PredRel {
   6544 let Inst{0-0} = 0b0;
   6545 let Inst{13-8} = 0b100000;
   6546 let Inst{31-22} = 0b0001000110;
   6547 let isPredicated = 1;
   6548 let isTerminator = 1;
   6549 let isBranch = 1;
   6550 let isPredicatedNew = 1;
   6551 let cofRelax1 = 1;
   6552 let cofRelax2 = 1;
   6553 let cofMax1 = 1;
   6554 let Uses = [P0];
   6555 let Defs = [P0, PC];
   6556 let BaseOpcode = "J4_cmpeqn1p0";
   6557 let isTaken = Inst{13};
   6558 let isExtendable = 1;
   6559 let opExtendable = 2;
   6560 let isExtentSigned = 1;
   6561 let opExtentBits = 11;
   6562 let opExtentAlign = 2;
   6563 }
   6564 def J4_cmpeqn1_tp1_jump_nt : HInst<
   6565 (outs),
   6566 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6567 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
   6568 tc_99be14ca, TypeCJ>, Enc_736575, PredRel {
   6569 let Inst{0-0} = 0b0;
   6570 let Inst{13-8} = 0b000000;
   6571 let Inst{31-22} = 0b0001001110;
   6572 let isPredicated = 1;
   6573 let isTerminator = 1;
   6574 let isBranch = 1;
   6575 let isPredicatedNew = 1;
   6576 let cofRelax1 = 1;
   6577 let cofRelax2 = 1;
   6578 let cofMax1 = 1;
   6579 let Uses = [P1];
   6580 let Defs = [P1, PC];
   6581 let BaseOpcode = "J4_cmpeqn1p1";
   6582 let isTaken = Inst{13};
   6583 let isExtendable = 1;
   6584 let opExtendable = 2;
   6585 let isExtentSigned = 1;
   6586 let opExtentBits = 11;
   6587 let opExtentAlign = 2;
   6588 }
   6589 def J4_cmpeqn1_tp1_jump_t : HInst<
   6590 (outs),
   6591 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   6592 "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
   6593 tc_99be14ca, TypeCJ>, Enc_8e583a, PredRel {
   6594 let Inst{0-0} = 0b0;
   6595 let Inst{13-8} = 0b100000;
   6596 let Inst{31-22} = 0b0001001110;
   6597 let isPredicated = 1;
   6598 let isTerminator = 1;
   6599 let isBranch = 1;
   6600 let isPredicatedNew = 1;
   6601 let cofRelax1 = 1;
   6602 let cofRelax2 = 1;
   6603 let cofMax1 = 1;
   6604 let Uses = [P1];
   6605 let Defs = [P1, PC];
   6606 let BaseOpcode = "J4_cmpeqn1p1";
   6607 let isTaken = Inst{13};
   6608 let isExtendable = 1;
   6609 let opExtendable = 2;
   6610 let isExtentSigned = 1;
   6611 let opExtentBits = 11;
   6612 let opExtentAlign = 2;
   6613 }
   6614 def J4_cmpgt_f_jumpnv_nt : HInst<
   6615 (outs),
   6616 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   6617 "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
   6618 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   6619 let Inst{0-0} = 0b0;
   6620 let Inst{13-13} = 0b0;
   6621 let Inst{19-19} = 0b0;
   6622 let Inst{31-22} = 0b0010000011;
   6623 let isPredicated = 1;
   6624 let isPredicatedFalse = 1;
   6625 let isTerminator = 1;
   6626 let isBranch = 1;
   6627 let isNewValue = 1;
   6628 let cofMax1 = 1;
   6629 let isRestrictNoSlot1Store = 1;
   6630 let Defs = [PC];
   6631 let BaseOpcode = "J4_cmpgtr";
   6632 let isTaken = Inst{13};
   6633 let isExtendable = 1;
   6634 let opExtendable = 2;
   6635 let isExtentSigned = 1;
   6636 let opExtentBits = 11;
   6637 let opExtentAlign = 2;
   6638 let opNewValue = 0;
   6639 }
   6640 def J4_cmpgt_f_jumpnv_t : HInst<
   6641 (outs),
   6642 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   6643 "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
   6644 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   6645 let Inst{0-0} = 0b0;
   6646 let Inst{13-13} = 0b1;
   6647 let Inst{19-19} = 0b0;
   6648 let Inst{31-22} = 0b0010000011;
   6649 let isPredicated = 1;
   6650 let isPredicatedFalse = 1;
   6651 let isTerminator = 1;
   6652 let isBranch = 1;
   6653 let isNewValue = 1;
   6654 let cofMax1 = 1;
   6655 let isRestrictNoSlot1Store = 1;
   6656 let Defs = [PC];
   6657 let BaseOpcode = "J4_cmpgtr";
   6658 let isTaken = Inst{13};
   6659 let isExtendable = 1;
   6660 let opExtendable = 2;
   6661 let isExtentSigned = 1;
   6662 let opExtentBits = 11;
   6663 let opExtentAlign = 2;
   6664 let opNewValue = 0;
   6665 }
   6666 def J4_cmpgt_fp0_jump_nt : HInst<
   6667 (outs),
   6668 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6669 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
   6670 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6671 let Inst{0-0} = 0b0;
   6672 let Inst{13-12} = 0b00;
   6673 let Inst{31-22} = 0b0001010011;
   6674 let isPredicated = 1;
   6675 let isPredicatedFalse = 1;
   6676 let isTerminator = 1;
   6677 let isBranch = 1;
   6678 let isPredicatedNew = 1;
   6679 let cofRelax1 = 1;
   6680 let cofRelax2 = 1;
   6681 let cofMax1 = 1;
   6682 let Uses = [P0];
   6683 let Defs = [P0, PC];
   6684 let BaseOpcode = "J4_cmpgtp0";
   6685 let isTaken = Inst{13};
   6686 let isExtendable = 1;
   6687 let opExtendable = 2;
   6688 let isExtentSigned = 1;
   6689 let opExtentBits = 11;
   6690 let opExtentAlign = 2;
   6691 }
   6692 def J4_cmpgt_fp0_jump_t : HInst<
   6693 (outs),
   6694 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6695 "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
   6696 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6697 let Inst{0-0} = 0b0;
   6698 let Inst{13-12} = 0b10;
   6699 let Inst{31-22} = 0b0001010011;
   6700 let isPredicated = 1;
   6701 let isPredicatedFalse = 1;
   6702 let isTerminator = 1;
   6703 let isBranch = 1;
   6704 let isPredicatedNew = 1;
   6705 let cofRelax1 = 1;
   6706 let cofRelax2 = 1;
   6707 let cofMax1 = 1;
   6708 let Uses = [P0];
   6709 let Defs = [P0, PC];
   6710 let BaseOpcode = "J4_cmpgtp0";
   6711 let isTaken = Inst{13};
   6712 let isExtendable = 1;
   6713 let opExtendable = 2;
   6714 let isExtentSigned = 1;
   6715 let opExtentBits = 11;
   6716 let opExtentAlign = 2;
   6717 }
   6718 def J4_cmpgt_fp1_jump_nt : HInst<
   6719 (outs),
   6720 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6721 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
   6722 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6723 let Inst{0-0} = 0b0;
   6724 let Inst{13-12} = 0b01;
   6725 let Inst{31-22} = 0b0001010011;
   6726 let isPredicated = 1;
   6727 let isPredicatedFalse = 1;
   6728 let isTerminator = 1;
   6729 let isBranch = 1;
   6730 let isPredicatedNew = 1;
   6731 let cofRelax1 = 1;
   6732 let cofRelax2 = 1;
   6733 let cofMax1 = 1;
   6734 let Uses = [P1];
   6735 let Defs = [P1, PC];
   6736 let BaseOpcode = "J4_cmpgtp1";
   6737 let isTaken = Inst{13};
   6738 let isExtendable = 1;
   6739 let opExtendable = 2;
   6740 let isExtentSigned = 1;
   6741 let opExtentBits = 11;
   6742 let opExtentAlign = 2;
   6743 }
   6744 def J4_cmpgt_fp1_jump_t : HInst<
   6745 (outs),
   6746 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6747 "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
   6748 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6749 let Inst{0-0} = 0b0;
   6750 let Inst{13-12} = 0b11;
   6751 let Inst{31-22} = 0b0001010011;
   6752 let isPredicated = 1;
   6753 let isPredicatedFalse = 1;
   6754 let isTerminator = 1;
   6755 let isBranch = 1;
   6756 let isPredicatedNew = 1;
   6757 let cofRelax1 = 1;
   6758 let cofRelax2 = 1;
   6759 let cofMax1 = 1;
   6760 let Uses = [P1];
   6761 let Defs = [P1, PC];
   6762 let BaseOpcode = "J4_cmpgtp1";
   6763 let isTaken = Inst{13};
   6764 let isExtendable = 1;
   6765 let opExtendable = 2;
   6766 let isExtentSigned = 1;
   6767 let opExtentBits = 11;
   6768 let opExtentAlign = 2;
   6769 }
   6770 def J4_cmpgt_t_jumpnv_nt : HInst<
   6771 (outs),
   6772 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   6773 "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
   6774 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   6775 let Inst{0-0} = 0b0;
   6776 let Inst{13-13} = 0b0;
   6777 let Inst{19-19} = 0b0;
   6778 let Inst{31-22} = 0b0010000010;
   6779 let isPredicated = 1;
   6780 let isTerminator = 1;
   6781 let isBranch = 1;
   6782 let isNewValue = 1;
   6783 let cofMax1 = 1;
   6784 let isRestrictNoSlot1Store = 1;
   6785 let Defs = [PC];
   6786 let BaseOpcode = "J4_cmpgtr";
   6787 let isTaken = Inst{13};
   6788 let isExtendable = 1;
   6789 let opExtendable = 2;
   6790 let isExtentSigned = 1;
   6791 let opExtentBits = 11;
   6792 let opExtentAlign = 2;
   6793 let opNewValue = 0;
   6794 }
   6795 def J4_cmpgt_t_jumpnv_t : HInst<
   6796 (outs),
   6797 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   6798 "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
   6799 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   6800 let Inst{0-0} = 0b0;
   6801 let Inst{13-13} = 0b1;
   6802 let Inst{19-19} = 0b0;
   6803 let Inst{31-22} = 0b0010000010;
   6804 let isPredicated = 1;
   6805 let isTerminator = 1;
   6806 let isBranch = 1;
   6807 let isNewValue = 1;
   6808 let cofMax1 = 1;
   6809 let isRestrictNoSlot1Store = 1;
   6810 let Defs = [PC];
   6811 let BaseOpcode = "J4_cmpgtr";
   6812 let isTaken = Inst{13};
   6813 let isExtendable = 1;
   6814 let opExtendable = 2;
   6815 let isExtentSigned = 1;
   6816 let opExtentBits = 11;
   6817 let opExtentAlign = 2;
   6818 let opNewValue = 0;
   6819 }
   6820 def J4_cmpgt_tp0_jump_nt : HInst<
   6821 (outs),
   6822 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6823 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
   6824 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6825 let Inst{0-0} = 0b0;
   6826 let Inst{13-12} = 0b00;
   6827 let Inst{31-22} = 0b0001010010;
   6828 let isPredicated = 1;
   6829 let isTerminator = 1;
   6830 let isBranch = 1;
   6831 let isPredicatedNew = 1;
   6832 let cofRelax1 = 1;
   6833 let cofRelax2 = 1;
   6834 let cofMax1 = 1;
   6835 let Uses = [P0];
   6836 let Defs = [P0, PC];
   6837 let BaseOpcode = "J4_cmpgtp0";
   6838 let isTaken = Inst{13};
   6839 let isExtendable = 1;
   6840 let opExtendable = 2;
   6841 let isExtentSigned = 1;
   6842 let opExtentBits = 11;
   6843 let opExtentAlign = 2;
   6844 }
   6845 def J4_cmpgt_tp0_jump_t : HInst<
   6846 (outs),
   6847 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6848 "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
   6849 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6850 let Inst{0-0} = 0b0;
   6851 let Inst{13-12} = 0b10;
   6852 let Inst{31-22} = 0b0001010010;
   6853 let isPredicated = 1;
   6854 let isTerminator = 1;
   6855 let isBranch = 1;
   6856 let isPredicatedNew = 1;
   6857 let cofRelax1 = 1;
   6858 let cofRelax2 = 1;
   6859 let cofMax1 = 1;
   6860 let Uses = [P0];
   6861 let Defs = [P0, PC];
   6862 let BaseOpcode = "J4_cmpgtp0";
   6863 let isTaken = Inst{13};
   6864 let isExtendable = 1;
   6865 let opExtendable = 2;
   6866 let isExtentSigned = 1;
   6867 let opExtentBits = 11;
   6868 let opExtentAlign = 2;
   6869 }
   6870 def J4_cmpgt_tp1_jump_nt : HInst<
   6871 (outs),
   6872 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6873 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
   6874 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6875 let Inst{0-0} = 0b0;
   6876 let Inst{13-12} = 0b01;
   6877 let Inst{31-22} = 0b0001010010;
   6878 let isPredicated = 1;
   6879 let isTerminator = 1;
   6880 let isBranch = 1;
   6881 let isPredicatedNew = 1;
   6882 let cofRelax1 = 1;
   6883 let cofRelax2 = 1;
   6884 let cofMax1 = 1;
   6885 let Uses = [P1];
   6886 let Defs = [P1, PC];
   6887 let BaseOpcode = "J4_cmpgtp1";
   6888 let isTaken = Inst{13};
   6889 let isExtendable = 1;
   6890 let opExtendable = 2;
   6891 let isExtentSigned = 1;
   6892 let opExtentBits = 11;
   6893 let opExtentAlign = 2;
   6894 }
   6895 def J4_cmpgt_tp1_jump_t : HInst<
   6896 (outs),
   6897 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   6898 "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
   6899 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   6900 let Inst{0-0} = 0b0;
   6901 let Inst{13-12} = 0b11;
   6902 let Inst{31-22} = 0b0001010010;
   6903 let isPredicated = 1;
   6904 let isTerminator = 1;
   6905 let isBranch = 1;
   6906 let isPredicatedNew = 1;
   6907 let cofRelax1 = 1;
   6908 let cofRelax2 = 1;
   6909 let cofMax1 = 1;
   6910 let Uses = [P1];
   6911 let Defs = [P1, PC];
   6912 let BaseOpcode = "J4_cmpgtp1";
   6913 let isTaken = Inst{13};
   6914 let isExtendable = 1;
   6915 let opExtendable = 2;
   6916 let isExtentSigned = 1;
   6917 let opExtentBits = 11;
   6918 let opExtentAlign = 2;
   6919 }
   6920 def J4_cmpgti_f_jumpnv_nt : HInst<
   6921 (outs),
   6922 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6923 "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
   6924 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6925 let Inst{0-0} = 0b0;
   6926 let Inst{13-13} = 0b0;
   6927 let Inst{19-19} = 0b0;
   6928 let Inst{31-22} = 0b0010010011;
   6929 let isPredicated = 1;
   6930 let isPredicatedFalse = 1;
   6931 let isTerminator = 1;
   6932 let isBranch = 1;
   6933 let isNewValue = 1;
   6934 let cofMax1 = 1;
   6935 let isRestrictNoSlot1Store = 1;
   6936 let Defs = [PC];
   6937 let BaseOpcode = "J4_cmpgtir";
   6938 let isTaken = Inst{13};
   6939 let isExtendable = 1;
   6940 let opExtendable = 2;
   6941 let isExtentSigned = 1;
   6942 let opExtentBits = 11;
   6943 let opExtentAlign = 2;
   6944 let opNewValue = 0;
   6945 }
   6946 def J4_cmpgti_f_jumpnv_t : HInst<
   6947 (outs),
   6948 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   6949 "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
   6950 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   6951 let Inst{0-0} = 0b0;
   6952 let Inst{13-13} = 0b1;
   6953 let Inst{19-19} = 0b0;
   6954 let Inst{31-22} = 0b0010010011;
   6955 let isPredicated = 1;
   6956 let isPredicatedFalse = 1;
   6957 let isTerminator = 1;
   6958 let isBranch = 1;
   6959 let isNewValue = 1;
   6960 let cofMax1 = 1;
   6961 let isRestrictNoSlot1Store = 1;
   6962 let Defs = [PC];
   6963 let BaseOpcode = "J4_cmpgtir";
   6964 let isTaken = Inst{13};
   6965 let isExtendable = 1;
   6966 let opExtendable = 2;
   6967 let isExtentSigned = 1;
   6968 let opExtentBits = 11;
   6969 let opExtentAlign = 2;
   6970 let opNewValue = 0;
   6971 }
   6972 def J4_cmpgti_fp0_jump_nt : HInst<
   6973 (outs),
   6974 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   6975 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
   6976 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   6977 let Inst{0-0} = 0b0;
   6978 let Inst{13-13} = 0b0;
   6979 let Inst{31-22} = 0b0001000011;
   6980 let isPredicated = 1;
   6981 let isPredicatedFalse = 1;
   6982 let isTerminator = 1;
   6983 let isBranch = 1;
   6984 let isPredicatedNew = 1;
   6985 let cofRelax1 = 1;
   6986 let cofRelax2 = 1;
   6987 let cofMax1 = 1;
   6988 let Uses = [P0];
   6989 let Defs = [P0, PC];
   6990 let BaseOpcode = "J4_cmpgtip0";
   6991 let isTaken = Inst{13};
   6992 let isExtendable = 1;
   6993 let opExtendable = 2;
   6994 let isExtentSigned = 1;
   6995 let opExtentBits = 11;
   6996 let opExtentAlign = 2;
   6997 }
   6998 def J4_cmpgti_fp0_jump_t : HInst<
   6999 (outs),
   7000 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7001 "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
   7002 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7003 let Inst{0-0} = 0b0;
   7004 let Inst{13-13} = 0b1;
   7005 let Inst{31-22} = 0b0001000011;
   7006 let isPredicated = 1;
   7007 let isPredicatedFalse = 1;
   7008 let isTerminator = 1;
   7009 let isBranch = 1;
   7010 let isPredicatedNew = 1;
   7011 let cofRelax1 = 1;
   7012 let cofRelax2 = 1;
   7013 let cofMax1 = 1;
   7014 let Uses = [P0];
   7015 let Defs = [P0, PC];
   7016 let BaseOpcode = "J4_cmpgtip0";
   7017 let isTaken = Inst{13};
   7018 let isExtendable = 1;
   7019 let opExtendable = 2;
   7020 let isExtentSigned = 1;
   7021 let opExtentBits = 11;
   7022 let opExtentAlign = 2;
   7023 }
   7024 def J4_cmpgti_fp1_jump_nt : HInst<
   7025 (outs),
   7026 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7027 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
   7028 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7029 let Inst{0-0} = 0b0;
   7030 let Inst{13-13} = 0b0;
   7031 let Inst{31-22} = 0b0001001011;
   7032 let isPredicated = 1;
   7033 let isPredicatedFalse = 1;
   7034 let isTerminator = 1;
   7035 let isBranch = 1;
   7036 let isPredicatedNew = 1;
   7037 let cofRelax1 = 1;
   7038 let cofRelax2 = 1;
   7039 let cofMax1 = 1;
   7040 let Uses = [P1];
   7041 let Defs = [P1, PC];
   7042 let BaseOpcode = "J4_cmpgtip1";
   7043 let isTaken = Inst{13};
   7044 let isExtendable = 1;
   7045 let opExtendable = 2;
   7046 let isExtentSigned = 1;
   7047 let opExtentBits = 11;
   7048 let opExtentAlign = 2;
   7049 }
   7050 def J4_cmpgti_fp1_jump_t : HInst<
   7051 (outs),
   7052 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7053 "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
   7054 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7055 let Inst{0-0} = 0b0;
   7056 let Inst{13-13} = 0b1;
   7057 let Inst{31-22} = 0b0001001011;
   7058 let isPredicated = 1;
   7059 let isPredicatedFalse = 1;
   7060 let isTerminator = 1;
   7061 let isBranch = 1;
   7062 let isPredicatedNew = 1;
   7063 let cofRelax1 = 1;
   7064 let cofRelax2 = 1;
   7065 let cofMax1 = 1;
   7066 let Uses = [P1];
   7067 let Defs = [P1, PC];
   7068 let BaseOpcode = "J4_cmpgtip1";
   7069 let isTaken = Inst{13};
   7070 let isExtendable = 1;
   7071 let opExtendable = 2;
   7072 let isExtentSigned = 1;
   7073 let opExtentBits = 11;
   7074 let opExtentAlign = 2;
   7075 }
   7076 def J4_cmpgti_t_jumpnv_nt : HInst<
   7077 (outs),
   7078 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   7079 "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
   7080 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   7081 let Inst{0-0} = 0b0;
   7082 let Inst{13-13} = 0b0;
   7083 let Inst{19-19} = 0b0;
   7084 let Inst{31-22} = 0b0010010010;
   7085 let isPredicated = 1;
   7086 let isTerminator = 1;
   7087 let isBranch = 1;
   7088 let isNewValue = 1;
   7089 let cofMax1 = 1;
   7090 let isRestrictNoSlot1Store = 1;
   7091 let Defs = [PC];
   7092 let BaseOpcode = "J4_cmpgtir";
   7093 let isTaken = Inst{13};
   7094 let isExtendable = 1;
   7095 let opExtendable = 2;
   7096 let isExtentSigned = 1;
   7097 let opExtentBits = 11;
   7098 let opExtentAlign = 2;
   7099 let opNewValue = 0;
   7100 }
   7101 def J4_cmpgti_t_jumpnv_t : HInst<
   7102 (outs),
   7103 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   7104 "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
   7105 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   7106 let Inst{0-0} = 0b0;
   7107 let Inst{13-13} = 0b1;
   7108 let Inst{19-19} = 0b0;
   7109 let Inst{31-22} = 0b0010010010;
   7110 let isPredicated = 1;
   7111 let isTerminator = 1;
   7112 let isBranch = 1;
   7113 let isNewValue = 1;
   7114 let cofMax1 = 1;
   7115 let isRestrictNoSlot1Store = 1;
   7116 let Defs = [PC];
   7117 let BaseOpcode = "J4_cmpgtir";
   7118 let isTaken = Inst{13};
   7119 let isExtendable = 1;
   7120 let opExtendable = 2;
   7121 let isExtentSigned = 1;
   7122 let opExtentBits = 11;
   7123 let opExtentAlign = 2;
   7124 let opNewValue = 0;
   7125 }
   7126 def J4_cmpgti_tp0_jump_nt : HInst<
   7127 (outs),
   7128 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7129 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
   7130 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7131 let Inst{0-0} = 0b0;
   7132 let Inst{13-13} = 0b0;
   7133 let Inst{31-22} = 0b0001000010;
   7134 let isPredicated = 1;
   7135 let isTerminator = 1;
   7136 let isBranch = 1;
   7137 let isPredicatedNew = 1;
   7138 let cofRelax1 = 1;
   7139 let cofRelax2 = 1;
   7140 let cofMax1 = 1;
   7141 let Uses = [P0];
   7142 let Defs = [P0, PC];
   7143 let BaseOpcode = "J4_cmpgtip0";
   7144 let isTaken = Inst{13};
   7145 let isExtendable = 1;
   7146 let opExtendable = 2;
   7147 let isExtentSigned = 1;
   7148 let opExtentBits = 11;
   7149 let opExtentAlign = 2;
   7150 }
   7151 def J4_cmpgti_tp0_jump_t : HInst<
   7152 (outs),
   7153 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7154 "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
   7155 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7156 let Inst{0-0} = 0b0;
   7157 let Inst{13-13} = 0b1;
   7158 let Inst{31-22} = 0b0001000010;
   7159 let isPredicated = 1;
   7160 let isTerminator = 1;
   7161 let isBranch = 1;
   7162 let isPredicatedNew = 1;
   7163 let cofRelax1 = 1;
   7164 let cofRelax2 = 1;
   7165 let cofMax1 = 1;
   7166 let Uses = [P0];
   7167 let Defs = [P0, PC];
   7168 let BaseOpcode = "J4_cmpgtip0";
   7169 let isTaken = Inst{13};
   7170 let isExtendable = 1;
   7171 let opExtendable = 2;
   7172 let isExtentSigned = 1;
   7173 let opExtentBits = 11;
   7174 let opExtentAlign = 2;
   7175 }
   7176 def J4_cmpgti_tp1_jump_nt : HInst<
   7177 (outs),
   7178 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7179 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
   7180 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7181 let Inst{0-0} = 0b0;
   7182 let Inst{13-13} = 0b0;
   7183 let Inst{31-22} = 0b0001001010;
   7184 let isPredicated = 1;
   7185 let isTerminator = 1;
   7186 let isBranch = 1;
   7187 let isPredicatedNew = 1;
   7188 let cofRelax1 = 1;
   7189 let cofRelax2 = 1;
   7190 let cofMax1 = 1;
   7191 let Uses = [P1];
   7192 let Defs = [P1, PC];
   7193 let BaseOpcode = "J4_cmpgtip1";
   7194 let isTaken = Inst{13};
   7195 let isExtendable = 1;
   7196 let opExtendable = 2;
   7197 let isExtentSigned = 1;
   7198 let opExtentBits = 11;
   7199 let opExtentAlign = 2;
   7200 }
   7201 def J4_cmpgti_tp1_jump_t : HInst<
   7202 (outs),
   7203 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7204 "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
   7205 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7206 let Inst{0-0} = 0b0;
   7207 let Inst{13-13} = 0b1;
   7208 let Inst{31-22} = 0b0001001010;
   7209 let isPredicated = 1;
   7210 let isTerminator = 1;
   7211 let isBranch = 1;
   7212 let isPredicatedNew = 1;
   7213 let cofRelax1 = 1;
   7214 let cofRelax2 = 1;
   7215 let cofMax1 = 1;
   7216 let Uses = [P1];
   7217 let Defs = [P1, PC];
   7218 let BaseOpcode = "J4_cmpgtip1";
   7219 let isTaken = Inst{13};
   7220 let isExtendable = 1;
   7221 let opExtendable = 2;
   7222 let isExtentSigned = 1;
   7223 let opExtentBits = 11;
   7224 let opExtentAlign = 2;
   7225 }
   7226 def J4_cmpgtn1_f_jumpnv_nt : HInst<
   7227 (outs),
   7228 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   7229 "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
   7230 tc_bde7aaf4, TypeNCJ>, Enc_3694bd, PredRel {
   7231 let Inst{0-0} = 0b0;
   7232 let Inst{13-8} = 0b000000;
   7233 let Inst{19-19} = 0b0;
   7234 let Inst{31-22} = 0b0010011011;
   7235 let isPredicated = 1;
   7236 let isPredicatedFalse = 1;
   7237 let isTerminator = 1;
   7238 let isBranch = 1;
   7239 let isNewValue = 1;
   7240 let cofMax1 = 1;
   7241 let isRestrictNoSlot1Store = 1;
   7242 let Defs = [PC];
   7243 let BaseOpcode = "J4_cmpgtn1r";
   7244 let isTaken = Inst{13};
   7245 let isExtendable = 1;
   7246 let opExtendable = 2;
   7247 let isExtentSigned = 1;
   7248 let opExtentBits = 11;
   7249 let opExtentAlign = 2;
   7250 let opNewValue = 0;
   7251 }
   7252 def J4_cmpgtn1_f_jumpnv_t : HInst<
   7253 (outs),
   7254 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   7255 "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
   7256 tc_bde7aaf4, TypeNCJ>, Enc_a6853f, PredRel {
   7257 let Inst{0-0} = 0b0;
   7258 let Inst{13-8} = 0b100000;
   7259 let Inst{19-19} = 0b0;
   7260 let Inst{31-22} = 0b0010011011;
   7261 let isPredicated = 1;
   7262 let isPredicatedFalse = 1;
   7263 let isTerminator = 1;
   7264 let isBranch = 1;
   7265 let isNewValue = 1;
   7266 let cofMax1 = 1;
   7267 let isRestrictNoSlot1Store = 1;
   7268 let Defs = [PC];
   7269 let BaseOpcode = "J4_cmpgtn1r";
   7270 let isTaken = Inst{13};
   7271 let isExtendable = 1;
   7272 let opExtendable = 2;
   7273 let isExtentSigned = 1;
   7274 let opExtentBits = 11;
   7275 let opExtentAlign = 2;
   7276 let opNewValue = 0;
   7277 }
   7278 def J4_cmpgtn1_fp0_jump_nt : HInst<
   7279 (outs),
   7280 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7281 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
   7282 tc_99be14ca, TypeCJ>, Enc_a42857, PredRel {
   7283 let Inst{0-0} = 0b0;
   7284 let Inst{13-8} = 0b000001;
   7285 let Inst{31-22} = 0b0001000111;
   7286 let isPredicated = 1;
   7287 let isPredicatedFalse = 1;
   7288 let isTerminator = 1;
   7289 let isBranch = 1;
   7290 let isPredicatedNew = 1;
   7291 let cofRelax1 = 1;
   7292 let cofRelax2 = 1;
   7293 let cofMax1 = 1;
   7294 let Uses = [P0];
   7295 let Defs = [P0, PC];
   7296 let BaseOpcode = "J4_cmpgtn1p0";
   7297 let isTaken = Inst{13};
   7298 let isExtendable = 1;
   7299 let opExtendable = 2;
   7300 let isExtentSigned = 1;
   7301 let opExtentBits = 11;
   7302 let opExtentAlign = 2;
   7303 }
   7304 def J4_cmpgtn1_fp0_jump_t : HInst<
   7305 (outs),
   7306 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7307 "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
   7308 tc_99be14ca, TypeCJ>, Enc_f6fe0b, PredRel {
   7309 let Inst{0-0} = 0b0;
   7310 let Inst{13-8} = 0b100001;
   7311 let Inst{31-22} = 0b0001000111;
   7312 let isPredicated = 1;
   7313 let isPredicatedFalse = 1;
   7314 let isTerminator = 1;
   7315 let isBranch = 1;
   7316 let isPredicatedNew = 1;
   7317 let cofRelax1 = 1;
   7318 let cofRelax2 = 1;
   7319 let cofMax1 = 1;
   7320 let Uses = [P0];
   7321 let Defs = [P0, PC];
   7322 let BaseOpcode = "J4_cmpgtn1p0";
   7323 let isTaken = Inst{13};
   7324 let isExtendable = 1;
   7325 let opExtendable = 2;
   7326 let isExtentSigned = 1;
   7327 let opExtentBits = 11;
   7328 let opExtentAlign = 2;
   7329 }
   7330 def J4_cmpgtn1_fp1_jump_nt : HInst<
   7331 (outs),
   7332 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7333 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
   7334 tc_99be14ca, TypeCJ>, Enc_3e3989, PredRel {
   7335 let Inst{0-0} = 0b0;
   7336 let Inst{13-8} = 0b000001;
   7337 let Inst{31-22} = 0b0001001111;
   7338 let isPredicated = 1;
   7339 let isPredicatedFalse = 1;
   7340 let isTerminator = 1;
   7341 let isBranch = 1;
   7342 let isPredicatedNew = 1;
   7343 let cofRelax1 = 1;
   7344 let cofRelax2 = 1;
   7345 let cofMax1 = 1;
   7346 let Uses = [P1];
   7347 let Defs = [P1, PC];
   7348 let BaseOpcode = "J4_cmpgtn1p1";
   7349 let isTaken = Inst{13};
   7350 let isExtendable = 1;
   7351 let opExtendable = 2;
   7352 let isExtentSigned = 1;
   7353 let opExtentBits = 11;
   7354 let opExtentAlign = 2;
   7355 }
   7356 def J4_cmpgtn1_fp1_jump_t : HInst<
   7357 (outs),
   7358 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7359 "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
   7360 tc_99be14ca, TypeCJ>, Enc_b909d2, PredRel {
   7361 let Inst{0-0} = 0b0;
   7362 let Inst{13-8} = 0b100001;
   7363 let Inst{31-22} = 0b0001001111;
   7364 let isPredicated = 1;
   7365 let isPredicatedFalse = 1;
   7366 let isTerminator = 1;
   7367 let isBranch = 1;
   7368 let isPredicatedNew = 1;
   7369 let cofRelax1 = 1;
   7370 let cofRelax2 = 1;
   7371 let cofMax1 = 1;
   7372 let Uses = [P1];
   7373 let Defs = [P1, PC];
   7374 let BaseOpcode = "J4_cmpgtn1p1";
   7375 let isTaken = Inst{13};
   7376 let isExtendable = 1;
   7377 let opExtendable = 2;
   7378 let isExtentSigned = 1;
   7379 let opExtentBits = 11;
   7380 let opExtentAlign = 2;
   7381 }
   7382 def J4_cmpgtn1_t_jumpnv_nt : HInst<
   7383 (outs),
   7384 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   7385 "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
   7386 tc_bde7aaf4, TypeNCJ>, Enc_f82302, PredRel {
   7387 let Inst{0-0} = 0b0;
   7388 let Inst{13-8} = 0b000000;
   7389 let Inst{19-19} = 0b0;
   7390 let Inst{31-22} = 0b0010011010;
   7391 let isPredicated = 1;
   7392 let isTerminator = 1;
   7393 let isBranch = 1;
   7394 let isNewValue = 1;
   7395 let cofMax1 = 1;
   7396 let isRestrictNoSlot1Store = 1;
   7397 let Defs = [PC];
   7398 let BaseOpcode = "J4_cmpgtn1r";
   7399 let isTaken = Inst{13};
   7400 let isExtendable = 1;
   7401 let opExtendable = 2;
   7402 let isExtentSigned = 1;
   7403 let opExtentBits = 11;
   7404 let opExtentAlign = 2;
   7405 let opNewValue = 0;
   7406 }
   7407 def J4_cmpgtn1_t_jumpnv_t : HInst<
   7408 (outs),
   7409 (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
   7410 "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
   7411 tc_bde7aaf4, TypeNCJ>, Enc_6413b6, PredRel {
   7412 let Inst{0-0} = 0b0;
   7413 let Inst{13-8} = 0b100000;
   7414 let Inst{19-19} = 0b0;
   7415 let Inst{31-22} = 0b0010011010;
   7416 let isPredicated = 1;
   7417 let isTerminator = 1;
   7418 let isBranch = 1;
   7419 let isNewValue = 1;
   7420 let cofMax1 = 1;
   7421 let isRestrictNoSlot1Store = 1;
   7422 let Defs = [PC];
   7423 let BaseOpcode = "J4_cmpgtn1r";
   7424 let isTaken = Inst{13};
   7425 let isExtendable = 1;
   7426 let opExtendable = 2;
   7427 let isExtentSigned = 1;
   7428 let opExtentBits = 11;
   7429 let opExtentAlign = 2;
   7430 let opNewValue = 0;
   7431 }
   7432 def J4_cmpgtn1_tp0_jump_nt : HInst<
   7433 (outs),
   7434 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7435 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
   7436 tc_99be14ca, TypeCJ>, Enc_b78edd, PredRel {
   7437 let Inst{0-0} = 0b0;
   7438 let Inst{13-8} = 0b000001;
   7439 let Inst{31-22} = 0b0001000110;
   7440 let isPredicated = 1;
   7441 let isTerminator = 1;
   7442 let isBranch = 1;
   7443 let isPredicatedNew = 1;
   7444 let cofRelax1 = 1;
   7445 let cofRelax2 = 1;
   7446 let cofMax1 = 1;
   7447 let Uses = [P0];
   7448 let Defs = [P0, PC];
   7449 let BaseOpcode = "J4_cmpgtn1p0";
   7450 let isTaken = Inst{13};
   7451 let isExtendable = 1;
   7452 let opExtendable = 2;
   7453 let isExtentSigned = 1;
   7454 let opExtentBits = 11;
   7455 let opExtentAlign = 2;
   7456 }
   7457 def J4_cmpgtn1_tp0_jump_t : HInst<
   7458 (outs),
   7459 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7460 "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
   7461 tc_99be14ca, TypeCJ>, Enc_041d7b, PredRel {
   7462 let Inst{0-0} = 0b0;
   7463 let Inst{13-8} = 0b100001;
   7464 let Inst{31-22} = 0b0001000110;
   7465 let isPredicated = 1;
   7466 let isTerminator = 1;
   7467 let isBranch = 1;
   7468 let isPredicatedNew = 1;
   7469 let cofRelax1 = 1;
   7470 let cofRelax2 = 1;
   7471 let cofMax1 = 1;
   7472 let Uses = [P0];
   7473 let Defs = [P0, PC];
   7474 let BaseOpcode = "J4_cmpgtn1p0";
   7475 let isTaken = Inst{13};
   7476 let isExtendable = 1;
   7477 let opExtendable = 2;
   7478 let isExtentSigned = 1;
   7479 let opExtentBits = 11;
   7480 let opExtentAlign = 2;
   7481 }
   7482 def J4_cmpgtn1_tp1_jump_nt : HInst<
   7483 (outs),
   7484 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7485 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
   7486 tc_99be14ca, TypeCJ>, Enc_b1e1fb, PredRel {
   7487 let Inst{0-0} = 0b0;
   7488 let Inst{13-8} = 0b000001;
   7489 let Inst{31-22} = 0b0001001110;
   7490 let isPredicated = 1;
   7491 let isTerminator = 1;
   7492 let isBranch = 1;
   7493 let isPredicatedNew = 1;
   7494 let cofRelax1 = 1;
   7495 let cofRelax2 = 1;
   7496 let cofMax1 = 1;
   7497 let Uses = [P1];
   7498 let Defs = [P1, PC];
   7499 let BaseOpcode = "J4_cmpgtn1p1";
   7500 let isTaken = Inst{13};
   7501 let isExtendable = 1;
   7502 let opExtendable = 2;
   7503 let isExtentSigned = 1;
   7504 let opExtentBits = 11;
   7505 let opExtentAlign = 2;
   7506 }
   7507 def J4_cmpgtn1_tp1_jump_t : HInst<
   7508 (outs),
   7509 (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
   7510 "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
   7511 tc_99be14ca, TypeCJ>, Enc_178717, PredRel {
   7512 let Inst{0-0} = 0b0;
   7513 let Inst{13-8} = 0b100001;
   7514 let Inst{31-22} = 0b0001001110;
   7515 let isPredicated = 1;
   7516 let isTerminator = 1;
   7517 let isBranch = 1;
   7518 let isPredicatedNew = 1;
   7519 let cofRelax1 = 1;
   7520 let cofRelax2 = 1;
   7521 let cofMax1 = 1;
   7522 let Uses = [P1];
   7523 let Defs = [P1, PC];
   7524 let BaseOpcode = "J4_cmpgtn1p1";
   7525 let isTaken = Inst{13};
   7526 let isExtendable = 1;
   7527 let opExtendable = 2;
   7528 let isExtentSigned = 1;
   7529 let opExtentBits = 11;
   7530 let opExtentAlign = 2;
   7531 }
   7532 def J4_cmpgtu_f_jumpnv_nt : HInst<
   7533 (outs),
   7534 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   7535 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
   7536 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   7537 let Inst{0-0} = 0b0;
   7538 let Inst{13-13} = 0b0;
   7539 let Inst{19-19} = 0b0;
   7540 let Inst{31-22} = 0b0010000101;
   7541 let isPredicated = 1;
   7542 let isPredicatedFalse = 1;
   7543 let isTerminator = 1;
   7544 let isBranch = 1;
   7545 let isNewValue = 1;
   7546 let cofMax1 = 1;
   7547 let isRestrictNoSlot1Store = 1;
   7548 let Defs = [PC];
   7549 let BaseOpcode = "J4_cmpgtur";
   7550 let isTaken = Inst{13};
   7551 let isExtendable = 1;
   7552 let opExtendable = 2;
   7553 let isExtentSigned = 1;
   7554 let opExtentBits = 11;
   7555 let opExtentAlign = 2;
   7556 let opNewValue = 0;
   7557 }
   7558 def J4_cmpgtu_f_jumpnv_t : HInst<
   7559 (outs),
   7560 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   7561 "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
   7562 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   7563 let Inst{0-0} = 0b0;
   7564 let Inst{13-13} = 0b1;
   7565 let Inst{19-19} = 0b0;
   7566 let Inst{31-22} = 0b0010000101;
   7567 let isPredicated = 1;
   7568 let isPredicatedFalse = 1;
   7569 let isTerminator = 1;
   7570 let isBranch = 1;
   7571 let isNewValue = 1;
   7572 let cofMax1 = 1;
   7573 let isRestrictNoSlot1Store = 1;
   7574 let Defs = [PC];
   7575 let BaseOpcode = "J4_cmpgtur";
   7576 let isTaken = Inst{13};
   7577 let isExtendable = 1;
   7578 let opExtendable = 2;
   7579 let isExtentSigned = 1;
   7580 let opExtentBits = 11;
   7581 let opExtentAlign = 2;
   7582 let opNewValue = 0;
   7583 }
   7584 def J4_cmpgtu_fp0_jump_nt : HInst<
   7585 (outs),
   7586 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7587 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
   7588 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7589 let Inst{0-0} = 0b0;
   7590 let Inst{13-12} = 0b00;
   7591 let Inst{31-22} = 0b0001010101;
   7592 let isPredicated = 1;
   7593 let isPredicatedFalse = 1;
   7594 let isTerminator = 1;
   7595 let isBranch = 1;
   7596 let isPredicatedNew = 1;
   7597 let cofRelax1 = 1;
   7598 let cofRelax2 = 1;
   7599 let cofMax1 = 1;
   7600 let Uses = [P0];
   7601 let Defs = [P0, PC];
   7602 let BaseOpcode = "J4_cmpgtup0";
   7603 let isTaken = Inst{13};
   7604 let isExtendable = 1;
   7605 let opExtendable = 2;
   7606 let isExtentSigned = 1;
   7607 let opExtentBits = 11;
   7608 let opExtentAlign = 2;
   7609 }
   7610 def J4_cmpgtu_fp0_jump_t : HInst<
   7611 (outs),
   7612 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7613 "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
   7614 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7615 let Inst{0-0} = 0b0;
   7616 let Inst{13-12} = 0b10;
   7617 let Inst{31-22} = 0b0001010101;
   7618 let isPredicated = 1;
   7619 let isPredicatedFalse = 1;
   7620 let isTerminator = 1;
   7621 let isBranch = 1;
   7622 let isPredicatedNew = 1;
   7623 let cofRelax1 = 1;
   7624 let cofRelax2 = 1;
   7625 let cofMax1 = 1;
   7626 let Uses = [P0];
   7627 let Defs = [P0, PC];
   7628 let BaseOpcode = "J4_cmpgtup0";
   7629 let isTaken = Inst{13};
   7630 let isExtendable = 1;
   7631 let opExtendable = 2;
   7632 let isExtentSigned = 1;
   7633 let opExtentBits = 11;
   7634 let opExtentAlign = 2;
   7635 }
   7636 def J4_cmpgtu_fp1_jump_nt : HInst<
   7637 (outs),
   7638 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7639 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
   7640 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7641 let Inst{0-0} = 0b0;
   7642 let Inst{13-12} = 0b01;
   7643 let Inst{31-22} = 0b0001010101;
   7644 let isPredicated = 1;
   7645 let isPredicatedFalse = 1;
   7646 let isTerminator = 1;
   7647 let isBranch = 1;
   7648 let isPredicatedNew = 1;
   7649 let cofRelax1 = 1;
   7650 let cofRelax2 = 1;
   7651 let cofMax1 = 1;
   7652 let Uses = [P1];
   7653 let Defs = [P1, PC];
   7654 let BaseOpcode = "J4_cmpgtup1";
   7655 let isTaken = Inst{13};
   7656 let isExtendable = 1;
   7657 let opExtendable = 2;
   7658 let isExtentSigned = 1;
   7659 let opExtentBits = 11;
   7660 let opExtentAlign = 2;
   7661 }
   7662 def J4_cmpgtu_fp1_jump_t : HInst<
   7663 (outs),
   7664 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7665 "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
   7666 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7667 let Inst{0-0} = 0b0;
   7668 let Inst{13-12} = 0b11;
   7669 let Inst{31-22} = 0b0001010101;
   7670 let isPredicated = 1;
   7671 let isPredicatedFalse = 1;
   7672 let isTerminator = 1;
   7673 let isBranch = 1;
   7674 let isPredicatedNew = 1;
   7675 let cofRelax1 = 1;
   7676 let cofRelax2 = 1;
   7677 let cofMax1 = 1;
   7678 let Uses = [P1];
   7679 let Defs = [P1, PC];
   7680 let BaseOpcode = "J4_cmpgtup1";
   7681 let isTaken = Inst{13};
   7682 let isExtendable = 1;
   7683 let opExtendable = 2;
   7684 let isExtentSigned = 1;
   7685 let opExtentBits = 11;
   7686 let opExtentAlign = 2;
   7687 }
   7688 def J4_cmpgtu_t_jumpnv_nt : HInst<
   7689 (outs),
   7690 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   7691 "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
   7692 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   7693 let Inst{0-0} = 0b0;
   7694 let Inst{13-13} = 0b0;
   7695 let Inst{19-19} = 0b0;
   7696 let Inst{31-22} = 0b0010000100;
   7697 let isPredicated = 1;
   7698 let isTerminator = 1;
   7699 let isBranch = 1;
   7700 let isNewValue = 1;
   7701 let cofMax1 = 1;
   7702 let isRestrictNoSlot1Store = 1;
   7703 let Defs = [PC];
   7704 let BaseOpcode = "J4_cmpgtur";
   7705 let isTaken = Inst{13};
   7706 let isExtendable = 1;
   7707 let opExtendable = 2;
   7708 let isExtentSigned = 1;
   7709 let opExtentBits = 11;
   7710 let opExtentAlign = 2;
   7711 let opNewValue = 0;
   7712 }
   7713 def J4_cmpgtu_t_jumpnv_t : HInst<
   7714 (outs),
   7715 (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
   7716 "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
   7717 tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel {
   7718 let Inst{0-0} = 0b0;
   7719 let Inst{13-13} = 0b1;
   7720 let Inst{19-19} = 0b0;
   7721 let Inst{31-22} = 0b0010000100;
   7722 let isPredicated = 1;
   7723 let isTerminator = 1;
   7724 let isBranch = 1;
   7725 let isNewValue = 1;
   7726 let cofMax1 = 1;
   7727 let isRestrictNoSlot1Store = 1;
   7728 let Defs = [PC];
   7729 let BaseOpcode = "J4_cmpgtur";
   7730 let isTaken = Inst{13};
   7731 let isExtendable = 1;
   7732 let opExtendable = 2;
   7733 let isExtentSigned = 1;
   7734 let opExtentBits = 11;
   7735 let opExtentAlign = 2;
   7736 let opNewValue = 0;
   7737 }
   7738 def J4_cmpgtu_tp0_jump_nt : HInst<
   7739 (outs),
   7740 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7741 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
   7742 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7743 let Inst{0-0} = 0b0;
   7744 let Inst{13-12} = 0b00;
   7745 let Inst{31-22} = 0b0001010100;
   7746 let isPredicated = 1;
   7747 let isTerminator = 1;
   7748 let isBranch = 1;
   7749 let isPredicatedNew = 1;
   7750 let cofRelax1 = 1;
   7751 let cofRelax2 = 1;
   7752 let cofMax1 = 1;
   7753 let Uses = [P0];
   7754 let Defs = [P0, PC];
   7755 let BaseOpcode = "J4_cmpgtup0";
   7756 let isTaken = Inst{13};
   7757 let isExtendable = 1;
   7758 let opExtendable = 2;
   7759 let isExtentSigned = 1;
   7760 let opExtentBits = 11;
   7761 let opExtentAlign = 2;
   7762 }
   7763 def J4_cmpgtu_tp0_jump_t : HInst<
   7764 (outs),
   7765 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7766 "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
   7767 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7768 let Inst{0-0} = 0b0;
   7769 let Inst{13-12} = 0b10;
   7770 let Inst{31-22} = 0b0001010100;
   7771 let isPredicated = 1;
   7772 let isTerminator = 1;
   7773 let isBranch = 1;
   7774 let isPredicatedNew = 1;
   7775 let cofRelax1 = 1;
   7776 let cofRelax2 = 1;
   7777 let cofMax1 = 1;
   7778 let Uses = [P0];
   7779 let Defs = [P0, PC];
   7780 let BaseOpcode = "J4_cmpgtup0";
   7781 let isTaken = Inst{13};
   7782 let isExtendable = 1;
   7783 let opExtendable = 2;
   7784 let isExtentSigned = 1;
   7785 let opExtentBits = 11;
   7786 let opExtentAlign = 2;
   7787 }
   7788 def J4_cmpgtu_tp1_jump_nt : HInst<
   7789 (outs),
   7790 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7791 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
   7792 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7793 let Inst{0-0} = 0b0;
   7794 let Inst{13-12} = 0b01;
   7795 let Inst{31-22} = 0b0001010100;
   7796 let isPredicated = 1;
   7797 let isTerminator = 1;
   7798 let isBranch = 1;
   7799 let isPredicatedNew = 1;
   7800 let cofRelax1 = 1;
   7801 let cofRelax2 = 1;
   7802 let cofMax1 = 1;
   7803 let Uses = [P1];
   7804 let Defs = [P1, PC];
   7805 let BaseOpcode = "J4_cmpgtup1";
   7806 let isTaken = Inst{13};
   7807 let isExtendable = 1;
   7808 let opExtendable = 2;
   7809 let isExtentSigned = 1;
   7810 let opExtentBits = 11;
   7811 let opExtentAlign = 2;
   7812 }
   7813 def J4_cmpgtu_tp1_jump_t : HInst<
   7814 (outs),
   7815 (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
   7816 "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
   7817 tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel {
   7818 let Inst{0-0} = 0b0;
   7819 let Inst{13-12} = 0b11;
   7820 let Inst{31-22} = 0b0001010100;
   7821 let isPredicated = 1;
   7822 let isTerminator = 1;
   7823 let isBranch = 1;
   7824 let isPredicatedNew = 1;
   7825 let cofRelax1 = 1;
   7826 let cofRelax2 = 1;
   7827 let cofMax1 = 1;
   7828 let Uses = [P1];
   7829 let Defs = [P1, PC];
   7830 let BaseOpcode = "J4_cmpgtup1";
   7831 let isTaken = Inst{13};
   7832 let isExtendable = 1;
   7833 let opExtendable = 2;
   7834 let isExtentSigned = 1;
   7835 let opExtentBits = 11;
   7836 let opExtentAlign = 2;
   7837 }
   7838 def J4_cmpgtui_f_jumpnv_nt : HInst<
   7839 (outs),
   7840 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   7841 "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
   7842 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   7843 let Inst{0-0} = 0b0;
   7844 let Inst{13-13} = 0b0;
   7845 let Inst{19-19} = 0b0;
   7846 let Inst{31-22} = 0b0010010101;
   7847 let isPredicated = 1;
   7848 let isPredicatedFalse = 1;
   7849 let isTerminator = 1;
   7850 let isBranch = 1;
   7851 let isNewValue = 1;
   7852 let cofMax1 = 1;
   7853 let isRestrictNoSlot1Store = 1;
   7854 let Defs = [PC];
   7855 let BaseOpcode = "J4_cmpgtuir";
   7856 let isTaken = Inst{13};
   7857 let isExtendable = 1;
   7858 let opExtendable = 2;
   7859 let isExtentSigned = 1;
   7860 let opExtentBits = 11;
   7861 let opExtentAlign = 2;
   7862 let opNewValue = 0;
   7863 }
   7864 def J4_cmpgtui_f_jumpnv_t : HInst<
   7865 (outs),
   7866 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   7867 "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
   7868 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   7869 let Inst{0-0} = 0b0;
   7870 let Inst{13-13} = 0b1;
   7871 let Inst{19-19} = 0b0;
   7872 let Inst{31-22} = 0b0010010101;
   7873 let isPredicated = 1;
   7874 let isPredicatedFalse = 1;
   7875 let isTerminator = 1;
   7876 let isBranch = 1;
   7877 let isNewValue = 1;
   7878 let cofMax1 = 1;
   7879 let isRestrictNoSlot1Store = 1;
   7880 let Defs = [PC];
   7881 let BaseOpcode = "J4_cmpgtuir";
   7882 let isTaken = Inst{13};
   7883 let isExtendable = 1;
   7884 let opExtendable = 2;
   7885 let isExtentSigned = 1;
   7886 let opExtentBits = 11;
   7887 let opExtentAlign = 2;
   7888 let opNewValue = 0;
   7889 }
   7890 def J4_cmpgtui_fp0_jump_nt : HInst<
   7891 (outs),
   7892 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7893 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
   7894 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7895 let Inst{0-0} = 0b0;
   7896 let Inst{13-13} = 0b0;
   7897 let Inst{31-22} = 0b0001000101;
   7898 let isPredicated = 1;
   7899 let isPredicatedFalse = 1;
   7900 let isTerminator = 1;
   7901 let isBranch = 1;
   7902 let isPredicatedNew = 1;
   7903 let cofRelax1 = 1;
   7904 let cofRelax2 = 1;
   7905 let cofMax1 = 1;
   7906 let Uses = [P0];
   7907 let Defs = [P0, PC];
   7908 let BaseOpcode = "J4_cmpgtuip0";
   7909 let isTaken = Inst{13};
   7910 let isExtendable = 1;
   7911 let opExtendable = 2;
   7912 let isExtentSigned = 1;
   7913 let opExtentBits = 11;
   7914 let opExtentAlign = 2;
   7915 }
   7916 def J4_cmpgtui_fp0_jump_t : HInst<
   7917 (outs),
   7918 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7919 "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
   7920 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7921 let Inst{0-0} = 0b0;
   7922 let Inst{13-13} = 0b1;
   7923 let Inst{31-22} = 0b0001000101;
   7924 let isPredicated = 1;
   7925 let isPredicatedFalse = 1;
   7926 let isTerminator = 1;
   7927 let isBranch = 1;
   7928 let isPredicatedNew = 1;
   7929 let cofRelax1 = 1;
   7930 let cofRelax2 = 1;
   7931 let cofMax1 = 1;
   7932 let Uses = [P0];
   7933 let Defs = [P0, PC];
   7934 let BaseOpcode = "J4_cmpgtuip0";
   7935 let isTaken = Inst{13};
   7936 let isExtendable = 1;
   7937 let opExtendable = 2;
   7938 let isExtentSigned = 1;
   7939 let opExtentBits = 11;
   7940 let opExtentAlign = 2;
   7941 }
   7942 def J4_cmpgtui_fp1_jump_nt : HInst<
   7943 (outs),
   7944 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7945 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
   7946 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7947 let Inst{0-0} = 0b0;
   7948 let Inst{13-13} = 0b0;
   7949 let Inst{31-22} = 0b0001001101;
   7950 let isPredicated = 1;
   7951 let isPredicatedFalse = 1;
   7952 let isTerminator = 1;
   7953 let isBranch = 1;
   7954 let isPredicatedNew = 1;
   7955 let cofRelax1 = 1;
   7956 let cofRelax2 = 1;
   7957 let cofMax1 = 1;
   7958 let Uses = [P1];
   7959 let Defs = [P1, PC];
   7960 let BaseOpcode = "J4_cmpgtuip1";
   7961 let isTaken = Inst{13};
   7962 let isExtendable = 1;
   7963 let opExtendable = 2;
   7964 let isExtentSigned = 1;
   7965 let opExtentBits = 11;
   7966 let opExtentAlign = 2;
   7967 }
   7968 def J4_cmpgtui_fp1_jump_t : HInst<
   7969 (outs),
   7970 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   7971 "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
   7972 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   7973 let Inst{0-0} = 0b0;
   7974 let Inst{13-13} = 0b1;
   7975 let Inst{31-22} = 0b0001001101;
   7976 let isPredicated = 1;
   7977 let isPredicatedFalse = 1;
   7978 let isTerminator = 1;
   7979 let isBranch = 1;
   7980 let isPredicatedNew = 1;
   7981 let cofRelax1 = 1;
   7982 let cofRelax2 = 1;
   7983 let cofMax1 = 1;
   7984 let Uses = [P1];
   7985 let Defs = [P1, PC];
   7986 let BaseOpcode = "J4_cmpgtuip1";
   7987 let isTaken = Inst{13};
   7988 let isExtendable = 1;
   7989 let opExtendable = 2;
   7990 let isExtentSigned = 1;
   7991 let opExtentBits = 11;
   7992 let opExtentAlign = 2;
   7993 }
   7994 def J4_cmpgtui_t_jumpnv_nt : HInst<
   7995 (outs),
   7996 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   7997 "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
   7998 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   7999 let Inst{0-0} = 0b0;
   8000 let Inst{13-13} = 0b0;
   8001 let Inst{19-19} = 0b0;
   8002 let Inst{31-22} = 0b0010010100;
   8003 let isPredicated = 1;
   8004 let isTerminator = 1;
   8005 let isBranch = 1;
   8006 let isNewValue = 1;
   8007 let cofMax1 = 1;
   8008 let isRestrictNoSlot1Store = 1;
   8009 let Defs = [PC];
   8010 let BaseOpcode = "J4_cmpgtuir";
   8011 let isTaken = Inst{13};
   8012 let isExtendable = 1;
   8013 let opExtendable = 2;
   8014 let isExtentSigned = 1;
   8015 let opExtentBits = 11;
   8016 let opExtentAlign = 2;
   8017 let opNewValue = 0;
   8018 }
   8019 def J4_cmpgtui_t_jumpnv_t : HInst<
   8020 (outs),
   8021 (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
   8022 "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
   8023 tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel {
   8024 let Inst{0-0} = 0b0;
   8025 let Inst{13-13} = 0b1;
   8026 let Inst{19-19} = 0b0;
   8027 let Inst{31-22} = 0b0010010100;
   8028 let isPredicated = 1;
   8029 let isTerminator = 1;
   8030 let isBranch = 1;
   8031 let isNewValue = 1;
   8032 let cofMax1 = 1;
   8033 let isRestrictNoSlot1Store = 1;
   8034 let Defs = [PC];
   8035 let BaseOpcode = "J4_cmpgtuir";
   8036 let isTaken = Inst{13};
   8037 let isExtendable = 1;
   8038 let opExtendable = 2;
   8039 let isExtentSigned = 1;
   8040 let opExtentBits = 11;
   8041 let opExtentAlign = 2;
   8042 let opNewValue = 0;
   8043 }
   8044 def J4_cmpgtui_tp0_jump_nt : HInst<
   8045 (outs),
   8046 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   8047 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
   8048 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   8049 let Inst{0-0} = 0b0;
   8050 let Inst{13-13} = 0b0;
   8051 let Inst{31-22} = 0b0001000100;
   8052 let isPredicated = 1;
   8053 let isTerminator = 1;
   8054 let isBranch = 1;
   8055 let isPredicatedNew = 1;
   8056 let cofRelax1 = 1;
   8057 let cofRelax2 = 1;
   8058 let cofMax1 = 1;
   8059 let Uses = [P0];
   8060 let Defs = [P0, PC];
   8061 let BaseOpcode = "J4_cmpgtuip0";
   8062 let isTaken = Inst{13};
   8063 let isExtendable = 1;
   8064 let opExtendable = 2;
   8065 let isExtentSigned = 1;
   8066 let opExtentBits = 11;
   8067 let opExtentAlign = 2;
   8068 }
   8069 def J4_cmpgtui_tp0_jump_t : HInst<
   8070 (outs),
   8071 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   8072 "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
   8073 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   8074 let Inst{0-0} = 0b0;
   8075 let Inst{13-13} = 0b1;
   8076 let Inst{31-22} = 0b0001000100;
   8077 let isPredicated = 1;
   8078 let isTerminator = 1;
   8079 let isBranch = 1;
   8080 let isPredicatedNew = 1;
   8081 let cofRelax1 = 1;
   8082 let cofRelax2 = 1;
   8083 let cofMax1 = 1;
   8084 let Uses = [P0];
   8085 let Defs = [P0, PC];
   8086 let BaseOpcode = "J4_cmpgtuip0";
   8087 let isTaken = Inst{13};
   8088 let isExtendable = 1;
   8089 let opExtendable = 2;
   8090 let isExtentSigned = 1;
   8091 let opExtentBits = 11;
   8092 let opExtentAlign = 2;
   8093 }
   8094 def J4_cmpgtui_tp1_jump_nt : HInst<
   8095 (outs),
   8096 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   8097 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
   8098 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   8099 let Inst{0-0} = 0b0;
   8100 let Inst{13-13} = 0b0;
   8101 let Inst{31-22} = 0b0001001100;
   8102 let isPredicated = 1;
   8103 let isTerminator = 1;
   8104 let isBranch = 1;
   8105 let isPredicatedNew = 1;
   8106 let cofRelax1 = 1;
   8107 let cofRelax2 = 1;
   8108 let cofMax1 = 1;
   8109 let Uses = [P1];
   8110 let Defs = [P1, PC];
   8111 let BaseOpcode = "J4_cmpgtuip1";
   8112 let isTaken = Inst{13};
   8113 let isExtendable = 1;
   8114 let opExtendable = 2;
   8115 let isExtentSigned = 1;
   8116 let opExtentBits = 11;
   8117 let opExtentAlign = 2;
   8118 }
   8119 def J4_cmpgtui_tp1_jump_t : HInst<
   8120 (outs),
   8121 (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
   8122 "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
   8123 tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel {
   8124 let Inst{0-0} = 0b0;
   8125 let Inst{13-13} = 0b1;
   8126 let Inst{31-22} = 0b0001001100;
   8127 let isPredicated = 1;
   8128 let isTerminator = 1;
   8129 let isBranch = 1;
   8130 let isPredicatedNew = 1;
   8131 let cofRelax1 = 1;
   8132 let cofRelax2 = 1;
   8133 let cofMax1 = 1;
   8134 let Uses = [P1];
   8135 let Defs = [P1, PC];
   8136 let BaseOpcode = "J4_cmpgtuip1";
   8137 let isTaken = Inst{13};
   8138 let isExtendable = 1;
   8139 let opExtendable = 2;
   8140 let isExtentSigned = 1;
   8141 let opExtentBits = 11;
   8142 let opExtentAlign = 2;
   8143 }
   8144 def J4_cmplt_f_jumpnv_nt : HInst<
   8145 (outs),
   8146 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8147 "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
   8148 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8149 let Inst{0-0} = 0b0;
   8150 let Inst{13-13} = 0b0;
   8151 let Inst{19-19} = 0b0;
   8152 let Inst{31-22} = 0b0010000111;
   8153 let isPredicated = 1;
   8154 let isPredicatedFalse = 1;
   8155 let isTerminator = 1;
   8156 let isBranch = 1;
   8157 let isNewValue = 1;
   8158 let cofMax1 = 1;
   8159 let isRestrictNoSlot1Store = 1;
   8160 let Defs = [PC];
   8161 let BaseOpcode = "J4_cmpltr";
   8162 let isTaken = Inst{13};
   8163 let isExtendable = 1;
   8164 let opExtendable = 2;
   8165 let isExtentSigned = 1;
   8166 let opExtentBits = 11;
   8167 let opExtentAlign = 2;
   8168 let opNewValue = 1;
   8169 }
   8170 def J4_cmplt_f_jumpnv_t : HInst<
   8171 (outs),
   8172 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8173 "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
   8174 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8175 let Inst{0-0} = 0b0;
   8176 let Inst{13-13} = 0b1;
   8177 let Inst{19-19} = 0b0;
   8178 let Inst{31-22} = 0b0010000111;
   8179 let isPredicated = 1;
   8180 let isPredicatedFalse = 1;
   8181 let isTerminator = 1;
   8182 let isBranch = 1;
   8183 let isNewValue = 1;
   8184 let cofMax1 = 1;
   8185 let isRestrictNoSlot1Store = 1;
   8186 let Defs = [PC];
   8187 let BaseOpcode = "J4_cmpltr";
   8188 let isTaken = Inst{13};
   8189 let isExtendable = 1;
   8190 let opExtendable = 2;
   8191 let isExtentSigned = 1;
   8192 let opExtentBits = 11;
   8193 let opExtentAlign = 2;
   8194 let opNewValue = 1;
   8195 }
   8196 def J4_cmplt_t_jumpnv_nt : HInst<
   8197 (outs),
   8198 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8199 "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
   8200 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8201 let Inst{0-0} = 0b0;
   8202 let Inst{13-13} = 0b0;
   8203 let Inst{19-19} = 0b0;
   8204 let Inst{31-22} = 0b0010000110;
   8205 let isPredicated = 1;
   8206 let isTerminator = 1;
   8207 let isBranch = 1;
   8208 let isNewValue = 1;
   8209 let cofMax1 = 1;
   8210 let isRestrictNoSlot1Store = 1;
   8211 let Defs = [PC];
   8212 let BaseOpcode = "J4_cmpltr";
   8213 let isTaken = Inst{13};
   8214 let isExtendable = 1;
   8215 let opExtendable = 2;
   8216 let isExtentSigned = 1;
   8217 let opExtentBits = 11;
   8218 let opExtentAlign = 2;
   8219 let opNewValue = 1;
   8220 }
   8221 def J4_cmplt_t_jumpnv_t : HInst<
   8222 (outs),
   8223 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8224 "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
   8225 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8226 let Inst{0-0} = 0b0;
   8227 let Inst{13-13} = 0b1;
   8228 let Inst{19-19} = 0b0;
   8229 let Inst{31-22} = 0b0010000110;
   8230 let isPredicated = 1;
   8231 let isTerminator = 1;
   8232 let isBranch = 1;
   8233 let isNewValue = 1;
   8234 let cofMax1 = 1;
   8235 let isRestrictNoSlot1Store = 1;
   8236 let Defs = [PC];
   8237 let BaseOpcode = "J4_cmpltr";
   8238 let isTaken = Inst{13};
   8239 let isExtendable = 1;
   8240 let opExtendable = 2;
   8241 let isExtentSigned = 1;
   8242 let opExtentBits = 11;
   8243 let opExtentAlign = 2;
   8244 let opNewValue = 1;
   8245 }
   8246 def J4_cmpltu_f_jumpnv_nt : HInst<
   8247 (outs),
   8248 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8249 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
   8250 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8251 let Inst{0-0} = 0b0;
   8252 let Inst{13-13} = 0b0;
   8253 let Inst{19-19} = 0b0;
   8254 let Inst{31-22} = 0b0010001001;
   8255 let isPredicated = 1;
   8256 let isPredicatedFalse = 1;
   8257 let isTerminator = 1;
   8258 let isBranch = 1;
   8259 let isNewValue = 1;
   8260 let cofMax1 = 1;
   8261 let isRestrictNoSlot1Store = 1;
   8262 let Defs = [PC];
   8263 let BaseOpcode = "J4_cmpltur";
   8264 let isTaken = Inst{13};
   8265 let isExtendable = 1;
   8266 let opExtendable = 2;
   8267 let isExtentSigned = 1;
   8268 let opExtentBits = 11;
   8269 let opExtentAlign = 2;
   8270 let opNewValue = 1;
   8271 }
   8272 def J4_cmpltu_f_jumpnv_t : HInst<
   8273 (outs),
   8274 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8275 "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
   8276 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8277 let Inst{0-0} = 0b0;
   8278 let Inst{13-13} = 0b1;
   8279 let Inst{19-19} = 0b0;
   8280 let Inst{31-22} = 0b0010001001;
   8281 let isPredicated = 1;
   8282 let isPredicatedFalse = 1;
   8283 let isTerminator = 1;
   8284 let isBranch = 1;
   8285 let isNewValue = 1;
   8286 let cofMax1 = 1;
   8287 let isRestrictNoSlot1Store = 1;
   8288 let Defs = [PC];
   8289 let BaseOpcode = "J4_cmpltur";
   8290 let isTaken = Inst{13};
   8291 let isExtendable = 1;
   8292 let opExtendable = 2;
   8293 let isExtentSigned = 1;
   8294 let opExtentBits = 11;
   8295 let opExtentAlign = 2;
   8296 let opNewValue = 1;
   8297 }
   8298 def J4_cmpltu_t_jumpnv_nt : HInst<
   8299 (outs),
   8300 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8301 "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
   8302 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8303 let Inst{0-0} = 0b0;
   8304 let Inst{13-13} = 0b0;
   8305 let Inst{19-19} = 0b0;
   8306 let Inst{31-22} = 0b0010001000;
   8307 let isPredicated = 1;
   8308 let isTerminator = 1;
   8309 let isBranch = 1;
   8310 let isNewValue = 1;
   8311 let cofMax1 = 1;
   8312 let isRestrictNoSlot1Store = 1;
   8313 let Defs = [PC];
   8314 let BaseOpcode = "J4_cmpltur";
   8315 let isTaken = Inst{13};
   8316 let isExtendable = 1;
   8317 let opExtendable = 2;
   8318 let isExtentSigned = 1;
   8319 let opExtentBits = 11;
   8320 let opExtentAlign = 2;
   8321 let opNewValue = 1;
   8322 }
   8323 def J4_cmpltu_t_jumpnv_t : HInst<
   8324 (outs),
   8325 (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
   8326 "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
   8327 tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel {
   8328 let Inst{0-0} = 0b0;
   8329 let Inst{13-13} = 0b1;
   8330 let Inst{19-19} = 0b0;
   8331 let Inst{31-22} = 0b0010001000;
   8332 let isPredicated = 1;
   8333 let isTerminator = 1;
   8334 let isBranch = 1;
   8335 let isNewValue = 1;
   8336 let cofMax1 = 1;
   8337 let isRestrictNoSlot1Store = 1;
   8338 let Defs = [PC];
   8339 let BaseOpcode = "J4_cmpltur";
   8340 let isTaken = Inst{13};
   8341 let isExtendable = 1;
   8342 let opExtendable = 2;
   8343 let isExtentSigned = 1;
   8344 let opExtentBits = 11;
   8345 let opExtentAlign = 2;
   8346 let opNewValue = 1;
   8347 }
   8348 def J4_hintjumpr : HInst<
   8349 (outs),
   8350 (ins IntRegs:$Rs32),
   8351 "hintjr($Rs32)",
   8352 tc_9faf76ae, TypeJ>, Enc_ecbcc8 {
   8353 let Inst{13-0} = 0b00000000000000;
   8354 let Inst{31-21} = 0b01010010101;
   8355 let isTerminator = 1;
   8356 let isIndirectBranch = 1;
   8357 let isBranch = 1;
   8358 let cofMax1 = 1;
   8359 }
   8360 def J4_jumpseti : HInst<
   8361 (outs GeneralSubRegs:$Rd16),
   8362 (ins u6_0Imm:$II, b30_2Imm:$Ii),
   8363 "$Rd16 = #$II ; jump $Ii",
   8364 tc_49eb22c8, TypeCJ>, Enc_9e4c3f {
   8365 let Inst{0-0} = 0b0;
   8366 let Inst{31-22} = 0b0001011000;
   8367 let hasNewValue = 1;
   8368 let opNewValue = 0;
   8369 let isTerminator = 1;
   8370 let isBranch = 1;
   8371 let cofRelax2 = 1;
   8372 let cofMax1 = 1;
   8373 let Defs = [PC];
   8374 let isExtendable = 1;
   8375 let opExtendable = 2;
   8376 let isExtentSigned = 1;
   8377 let opExtentBits = 11;
   8378 let opExtentAlign = 2;
   8379 }
   8380 def J4_jumpsetr : HInst<
   8381 (outs GeneralSubRegs:$Rd16),
   8382 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8383 "$Rd16 = $Rs16 ; jump $Ii",
   8384 tc_49eb22c8, TypeCJ>, Enc_66bce1 {
   8385 let Inst{0-0} = 0b0;
   8386 let Inst{13-12} = 0b00;
   8387 let Inst{31-22} = 0b0001011100;
   8388 let hasNewValue = 1;
   8389 let opNewValue = 0;
   8390 let isTerminator = 1;
   8391 let isBranch = 1;
   8392 let cofRelax2 = 1;
   8393 let cofMax1 = 1;
   8394 let Defs = [PC];
   8395 let isExtendable = 1;
   8396 let opExtendable = 2;
   8397 let isExtentSigned = 1;
   8398 let opExtentBits = 11;
   8399 let opExtentAlign = 2;
   8400 }
   8401 def J4_tstbit0_f_jumpnv_nt : HInst<
   8402 (outs),
   8403 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
   8404 "if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
   8405 tc_746baa8e, TypeNCJ>, Enc_69d63b {
   8406 let Inst{0-0} = 0b0;
   8407 let Inst{13-8} = 0b000000;
   8408 let Inst{19-19} = 0b0;
   8409 let Inst{31-22} = 0b0010010111;
   8410 let isPredicated = 1;
   8411 let isPredicatedFalse = 1;
   8412 let isTerminator = 1;
   8413 let isBranch = 1;
   8414 let isNewValue = 1;
   8415 let cofMax1 = 1;
   8416 let isRestrictNoSlot1Store = 1;
   8417 let Defs = [PC];
   8418 let isTaken = Inst{13};
   8419 let isExtendable = 1;
   8420 let opExtendable = 1;
   8421 let isExtentSigned = 1;
   8422 let opExtentBits = 11;
   8423 let opExtentAlign = 2;
   8424 let opNewValue = 0;
   8425 }
   8426 def J4_tstbit0_f_jumpnv_t : HInst<
   8427 (outs),
   8428 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
   8429 "if (!tstbit($Ns8.new,#0)) jump:t $Ii",
   8430 tc_746baa8e, TypeNCJ>, Enc_69d63b {
   8431 let Inst{0-0} = 0b0;
   8432 let Inst{13-8} = 0b100000;
   8433 let Inst{19-19} = 0b0;
   8434 let Inst{31-22} = 0b0010010111;
   8435 let isPredicated = 1;
   8436 let isPredicatedFalse = 1;
   8437 let isTerminator = 1;
   8438 let isBranch = 1;
   8439 let isNewValue = 1;
   8440 let cofMax1 = 1;
   8441 let isRestrictNoSlot1Store = 1;
   8442 let Defs = [PC];
   8443 let isTaken = Inst{13};
   8444 let isExtendable = 1;
   8445 let opExtendable = 1;
   8446 let isExtentSigned = 1;
   8447 let opExtentBits = 11;
   8448 let opExtentAlign = 2;
   8449 let opNewValue = 0;
   8450 }
   8451 def J4_tstbit0_fp0_jump_nt : HInst<
   8452 (outs),
   8453 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8454 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
   8455 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8456 let Inst{0-0} = 0b0;
   8457 let Inst{13-8} = 0b000011;
   8458 let Inst{31-22} = 0b0001000111;
   8459 let isPredicated = 1;
   8460 let isPredicatedFalse = 1;
   8461 let isTerminator = 1;
   8462 let isBranch = 1;
   8463 let isPredicatedNew = 1;
   8464 let cofRelax1 = 1;
   8465 let cofRelax2 = 1;
   8466 let cofMax1 = 1;
   8467 let Uses = [P0];
   8468 let Defs = [P0, PC];
   8469 let isTaken = Inst{13};
   8470 let isExtendable = 1;
   8471 let opExtendable = 1;
   8472 let isExtentSigned = 1;
   8473 let opExtentBits = 11;
   8474 let opExtentAlign = 2;
   8475 }
   8476 def J4_tstbit0_fp0_jump_t : HInst<
   8477 (outs),
   8478 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8479 "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
   8480 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8481 let Inst{0-0} = 0b0;
   8482 let Inst{13-8} = 0b100011;
   8483 let Inst{31-22} = 0b0001000111;
   8484 let isPredicated = 1;
   8485 let isPredicatedFalse = 1;
   8486 let isTerminator = 1;
   8487 let isBranch = 1;
   8488 let isPredicatedNew = 1;
   8489 let cofRelax1 = 1;
   8490 let cofRelax2 = 1;
   8491 let cofMax1 = 1;
   8492 let Uses = [P0];
   8493 let Defs = [P0, PC];
   8494 let isTaken = Inst{13};
   8495 let isExtendable = 1;
   8496 let opExtendable = 1;
   8497 let isExtentSigned = 1;
   8498 let opExtentBits = 11;
   8499 let opExtentAlign = 2;
   8500 }
   8501 def J4_tstbit0_fp1_jump_nt : HInst<
   8502 (outs),
   8503 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8504 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
   8505 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8506 let Inst{0-0} = 0b0;
   8507 let Inst{13-8} = 0b000011;
   8508 let Inst{31-22} = 0b0001001111;
   8509 let isPredicated = 1;
   8510 let isPredicatedFalse = 1;
   8511 let isTerminator = 1;
   8512 let isBranch = 1;
   8513 let isPredicatedNew = 1;
   8514 let cofRelax1 = 1;
   8515 let cofRelax2 = 1;
   8516 let cofMax1 = 1;
   8517 let Uses = [P1];
   8518 let Defs = [P1, PC];
   8519 let isTaken = Inst{13};
   8520 let isExtendable = 1;
   8521 let opExtendable = 1;
   8522 let isExtentSigned = 1;
   8523 let opExtentBits = 11;
   8524 let opExtentAlign = 2;
   8525 }
   8526 def J4_tstbit0_fp1_jump_t : HInst<
   8527 (outs),
   8528 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8529 "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
   8530 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8531 let Inst{0-0} = 0b0;
   8532 let Inst{13-8} = 0b100011;
   8533 let Inst{31-22} = 0b0001001111;
   8534 let isPredicated = 1;
   8535 let isPredicatedFalse = 1;
   8536 let isTerminator = 1;
   8537 let isBranch = 1;
   8538 let isPredicatedNew = 1;
   8539 let cofRelax1 = 1;
   8540 let cofRelax2 = 1;
   8541 let cofMax1 = 1;
   8542 let Uses = [P1];
   8543 let Defs = [P1, PC];
   8544 let isTaken = Inst{13};
   8545 let isExtendable = 1;
   8546 let opExtendable = 1;
   8547 let isExtentSigned = 1;
   8548 let opExtentBits = 11;
   8549 let opExtentAlign = 2;
   8550 }
   8551 def J4_tstbit0_t_jumpnv_nt : HInst<
   8552 (outs),
   8553 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
   8554 "if (tstbit($Ns8.new,#0)) jump:nt $Ii",
   8555 tc_746baa8e, TypeNCJ>, Enc_69d63b {
   8556 let Inst{0-0} = 0b0;
   8557 let Inst{13-8} = 0b000000;
   8558 let Inst{19-19} = 0b0;
   8559 let Inst{31-22} = 0b0010010110;
   8560 let isPredicated = 1;
   8561 let isTerminator = 1;
   8562 let isBranch = 1;
   8563 let isNewValue = 1;
   8564 let cofMax1 = 1;
   8565 let isRestrictNoSlot1Store = 1;
   8566 let Defs = [PC];
   8567 let isTaken = Inst{13};
   8568 let isExtendable = 1;
   8569 let opExtendable = 1;
   8570 let isExtentSigned = 1;
   8571 let opExtentBits = 11;
   8572 let opExtentAlign = 2;
   8573 let opNewValue = 0;
   8574 }
   8575 def J4_tstbit0_t_jumpnv_t : HInst<
   8576 (outs),
   8577 (ins IntRegs:$Ns8, b30_2Imm:$Ii),
   8578 "if (tstbit($Ns8.new,#0)) jump:t $Ii",
   8579 tc_746baa8e, TypeNCJ>, Enc_69d63b {
   8580 let Inst{0-0} = 0b0;
   8581 let Inst{13-8} = 0b100000;
   8582 let Inst{19-19} = 0b0;
   8583 let Inst{31-22} = 0b0010010110;
   8584 let isPredicated = 1;
   8585 let isTerminator = 1;
   8586 let isBranch = 1;
   8587 let isNewValue = 1;
   8588 let cofMax1 = 1;
   8589 let isRestrictNoSlot1Store = 1;
   8590 let Defs = [PC];
   8591 let isTaken = Inst{13};
   8592 let isExtendable = 1;
   8593 let opExtendable = 1;
   8594 let isExtentSigned = 1;
   8595 let opExtentBits = 11;
   8596 let opExtentAlign = 2;
   8597 let opNewValue = 0;
   8598 }
   8599 def J4_tstbit0_tp0_jump_nt : HInst<
   8600 (outs),
   8601 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8602 "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
   8603 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8604 let Inst{0-0} = 0b0;
   8605 let Inst{13-8} = 0b000011;
   8606 let Inst{31-22} = 0b0001000110;
   8607 let isPredicated = 1;
   8608 let isTerminator = 1;
   8609 let isBranch = 1;
   8610 let isPredicatedNew = 1;
   8611 let cofRelax1 = 1;
   8612 let cofRelax2 = 1;
   8613 let cofMax1 = 1;
   8614 let Uses = [P0];
   8615 let Defs = [P0, PC];
   8616 let isTaken = Inst{13};
   8617 let isExtendable = 1;
   8618 let opExtendable = 1;
   8619 let isExtentSigned = 1;
   8620 let opExtentBits = 11;
   8621 let opExtentAlign = 2;
   8622 }
   8623 def J4_tstbit0_tp0_jump_t : HInst<
   8624 (outs),
   8625 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8626 "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
   8627 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8628 let Inst{0-0} = 0b0;
   8629 let Inst{13-8} = 0b100011;
   8630 let Inst{31-22} = 0b0001000110;
   8631 let isPredicated = 1;
   8632 let isTerminator = 1;
   8633 let isBranch = 1;
   8634 let isPredicatedNew = 1;
   8635 let cofRelax1 = 1;
   8636 let cofRelax2 = 1;
   8637 let cofMax1 = 1;
   8638 let Uses = [P0];
   8639 let Defs = [P0, PC];
   8640 let isTaken = Inst{13};
   8641 let isExtendable = 1;
   8642 let opExtendable = 1;
   8643 let isExtentSigned = 1;
   8644 let opExtentBits = 11;
   8645 let opExtentAlign = 2;
   8646 }
   8647 def J4_tstbit0_tp1_jump_nt : HInst<
   8648 (outs),
   8649 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8650 "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
   8651 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8652 let Inst{0-0} = 0b0;
   8653 let Inst{13-8} = 0b000011;
   8654 let Inst{31-22} = 0b0001001110;
   8655 let isPredicated = 1;
   8656 let isTerminator = 1;
   8657 let isBranch = 1;
   8658 let isPredicatedNew = 1;
   8659 let cofRelax1 = 1;
   8660 let cofRelax2 = 1;
   8661 let cofMax1 = 1;
   8662 let Uses = [P1];
   8663 let Defs = [P1, PC];
   8664 let isTaken = Inst{13};
   8665 let isExtendable = 1;
   8666 let opExtendable = 1;
   8667 let isExtentSigned = 1;
   8668 let opExtentBits = 11;
   8669 let opExtentAlign = 2;
   8670 }
   8671 def J4_tstbit0_tp1_jump_t : HInst<
   8672 (outs),
   8673 (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
   8674 "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
   8675 tc_3cb8ea06, TypeCJ>, Enc_ad1c74 {
   8676 let Inst{0-0} = 0b0;
   8677 let Inst{13-8} = 0b100011;
   8678 let Inst{31-22} = 0b0001001110;
   8679 let isPredicated = 1;
   8680 let isTerminator = 1;
   8681 let isBranch = 1;
   8682 let isPredicatedNew = 1;
   8683 let cofRelax1 = 1;
   8684 let cofRelax2 = 1;
   8685 let cofMax1 = 1;
   8686 let Uses = [P1];
   8687 let Defs = [P1, PC];
   8688 let isTaken = Inst{13};
   8689 let isExtendable = 1;
   8690 let opExtendable = 1;
   8691 let isExtentSigned = 1;
   8692 let opExtentBits = 11;
   8693 let opExtentAlign = 2;
   8694 }
   8695 def L2_deallocframe : HInst<
   8696 (outs DoubleRegs:$Rdd32),
   8697 (ins IntRegs:$Rs32),
   8698 "$Rdd32 = deallocframe($Rs32):raw",
   8699 tc_d1090e34, TypeLD>, Enc_3a3d62 {
   8700 let Inst{13-5} = 0b000000000;
   8701 let Inst{31-21} = 0b10010000000;
   8702 let accessSize = DoubleWordAccess;
   8703 let mayLoad = 1;
   8704 let Uses = [FRAMEKEY];
   8705 let Defs = [R29];
   8706 }
   8707 def L2_loadalignb_io : HInst<
   8708 (outs DoubleRegs:$Ryy32),
   8709 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
   8710 "$Ryy32 = memb_fifo($Rs32+#$Ii)",
   8711 tc_ef52ed71, TypeLD>, Enc_a27588 {
   8712 let Inst{24-21} = 0b0100;
   8713 let Inst{31-27} = 0b10010;
   8714 let addrMode = BaseImmOffset;
   8715 let accessSize = ByteAccess;
   8716 let mayLoad = 1;
   8717 let isExtendable = 1;
   8718 let opExtendable = 3;
   8719 let isExtentSigned = 1;
   8720 let opExtentBits = 11;
   8721 let opExtentAlign = 0;
   8722 let Constraints = "$Ryy32 = $Ryy32in";
   8723 }
   8724 def L2_loadalignb_pbr : HInst<
   8725 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8726 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8727 "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
   8728 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8729 let Inst{12-5} = 0b00000000;
   8730 let Inst{31-21} = 0b10011110100;
   8731 let accessSize = ByteAccess;
   8732 let mayLoad = 1;
   8733 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8734 }
   8735 def L2_loadalignb_pci : HInst<
   8736 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8737 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
   8738 "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
   8739 tc_03220ffa, TypeLD>, Enc_74aef2 {
   8740 let Inst{12-9} = 0b0000;
   8741 let Inst{31-21} = 0b10011000100;
   8742 let addrMode = PostInc;
   8743 let accessSize = ByteAccess;
   8744 let mayLoad = 1;
   8745 let Uses = [CS];
   8746 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8747 }
   8748 def L2_loadalignb_pcr : HInst<
   8749 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8750 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8751 "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
   8752 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8753 let Inst{12-5} = 0b00010000;
   8754 let Inst{31-21} = 0b10011000100;
   8755 let addrMode = PostInc;
   8756 let accessSize = ByteAccess;
   8757 let mayLoad = 1;
   8758 let Uses = [CS];
   8759 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8760 }
   8761 def L2_loadalignb_pi : HInst<
   8762 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8763 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
   8764 "$Ryy32 = memb_fifo($Rx32++#$Ii)",
   8765 tc_bad2bcaf, TypeLD>, Enc_6b197f {
   8766 let Inst{13-9} = 0b00000;
   8767 let Inst{31-21} = 0b10011010100;
   8768 let addrMode = PostInc;
   8769 let accessSize = ByteAccess;
   8770 let mayLoad = 1;
   8771 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8772 }
   8773 def L2_loadalignb_pr : HInst<
   8774 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8775 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8776 "$Ryy32 = memb_fifo($Rx32++$Mu2)",
   8777 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8778 let Inst{12-5} = 0b00000000;
   8779 let Inst{31-21} = 0b10011100100;
   8780 let addrMode = PostInc;
   8781 let accessSize = ByteAccess;
   8782 let mayLoad = 1;
   8783 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8784 }
   8785 def L2_loadalignb_zomap : HInst<
   8786 (outs DoubleRegs:$Ryy32),
   8787 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
   8788 "$Ryy32 = memb_fifo($Rs32)",
   8789 tc_ef52ed71, TypeMAPPING> {
   8790 let isPseudo = 1;
   8791 let isCodeGenOnly = 1;
   8792 let Constraints = "$Ryy32 = $Ryy32in";
   8793 }
   8794 def L2_loadalignh_io : HInst<
   8795 (outs DoubleRegs:$Ryy32),
   8796 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
   8797 "$Ryy32 = memh_fifo($Rs32+#$Ii)",
   8798 tc_ef52ed71, TypeLD>, Enc_5cd7e9 {
   8799 let Inst{24-21} = 0b0010;
   8800 let Inst{31-27} = 0b10010;
   8801 let addrMode = BaseImmOffset;
   8802 let accessSize = HalfWordAccess;
   8803 let mayLoad = 1;
   8804 let isExtendable = 1;
   8805 let opExtendable = 3;
   8806 let isExtentSigned = 1;
   8807 let opExtentBits = 12;
   8808 let opExtentAlign = 1;
   8809 let Constraints = "$Ryy32 = $Ryy32in";
   8810 }
   8811 def L2_loadalignh_pbr : HInst<
   8812 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8813 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8814 "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
   8815 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8816 let Inst{12-5} = 0b00000000;
   8817 let Inst{31-21} = 0b10011110010;
   8818 let accessSize = HalfWordAccess;
   8819 let mayLoad = 1;
   8820 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8821 }
   8822 def L2_loadalignh_pci : HInst<
   8823 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8824 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
   8825 "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
   8826 tc_03220ffa, TypeLD>, Enc_9e2e1c {
   8827 let Inst{12-9} = 0b0000;
   8828 let Inst{31-21} = 0b10011000010;
   8829 let addrMode = PostInc;
   8830 let accessSize = HalfWordAccess;
   8831 let mayLoad = 1;
   8832 let Uses = [CS];
   8833 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8834 }
   8835 def L2_loadalignh_pcr : HInst<
   8836 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8837 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8838 "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
   8839 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8840 let Inst{12-5} = 0b00010000;
   8841 let Inst{31-21} = 0b10011000010;
   8842 let addrMode = PostInc;
   8843 let accessSize = HalfWordAccess;
   8844 let mayLoad = 1;
   8845 let Uses = [CS];
   8846 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8847 }
   8848 def L2_loadalignh_pi : HInst<
   8849 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8850 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
   8851 "$Ryy32 = memh_fifo($Rx32++#$Ii)",
   8852 tc_bad2bcaf, TypeLD>, Enc_bd1cbc {
   8853 let Inst{13-9} = 0b00000;
   8854 let Inst{31-21} = 0b10011010010;
   8855 let addrMode = PostInc;
   8856 let accessSize = HalfWordAccess;
   8857 let mayLoad = 1;
   8858 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8859 }
   8860 def L2_loadalignh_pr : HInst<
   8861 (outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
   8862 (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
   8863 "$Ryy32 = memh_fifo($Rx32++$Mu2)",
   8864 tc_bad2bcaf, TypeLD>, Enc_1f5d8f {
   8865 let Inst{12-5} = 0b00000000;
   8866 let Inst{31-21} = 0b10011100010;
   8867 let addrMode = PostInc;
   8868 let accessSize = HalfWordAccess;
   8869 let mayLoad = 1;
   8870 let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
   8871 }
   8872 def L2_loadalignh_zomap : HInst<
   8873 (outs DoubleRegs:$Ryy32),
   8874 (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
   8875 "$Ryy32 = memh_fifo($Rs32)",
   8876 tc_ef52ed71, TypeMAPPING> {
   8877 let isPseudo = 1;
   8878 let isCodeGenOnly = 1;
   8879 let Constraints = "$Ryy32 = $Ryy32in";
   8880 }
   8881 def L2_loadbsw2_io : HInst<
   8882 (outs IntRegs:$Rd32),
   8883 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
   8884 "$Rd32 = membh($Rs32+#$Ii)",
   8885 tc_7f881c76, TypeLD>, Enc_de0214 {
   8886 let Inst{24-21} = 0b0001;
   8887 let Inst{31-27} = 0b10010;
   8888 let hasNewValue = 1;
   8889 let opNewValue = 0;
   8890 let addrMode = BaseImmOffset;
   8891 let accessSize = HalfWordAccess;
   8892 let mayLoad = 1;
   8893 let isExtendable = 1;
   8894 let opExtendable = 2;
   8895 let isExtentSigned = 1;
   8896 let opExtentBits = 12;
   8897 let opExtentAlign = 1;
   8898 }
   8899 def L2_loadbsw2_pbr : HInst<
   8900 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   8901 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   8902 "$Rd32 = membh($Rx32++$Mu2:brev)",
   8903 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   8904 let Inst{12-5} = 0b00000000;
   8905 let Inst{31-21} = 0b10011110001;
   8906 let hasNewValue = 1;
   8907 let opNewValue = 0;
   8908 let accessSize = HalfWordAccess;
   8909 let mayLoad = 1;
   8910 let Constraints = "$Rx32 = $Rx32in";
   8911 }
   8912 def L2_loadbsw2_pci : HInst<
   8913 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   8914 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
   8915 "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
   8916 tc_4403ca65, TypeLD>, Enc_e83554 {
   8917 let Inst{12-9} = 0b0000;
   8918 let Inst{31-21} = 0b10011000001;
   8919 let hasNewValue = 1;
   8920 let opNewValue = 0;
   8921 let addrMode = PostInc;
   8922 let accessSize = HalfWordAccess;
   8923 let mayLoad = 1;
   8924 let Uses = [CS];
   8925 let Constraints = "$Rx32 = $Rx32in";
   8926 }
   8927 def L2_loadbsw2_pcr : HInst<
   8928 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   8929 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   8930 "$Rd32 = membh($Rx32++I:circ($Mu2))",
   8931 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   8932 let Inst{12-5} = 0b00010000;
   8933 let Inst{31-21} = 0b10011000001;
   8934 let hasNewValue = 1;
   8935 let opNewValue = 0;
   8936 let addrMode = PostInc;
   8937 let accessSize = HalfWordAccess;
   8938 let mayLoad = 1;
   8939 let Uses = [CS];
   8940 let Constraints = "$Rx32 = $Rx32in";
   8941 }
   8942 def L2_loadbsw2_pi : HInst<
   8943 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   8944 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
   8945 "$Rd32 = membh($Rx32++#$Ii)",
   8946 tc_2fc0c436, TypeLD>, Enc_152467 {
   8947 let Inst{13-9} = 0b00000;
   8948 let Inst{31-21} = 0b10011010001;
   8949 let hasNewValue = 1;
   8950 let opNewValue = 0;
   8951 let addrMode = PostInc;
   8952 let accessSize = HalfWordAccess;
   8953 let mayLoad = 1;
   8954 let Constraints = "$Rx32 = $Rx32in";
   8955 }
   8956 def L2_loadbsw2_pr : HInst<
   8957 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   8958 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   8959 "$Rd32 = membh($Rx32++$Mu2)",
   8960 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   8961 let Inst{12-5} = 0b00000000;
   8962 let Inst{31-21} = 0b10011100001;
   8963 let hasNewValue = 1;
   8964 let opNewValue = 0;
   8965 let addrMode = PostInc;
   8966 let accessSize = HalfWordAccess;
   8967 let mayLoad = 1;
   8968 let Constraints = "$Rx32 = $Rx32in";
   8969 }
   8970 def L2_loadbsw2_zomap : HInst<
   8971 (outs IntRegs:$Rd32),
   8972 (ins IntRegs:$Rs32),
   8973 "$Rd32 = membh($Rs32)",
   8974 tc_7f881c76, TypeMAPPING> {
   8975 let hasNewValue = 1;
   8976 let opNewValue = 0;
   8977 let isPseudo = 1;
   8978 let isCodeGenOnly = 1;
   8979 }
   8980 def L2_loadbsw4_io : HInst<
   8981 (outs DoubleRegs:$Rdd32),
   8982 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
   8983 "$Rdd32 = membh($Rs32+#$Ii)",
   8984 tc_7f881c76, TypeLD>, Enc_2d7491 {
   8985 let Inst{24-21} = 0b0111;
   8986 let Inst{31-27} = 0b10010;
   8987 let addrMode = BaseImmOffset;
   8988 let accessSize = WordAccess;
   8989 let mayLoad = 1;
   8990 let isExtendable = 1;
   8991 let opExtendable = 2;
   8992 let isExtentSigned = 1;
   8993 let opExtentBits = 13;
   8994 let opExtentAlign = 2;
   8995 }
   8996 def L2_loadbsw4_pbr : HInst<
   8997 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   8998 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   8999 "$Rdd32 = membh($Rx32++$Mu2:brev)",
   9000 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9001 let Inst{12-5} = 0b00000000;
   9002 let Inst{31-21} = 0b10011110111;
   9003 let accessSize = WordAccess;
   9004 let mayLoad = 1;
   9005 let Constraints = "$Rx32 = $Rx32in";
   9006 }
   9007 def L2_loadbsw4_pci : HInst<
   9008 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9009 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
   9010 "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
   9011 tc_4403ca65, TypeLD>, Enc_70b24b {
   9012 let Inst{12-9} = 0b0000;
   9013 let Inst{31-21} = 0b10011000111;
   9014 let addrMode = PostInc;
   9015 let accessSize = WordAccess;
   9016 let mayLoad = 1;
   9017 let Uses = [CS];
   9018 let Constraints = "$Rx32 = $Rx32in";
   9019 }
   9020 def L2_loadbsw4_pcr : HInst<
   9021 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9022 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9023 "$Rdd32 = membh($Rx32++I:circ($Mu2))",
   9024 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9025 let Inst{12-5} = 0b00010000;
   9026 let Inst{31-21} = 0b10011000111;
   9027 let addrMode = PostInc;
   9028 let accessSize = WordAccess;
   9029 let mayLoad = 1;
   9030 let Uses = [CS];
   9031 let Constraints = "$Rx32 = $Rx32in";
   9032 }
   9033 def L2_loadbsw4_pi : HInst<
   9034 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9035 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
   9036 "$Rdd32 = membh($Rx32++#$Ii)",
   9037 tc_2fc0c436, TypeLD>, Enc_71f1b4 {
   9038 let Inst{13-9} = 0b00000;
   9039 let Inst{31-21} = 0b10011010111;
   9040 let addrMode = PostInc;
   9041 let accessSize = WordAccess;
   9042 let mayLoad = 1;
   9043 let Constraints = "$Rx32 = $Rx32in";
   9044 }
   9045 def L2_loadbsw4_pr : HInst<
   9046 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9047 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9048 "$Rdd32 = membh($Rx32++$Mu2)",
   9049 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9050 let Inst{12-5} = 0b00000000;
   9051 let Inst{31-21} = 0b10011100111;
   9052 let addrMode = PostInc;
   9053 let accessSize = WordAccess;
   9054 let mayLoad = 1;
   9055 let Constraints = "$Rx32 = $Rx32in";
   9056 }
   9057 def L2_loadbsw4_zomap : HInst<
   9058 (outs DoubleRegs:$Rdd32),
   9059 (ins IntRegs:$Rs32),
   9060 "$Rdd32 = membh($Rs32)",
   9061 tc_7f881c76, TypeMAPPING> {
   9062 let isPseudo = 1;
   9063 let isCodeGenOnly = 1;
   9064 }
   9065 def L2_loadbzw2_io : HInst<
   9066 (outs IntRegs:$Rd32),
   9067 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
   9068 "$Rd32 = memubh($Rs32+#$Ii)",
   9069 tc_7f881c76, TypeLD>, Enc_de0214 {
   9070 let Inst{24-21} = 0b0011;
   9071 let Inst{31-27} = 0b10010;
   9072 let hasNewValue = 1;
   9073 let opNewValue = 0;
   9074 let addrMode = BaseImmOffset;
   9075 let accessSize = HalfWordAccess;
   9076 let mayLoad = 1;
   9077 let isExtendable = 1;
   9078 let opExtendable = 2;
   9079 let isExtentSigned = 1;
   9080 let opExtentBits = 12;
   9081 let opExtentAlign = 1;
   9082 }
   9083 def L2_loadbzw2_pbr : HInst<
   9084 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9085 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9086 "$Rd32 = memubh($Rx32++$Mu2:brev)",
   9087 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9088 let Inst{12-5} = 0b00000000;
   9089 let Inst{31-21} = 0b10011110011;
   9090 let hasNewValue = 1;
   9091 let opNewValue = 0;
   9092 let accessSize = HalfWordAccess;
   9093 let mayLoad = 1;
   9094 let Constraints = "$Rx32 = $Rx32in";
   9095 }
   9096 def L2_loadbzw2_pci : HInst<
   9097 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9098 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
   9099 "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
   9100 tc_4403ca65, TypeLD>, Enc_e83554 {
   9101 let Inst{12-9} = 0b0000;
   9102 let Inst{31-21} = 0b10011000011;
   9103 let hasNewValue = 1;
   9104 let opNewValue = 0;
   9105 let addrMode = PostInc;
   9106 let accessSize = HalfWordAccess;
   9107 let mayLoad = 1;
   9108 let Uses = [CS];
   9109 let Constraints = "$Rx32 = $Rx32in";
   9110 }
   9111 def L2_loadbzw2_pcr : HInst<
   9112 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9113 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9114 "$Rd32 = memubh($Rx32++I:circ($Mu2))",
   9115 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9116 let Inst{12-5} = 0b00010000;
   9117 let Inst{31-21} = 0b10011000011;
   9118 let hasNewValue = 1;
   9119 let opNewValue = 0;
   9120 let addrMode = PostInc;
   9121 let accessSize = HalfWordAccess;
   9122 let mayLoad = 1;
   9123 let Uses = [CS];
   9124 let Constraints = "$Rx32 = $Rx32in";
   9125 }
   9126 def L2_loadbzw2_pi : HInst<
   9127 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9128 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
   9129 "$Rd32 = memubh($Rx32++#$Ii)",
   9130 tc_2fc0c436, TypeLD>, Enc_152467 {
   9131 let Inst{13-9} = 0b00000;
   9132 let Inst{31-21} = 0b10011010011;
   9133 let hasNewValue = 1;
   9134 let opNewValue = 0;
   9135 let addrMode = PostInc;
   9136 let accessSize = HalfWordAccess;
   9137 let mayLoad = 1;
   9138 let Constraints = "$Rx32 = $Rx32in";
   9139 }
   9140 def L2_loadbzw2_pr : HInst<
   9141 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9142 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9143 "$Rd32 = memubh($Rx32++$Mu2)",
   9144 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9145 let Inst{12-5} = 0b00000000;
   9146 let Inst{31-21} = 0b10011100011;
   9147 let hasNewValue = 1;
   9148 let opNewValue = 0;
   9149 let addrMode = PostInc;
   9150 let accessSize = HalfWordAccess;
   9151 let mayLoad = 1;
   9152 let Constraints = "$Rx32 = $Rx32in";
   9153 }
   9154 def L2_loadbzw2_zomap : HInst<
   9155 (outs IntRegs:$Rd32),
   9156 (ins IntRegs:$Rs32),
   9157 "$Rd32 = memubh($Rs32)",
   9158 tc_7f881c76, TypeMAPPING> {
   9159 let hasNewValue = 1;
   9160 let opNewValue = 0;
   9161 let isPseudo = 1;
   9162 let isCodeGenOnly = 1;
   9163 }
   9164 def L2_loadbzw4_io : HInst<
   9165 (outs DoubleRegs:$Rdd32),
   9166 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
   9167 "$Rdd32 = memubh($Rs32+#$Ii)",
   9168 tc_7f881c76, TypeLD>, Enc_2d7491 {
   9169 let Inst{24-21} = 0b0101;
   9170 let Inst{31-27} = 0b10010;
   9171 let addrMode = BaseImmOffset;
   9172 let accessSize = WordAccess;
   9173 let mayLoad = 1;
   9174 let isExtendable = 1;
   9175 let opExtendable = 2;
   9176 let isExtentSigned = 1;
   9177 let opExtentBits = 13;
   9178 let opExtentAlign = 2;
   9179 }
   9180 def L2_loadbzw4_pbr : HInst<
   9181 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9182 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9183 "$Rdd32 = memubh($Rx32++$Mu2:brev)",
   9184 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9185 let Inst{12-5} = 0b00000000;
   9186 let Inst{31-21} = 0b10011110101;
   9187 let accessSize = WordAccess;
   9188 let mayLoad = 1;
   9189 let Constraints = "$Rx32 = $Rx32in";
   9190 }
   9191 def L2_loadbzw4_pci : HInst<
   9192 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9193 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
   9194 "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
   9195 tc_4403ca65, TypeLD>, Enc_70b24b {
   9196 let Inst{12-9} = 0b0000;
   9197 let Inst{31-21} = 0b10011000101;
   9198 let addrMode = PostInc;
   9199 let accessSize = WordAccess;
   9200 let mayLoad = 1;
   9201 let Uses = [CS];
   9202 let Constraints = "$Rx32 = $Rx32in";
   9203 }
   9204 def L2_loadbzw4_pcr : HInst<
   9205 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9206 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9207 "$Rdd32 = memubh($Rx32++I:circ($Mu2))",
   9208 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9209 let Inst{12-5} = 0b00010000;
   9210 let Inst{31-21} = 0b10011000101;
   9211 let addrMode = PostInc;
   9212 let accessSize = WordAccess;
   9213 let mayLoad = 1;
   9214 let Uses = [CS];
   9215 let Constraints = "$Rx32 = $Rx32in";
   9216 }
   9217 def L2_loadbzw4_pi : HInst<
   9218 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9219 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
   9220 "$Rdd32 = memubh($Rx32++#$Ii)",
   9221 tc_2fc0c436, TypeLD>, Enc_71f1b4 {
   9222 let Inst{13-9} = 0b00000;
   9223 let Inst{31-21} = 0b10011010101;
   9224 let addrMode = PostInc;
   9225 let accessSize = WordAccess;
   9226 let mayLoad = 1;
   9227 let Constraints = "$Rx32 = $Rx32in";
   9228 }
   9229 def L2_loadbzw4_pr : HInst<
   9230 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9231 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9232 "$Rdd32 = memubh($Rx32++$Mu2)",
   9233 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9234 let Inst{12-5} = 0b00000000;
   9235 let Inst{31-21} = 0b10011100101;
   9236 let addrMode = PostInc;
   9237 let accessSize = WordAccess;
   9238 let mayLoad = 1;
   9239 let Constraints = "$Rx32 = $Rx32in";
   9240 }
   9241 def L2_loadbzw4_zomap : HInst<
   9242 (outs DoubleRegs:$Rdd32),
   9243 (ins IntRegs:$Rs32),
   9244 "$Rdd32 = memubh($Rs32)",
   9245 tc_7f881c76, TypeMAPPING> {
   9246 let isPseudo = 1;
   9247 let isCodeGenOnly = 1;
   9248 }
   9249 def L2_loadrb_io : HInst<
   9250 (outs IntRegs:$Rd32),
   9251 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   9252 "$Rd32 = memb($Rs32+#$Ii)",
   9253 tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
   9254 let Inst{24-21} = 0b1000;
   9255 let Inst{31-27} = 0b10010;
   9256 let hasNewValue = 1;
   9257 let opNewValue = 0;
   9258 let addrMode = BaseImmOffset;
   9259 let accessSize = ByteAccess;
   9260 let mayLoad = 1;
   9261 let CextOpcode = "L2_loadrb";
   9262 let BaseOpcode = "L2_loadrb_io";
   9263 let isPredicable = 1;
   9264 let isExtendable = 1;
   9265 let opExtendable = 2;
   9266 let isExtentSigned = 1;
   9267 let opExtentBits = 11;
   9268 let opExtentAlign = 0;
   9269 }
   9270 def L2_loadrb_pbr : HInst<
   9271 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9272 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9273 "$Rd32 = memb($Rx32++$Mu2:brev)",
   9274 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9275 let Inst{12-5} = 0b00000000;
   9276 let Inst{31-21} = 0b10011111000;
   9277 let hasNewValue = 1;
   9278 let opNewValue = 0;
   9279 let accessSize = ByteAccess;
   9280 let mayLoad = 1;
   9281 let Constraints = "$Rx32 = $Rx32in";
   9282 }
   9283 def L2_loadrb_pci : HInst<
   9284 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9285 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
   9286 "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
   9287 tc_4403ca65, TypeLD>, Enc_e0a47a {
   9288 let Inst{12-9} = 0b0000;
   9289 let Inst{31-21} = 0b10011001000;
   9290 let hasNewValue = 1;
   9291 let opNewValue = 0;
   9292 let addrMode = PostInc;
   9293 let accessSize = ByteAccess;
   9294 let mayLoad = 1;
   9295 let Uses = [CS];
   9296 let Constraints = "$Rx32 = $Rx32in";
   9297 }
   9298 def L2_loadrb_pcr : HInst<
   9299 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9300 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9301 "$Rd32 = memb($Rx32++I:circ($Mu2))",
   9302 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9303 let Inst{12-5} = 0b00010000;
   9304 let Inst{31-21} = 0b10011001000;
   9305 let hasNewValue = 1;
   9306 let opNewValue = 0;
   9307 let addrMode = PostInc;
   9308 let accessSize = ByteAccess;
   9309 let mayLoad = 1;
   9310 let Uses = [CS];
   9311 let Constraints = "$Rx32 = $Rx32in";
   9312 }
   9313 def L2_loadrb_pi : HInst<
   9314 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9315 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
   9316 "$Rd32 = memb($Rx32++#$Ii)",
   9317 tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
   9318 let Inst{13-9} = 0b00000;
   9319 let Inst{31-21} = 0b10011011000;
   9320 let hasNewValue = 1;
   9321 let opNewValue = 0;
   9322 let addrMode = PostInc;
   9323 let accessSize = ByteAccess;
   9324 let mayLoad = 1;
   9325 let CextOpcode = "L2_loadrb";
   9326 let BaseOpcode = "L2_loadrb_pi";
   9327 let isPredicable = 1;
   9328 let Constraints = "$Rx32 = $Rx32in";
   9329 }
   9330 def L2_loadrb_pr : HInst<
   9331 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9332 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9333 "$Rd32 = memb($Rx32++$Mu2)",
   9334 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9335 let Inst{12-5} = 0b00000000;
   9336 let Inst{31-21} = 0b10011101000;
   9337 let hasNewValue = 1;
   9338 let opNewValue = 0;
   9339 let addrMode = PostInc;
   9340 let accessSize = ByteAccess;
   9341 let mayLoad = 1;
   9342 let Constraints = "$Rx32 = $Rx32in";
   9343 }
   9344 def L2_loadrb_zomap : HInst<
   9345 (outs IntRegs:$Rd32),
   9346 (ins IntRegs:$Rs32),
   9347 "$Rd32 = memb($Rs32)",
   9348 tc_7f881c76, TypeMAPPING> {
   9349 let hasNewValue = 1;
   9350 let opNewValue = 0;
   9351 let isPseudo = 1;
   9352 let isCodeGenOnly = 1;
   9353 }
   9354 def L2_loadrbgp : HInst<
   9355 (outs IntRegs:$Rd32),
   9356 (ins u32_0Imm:$Ii),
   9357 "$Rd32 = memb(gp+#$Ii)",
   9358 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
   9359 let Inst{24-21} = 0b1000;
   9360 let Inst{31-27} = 0b01001;
   9361 let hasNewValue = 1;
   9362 let opNewValue = 0;
   9363 let accessSize = ByteAccess;
   9364 let mayLoad = 1;
   9365 let Uses = [GP];
   9366 let BaseOpcode = "L4_loadrb_abs";
   9367 let isPredicable = 1;
   9368 let opExtendable = 1;
   9369 let isExtentSigned = 0;
   9370 let opExtentBits = 16;
   9371 let opExtentAlign = 0;
   9372 }
   9373 def L2_loadrd_io : HInst<
   9374 (outs DoubleRegs:$Rdd32),
   9375 (ins IntRegs:$Rs32, s29_3Imm:$Ii),
   9376 "$Rdd32 = memd($Rs32+#$Ii)",
   9377 tc_7f881c76, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
   9378 let Inst{24-21} = 0b1110;
   9379 let Inst{31-27} = 0b10010;
   9380 let addrMode = BaseImmOffset;
   9381 let accessSize = DoubleWordAccess;
   9382 let mayLoad = 1;
   9383 let CextOpcode = "L2_loadrd";
   9384 let BaseOpcode = "L2_loadrd_io";
   9385 let isPredicable = 1;
   9386 let isExtendable = 1;
   9387 let opExtendable = 2;
   9388 let isExtentSigned = 1;
   9389 let opExtentBits = 14;
   9390 let opExtentAlign = 3;
   9391 }
   9392 def L2_loadrd_pbr : HInst<
   9393 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9394 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9395 "$Rdd32 = memd($Rx32++$Mu2:brev)",
   9396 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9397 let Inst{12-5} = 0b00000000;
   9398 let Inst{31-21} = 0b10011111110;
   9399 let accessSize = DoubleWordAccess;
   9400 let mayLoad = 1;
   9401 let Constraints = "$Rx32 = $Rx32in";
   9402 }
   9403 def L2_loadrd_pci : HInst<
   9404 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9405 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
   9406 "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
   9407 tc_4403ca65, TypeLD>, Enc_b05839 {
   9408 let Inst{12-9} = 0b0000;
   9409 let Inst{31-21} = 0b10011001110;
   9410 let addrMode = PostInc;
   9411 let accessSize = DoubleWordAccess;
   9412 let mayLoad = 1;
   9413 let Uses = [CS];
   9414 let Constraints = "$Rx32 = $Rx32in";
   9415 }
   9416 def L2_loadrd_pcr : HInst<
   9417 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9418 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9419 "$Rdd32 = memd($Rx32++I:circ($Mu2))",
   9420 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9421 let Inst{12-5} = 0b00010000;
   9422 let Inst{31-21} = 0b10011001110;
   9423 let addrMode = PostInc;
   9424 let accessSize = DoubleWordAccess;
   9425 let mayLoad = 1;
   9426 let Uses = [CS];
   9427 let Constraints = "$Rx32 = $Rx32in";
   9428 }
   9429 def L2_loadrd_pi : HInst<
   9430 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9431 (ins IntRegs:$Rx32in, s4_3Imm:$Ii),
   9432 "$Rdd32 = memd($Rx32++#$Ii)",
   9433 tc_2fc0c436, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
   9434 let Inst{13-9} = 0b00000;
   9435 let Inst{31-21} = 0b10011011110;
   9436 let addrMode = PostInc;
   9437 let accessSize = DoubleWordAccess;
   9438 let mayLoad = 1;
   9439 let CextOpcode = "L2_loadrd";
   9440 let BaseOpcode = "L2_loadrd_pi";
   9441 let isPredicable = 1;
   9442 let Constraints = "$Rx32 = $Rx32in";
   9443 }
   9444 def L2_loadrd_pr : HInst<
   9445 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   9446 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9447 "$Rdd32 = memd($Rx32++$Mu2)",
   9448 tc_2fc0c436, TypeLD>, Enc_7eee72 {
   9449 let Inst{12-5} = 0b00000000;
   9450 let Inst{31-21} = 0b10011101110;
   9451 let addrMode = PostInc;
   9452 let accessSize = DoubleWordAccess;
   9453 let mayLoad = 1;
   9454 let Constraints = "$Rx32 = $Rx32in";
   9455 }
   9456 def L2_loadrd_zomap : HInst<
   9457 (outs DoubleRegs:$Rdd32),
   9458 (ins IntRegs:$Rs32),
   9459 "$Rdd32 = memd($Rs32)",
   9460 tc_7f881c76, TypeMAPPING> {
   9461 let isPseudo = 1;
   9462 let isCodeGenOnly = 1;
   9463 }
   9464 def L2_loadrdgp : HInst<
   9465 (outs DoubleRegs:$Rdd32),
   9466 (ins u29_3Imm:$Ii),
   9467 "$Rdd32 = memd(gp+#$Ii)",
   9468 tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
   9469 let Inst{24-21} = 0b1110;
   9470 let Inst{31-27} = 0b01001;
   9471 let accessSize = DoubleWordAccess;
   9472 let mayLoad = 1;
   9473 let Uses = [GP];
   9474 let BaseOpcode = "L4_loadrd_abs";
   9475 let isPredicable = 1;
   9476 let opExtendable = 1;
   9477 let isExtentSigned = 0;
   9478 let opExtentBits = 19;
   9479 let opExtentAlign = 3;
   9480 }
   9481 def L2_loadrh_io : HInst<
   9482 (outs IntRegs:$Rd32),
   9483 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
   9484 "$Rd32 = memh($Rs32+#$Ii)",
   9485 tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
   9486 let Inst{24-21} = 0b1010;
   9487 let Inst{31-27} = 0b10010;
   9488 let hasNewValue = 1;
   9489 let opNewValue = 0;
   9490 let addrMode = BaseImmOffset;
   9491 let accessSize = HalfWordAccess;
   9492 let mayLoad = 1;
   9493 let CextOpcode = "L2_loadrh";
   9494 let BaseOpcode = "L2_loadrh_io";
   9495 let isPredicable = 1;
   9496 let isExtendable = 1;
   9497 let opExtendable = 2;
   9498 let isExtentSigned = 1;
   9499 let opExtentBits = 12;
   9500 let opExtentAlign = 1;
   9501 }
   9502 def L2_loadrh_pbr : HInst<
   9503 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9504 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9505 "$Rd32 = memh($Rx32++$Mu2:brev)",
   9506 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9507 let Inst{12-5} = 0b00000000;
   9508 let Inst{31-21} = 0b10011111010;
   9509 let hasNewValue = 1;
   9510 let opNewValue = 0;
   9511 let accessSize = HalfWordAccess;
   9512 let mayLoad = 1;
   9513 let Constraints = "$Rx32 = $Rx32in";
   9514 }
   9515 def L2_loadrh_pci : HInst<
   9516 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9517 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
   9518 "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
   9519 tc_4403ca65, TypeLD>, Enc_e83554 {
   9520 let Inst{12-9} = 0b0000;
   9521 let Inst{31-21} = 0b10011001010;
   9522 let hasNewValue = 1;
   9523 let opNewValue = 0;
   9524 let addrMode = PostInc;
   9525 let accessSize = HalfWordAccess;
   9526 let mayLoad = 1;
   9527 let Uses = [CS];
   9528 let Constraints = "$Rx32 = $Rx32in";
   9529 }
   9530 def L2_loadrh_pcr : HInst<
   9531 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9532 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9533 "$Rd32 = memh($Rx32++I:circ($Mu2))",
   9534 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9535 let Inst{12-5} = 0b00010000;
   9536 let Inst{31-21} = 0b10011001010;
   9537 let hasNewValue = 1;
   9538 let opNewValue = 0;
   9539 let addrMode = PostInc;
   9540 let accessSize = HalfWordAccess;
   9541 let mayLoad = 1;
   9542 let Uses = [CS];
   9543 let Constraints = "$Rx32 = $Rx32in";
   9544 }
   9545 def L2_loadrh_pi : HInst<
   9546 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9547 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
   9548 "$Rd32 = memh($Rx32++#$Ii)",
   9549 tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
   9550 let Inst{13-9} = 0b00000;
   9551 let Inst{31-21} = 0b10011011010;
   9552 let hasNewValue = 1;
   9553 let opNewValue = 0;
   9554 let addrMode = PostInc;
   9555 let accessSize = HalfWordAccess;
   9556 let mayLoad = 1;
   9557 let CextOpcode = "L2_loadrh";
   9558 let BaseOpcode = "L2_loadrh_pi";
   9559 let isPredicable = 1;
   9560 let Constraints = "$Rx32 = $Rx32in";
   9561 }
   9562 def L2_loadrh_pr : HInst<
   9563 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9564 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9565 "$Rd32 = memh($Rx32++$Mu2)",
   9566 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9567 let Inst{12-5} = 0b00000000;
   9568 let Inst{31-21} = 0b10011101010;
   9569 let hasNewValue = 1;
   9570 let opNewValue = 0;
   9571 let addrMode = PostInc;
   9572 let accessSize = HalfWordAccess;
   9573 let mayLoad = 1;
   9574 let Constraints = "$Rx32 = $Rx32in";
   9575 }
   9576 def L2_loadrh_zomap : HInst<
   9577 (outs IntRegs:$Rd32),
   9578 (ins IntRegs:$Rs32),
   9579 "$Rd32 = memh($Rs32)",
   9580 tc_7f881c76, TypeMAPPING> {
   9581 let hasNewValue = 1;
   9582 let opNewValue = 0;
   9583 let isPseudo = 1;
   9584 let isCodeGenOnly = 1;
   9585 }
   9586 def L2_loadrhgp : HInst<
   9587 (outs IntRegs:$Rd32),
   9588 (ins u31_1Imm:$Ii),
   9589 "$Rd32 = memh(gp+#$Ii)",
   9590 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
   9591 let Inst{24-21} = 0b1010;
   9592 let Inst{31-27} = 0b01001;
   9593 let hasNewValue = 1;
   9594 let opNewValue = 0;
   9595 let accessSize = HalfWordAccess;
   9596 let mayLoad = 1;
   9597 let Uses = [GP];
   9598 let BaseOpcode = "L4_loadrh_abs";
   9599 let isPredicable = 1;
   9600 let opExtendable = 1;
   9601 let isExtentSigned = 0;
   9602 let opExtentBits = 17;
   9603 let opExtentAlign = 1;
   9604 }
   9605 def L2_loadri_io : HInst<
   9606 (outs IntRegs:$Rd32),
   9607 (ins IntRegs:$Rs32, s30_2Imm:$Ii),
   9608 "$Rd32 = memw($Rs32+#$Ii)",
   9609 tc_7f881c76, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
   9610 let Inst{24-21} = 0b1100;
   9611 let Inst{31-27} = 0b10010;
   9612 let hasNewValue = 1;
   9613 let opNewValue = 0;
   9614 let addrMode = BaseImmOffset;
   9615 let accessSize = WordAccess;
   9616 let mayLoad = 1;
   9617 let CextOpcode = "L2_loadri";
   9618 let BaseOpcode = "L2_loadri_io";
   9619 let isPredicable = 1;
   9620 let isExtendable = 1;
   9621 let opExtendable = 2;
   9622 let isExtentSigned = 1;
   9623 let opExtentBits = 13;
   9624 let opExtentAlign = 2;
   9625 }
   9626 def L2_loadri_pbr : HInst<
   9627 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9628 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9629 "$Rd32 = memw($Rx32++$Mu2:brev)",
   9630 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9631 let Inst{12-5} = 0b00000000;
   9632 let Inst{31-21} = 0b10011111100;
   9633 let hasNewValue = 1;
   9634 let opNewValue = 0;
   9635 let accessSize = WordAccess;
   9636 let mayLoad = 1;
   9637 let Constraints = "$Rx32 = $Rx32in";
   9638 }
   9639 def L2_loadri_pci : HInst<
   9640 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9641 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
   9642 "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
   9643 tc_4403ca65, TypeLD>, Enc_27fd0e {
   9644 let Inst{12-9} = 0b0000;
   9645 let Inst{31-21} = 0b10011001100;
   9646 let hasNewValue = 1;
   9647 let opNewValue = 0;
   9648 let addrMode = PostInc;
   9649 let accessSize = WordAccess;
   9650 let mayLoad = 1;
   9651 let Uses = [CS];
   9652 let Constraints = "$Rx32 = $Rx32in";
   9653 }
   9654 def L2_loadri_pcr : HInst<
   9655 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9656 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9657 "$Rd32 = memw($Rx32++I:circ($Mu2))",
   9658 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9659 let Inst{12-5} = 0b00010000;
   9660 let Inst{31-21} = 0b10011001100;
   9661 let hasNewValue = 1;
   9662 let opNewValue = 0;
   9663 let addrMode = PostInc;
   9664 let accessSize = WordAccess;
   9665 let mayLoad = 1;
   9666 let Uses = [CS];
   9667 let Constraints = "$Rx32 = $Rx32in";
   9668 }
   9669 def L2_loadri_pi : HInst<
   9670 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9671 (ins IntRegs:$Rx32in, s4_2Imm:$Ii),
   9672 "$Rd32 = memw($Rx32++#$Ii)",
   9673 tc_2fc0c436, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
   9674 let Inst{13-9} = 0b00000;
   9675 let Inst{31-21} = 0b10011011100;
   9676 let hasNewValue = 1;
   9677 let opNewValue = 0;
   9678 let addrMode = PostInc;
   9679 let accessSize = WordAccess;
   9680 let mayLoad = 1;
   9681 let CextOpcode = "L2_loadri";
   9682 let BaseOpcode = "L2_loadri_pi";
   9683 let isPredicable = 1;
   9684 let Constraints = "$Rx32 = $Rx32in";
   9685 }
   9686 def L2_loadri_pr : HInst<
   9687 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9688 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9689 "$Rd32 = memw($Rx32++$Mu2)",
   9690 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9691 let Inst{12-5} = 0b00000000;
   9692 let Inst{31-21} = 0b10011101100;
   9693 let hasNewValue = 1;
   9694 let opNewValue = 0;
   9695 let addrMode = PostInc;
   9696 let accessSize = WordAccess;
   9697 let mayLoad = 1;
   9698 let Constraints = "$Rx32 = $Rx32in";
   9699 }
   9700 def L2_loadri_zomap : HInst<
   9701 (outs IntRegs:$Rd32),
   9702 (ins IntRegs:$Rs32),
   9703 "$Rd32 = memw($Rs32)",
   9704 tc_7f881c76, TypeMAPPING> {
   9705 let hasNewValue = 1;
   9706 let opNewValue = 0;
   9707 let isPseudo = 1;
   9708 let isCodeGenOnly = 1;
   9709 }
   9710 def L2_loadrigp : HInst<
   9711 (outs IntRegs:$Rd32),
   9712 (ins u30_2Imm:$Ii),
   9713 "$Rd32 = memw(gp+#$Ii)",
   9714 tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
   9715 let Inst{24-21} = 0b1100;
   9716 let Inst{31-27} = 0b01001;
   9717 let hasNewValue = 1;
   9718 let opNewValue = 0;
   9719 let accessSize = WordAccess;
   9720 let mayLoad = 1;
   9721 let Uses = [GP];
   9722 let BaseOpcode = "L4_loadri_abs";
   9723 let isPredicable = 1;
   9724 let opExtendable = 1;
   9725 let isExtentSigned = 0;
   9726 let opExtentBits = 18;
   9727 let opExtentAlign = 2;
   9728 }
   9729 def L2_loadrub_io : HInst<
   9730 (outs IntRegs:$Rd32),
   9731 (ins IntRegs:$Rs32, s32_0Imm:$Ii),
   9732 "$Rd32 = memub($Rs32+#$Ii)",
   9733 tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
   9734 let Inst{24-21} = 0b1001;
   9735 let Inst{31-27} = 0b10010;
   9736 let hasNewValue = 1;
   9737 let opNewValue = 0;
   9738 let addrMode = BaseImmOffset;
   9739 let accessSize = ByteAccess;
   9740 let mayLoad = 1;
   9741 let CextOpcode = "L2_loadrub";
   9742 let BaseOpcode = "L2_loadrub_io";
   9743 let isPredicable = 1;
   9744 let isExtendable = 1;
   9745 let opExtendable = 2;
   9746 let isExtentSigned = 1;
   9747 let opExtentBits = 11;
   9748 let opExtentAlign = 0;
   9749 }
   9750 def L2_loadrub_pbr : HInst<
   9751 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9752 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9753 "$Rd32 = memub($Rx32++$Mu2:brev)",
   9754 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9755 let Inst{12-5} = 0b00000000;
   9756 let Inst{31-21} = 0b10011111001;
   9757 let hasNewValue = 1;
   9758 let opNewValue = 0;
   9759 let accessSize = ByteAccess;
   9760 let mayLoad = 1;
   9761 let Constraints = "$Rx32 = $Rx32in";
   9762 }
   9763 def L2_loadrub_pci : HInst<
   9764 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9765 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
   9766 "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
   9767 tc_4403ca65, TypeLD>, Enc_e0a47a {
   9768 let Inst{12-9} = 0b0000;
   9769 let Inst{31-21} = 0b10011001001;
   9770 let hasNewValue = 1;
   9771 let opNewValue = 0;
   9772 let addrMode = PostInc;
   9773 let accessSize = ByteAccess;
   9774 let mayLoad = 1;
   9775 let Uses = [CS];
   9776 let Constraints = "$Rx32 = $Rx32in";
   9777 }
   9778 def L2_loadrub_pcr : HInst<
   9779 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9780 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9781 "$Rd32 = memub($Rx32++I:circ($Mu2))",
   9782 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9783 let Inst{12-5} = 0b00010000;
   9784 let Inst{31-21} = 0b10011001001;
   9785 let hasNewValue = 1;
   9786 let opNewValue = 0;
   9787 let addrMode = PostInc;
   9788 let accessSize = ByteAccess;
   9789 let mayLoad = 1;
   9790 let Uses = [CS];
   9791 let Constraints = "$Rx32 = $Rx32in";
   9792 }
   9793 def L2_loadrub_pi : HInst<
   9794 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9795 (ins IntRegs:$Rx32in, s4_0Imm:$Ii),
   9796 "$Rd32 = memub($Rx32++#$Ii)",
   9797 tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
   9798 let Inst{13-9} = 0b00000;
   9799 let Inst{31-21} = 0b10011011001;
   9800 let hasNewValue = 1;
   9801 let opNewValue = 0;
   9802 let addrMode = PostInc;
   9803 let accessSize = ByteAccess;
   9804 let mayLoad = 1;
   9805 let CextOpcode = "L2_loadrub";
   9806 let BaseOpcode = "L2_loadrub_pi";
   9807 let isPredicable = 1;
   9808 let Constraints = "$Rx32 = $Rx32in";
   9809 }
   9810 def L2_loadrub_pr : HInst<
   9811 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9812 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9813 "$Rd32 = memub($Rx32++$Mu2)",
   9814 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9815 let Inst{12-5} = 0b00000000;
   9816 let Inst{31-21} = 0b10011101001;
   9817 let hasNewValue = 1;
   9818 let opNewValue = 0;
   9819 let addrMode = PostInc;
   9820 let accessSize = ByteAccess;
   9821 let mayLoad = 1;
   9822 let Constraints = "$Rx32 = $Rx32in";
   9823 }
   9824 def L2_loadrub_zomap : HInst<
   9825 (outs IntRegs:$Rd32),
   9826 (ins IntRegs:$Rs32),
   9827 "$Rd32 = memub($Rs32)",
   9828 tc_7f881c76, TypeMAPPING> {
   9829 let hasNewValue = 1;
   9830 let opNewValue = 0;
   9831 let isPseudo = 1;
   9832 let isCodeGenOnly = 1;
   9833 }
   9834 def L2_loadrubgp : HInst<
   9835 (outs IntRegs:$Rd32),
   9836 (ins u32_0Imm:$Ii),
   9837 "$Rd32 = memub(gp+#$Ii)",
   9838 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
   9839 let Inst{24-21} = 0b1001;
   9840 let Inst{31-27} = 0b01001;
   9841 let hasNewValue = 1;
   9842 let opNewValue = 0;
   9843 let accessSize = ByteAccess;
   9844 let mayLoad = 1;
   9845 let Uses = [GP];
   9846 let BaseOpcode = "L4_loadrub_abs";
   9847 let isPredicable = 1;
   9848 let opExtendable = 1;
   9849 let isExtentSigned = 0;
   9850 let opExtentBits = 16;
   9851 let opExtentAlign = 0;
   9852 }
   9853 def L2_loadruh_io : HInst<
   9854 (outs IntRegs:$Rd32),
   9855 (ins IntRegs:$Rs32, s31_1Imm:$Ii),
   9856 "$Rd32 = memuh($Rs32+#$Ii)",
   9857 tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
   9858 let Inst{24-21} = 0b1011;
   9859 let Inst{31-27} = 0b10010;
   9860 let hasNewValue = 1;
   9861 let opNewValue = 0;
   9862 let addrMode = BaseImmOffset;
   9863 let accessSize = HalfWordAccess;
   9864 let mayLoad = 1;
   9865 let CextOpcode = "L2_loadruh";
   9866 let BaseOpcode = "L2_loadruh_io";
   9867 let isPredicable = 1;
   9868 let isExtendable = 1;
   9869 let opExtendable = 2;
   9870 let isExtentSigned = 1;
   9871 let opExtentBits = 12;
   9872 let opExtentAlign = 1;
   9873 }
   9874 def L2_loadruh_pbr : HInst<
   9875 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9876 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9877 "$Rd32 = memuh($Rx32++$Mu2:brev)",
   9878 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9879 let Inst{12-5} = 0b00000000;
   9880 let Inst{31-21} = 0b10011111011;
   9881 let hasNewValue = 1;
   9882 let opNewValue = 0;
   9883 let accessSize = HalfWordAccess;
   9884 let mayLoad = 1;
   9885 let Constraints = "$Rx32 = $Rx32in";
   9886 }
   9887 def L2_loadruh_pci : HInst<
   9888 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9889 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
   9890 "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
   9891 tc_4403ca65, TypeLD>, Enc_e83554 {
   9892 let Inst{12-9} = 0b0000;
   9893 let Inst{31-21} = 0b10011001011;
   9894 let hasNewValue = 1;
   9895 let opNewValue = 0;
   9896 let addrMode = PostInc;
   9897 let accessSize = HalfWordAccess;
   9898 let mayLoad = 1;
   9899 let Uses = [CS];
   9900 let Constraints = "$Rx32 = $Rx32in";
   9901 }
   9902 def L2_loadruh_pcr : HInst<
   9903 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9904 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9905 "$Rd32 = memuh($Rx32++I:circ($Mu2))",
   9906 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9907 let Inst{12-5} = 0b00010000;
   9908 let Inst{31-21} = 0b10011001011;
   9909 let hasNewValue = 1;
   9910 let opNewValue = 0;
   9911 let addrMode = PostInc;
   9912 let accessSize = HalfWordAccess;
   9913 let mayLoad = 1;
   9914 let Uses = [CS];
   9915 let Constraints = "$Rx32 = $Rx32in";
   9916 }
   9917 def L2_loadruh_pi : HInst<
   9918 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9919 (ins IntRegs:$Rx32in, s4_1Imm:$Ii),
   9920 "$Rd32 = memuh($Rx32++#$Ii)",
   9921 tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
   9922 let Inst{13-9} = 0b00000;
   9923 let Inst{31-21} = 0b10011011011;
   9924 let hasNewValue = 1;
   9925 let opNewValue = 0;
   9926 let addrMode = PostInc;
   9927 let accessSize = HalfWordAccess;
   9928 let mayLoad = 1;
   9929 let CextOpcode = "L2_loadruh";
   9930 let BaseOpcode = "L2_loadruh_pi";
   9931 let isPredicable = 1;
   9932 let Constraints = "$Rx32 = $Rx32in";
   9933 }
   9934 def L2_loadruh_pr : HInst<
   9935 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   9936 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   9937 "$Rd32 = memuh($Rx32++$Mu2)",
   9938 tc_2fc0c436, TypeLD>, Enc_74d4e5 {
   9939 let Inst{12-5} = 0b00000000;
   9940 let Inst{31-21} = 0b10011101011;
   9941 let hasNewValue = 1;
   9942 let opNewValue = 0;
   9943 let addrMode = PostInc;
   9944 let accessSize = HalfWordAccess;
   9945 let mayLoad = 1;
   9946 let Constraints = "$Rx32 = $Rx32in";
   9947 }
   9948 def L2_loadruh_zomap : HInst<
   9949 (outs IntRegs:$Rd32),
   9950 (ins IntRegs:$Rs32),
   9951 "$Rd32 = memuh($Rs32)",
   9952 tc_7f881c76, TypeMAPPING> {
   9953 let hasNewValue = 1;
   9954 let opNewValue = 0;
   9955 let isPseudo = 1;
   9956 let isCodeGenOnly = 1;
   9957 }
   9958 def L2_loadruhgp : HInst<
   9959 (outs IntRegs:$Rd32),
   9960 (ins u31_1Imm:$Ii),
   9961 "$Rd32 = memuh(gp+#$Ii)",
   9962 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
   9963 let Inst{24-21} = 0b1011;
   9964 let Inst{31-27} = 0b01001;
   9965 let hasNewValue = 1;
   9966 let opNewValue = 0;
   9967 let accessSize = HalfWordAccess;
   9968 let mayLoad = 1;
   9969 let Uses = [GP];
   9970 let BaseOpcode = "L4_loadruh_abs";
   9971 let isPredicable = 1;
   9972 let opExtendable = 1;
   9973 let isExtentSigned = 0;
   9974 let opExtentBits = 17;
   9975 let opExtentAlign = 1;
   9976 }
   9977 def L2_loadw_locked : HInst<
   9978 (outs IntRegs:$Rd32),
   9979 (ins IntRegs:$Rs32),
   9980 "$Rd32 = memw_locked($Rs32)",
   9981 tc_6aa5711a, TypeLD>, Enc_5e2823 {
   9982 let Inst{13-5} = 0b000000000;
   9983 let Inst{31-21} = 0b10010010000;
   9984 let hasNewValue = 1;
   9985 let opNewValue = 0;
   9986 let accessSize = WordAccess;
   9987 let mayLoad = 1;
   9988 let isSoloAX = 1;
   9989 }
   9990 def L2_ploadrbf_io : HInst<
   9991 (outs IntRegs:$Rd32),
   9992 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   9993 "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
   9994 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   9995 let Inst{13-13} = 0b0;
   9996 let Inst{31-21} = 0b01000101000;
   9997 let isPredicated = 1;
   9998 let isPredicatedFalse = 1;
   9999 let hasNewValue = 1;
   10000 let opNewValue = 0;
   10001 let addrMode = BaseImmOffset;
   10002 let accessSize = ByteAccess;
   10003 let mayLoad = 1;
   10004 let CextOpcode = "L2_loadrb";
   10005 let BaseOpcode = "L2_loadrb_io";
   10006 let isExtendable = 1;
   10007 let opExtendable = 3;
   10008 let isExtentSigned = 0;
   10009 let opExtentBits = 6;
   10010 let opExtentAlign = 0;
   10011 }
   10012 def L2_ploadrbf_pi : HInst<
   10013 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10014 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10015 "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
   10016 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
   10017 let Inst{13-11} = 0b101;
   10018 let Inst{31-21} = 0b10011011000;
   10019 let isPredicated = 1;
   10020 let isPredicatedFalse = 1;
   10021 let hasNewValue = 1;
   10022 let opNewValue = 0;
   10023 let addrMode = PostInc;
   10024 let accessSize = ByteAccess;
   10025 let mayLoad = 1;
   10026 let BaseOpcode = "L2_loadrb_pi";
   10027 let Constraints = "$Rx32 = $Rx32in";
   10028 }
   10029 def L2_ploadrbf_zomap : HInst<
   10030 (outs IntRegs:$Rd32),
   10031 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10032 "if (!$Pt4) $Rd32 = memb($Rs32)",
   10033 tc_ef52ed71, TypeMAPPING> {
   10034 let hasNewValue = 1;
   10035 let opNewValue = 0;
   10036 let isPseudo = 1;
   10037 let isCodeGenOnly = 1;
   10038 }
   10039 def L2_ploadrbfnew_io : HInst<
   10040 (outs IntRegs:$Rd32),
   10041 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10042 "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
   10043 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10044 let Inst{13-13} = 0b0;
   10045 let Inst{31-21} = 0b01000111000;
   10046 let isPredicated = 1;
   10047 let isPredicatedFalse = 1;
   10048 let hasNewValue = 1;
   10049 let opNewValue = 0;
   10050 let addrMode = BaseImmOffset;
   10051 let accessSize = ByteAccess;
   10052 let isPredicatedNew = 1;
   10053 let mayLoad = 1;
   10054 let CextOpcode = "L2_loadrb";
   10055 let BaseOpcode = "L2_loadrb_io";
   10056 let isExtendable = 1;
   10057 let opExtendable = 3;
   10058 let isExtentSigned = 0;
   10059 let opExtentBits = 6;
   10060 let opExtentAlign = 0;
   10061 }
   10062 def L2_ploadrbfnew_pi : HInst<
   10063 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10064 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10065 "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
   10066 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
   10067 let Inst{13-11} = 0b111;
   10068 let Inst{31-21} = 0b10011011000;
   10069 let isPredicated = 1;
   10070 let isPredicatedFalse = 1;
   10071 let hasNewValue = 1;
   10072 let opNewValue = 0;
   10073 let addrMode = PostInc;
   10074 let accessSize = ByteAccess;
   10075 let isPredicatedNew = 1;
   10076 let mayLoad = 1;
   10077 let BaseOpcode = "L2_loadrb_pi";
   10078 let Constraints = "$Rx32 = $Rx32in";
   10079 }
   10080 def L2_ploadrbfnew_zomap : HInst<
   10081 (outs IntRegs:$Rd32),
   10082 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10083 "if (!$Pt4.new) $Rd32 = memb($Rs32)",
   10084 tc_2fc0c436, TypeMAPPING> {
   10085 let hasNewValue = 1;
   10086 let opNewValue = 0;
   10087 let isPseudo = 1;
   10088 let isCodeGenOnly = 1;
   10089 }
   10090 def L2_ploadrbt_io : HInst<
   10091 (outs IntRegs:$Rd32),
   10092 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10093 "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
   10094 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10095 let Inst{13-13} = 0b0;
   10096 let Inst{31-21} = 0b01000001000;
   10097 let isPredicated = 1;
   10098 let hasNewValue = 1;
   10099 let opNewValue = 0;
   10100 let addrMode = BaseImmOffset;
   10101 let accessSize = ByteAccess;
   10102 let mayLoad = 1;
   10103 let CextOpcode = "L2_loadrb";
   10104 let BaseOpcode = "L2_loadrb_io";
   10105 let isExtendable = 1;
   10106 let opExtendable = 3;
   10107 let isExtentSigned = 0;
   10108 let opExtentBits = 6;
   10109 let opExtentAlign = 0;
   10110 }
   10111 def L2_ploadrbt_pi : HInst<
   10112 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10113 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10114 "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
   10115 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
   10116 let Inst{13-11} = 0b100;
   10117 let Inst{31-21} = 0b10011011000;
   10118 let isPredicated = 1;
   10119 let hasNewValue = 1;
   10120 let opNewValue = 0;
   10121 let addrMode = PostInc;
   10122 let accessSize = ByteAccess;
   10123 let mayLoad = 1;
   10124 let BaseOpcode = "L2_loadrb_pi";
   10125 let Constraints = "$Rx32 = $Rx32in";
   10126 }
   10127 def L2_ploadrbt_zomap : HInst<
   10128 (outs IntRegs:$Rd32),
   10129 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10130 "if ($Pt4) $Rd32 = memb($Rs32)",
   10131 tc_ef52ed71, TypeMAPPING> {
   10132 let hasNewValue = 1;
   10133 let opNewValue = 0;
   10134 let isPseudo = 1;
   10135 let isCodeGenOnly = 1;
   10136 }
   10137 def L2_ploadrbtnew_io : HInst<
   10138 (outs IntRegs:$Rd32),
   10139 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10140 "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
   10141 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10142 let Inst{13-13} = 0b0;
   10143 let Inst{31-21} = 0b01000011000;
   10144 let isPredicated = 1;
   10145 let hasNewValue = 1;
   10146 let opNewValue = 0;
   10147 let addrMode = BaseImmOffset;
   10148 let accessSize = ByteAccess;
   10149 let isPredicatedNew = 1;
   10150 let mayLoad = 1;
   10151 let CextOpcode = "L2_loadrb";
   10152 let BaseOpcode = "L2_loadrb_io";
   10153 let isExtendable = 1;
   10154 let opExtendable = 3;
   10155 let isExtentSigned = 0;
   10156 let opExtentBits = 6;
   10157 let opExtentAlign = 0;
   10158 }
   10159 def L2_ploadrbtnew_pi : HInst<
   10160 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10161 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10162 "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
   10163 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
   10164 let Inst{13-11} = 0b110;
   10165 let Inst{31-21} = 0b10011011000;
   10166 let isPredicated = 1;
   10167 let hasNewValue = 1;
   10168 let opNewValue = 0;
   10169 let addrMode = PostInc;
   10170 let accessSize = ByteAccess;
   10171 let isPredicatedNew = 1;
   10172 let mayLoad = 1;
   10173 let BaseOpcode = "L2_loadrb_pi";
   10174 let Constraints = "$Rx32 = $Rx32in";
   10175 }
   10176 def L2_ploadrbtnew_zomap : HInst<
   10177 (outs IntRegs:$Rd32),
   10178 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10179 "if ($Pt4.new) $Rd32 = memb($Rs32)",
   10180 tc_2fc0c436, TypeMAPPING> {
   10181 let hasNewValue = 1;
   10182 let opNewValue = 0;
   10183 let isPseudo = 1;
   10184 let isCodeGenOnly = 1;
   10185 }
   10186 def L2_ploadrdf_io : HInst<
   10187 (outs DoubleRegs:$Rdd32),
   10188 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
   10189 "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
   10190 tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
   10191 let Inst{13-13} = 0b0;
   10192 let Inst{31-21} = 0b01000101110;
   10193 let isPredicated = 1;
   10194 let isPredicatedFalse = 1;
   10195 let addrMode = BaseImmOffset;
   10196 let accessSize = DoubleWordAccess;
   10197 let mayLoad = 1;
   10198 let CextOpcode = "L2_loadrd";
   10199 let BaseOpcode = "L2_loadrd_io";
   10200 let isExtendable = 1;
   10201 let opExtendable = 3;
   10202 let isExtentSigned = 0;
   10203 let opExtentBits = 9;
   10204 let opExtentAlign = 3;
   10205 }
   10206 def L2_ploadrdf_pi : HInst<
   10207 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   10208 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
   10209 "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
   10210 tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
   10211 let Inst{13-11} = 0b101;
   10212 let Inst{31-21} = 0b10011011110;
   10213 let isPredicated = 1;
   10214 let isPredicatedFalse = 1;
   10215 let addrMode = PostInc;
   10216 let accessSize = DoubleWordAccess;
   10217 let mayLoad = 1;
   10218 let BaseOpcode = "L2_loadrd_pi";
   10219 let Constraints = "$Rx32 = $Rx32in";
   10220 }
   10221 def L2_ploadrdf_zomap : HInst<
   10222 (outs DoubleRegs:$Rdd32),
   10223 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10224 "if (!$Pt4) $Rdd32 = memd($Rs32)",
   10225 tc_ef52ed71, TypeMAPPING> {
   10226 let isPseudo = 1;
   10227 let isCodeGenOnly = 1;
   10228 }
   10229 def L2_ploadrdfnew_io : HInst<
   10230 (outs DoubleRegs:$Rdd32),
   10231 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
   10232 "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
   10233 tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
   10234 let Inst{13-13} = 0b0;
   10235 let Inst{31-21} = 0b01000111110;
   10236 let isPredicated = 1;
   10237 let isPredicatedFalse = 1;
   10238 let addrMode = BaseImmOffset;
   10239 let accessSize = DoubleWordAccess;
   10240 let isPredicatedNew = 1;
   10241 let mayLoad = 1;
   10242 let CextOpcode = "L2_loadrd";
   10243 let BaseOpcode = "L2_loadrd_io";
   10244 let isExtendable = 1;
   10245 let opExtendable = 3;
   10246 let isExtentSigned = 0;
   10247 let opExtentBits = 9;
   10248 let opExtentAlign = 3;
   10249 }
   10250 def L2_ploadrdfnew_pi : HInst<
   10251 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   10252 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
   10253 "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
   10254 tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
   10255 let Inst{13-11} = 0b111;
   10256 let Inst{31-21} = 0b10011011110;
   10257 let isPredicated = 1;
   10258 let isPredicatedFalse = 1;
   10259 let addrMode = PostInc;
   10260 let accessSize = DoubleWordAccess;
   10261 let isPredicatedNew = 1;
   10262 let mayLoad = 1;
   10263 let BaseOpcode = "L2_loadrd_pi";
   10264 let Constraints = "$Rx32 = $Rx32in";
   10265 }
   10266 def L2_ploadrdfnew_zomap : HInst<
   10267 (outs DoubleRegs:$Rdd32),
   10268 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10269 "if (!$Pt4.new) $Rdd32 = memd($Rs32)",
   10270 tc_2fc0c436, TypeMAPPING> {
   10271 let isPseudo = 1;
   10272 let isCodeGenOnly = 1;
   10273 }
   10274 def L2_ploadrdt_io : HInst<
   10275 (outs DoubleRegs:$Rdd32),
   10276 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
   10277 "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
   10278 tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
   10279 let Inst{13-13} = 0b0;
   10280 let Inst{31-21} = 0b01000001110;
   10281 let isPredicated = 1;
   10282 let addrMode = BaseImmOffset;
   10283 let accessSize = DoubleWordAccess;
   10284 let mayLoad = 1;
   10285 let CextOpcode = "L2_loadrd";
   10286 let BaseOpcode = "L2_loadrd_io";
   10287 let isExtendable = 1;
   10288 let opExtendable = 3;
   10289 let isExtentSigned = 0;
   10290 let opExtentBits = 9;
   10291 let opExtentAlign = 3;
   10292 }
   10293 def L2_ploadrdt_pi : HInst<
   10294 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   10295 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
   10296 "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
   10297 tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel {
   10298 let Inst{13-11} = 0b100;
   10299 let Inst{31-21} = 0b10011011110;
   10300 let isPredicated = 1;
   10301 let addrMode = PostInc;
   10302 let accessSize = DoubleWordAccess;
   10303 let mayLoad = 1;
   10304 let BaseOpcode = "L2_loadrd_pi";
   10305 let Constraints = "$Rx32 = $Rx32in";
   10306 }
   10307 def L2_ploadrdt_zomap : HInst<
   10308 (outs DoubleRegs:$Rdd32),
   10309 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10310 "if ($Pt4) $Rdd32 = memd($Rs32)",
   10311 tc_ef52ed71, TypeMAPPING> {
   10312 let isPseudo = 1;
   10313 let isCodeGenOnly = 1;
   10314 }
   10315 def L2_ploadrdtnew_io : HInst<
   10316 (outs DoubleRegs:$Rdd32),
   10317 (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
   10318 "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
   10319 tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
   10320 let Inst{13-13} = 0b0;
   10321 let Inst{31-21} = 0b01000011110;
   10322 let isPredicated = 1;
   10323 let addrMode = BaseImmOffset;
   10324 let accessSize = DoubleWordAccess;
   10325 let isPredicatedNew = 1;
   10326 let mayLoad = 1;
   10327 let CextOpcode = "L2_loadrd";
   10328 let BaseOpcode = "L2_loadrd_io";
   10329 let isExtendable = 1;
   10330 let opExtendable = 3;
   10331 let isExtentSigned = 0;
   10332 let opExtentBits = 9;
   10333 let opExtentAlign = 3;
   10334 }
   10335 def L2_ploadrdtnew_pi : HInst<
   10336 (outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
   10337 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
   10338 "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
   10339 tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel {
   10340 let Inst{13-11} = 0b110;
   10341 let Inst{31-21} = 0b10011011110;
   10342 let isPredicated = 1;
   10343 let addrMode = PostInc;
   10344 let accessSize = DoubleWordAccess;
   10345 let isPredicatedNew = 1;
   10346 let mayLoad = 1;
   10347 let BaseOpcode = "L2_loadrd_pi";
   10348 let Constraints = "$Rx32 = $Rx32in";
   10349 }
   10350 def L2_ploadrdtnew_zomap : HInst<
   10351 (outs DoubleRegs:$Rdd32),
   10352 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10353 "if ($Pt4.new) $Rdd32 = memd($Rs32)",
   10354 tc_2fc0c436, TypeMAPPING> {
   10355 let isPseudo = 1;
   10356 let isCodeGenOnly = 1;
   10357 }
   10358 def L2_ploadrhf_io : HInst<
   10359 (outs IntRegs:$Rd32),
   10360 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10361 "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
   10362 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   10363 let Inst{13-13} = 0b0;
   10364 let Inst{31-21} = 0b01000101010;
   10365 let isPredicated = 1;
   10366 let isPredicatedFalse = 1;
   10367 let hasNewValue = 1;
   10368 let opNewValue = 0;
   10369 let addrMode = BaseImmOffset;
   10370 let accessSize = HalfWordAccess;
   10371 let mayLoad = 1;
   10372 let CextOpcode = "L2_loadrh";
   10373 let BaseOpcode = "L2_loadrh_io";
   10374 let isExtendable = 1;
   10375 let opExtendable = 3;
   10376 let isExtentSigned = 0;
   10377 let opExtentBits = 7;
   10378 let opExtentAlign = 1;
   10379 }
   10380 def L2_ploadrhf_pi : HInst<
   10381 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10382 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   10383 "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
   10384 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
   10385 let Inst{13-11} = 0b101;
   10386 let Inst{31-21} = 0b10011011010;
   10387 let isPredicated = 1;
   10388 let isPredicatedFalse = 1;
   10389 let hasNewValue = 1;
   10390 let opNewValue = 0;
   10391 let addrMode = PostInc;
   10392 let accessSize = HalfWordAccess;
   10393 let mayLoad = 1;
   10394 let BaseOpcode = "L2_loadrh_pi";
   10395 let Constraints = "$Rx32 = $Rx32in";
   10396 }
   10397 def L2_ploadrhf_zomap : HInst<
   10398 (outs IntRegs:$Rd32),
   10399 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10400 "if (!$Pt4) $Rd32 = memh($Rs32)",
   10401 tc_ef52ed71, TypeMAPPING> {
   10402 let hasNewValue = 1;
   10403 let opNewValue = 0;
   10404 let isPseudo = 1;
   10405 let isCodeGenOnly = 1;
   10406 }
   10407 def L2_ploadrhfnew_io : HInst<
   10408 (outs IntRegs:$Rd32),
   10409 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10410 "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
   10411 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   10412 let Inst{13-13} = 0b0;
   10413 let Inst{31-21} = 0b01000111010;
   10414 let isPredicated = 1;
   10415 let isPredicatedFalse = 1;
   10416 let hasNewValue = 1;
   10417 let opNewValue = 0;
   10418 let addrMode = BaseImmOffset;
   10419 let accessSize = HalfWordAccess;
   10420 let isPredicatedNew = 1;
   10421 let mayLoad = 1;
   10422 let CextOpcode = "L2_loadrh";
   10423 let BaseOpcode = "L2_loadrh_io";
   10424 let isExtendable = 1;
   10425 let opExtendable = 3;
   10426 let isExtentSigned = 0;
   10427 let opExtentBits = 7;
   10428 let opExtentAlign = 1;
   10429 }
   10430 def L2_ploadrhfnew_pi : HInst<
   10431 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10432 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   10433 "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
   10434 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
   10435 let Inst{13-11} = 0b111;
   10436 let Inst{31-21} = 0b10011011010;
   10437 let isPredicated = 1;
   10438 let isPredicatedFalse = 1;
   10439 let hasNewValue = 1;
   10440 let opNewValue = 0;
   10441 let addrMode = PostInc;
   10442 let accessSize = HalfWordAccess;
   10443 let isPredicatedNew = 1;
   10444 let mayLoad = 1;
   10445 let BaseOpcode = "L2_loadrh_pi";
   10446 let Constraints = "$Rx32 = $Rx32in";
   10447 }
   10448 def L2_ploadrhfnew_zomap : HInst<
   10449 (outs IntRegs:$Rd32),
   10450 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10451 "if (!$Pt4.new) $Rd32 = memh($Rs32)",
   10452 tc_2fc0c436, TypeMAPPING> {
   10453 let hasNewValue = 1;
   10454 let opNewValue = 0;
   10455 let isPseudo = 1;
   10456 let isCodeGenOnly = 1;
   10457 }
   10458 def L2_ploadrht_io : HInst<
   10459 (outs IntRegs:$Rd32),
   10460 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10461 "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
   10462 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   10463 let Inst{13-13} = 0b0;
   10464 let Inst{31-21} = 0b01000001010;
   10465 let isPredicated = 1;
   10466 let hasNewValue = 1;
   10467 let opNewValue = 0;
   10468 let addrMode = BaseImmOffset;
   10469 let accessSize = HalfWordAccess;
   10470 let mayLoad = 1;
   10471 let CextOpcode = "L2_loadrh";
   10472 let BaseOpcode = "L2_loadrh_io";
   10473 let isExtendable = 1;
   10474 let opExtendable = 3;
   10475 let isExtentSigned = 0;
   10476 let opExtentBits = 7;
   10477 let opExtentAlign = 1;
   10478 }
   10479 def L2_ploadrht_pi : HInst<
   10480 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10481 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   10482 "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
   10483 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
   10484 let Inst{13-11} = 0b100;
   10485 let Inst{31-21} = 0b10011011010;
   10486 let isPredicated = 1;
   10487 let hasNewValue = 1;
   10488 let opNewValue = 0;
   10489 let addrMode = PostInc;
   10490 let accessSize = HalfWordAccess;
   10491 let mayLoad = 1;
   10492 let BaseOpcode = "L2_loadrh_pi";
   10493 let Constraints = "$Rx32 = $Rx32in";
   10494 }
   10495 def L2_ploadrht_zomap : HInst<
   10496 (outs IntRegs:$Rd32),
   10497 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10498 "if ($Pt4) $Rd32 = memh($Rs32)",
   10499 tc_ef52ed71, TypeMAPPING> {
   10500 let hasNewValue = 1;
   10501 let opNewValue = 0;
   10502 let isPseudo = 1;
   10503 let isCodeGenOnly = 1;
   10504 }
   10505 def L2_ploadrhtnew_io : HInst<
   10506 (outs IntRegs:$Rd32),
   10507 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10508 "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
   10509 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   10510 let Inst{13-13} = 0b0;
   10511 let Inst{31-21} = 0b01000011010;
   10512 let isPredicated = 1;
   10513 let hasNewValue = 1;
   10514 let opNewValue = 0;
   10515 let addrMode = BaseImmOffset;
   10516 let accessSize = HalfWordAccess;
   10517 let isPredicatedNew = 1;
   10518 let mayLoad = 1;
   10519 let CextOpcode = "L2_loadrh";
   10520 let BaseOpcode = "L2_loadrh_io";
   10521 let isExtendable = 1;
   10522 let opExtendable = 3;
   10523 let isExtentSigned = 0;
   10524 let opExtentBits = 7;
   10525 let opExtentAlign = 1;
   10526 }
   10527 def L2_ploadrhtnew_pi : HInst<
   10528 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10529 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   10530 "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
   10531 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
   10532 let Inst{13-11} = 0b110;
   10533 let Inst{31-21} = 0b10011011010;
   10534 let isPredicated = 1;
   10535 let hasNewValue = 1;
   10536 let opNewValue = 0;
   10537 let addrMode = PostInc;
   10538 let accessSize = HalfWordAccess;
   10539 let isPredicatedNew = 1;
   10540 let mayLoad = 1;
   10541 let BaseOpcode = "L2_loadrh_pi";
   10542 let Constraints = "$Rx32 = $Rx32in";
   10543 }
   10544 def L2_ploadrhtnew_zomap : HInst<
   10545 (outs IntRegs:$Rd32),
   10546 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10547 "if ($Pt4.new) $Rd32 = memh($Rs32)",
   10548 tc_2fc0c436, TypeMAPPING> {
   10549 let hasNewValue = 1;
   10550 let opNewValue = 0;
   10551 let isPseudo = 1;
   10552 let isCodeGenOnly = 1;
   10553 }
   10554 def L2_ploadrif_io : HInst<
   10555 (outs IntRegs:$Rd32),
   10556 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
   10557 "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
   10558 tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
   10559 let Inst{13-13} = 0b0;
   10560 let Inst{31-21} = 0b01000101100;
   10561 let isPredicated = 1;
   10562 let isPredicatedFalse = 1;
   10563 let hasNewValue = 1;
   10564 let opNewValue = 0;
   10565 let addrMode = BaseImmOffset;
   10566 let accessSize = WordAccess;
   10567 let mayLoad = 1;
   10568 let CextOpcode = "L2_loadri";
   10569 let BaseOpcode = "L2_loadri_io";
   10570 let isExtendable = 1;
   10571 let opExtendable = 3;
   10572 let isExtentSigned = 0;
   10573 let opExtentBits = 8;
   10574 let opExtentAlign = 2;
   10575 }
   10576 def L2_ploadrif_pi : HInst<
   10577 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10578 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
   10579 "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
   10580 tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
   10581 let Inst{13-11} = 0b101;
   10582 let Inst{31-21} = 0b10011011100;
   10583 let isPredicated = 1;
   10584 let isPredicatedFalse = 1;
   10585 let hasNewValue = 1;
   10586 let opNewValue = 0;
   10587 let addrMode = PostInc;
   10588 let accessSize = WordAccess;
   10589 let mayLoad = 1;
   10590 let BaseOpcode = "L2_loadri_pi";
   10591 let Constraints = "$Rx32 = $Rx32in";
   10592 }
   10593 def L2_ploadrif_zomap : HInst<
   10594 (outs IntRegs:$Rd32),
   10595 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10596 "if (!$Pt4) $Rd32 = memw($Rs32)",
   10597 tc_ef52ed71, TypeMAPPING> {
   10598 let hasNewValue = 1;
   10599 let opNewValue = 0;
   10600 let isPseudo = 1;
   10601 let isCodeGenOnly = 1;
   10602 }
   10603 def L2_ploadrifnew_io : HInst<
   10604 (outs IntRegs:$Rd32),
   10605 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
   10606 "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
   10607 tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
   10608 let Inst{13-13} = 0b0;
   10609 let Inst{31-21} = 0b01000111100;
   10610 let isPredicated = 1;
   10611 let isPredicatedFalse = 1;
   10612 let hasNewValue = 1;
   10613 let opNewValue = 0;
   10614 let addrMode = BaseImmOffset;
   10615 let accessSize = WordAccess;
   10616 let isPredicatedNew = 1;
   10617 let mayLoad = 1;
   10618 let CextOpcode = "L2_loadri";
   10619 let BaseOpcode = "L2_loadri_io";
   10620 let isExtendable = 1;
   10621 let opExtendable = 3;
   10622 let isExtentSigned = 0;
   10623 let opExtentBits = 8;
   10624 let opExtentAlign = 2;
   10625 }
   10626 def L2_ploadrifnew_pi : HInst<
   10627 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10628 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
   10629 "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
   10630 tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
   10631 let Inst{13-11} = 0b111;
   10632 let Inst{31-21} = 0b10011011100;
   10633 let isPredicated = 1;
   10634 let isPredicatedFalse = 1;
   10635 let hasNewValue = 1;
   10636 let opNewValue = 0;
   10637 let addrMode = PostInc;
   10638 let accessSize = WordAccess;
   10639 let isPredicatedNew = 1;
   10640 let mayLoad = 1;
   10641 let BaseOpcode = "L2_loadri_pi";
   10642 let Constraints = "$Rx32 = $Rx32in";
   10643 }
   10644 def L2_ploadrifnew_zomap : HInst<
   10645 (outs IntRegs:$Rd32),
   10646 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10647 "if (!$Pt4.new) $Rd32 = memw($Rs32)",
   10648 tc_2fc0c436, TypeMAPPING> {
   10649 let hasNewValue = 1;
   10650 let opNewValue = 0;
   10651 let isPseudo = 1;
   10652 let isCodeGenOnly = 1;
   10653 }
   10654 def L2_ploadrit_io : HInst<
   10655 (outs IntRegs:$Rd32),
   10656 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
   10657 "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
   10658 tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
   10659 let Inst{13-13} = 0b0;
   10660 let Inst{31-21} = 0b01000001100;
   10661 let isPredicated = 1;
   10662 let hasNewValue = 1;
   10663 let opNewValue = 0;
   10664 let addrMode = BaseImmOffset;
   10665 let accessSize = WordAccess;
   10666 let mayLoad = 1;
   10667 let CextOpcode = "L2_loadri";
   10668 let BaseOpcode = "L2_loadri_io";
   10669 let isExtendable = 1;
   10670 let opExtendable = 3;
   10671 let isExtentSigned = 0;
   10672 let opExtentBits = 8;
   10673 let opExtentAlign = 2;
   10674 }
   10675 def L2_ploadrit_pi : HInst<
   10676 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10677 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
   10678 "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
   10679 tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel {
   10680 let Inst{13-11} = 0b100;
   10681 let Inst{31-21} = 0b10011011100;
   10682 let isPredicated = 1;
   10683 let hasNewValue = 1;
   10684 let opNewValue = 0;
   10685 let addrMode = PostInc;
   10686 let accessSize = WordAccess;
   10687 let mayLoad = 1;
   10688 let BaseOpcode = "L2_loadri_pi";
   10689 let Constraints = "$Rx32 = $Rx32in";
   10690 }
   10691 def L2_ploadrit_zomap : HInst<
   10692 (outs IntRegs:$Rd32),
   10693 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10694 "if ($Pt4) $Rd32 = memw($Rs32)",
   10695 tc_ef52ed71, TypeMAPPING> {
   10696 let hasNewValue = 1;
   10697 let opNewValue = 0;
   10698 let isPseudo = 1;
   10699 let isCodeGenOnly = 1;
   10700 }
   10701 def L2_ploadritnew_io : HInst<
   10702 (outs IntRegs:$Rd32),
   10703 (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
   10704 "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
   10705 tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
   10706 let Inst{13-13} = 0b0;
   10707 let Inst{31-21} = 0b01000011100;
   10708 let isPredicated = 1;
   10709 let hasNewValue = 1;
   10710 let opNewValue = 0;
   10711 let addrMode = BaseImmOffset;
   10712 let accessSize = WordAccess;
   10713 let isPredicatedNew = 1;
   10714 let mayLoad = 1;
   10715 let CextOpcode = "L2_loadri";
   10716 let BaseOpcode = "L2_loadri_io";
   10717 let isExtendable = 1;
   10718 let opExtendable = 3;
   10719 let isExtentSigned = 0;
   10720 let opExtentBits = 8;
   10721 let opExtentAlign = 2;
   10722 }
   10723 def L2_ploadritnew_pi : HInst<
   10724 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10725 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
   10726 "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
   10727 tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel {
   10728 let Inst{13-11} = 0b110;
   10729 let Inst{31-21} = 0b10011011100;
   10730 let isPredicated = 1;
   10731 let hasNewValue = 1;
   10732 let opNewValue = 0;
   10733 let addrMode = PostInc;
   10734 let accessSize = WordAccess;
   10735 let isPredicatedNew = 1;
   10736 let mayLoad = 1;
   10737 let BaseOpcode = "L2_loadri_pi";
   10738 let Constraints = "$Rx32 = $Rx32in";
   10739 }
   10740 def L2_ploadritnew_zomap : HInst<
   10741 (outs IntRegs:$Rd32),
   10742 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10743 "if ($Pt4.new) $Rd32 = memw($Rs32)",
   10744 tc_2fc0c436, TypeMAPPING> {
   10745 let hasNewValue = 1;
   10746 let opNewValue = 0;
   10747 let isPseudo = 1;
   10748 let isCodeGenOnly = 1;
   10749 }
   10750 def L2_ploadrubf_io : HInst<
   10751 (outs IntRegs:$Rd32),
   10752 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10753 "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
   10754 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10755 let Inst{13-13} = 0b0;
   10756 let Inst{31-21} = 0b01000101001;
   10757 let isPredicated = 1;
   10758 let isPredicatedFalse = 1;
   10759 let hasNewValue = 1;
   10760 let opNewValue = 0;
   10761 let addrMode = BaseImmOffset;
   10762 let accessSize = ByteAccess;
   10763 let mayLoad = 1;
   10764 let CextOpcode = "L2_loadrub";
   10765 let BaseOpcode = "L2_loadrub_io";
   10766 let isExtendable = 1;
   10767 let opExtendable = 3;
   10768 let isExtentSigned = 0;
   10769 let opExtentBits = 6;
   10770 let opExtentAlign = 0;
   10771 }
   10772 def L2_ploadrubf_pi : HInst<
   10773 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10774 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10775 "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
   10776 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
   10777 let Inst{13-11} = 0b101;
   10778 let Inst{31-21} = 0b10011011001;
   10779 let isPredicated = 1;
   10780 let isPredicatedFalse = 1;
   10781 let hasNewValue = 1;
   10782 let opNewValue = 0;
   10783 let addrMode = PostInc;
   10784 let accessSize = ByteAccess;
   10785 let mayLoad = 1;
   10786 let BaseOpcode = "L2_loadrub_pi";
   10787 let Constraints = "$Rx32 = $Rx32in";
   10788 }
   10789 def L2_ploadrubf_zomap : HInst<
   10790 (outs IntRegs:$Rd32),
   10791 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10792 "if (!$Pt4) $Rd32 = memub($Rs32)",
   10793 tc_ef52ed71, TypeMAPPING> {
   10794 let hasNewValue = 1;
   10795 let opNewValue = 0;
   10796 let isPseudo = 1;
   10797 let isCodeGenOnly = 1;
   10798 }
   10799 def L2_ploadrubfnew_io : HInst<
   10800 (outs IntRegs:$Rd32),
   10801 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10802 "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
   10803 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10804 let Inst{13-13} = 0b0;
   10805 let Inst{31-21} = 0b01000111001;
   10806 let isPredicated = 1;
   10807 let isPredicatedFalse = 1;
   10808 let hasNewValue = 1;
   10809 let opNewValue = 0;
   10810 let addrMode = BaseImmOffset;
   10811 let accessSize = ByteAccess;
   10812 let isPredicatedNew = 1;
   10813 let mayLoad = 1;
   10814 let CextOpcode = "L2_loadrub";
   10815 let BaseOpcode = "L2_loadrub_io";
   10816 let isExtendable = 1;
   10817 let opExtendable = 3;
   10818 let isExtentSigned = 0;
   10819 let opExtentBits = 6;
   10820 let opExtentAlign = 0;
   10821 }
   10822 def L2_ploadrubfnew_pi : HInst<
   10823 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10824 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10825 "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
   10826 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
   10827 let Inst{13-11} = 0b111;
   10828 let Inst{31-21} = 0b10011011001;
   10829 let isPredicated = 1;
   10830 let isPredicatedFalse = 1;
   10831 let hasNewValue = 1;
   10832 let opNewValue = 0;
   10833 let addrMode = PostInc;
   10834 let accessSize = ByteAccess;
   10835 let isPredicatedNew = 1;
   10836 let mayLoad = 1;
   10837 let BaseOpcode = "L2_loadrub_pi";
   10838 let Constraints = "$Rx32 = $Rx32in";
   10839 }
   10840 def L2_ploadrubfnew_zomap : HInst<
   10841 (outs IntRegs:$Rd32),
   10842 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10843 "if (!$Pt4.new) $Rd32 = memub($Rs32)",
   10844 tc_2fc0c436, TypeMAPPING> {
   10845 let hasNewValue = 1;
   10846 let opNewValue = 0;
   10847 let isPseudo = 1;
   10848 let isCodeGenOnly = 1;
   10849 }
   10850 def L2_ploadrubt_io : HInst<
   10851 (outs IntRegs:$Rd32),
   10852 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10853 "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
   10854 tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10855 let Inst{13-13} = 0b0;
   10856 let Inst{31-21} = 0b01000001001;
   10857 let isPredicated = 1;
   10858 let hasNewValue = 1;
   10859 let opNewValue = 0;
   10860 let addrMode = BaseImmOffset;
   10861 let accessSize = ByteAccess;
   10862 let mayLoad = 1;
   10863 let CextOpcode = "L2_loadrub";
   10864 let BaseOpcode = "L2_loadrub_io";
   10865 let isExtendable = 1;
   10866 let opExtendable = 3;
   10867 let isExtentSigned = 0;
   10868 let opExtentBits = 6;
   10869 let opExtentAlign = 0;
   10870 }
   10871 def L2_ploadrubt_pi : HInst<
   10872 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10873 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10874 "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
   10875 tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel {
   10876 let Inst{13-11} = 0b100;
   10877 let Inst{31-21} = 0b10011011001;
   10878 let isPredicated = 1;
   10879 let hasNewValue = 1;
   10880 let opNewValue = 0;
   10881 let addrMode = PostInc;
   10882 let accessSize = ByteAccess;
   10883 let mayLoad = 1;
   10884 let BaseOpcode = "L2_loadrub_pi";
   10885 let Constraints = "$Rx32 = $Rx32in";
   10886 }
   10887 def L2_ploadrubt_zomap : HInst<
   10888 (outs IntRegs:$Rd32),
   10889 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10890 "if ($Pt4) $Rd32 = memub($Rs32)",
   10891 tc_ef52ed71, TypeMAPPING> {
   10892 let hasNewValue = 1;
   10893 let opNewValue = 0;
   10894 let isPseudo = 1;
   10895 let isCodeGenOnly = 1;
   10896 }
   10897 def L2_ploadrubtnew_io : HInst<
   10898 (outs IntRegs:$Rd32),
   10899 (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
   10900 "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
   10901 tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel {
   10902 let Inst{13-13} = 0b0;
   10903 let Inst{31-21} = 0b01000011001;
   10904 let isPredicated = 1;
   10905 let hasNewValue = 1;
   10906 let opNewValue = 0;
   10907 let addrMode = BaseImmOffset;
   10908 let accessSize = ByteAccess;
   10909 let isPredicatedNew = 1;
   10910 let mayLoad = 1;
   10911 let CextOpcode = "L2_loadrub";
   10912 let BaseOpcode = "L2_loadrub_io";
   10913 let isExtendable = 1;
   10914 let opExtendable = 3;
   10915 let isExtentSigned = 0;
   10916 let opExtentBits = 6;
   10917 let opExtentAlign = 0;
   10918 }
   10919 def L2_ploadrubtnew_pi : HInst<
   10920 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10921 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
   10922 "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
   10923 tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel {
   10924 let Inst{13-11} = 0b110;
   10925 let Inst{31-21} = 0b10011011001;
   10926 let isPredicated = 1;
   10927 let hasNewValue = 1;
   10928 let opNewValue = 0;
   10929 let addrMode = PostInc;
   10930 let accessSize = ByteAccess;
   10931 let isPredicatedNew = 1;
   10932 let mayLoad = 1;
   10933 let BaseOpcode = "L2_loadrub_pi";
   10934 let Constraints = "$Rx32 = $Rx32in";
   10935 }
   10936 def L2_ploadrubtnew_zomap : HInst<
   10937 (outs IntRegs:$Rd32),
   10938 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10939 "if ($Pt4.new) $Rd32 = memub($Rs32)",
   10940 tc_2fc0c436, TypeMAPPING> {
   10941 let hasNewValue = 1;
   10942 let opNewValue = 0;
   10943 let isPseudo = 1;
   10944 let isCodeGenOnly = 1;
   10945 }
   10946 def L2_ploadruhf_io : HInst<
   10947 (outs IntRegs:$Rd32),
   10948 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10949 "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
   10950 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   10951 let Inst{13-13} = 0b0;
   10952 let Inst{31-21} = 0b01000101011;
   10953 let isPredicated = 1;
   10954 let isPredicatedFalse = 1;
   10955 let hasNewValue = 1;
   10956 let opNewValue = 0;
   10957 let addrMode = BaseImmOffset;
   10958 let accessSize = HalfWordAccess;
   10959 let mayLoad = 1;
   10960 let CextOpcode = "L2_loadruh";
   10961 let BaseOpcode = "L2_loadruh_io";
   10962 let isExtendable = 1;
   10963 let opExtendable = 3;
   10964 let isExtentSigned = 0;
   10965 let opExtentBits = 7;
   10966 let opExtentAlign = 1;
   10967 }
   10968 def L2_ploadruhf_pi : HInst<
   10969 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   10970 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   10971 "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
   10972 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
   10973 let Inst{13-11} = 0b101;
   10974 let Inst{31-21} = 0b10011011011;
   10975 let isPredicated = 1;
   10976 let isPredicatedFalse = 1;
   10977 let hasNewValue = 1;
   10978 let opNewValue = 0;
   10979 let addrMode = PostInc;
   10980 let accessSize = HalfWordAccess;
   10981 let mayLoad = 1;
   10982 let BaseOpcode = "L2_loadruh_pi";
   10983 let Constraints = "$Rx32 = $Rx32in";
   10984 }
   10985 def L2_ploadruhf_zomap : HInst<
   10986 (outs IntRegs:$Rd32),
   10987 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   10988 "if (!$Pt4) $Rd32 = memuh($Rs32)",
   10989 tc_ef52ed71, TypeMAPPING> {
   10990 let hasNewValue = 1;
   10991 let opNewValue = 0;
   10992 let isPseudo = 1;
   10993 let isCodeGenOnly = 1;
   10994 }
   10995 def L2_ploadruhfnew_io : HInst<
   10996 (outs IntRegs:$Rd32),
   10997 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   10998 "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
   10999 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   11000 let Inst{13-13} = 0b0;
   11001 let Inst{31-21} = 0b01000111011;
   11002 let isPredicated = 1;
   11003 let isPredicatedFalse = 1;
   11004 let hasNewValue = 1;
   11005 let opNewValue = 0;
   11006 let addrMode = BaseImmOffset;
   11007 let accessSize = HalfWordAccess;
   11008 let isPredicatedNew = 1;
   11009 let mayLoad = 1;
   11010 let CextOpcode = "L2_loadruh";
   11011 let BaseOpcode = "L2_loadruh_io";
   11012 let isExtendable = 1;
   11013 let opExtendable = 3;
   11014 let isExtentSigned = 0;
   11015 let opExtentBits = 7;
   11016 let opExtentAlign = 1;
   11017 }
   11018 def L2_ploadruhfnew_pi : HInst<
   11019 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   11020 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   11021 "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
   11022 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
   11023 let Inst{13-11} = 0b111;
   11024 let Inst{31-21} = 0b10011011011;
   11025 let isPredicated = 1;
   11026 let isPredicatedFalse = 1;
   11027 let hasNewValue = 1;
   11028 let opNewValue = 0;
   11029 let addrMode = PostInc;
   11030 let accessSize = HalfWordAccess;
   11031 let isPredicatedNew = 1;
   11032 let mayLoad = 1;
   11033 let BaseOpcode = "L2_loadruh_pi";
   11034 let Constraints = "$Rx32 = $Rx32in";
   11035 }
   11036 def L2_ploadruhfnew_zomap : HInst<
   11037 (outs IntRegs:$Rd32),
   11038 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   11039 "if (!$Pt4.new) $Rd32 = memuh($Rs32)",
   11040 tc_2fc0c436, TypeMAPPING> {
   11041 let hasNewValue = 1;
   11042 let opNewValue = 0;
   11043 let isPseudo = 1;
   11044 let isCodeGenOnly = 1;
   11045 }
   11046 def L2_ploadruht_io : HInst<
   11047 (outs IntRegs:$Rd32),
   11048 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   11049 "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
   11050 tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   11051 let Inst{13-13} = 0b0;
   11052 let Inst{31-21} = 0b01000001011;
   11053 let isPredicated = 1;
   11054 let hasNewValue = 1;
   11055 let opNewValue = 0;
   11056 let addrMode = BaseImmOffset;
   11057 let accessSize = HalfWordAccess;
   11058 let mayLoad = 1;
   11059 let CextOpcode = "L2_loadruh";
   11060 let BaseOpcode = "L2_loadruh_io";
   11061 let isExtendable = 1;
   11062 let opExtendable = 3;
   11063 let isExtentSigned = 0;
   11064 let opExtentBits = 7;
   11065 let opExtentAlign = 1;
   11066 }
   11067 def L2_ploadruht_pi : HInst<
   11068 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   11069 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   11070 "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
   11071 tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel {
   11072 let Inst{13-11} = 0b100;
   11073 let Inst{31-21} = 0b10011011011;
   11074 let isPredicated = 1;
   11075 let hasNewValue = 1;
   11076 let opNewValue = 0;
   11077 let addrMode = PostInc;
   11078 let accessSize = HalfWordAccess;
   11079 let mayLoad = 1;
   11080 let BaseOpcode = "L2_loadruh_pi";
   11081 let Constraints = "$Rx32 = $Rx32in";
   11082 }
   11083 def L2_ploadruht_zomap : HInst<
   11084 (outs IntRegs:$Rd32),
   11085 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   11086 "if ($Pt4) $Rd32 = memuh($Rs32)",
   11087 tc_ef52ed71, TypeMAPPING> {
   11088 let hasNewValue = 1;
   11089 let opNewValue = 0;
   11090 let isPseudo = 1;
   11091 let isCodeGenOnly = 1;
   11092 }
   11093 def L2_ploadruhtnew_io : HInst<
   11094 (outs IntRegs:$Rd32),
   11095 (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
   11096 "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
   11097 tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel {
   11098 let Inst{13-13} = 0b0;
   11099 let Inst{31-21} = 0b01000011011;
   11100 let isPredicated = 1;
   11101 let hasNewValue = 1;
   11102 let opNewValue = 0;
   11103 let addrMode = BaseImmOffset;
   11104 let accessSize = HalfWordAccess;
   11105 let isPredicatedNew = 1;
   11106 let mayLoad = 1;
   11107 let CextOpcode = "L2_loadruh";
   11108 let BaseOpcode = "L2_loadruh_io";
   11109 let isExtendable = 1;
   11110 let opExtendable = 3;
   11111 let isExtentSigned = 0;
   11112 let opExtentBits = 7;
   11113 let opExtentAlign = 1;
   11114 }
   11115 def L2_ploadruhtnew_pi : HInst<
   11116 (outs IntRegs:$Rd32, IntRegs:$Rx32),
   11117 (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
   11118 "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
   11119 tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel {
   11120 let Inst{13-11} = 0b110;
   11121 let Inst{31-21} = 0b10011011011;
   11122 let isPredicated = 1;
   11123 let hasNewValue = 1;
   11124 let opNewValue = 0;
   11125 let addrMode = PostInc;
   11126 let accessSize = HalfWordAccess;
   11127 let isPredicatedNew = 1;
   11128 let mayLoad = 1;
   11129 let BaseOpcode = "L2_loadruh_pi";
   11130 let Constraints = "$Rx32 = $Rx32in";
   11131 }
   11132 def L2_ploadruhtnew_zomap : HInst<
   11133 (outs IntRegs:$Rd32),
   11134 (ins PredRegs:$Pt4, IntRegs:$Rs32),
   11135 "if ($Pt4.new) $Rd32 = memuh($Rs32)",
   11136 tc_2fc0c436, TypeMAPPING> {
   11137 let hasNewValue = 1;
   11138 let opNewValue = 0;
   11139 let isPseudo = 1;
   11140 let isCodeGenOnly = 1;
   11141 }
   11142 def L4_add_memopb_io : HInst<
   11143 (outs),
   11144 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   11145 "memb($Rs32+#$Ii) += $Rt32",
   11146 tc_44126683, TypeV4LDST>, Enc_d44e31 {
   11147 let Inst{6-5} = 0b00;
   11148 let Inst{13-13} = 0b0;
   11149 let Inst{31-21} = 0b00111110000;
   11150 let addrMode = BaseImmOffset;
   11151 let accessSize = ByteAccess;
   11152 let mayLoad = 1;
   11153 let isRestrictNoSlot1Store = 1;
   11154 let mayStore = 1;
   11155 let isExtendable = 1;
   11156 let opExtendable = 1;
   11157 let isExtentSigned = 0;
   11158 let opExtentBits = 6;
   11159 let opExtentAlign = 0;
   11160 }
   11161 def L4_add_memopb_zomap : HInst<
   11162 (outs),
   11163 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11164 "memb($Rs32) += $Rt32",
   11165 tc_44126683, TypeMAPPING> {
   11166 let isPseudo = 1;
   11167 let isCodeGenOnly = 1;
   11168 }
   11169 def L4_add_memoph_io : HInst<
   11170 (outs),
   11171 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   11172 "memh($Rs32+#$Ii) += $Rt32",
   11173 tc_44126683, TypeV4LDST>, Enc_163a3c {
   11174 let Inst{6-5} = 0b00;
   11175 let Inst{13-13} = 0b0;
   11176 let Inst{31-21} = 0b00111110001;
   11177 let addrMode = BaseImmOffset;
   11178 let accessSize = HalfWordAccess;
   11179 let mayLoad = 1;
   11180 let isRestrictNoSlot1Store = 1;
   11181 let mayStore = 1;
   11182 let isExtendable = 1;
   11183 let opExtendable = 1;
   11184 let isExtentSigned = 0;
   11185 let opExtentBits = 7;
   11186 let opExtentAlign = 1;
   11187 }
   11188 def L4_add_memoph_zomap : HInst<
   11189 (outs),
   11190 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11191 "memh($Rs32) += $Rt32",
   11192 tc_44126683, TypeMAPPING> {
   11193 let isPseudo = 1;
   11194 let isCodeGenOnly = 1;
   11195 }
   11196 def L4_add_memopw_io : HInst<
   11197 (outs),
   11198 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   11199 "memw($Rs32+#$Ii) += $Rt32",
   11200 tc_44126683, TypeV4LDST>, Enc_226535 {
   11201 let Inst{6-5} = 0b00;
   11202 let Inst{13-13} = 0b0;
   11203 let Inst{31-21} = 0b00111110010;
   11204 let addrMode = BaseImmOffset;
   11205 let accessSize = WordAccess;
   11206 let mayLoad = 1;
   11207 let isRestrictNoSlot1Store = 1;
   11208 let mayStore = 1;
   11209 let isExtendable = 1;
   11210 let opExtendable = 1;
   11211 let isExtentSigned = 0;
   11212 let opExtentBits = 8;
   11213 let opExtentAlign = 2;
   11214 }
   11215 def L4_add_memopw_zomap : HInst<
   11216 (outs),
   11217 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11218 "memw($Rs32) += $Rt32",
   11219 tc_44126683, TypeMAPPING> {
   11220 let isPseudo = 1;
   11221 let isCodeGenOnly = 1;
   11222 }
   11223 def L4_and_memopb_io : HInst<
   11224 (outs),
   11225 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   11226 "memb($Rs32+#$Ii) &= $Rt32",
   11227 tc_44126683, TypeV4LDST>, Enc_d44e31 {
   11228 let Inst{6-5} = 0b10;
   11229 let Inst{13-13} = 0b0;
   11230 let Inst{31-21} = 0b00111110000;
   11231 let addrMode = BaseImmOffset;
   11232 let accessSize = ByteAccess;
   11233 let mayLoad = 1;
   11234 let isRestrictNoSlot1Store = 1;
   11235 let mayStore = 1;
   11236 let isExtendable = 1;
   11237 let opExtendable = 1;
   11238 let isExtentSigned = 0;
   11239 let opExtentBits = 6;
   11240 let opExtentAlign = 0;
   11241 }
   11242 def L4_and_memopb_zomap : HInst<
   11243 (outs),
   11244 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11245 "memb($Rs32) &= $Rt32",
   11246 tc_44126683, TypeMAPPING> {
   11247 let isPseudo = 1;
   11248 let isCodeGenOnly = 1;
   11249 }
   11250 def L4_and_memoph_io : HInst<
   11251 (outs),
   11252 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   11253 "memh($Rs32+#$Ii) &= $Rt32",
   11254 tc_44126683, TypeV4LDST>, Enc_163a3c {
   11255 let Inst{6-5} = 0b10;
   11256 let Inst{13-13} = 0b0;
   11257 let Inst{31-21} = 0b00111110001;
   11258 let addrMode = BaseImmOffset;
   11259 let accessSize = HalfWordAccess;
   11260 let mayLoad = 1;
   11261 let isRestrictNoSlot1Store = 1;
   11262 let mayStore = 1;
   11263 let isExtendable = 1;
   11264 let opExtendable = 1;
   11265 let isExtentSigned = 0;
   11266 let opExtentBits = 7;
   11267 let opExtentAlign = 1;
   11268 }
   11269 def L4_and_memoph_zomap : HInst<
   11270 (outs),
   11271 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11272 "memh($Rs32) &= $Rt32",
   11273 tc_44126683, TypeMAPPING> {
   11274 let isPseudo = 1;
   11275 let isCodeGenOnly = 1;
   11276 }
   11277 def L4_and_memopw_io : HInst<
   11278 (outs),
   11279 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   11280 "memw($Rs32+#$Ii) &= $Rt32",
   11281 tc_44126683, TypeV4LDST>, Enc_226535 {
   11282 let Inst{6-5} = 0b10;
   11283 let Inst{13-13} = 0b0;
   11284 let Inst{31-21} = 0b00111110010;
   11285 let addrMode = BaseImmOffset;
   11286 let accessSize = WordAccess;
   11287 let mayLoad = 1;
   11288 let isRestrictNoSlot1Store = 1;
   11289 let mayStore = 1;
   11290 let isExtendable = 1;
   11291 let opExtendable = 1;
   11292 let isExtentSigned = 0;
   11293 let opExtentBits = 8;
   11294 let opExtentAlign = 2;
   11295 }
   11296 def L4_and_memopw_zomap : HInst<
   11297 (outs),
   11298 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   11299 "memw($Rs32) &= $Rt32",
   11300 tc_44126683, TypeMAPPING> {
   11301 let isPseudo = 1;
   11302 let isCodeGenOnly = 1;
   11303 }
   11304 def L4_iadd_memopb_io : HInst<
   11305 (outs),
   11306 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
   11307 "memb($Rs32+#$Ii) += #$II",
   11308 tc_44126683, TypeV4LDST>, Enc_46c951 {
   11309 let Inst{6-5} = 0b00;
   11310 let Inst{13-13} = 0b0;
   11311 let Inst{31-21} = 0b00111111000;
   11312 let addrMode = BaseImmOffset;
   11313 let accessSize = ByteAccess;
   11314 let mayLoad = 1;
   11315 let isRestrictNoSlot1Store = 1;
   11316 let mayStore = 1;
   11317 let isExtendable = 1;
   11318 let opExtendable = 1;
   11319 let isExtentSigned = 0;
   11320 let opExtentBits = 6;
   11321 let opExtentAlign = 0;
   11322 }
   11323 def L4_iadd_memopb_zomap : HInst<
   11324 (outs),
   11325 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11326 "memb($Rs32) += #$II",
   11327 tc_44126683, TypeMAPPING> {
   11328 let isPseudo = 1;
   11329 let isCodeGenOnly = 1;
   11330 }
   11331 def L4_iadd_memoph_io : HInst<
   11332 (outs),
   11333 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
   11334 "memh($Rs32+#$Ii) += #$II",
   11335 tc_44126683, TypeV4LDST>, Enc_e66a97 {
   11336 let Inst{6-5} = 0b00;
   11337 let Inst{13-13} = 0b0;
   11338 let Inst{31-21} = 0b00111111001;
   11339 let addrMode = BaseImmOffset;
   11340 let accessSize = HalfWordAccess;
   11341 let mayLoad = 1;
   11342 let isRestrictNoSlot1Store = 1;
   11343 let mayStore = 1;
   11344 let isExtendable = 1;
   11345 let opExtendable = 1;
   11346 let isExtentSigned = 0;
   11347 let opExtentBits = 7;
   11348 let opExtentAlign = 1;
   11349 }
   11350 def L4_iadd_memoph_zomap : HInst<
   11351 (outs),
   11352 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11353 "memh($Rs32) += #$II",
   11354 tc_44126683, TypeMAPPING> {
   11355 let isPseudo = 1;
   11356 let isCodeGenOnly = 1;
   11357 }
   11358 def L4_iadd_memopw_io : HInst<
   11359 (outs),
   11360 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
   11361 "memw($Rs32+#$Ii) += #$II",
   11362 tc_44126683, TypeV4LDST>, Enc_84b2cd {
   11363 let Inst{6-5} = 0b00;
   11364 let Inst{13-13} = 0b0;
   11365 let Inst{31-21} = 0b00111111010;
   11366 let addrMode = BaseImmOffset;
   11367 let accessSize = WordAccess;
   11368 let mayLoad = 1;
   11369 let isRestrictNoSlot1Store = 1;
   11370 let mayStore = 1;
   11371 let isExtendable = 1;
   11372 let opExtendable = 1;
   11373 let isExtentSigned = 0;
   11374 let opExtentBits = 8;
   11375 let opExtentAlign = 2;
   11376 }
   11377 def L4_iadd_memopw_zomap : HInst<
   11378 (outs),
   11379 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11380 "memw($Rs32) += #$II",
   11381 tc_44126683, TypeMAPPING> {
   11382 let isPseudo = 1;
   11383 let isCodeGenOnly = 1;
   11384 }
   11385 def L4_iand_memopb_io : HInst<
   11386 (outs),
   11387 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
   11388 "memb($Rs32+#$Ii) = clrbit(#$II)",
   11389 tc_44126683, TypeV4LDST>, Enc_46c951 {
   11390 let Inst{6-5} = 0b10;
   11391 let Inst{13-13} = 0b0;
   11392 let Inst{31-21} = 0b00111111000;
   11393 let addrMode = BaseImmOffset;
   11394 let accessSize = ByteAccess;
   11395 let mayLoad = 1;
   11396 let isRestrictNoSlot1Store = 1;
   11397 let mayStore = 1;
   11398 let isExtendable = 1;
   11399 let opExtendable = 1;
   11400 let isExtentSigned = 0;
   11401 let opExtentBits = 6;
   11402 let opExtentAlign = 0;
   11403 }
   11404 def L4_iand_memopb_zomap : HInst<
   11405 (outs),
   11406 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11407 "memb($Rs32) = clrbit(#$II)",
   11408 tc_44126683, TypeMAPPING> {
   11409 let isPseudo = 1;
   11410 let isCodeGenOnly = 1;
   11411 }
   11412 def L4_iand_memoph_io : HInst<
   11413 (outs),
   11414 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
   11415 "memh($Rs32+#$Ii) = clrbit(#$II)",
   11416 tc_44126683, TypeV4LDST>, Enc_e66a97 {
   11417 let Inst{6-5} = 0b10;
   11418 let Inst{13-13} = 0b0;
   11419 let Inst{31-21} = 0b00111111001;
   11420 let addrMode = BaseImmOffset;
   11421 let accessSize = HalfWordAccess;
   11422 let mayLoad = 1;
   11423 let isRestrictNoSlot1Store = 1;
   11424 let mayStore = 1;
   11425 let isExtendable = 1;
   11426 let opExtendable = 1;
   11427 let isExtentSigned = 0;
   11428 let opExtentBits = 7;
   11429 let opExtentAlign = 1;
   11430 }
   11431 def L4_iand_memoph_zomap : HInst<
   11432 (outs),
   11433 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11434 "memh($Rs32) = clrbit(#$II)",
   11435 tc_44126683, TypeMAPPING> {
   11436 let isPseudo = 1;
   11437 let isCodeGenOnly = 1;
   11438 }
   11439 def L4_iand_memopw_io : HInst<
   11440 (outs),
   11441 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
   11442 "memw($Rs32+#$Ii) = clrbit(#$II)",
   11443 tc_44126683, TypeV4LDST>, Enc_84b2cd {
   11444 let Inst{6-5} = 0b10;
   11445 let Inst{13-13} = 0b0;
   11446 let Inst{31-21} = 0b00111111010;
   11447 let addrMode = BaseImmOffset;
   11448 let accessSize = WordAccess;
   11449 let mayLoad = 1;
   11450 let isRestrictNoSlot1Store = 1;
   11451 let mayStore = 1;
   11452 let isExtendable = 1;
   11453 let opExtendable = 1;
   11454 let isExtentSigned = 0;
   11455 let opExtentBits = 8;
   11456 let opExtentAlign = 2;
   11457 }
   11458 def L4_iand_memopw_zomap : HInst<
   11459 (outs),
   11460 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11461 "memw($Rs32) = clrbit(#$II)",
   11462 tc_44126683, TypeMAPPING> {
   11463 let isPseudo = 1;
   11464 let isCodeGenOnly = 1;
   11465 }
   11466 def L4_ior_memopb_io : HInst<
   11467 (outs),
   11468 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
   11469 "memb($Rs32+#$Ii) = setbit(#$II)",
   11470 tc_44126683, TypeV4LDST>, Enc_46c951 {
   11471 let Inst{6-5} = 0b11;
   11472 let Inst{13-13} = 0b0;
   11473 let Inst{31-21} = 0b00111111000;
   11474 let addrMode = BaseImmOffset;
   11475 let accessSize = ByteAccess;
   11476 let mayLoad = 1;
   11477 let isRestrictNoSlot1Store = 1;
   11478 let mayStore = 1;
   11479 let isExtendable = 1;
   11480 let opExtendable = 1;
   11481 let isExtentSigned = 0;
   11482 let opExtentBits = 6;
   11483 let opExtentAlign = 0;
   11484 }
   11485 def L4_ior_memopb_zomap : HInst<
   11486 (outs),
   11487 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11488 "memb($Rs32) = setbit(#$II)",
   11489 tc_44126683, TypeMAPPING> {
   11490 let isPseudo = 1;
   11491 let isCodeGenOnly = 1;
   11492 }
   11493 def L4_ior_memoph_io : HInst<
   11494 (outs),
   11495 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
   11496 "memh($Rs32+#$Ii) = setbit(#$II)",
   11497 tc_44126683, TypeV4LDST>, Enc_e66a97 {
   11498 let Inst{6-5} = 0b11;
   11499 let Inst{13-13} = 0b0;
   11500 let Inst{31-21} = 0b00111111001;
   11501 let addrMode = BaseImmOffset;
   11502 let accessSize = HalfWordAccess;
   11503 let mayLoad = 1;
   11504 let isRestrictNoSlot1Store = 1;
   11505 let mayStore = 1;
   11506 let isExtendable = 1;
   11507 let opExtendable = 1;
   11508 let isExtentSigned = 0;
   11509 let opExtentBits = 7;
   11510 let opExtentAlign = 1;
   11511 }
   11512 def L4_ior_memoph_zomap : HInst<
   11513 (outs),
   11514 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11515 "memh($Rs32) = setbit(#$II)",
   11516 tc_44126683, TypeMAPPING> {
   11517 let isPseudo = 1;
   11518 let isCodeGenOnly = 1;
   11519 }
   11520 def L4_ior_memopw_io : HInst<
   11521 (outs),
   11522 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
   11523 "memw($Rs32+#$Ii) = setbit(#$II)",
   11524 tc_44126683, TypeV4LDST>, Enc_84b2cd {
   11525 let Inst{6-5} = 0b11;
   11526 let Inst{13-13} = 0b0;
   11527 let Inst{31-21} = 0b00111111010;
   11528 let addrMode = BaseImmOffset;
   11529 let accessSize = WordAccess;
   11530 let mayLoad = 1;
   11531 let isRestrictNoSlot1Store = 1;
   11532 let mayStore = 1;
   11533 let isExtendable = 1;
   11534 let opExtendable = 1;
   11535 let isExtentSigned = 0;
   11536 let opExtentBits = 8;
   11537 let opExtentAlign = 2;
   11538 }
   11539 def L4_ior_memopw_zomap : HInst<
   11540 (outs),
   11541 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11542 "memw($Rs32) = setbit(#$II)",
   11543 tc_44126683, TypeMAPPING> {
   11544 let isPseudo = 1;
   11545 let isCodeGenOnly = 1;
   11546 }
   11547 def L4_isub_memopb_io : HInst<
   11548 (outs),
   11549 (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
   11550 "memb($Rs32+#$Ii) -= #$II",
   11551 tc_44126683, TypeV4LDST>, Enc_46c951 {
   11552 let Inst{6-5} = 0b01;
   11553 let Inst{13-13} = 0b0;
   11554 let Inst{31-21} = 0b00111111000;
   11555 let addrMode = BaseImmOffset;
   11556 let accessSize = ByteAccess;
   11557 let mayLoad = 1;
   11558 let isRestrictNoSlot1Store = 1;
   11559 let mayStore = 1;
   11560 let isExtendable = 1;
   11561 let opExtendable = 1;
   11562 let isExtentSigned = 0;
   11563 let opExtentBits = 6;
   11564 let opExtentAlign = 0;
   11565 }
   11566 def L4_isub_memopb_zomap : HInst<
   11567 (outs),
   11568 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11569 "memb($Rs32) -= #$II",
   11570 tc_44126683, TypeMAPPING> {
   11571 let isPseudo = 1;
   11572 let isCodeGenOnly = 1;
   11573 }
   11574 def L4_isub_memoph_io : HInst<
   11575 (outs),
   11576 (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
   11577 "memh($Rs32+#$Ii) -= #$II",
   11578 tc_44126683, TypeV4LDST>, Enc_e66a97 {
   11579 let Inst{6-5} = 0b01;
   11580 let Inst{13-13} = 0b0;
   11581 let Inst{31-21} = 0b00111111001;
   11582 let addrMode = BaseImmOffset;
   11583 let accessSize = HalfWordAccess;
   11584 let mayLoad = 1;
   11585 let isRestrictNoSlot1Store = 1;
   11586 let mayStore = 1;
   11587 let isExtendable = 1;
   11588 let opExtendable = 1;
   11589 let isExtentSigned = 0;
   11590 let opExtentBits = 7;
   11591 let opExtentAlign = 1;
   11592 }
   11593 def L4_isub_memoph_zomap : HInst<
   11594 (outs),
   11595 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11596 "memh($Rs32) -= #$II",
   11597 tc_44126683, TypeMAPPING> {
   11598 let isPseudo = 1;
   11599 let isCodeGenOnly = 1;
   11600 }
   11601 def L4_isub_memopw_io : HInst<
   11602 (outs),
   11603 (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
   11604 "memw($Rs32+#$Ii) -= #$II",
   11605 tc_44126683, TypeV4LDST>, Enc_84b2cd {
   11606 let Inst{6-5} = 0b01;
   11607 let Inst{13-13} = 0b0;
   11608 let Inst{31-21} = 0b00111111010;
   11609 let addrMode = BaseImmOffset;
   11610 let accessSize = WordAccess;
   11611 let mayLoad = 1;
   11612 let isRestrictNoSlot1Store = 1;
   11613 let mayStore = 1;
   11614 let isExtendable = 1;
   11615 let opExtendable = 1;
   11616 let isExtentSigned = 0;
   11617 let opExtentBits = 8;
   11618 let opExtentAlign = 2;
   11619 }
   11620 def L4_isub_memopw_zomap : HInst<
   11621 (outs),
   11622 (ins IntRegs:$Rs32, u5_0Imm:$II),
   11623 "memw($Rs32) -= #$II",
   11624 tc_44126683, TypeMAPPING> {
   11625 let isPseudo = 1;
   11626 let isCodeGenOnly = 1;
   11627 }
   11628 def L4_loadalignb_ap : HInst<
   11629 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
   11630 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
   11631 "$Ryy32 = memb_fifo($Re32=#$II)",
   11632 tc_5acef64a, TypeLD>, Enc_f394d3 {
   11633 let Inst{7-7} = 0b0;
   11634 let Inst{13-12} = 0b01;
   11635 let Inst{31-21} = 0b10011010100;
   11636 let addrMode = AbsoluteSet;
   11637 let accessSize = ByteAccess;
   11638 let mayLoad = 1;
   11639 let isExtended = 1;
   11640 let DecoderNamespace = "MustExtend";
   11641 let isExtendable = 1;
   11642 let opExtendable = 3;
   11643 let isExtentSigned = 0;
   11644 let opExtentBits = 6;
   11645 let opExtentAlign = 0;
   11646 let Constraints = "$Ryy32 = $Ryy32in";
   11647 }
   11648 def L4_loadalignb_ur : HInst<
   11649 (outs DoubleRegs:$Ryy32),
   11650 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11651 "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
   11652 tc_0cd51c76, TypeLD>, Enc_04c959 {
   11653 let Inst{12-12} = 0b1;
   11654 let Inst{31-21} = 0b10011100100;
   11655 let addrMode = BaseLongOffset;
   11656 let accessSize = ByteAccess;
   11657 let mayLoad = 1;
   11658 let isExtended = 1;
   11659 let InputType = "imm";
   11660 let DecoderNamespace = "MustExtend";
   11661 let isExtendable = 1;
   11662 let opExtendable = 4;
   11663 let isExtentSigned = 0;
   11664 let opExtentBits = 6;
   11665 let opExtentAlign = 0;
   11666 let Constraints = "$Ryy32 = $Ryy32in";
   11667 }
   11668 def L4_loadalignh_ap : HInst<
   11669 (outs DoubleRegs:$Ryy32, IntRegs:$Re32),
   11670 (ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
   11671 "$Ryy32 = memh_fifo($Re32=#$II)",
   11672 tc_5acef64a, TypeLD>, Enc_f394d3 {
   11673 let Inst{7-7} = 0b0;
   11674 let Inst{13-12} = 0b01;
   11675 let Inst{31-21} = 0b10011010010;
   11676 let addrMode = AbsoluteSet;
   11677 let accessSize = HalfWordAccess;
   11678 let mayLoad = 1;
   11679 let isExtended = 1;
   11680 let DecoderNamespace = "MustExtend";
   11681 let isExtendable = 1;
   11682 let opExtendable = 3;
   11683 let isExtentSigned = 0;
   11684 let opExtentBits = 6;
   11685 let opExtentAlign = 0;
   11686 let Constraints = "$Ryy32 = $Ryy32in";
   11687 }
   11688 def L4_loadalignh_ur : HInst<
   11689 (outs DoubleRegs:$Ryy32),
   11690 (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11691 "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
   11692 tc_0cd51c76, TypeLD>, Enc_04c959 {
   11693 let Inst{12-12} = 0b1;
   11694 let Inst{31-21} = 0b10011100010;
   11695 let addrMode = BaseLongOffset;
   11696 let accessSize = HalfWordAccess;
   11697 let mayLoad = 1;
   11698 let isExtended = 1;
   11699 let InputType = "imm";
   11700 let DecoderNamespace = "MustExtend";
   11701 let isExtendable = 1;
   11702 let opExtendable = 4;
   11703 let isExtentSigned = 0;
   11704 let opExtentBits = 6;
   11705 let opExtentAlign = 0;
   11706 let Constraints = "$Ryy32 = $Ryy32in";
   11707 }
   11708 def L4_loadbsw2_ap : HInst<
   11709 (outs IntRegs:$Rd32, IntRegs:$Re32),
   11710 (ins u32_0Imm:$II),
   11711 "$Rd32 = membh($Re32=#$II)",
   11712 tc_b77c481f, TypeLD>, Enc_323f2d {
   11713 let Inst{7-7} = 0b0;
   11714 let Inst{13-12} = 0b01;
   11715 let Inst{31-21} = 0b10011010001;
   11716 let hasNewValue = 1;
   11717 let opNewValue = 0;
   11718 let addrMode = AbsoluteSet;
   11719 let accessSize = HalfWordAccess;
   11720 let mayLoad = 1;
   11721 let isExtended = 1;
   11722 let DecoderNamespace = "MustExtend";
   11723 let isExtendable = 1;
   11724 let opExtendable = 2;
   11725 let isExtentSigned = 0;
   11726 let opExtentBits = 6;
   11727 let opExtentAlign = 0;
   11728 }
   11729 def L4_loadbsw2_ur : HInst<
   11730 (outs IntRegs:$Rd32),
   11731 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11732 "$Rd32 = membh($Rt32<<#$Ii+#$II)",
   11733 tc_cf47a43f, TypeLD>, Enc_4f677b {
   11734 let Inst{12-12} = 0b1;
   11735 let Inst{31-21} = 0b10011100001;
   11736 let hasNewValue = 1;
   11737 let opNewValue = 0;
   11738 let addrMode = BaseLongOffset;
   11739 let accessSize = HalfWordAccess;
   11740 let mayLoad = 1;
   11741 let isExtended = 1;
   11742 let InputType = "imm";
   11743 let DecoderNamespace = "MustExtend";
   11744 let isExtendable = 1;
   11745 let opExtendable = 3;
   11746 let isExtentSigned = 0;
   11747 let opExtentBits = 6;
   11748 let opExtentAlign = 0;
   11749 }
   11750 def L4_loadbsw4_ap : HInst<
   11751 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
   11752 (ins u32_0Imm:$II),
   11753 "$Rdd32 = membh($Re32=#$II)",
   11754 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
   11755 let Inst{7-7} = 0b0;
   11756 let Inst{13-12} = 0b01;
   11757 let Inst{31-21} = 0b10011010111;
   11758 let addrMode = AbsoluteSet;
   11759 let accessSize = WordAccess;
   11760 let mayLoad = 1;
   11761 let isExtended = 1;
   11762 let DecoderNamespace = "MustExtend";
   11763 let isExtendable = 1;
   11764 let opExtendable = 2;
   11765 let isExtentSigned = 0;
   11766 let opExtentBits = 6;
   11767 let opExtentAlign = 0;
   11768 }
   11769 def L4_loadbsw4_ur : HInst<
   11770 (outs DoubleRegs:$Rdd32),
   11771 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11772 "$Rdd32 = membh($Rt32<<#$Ii+#$II)",
   11773 tc_cf47a43f, TypeLD>, Enc_6185fe {
   11774 let Inst{12-12} = 0b1;
   11775 let Inst{31-21} = 0b10011100111;
   11776 let addrMode = BaseLongOffset;
   11777 let accessSize = WordAccess;
   11778 let mayLoad = 1;
   11779 let isExtended = 1;
   11780 let InputType = "imm";
   11781 let DecoderNamespace = "MustExtend";
   11782 let isExtendable = 1;
   11783 let opExtendable = 3;
   11784 let isExtentSigned = 0;
   11785 let opExtentBits = 6;
   11786 let opExtentAlign = 0;
   11787 }
   11788 def L4_loadbzw2_ap : HInst<
   11789 (outs IntRegs:$Rd32, IntRegs:$Re32),
   11790 (ins u32_0Imm:$II),
   11791 "$Rd32 = memubh($Re32=#$II)",
   11792 tc_b77c481f, TypeLD>, Enc_323f2d {
   11793 let Inst{7-7} = 0b0;
   11794 let Inst{13-12} = 0b01;
   11795 let Inst{31-21} = 0b10011010011;
   11796 let hasNewValue = 1;
   11797 let opNewValue = 0;
   11798 let addrMode = AbsoluteSet;
   11799 let accessSize = HalfWordAccess;
   11800 let mayLoad = 1;
   11801 let isExtended = 1;
   11802 let DecoderNamespace = "MustExtend";
   11803 let isExtendable = 1;
   11804 let opExtendable = 2;
   11805 let isExtentSigned = 0;
   11806 let opExtentBits = 6;
   11807 let opExtentAlign = 0;
   11808 }
   11809 def L4_loadbzw2_ur : HInst<
   11810 (outs IntRegs:$Rd32),
   11811 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11812 "$Rd32 = memubh($Rt32<<#$Ii+#$II)",
   11813 tc_cf47a43f, TypeLD>, Enc_4f677b {
   11814 let Inst{12-12} = 0b1;
   11815 let Inst{31-21} = 0b10011100011;
   11816 let hasNewValue = 1;
   11817 let opNewValue = 0;
   11818 let addrMode = BaseLongOffset;
   11819 let accessSize = HalfWordAccess;
   11820 let mayLoad = 1;
   11821 let isExtended = 1;
   11822 let InputType = "imm";
   11823 let DecoderNamespace = "MustExtend";
   11824 let isExtendable = 1;
   11825 let opExtendable = 3;
   11826 let isExtentSigned = 0;
   11827 let opExtentBits = 6;
   11828 let opExtentAlign = 0;
   11829 }
   11830 def L4_loadbzw4_ap : HInst<
   11831 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
   11832 (ins u32_0Imm:$II),
   11833 "$Rdd32 = memubh($Re32=#$II)",
   11834 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
   11835 let Inst{7-7} = 0b0;
   11836 let Inst{13-12} = 0b01;
   11837 let Inst{31-21} = 0b10011010101;
   11838 let addrMode = AbsoluteSet;
   11839 let accessSize = WordAccess;
   11840 let mayLoad = 1;
   11841 let isExtended = 1;
   11842 let DecoderNamespace = "MustExtend";
   11843 let isExtendable = 1;
   11844 let opExtendable = 2;
   11845 let isExtentSigned = 0;
   11846 let opExtentBits = 6;
   11847 let opExtentAlign = 0;
   11848 }
   11849 def L4_loadbzw4_ur : HInst<
   11850 (outs DoubleRegs:$Rdd32),
   11851 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11852 "$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
   11853 tc_cf47a43f, TypeLD>, Enc_6185fe {
   11854 let Inst{12-12} = 0b1;
   11855 let Inst{31-21} = 0b10011100101;
   11856 let addrMode = BaseLongOffset;
   11857 let accessSize = WordAccess;
   11858 let mayLoad = 1;
   11859 let isExtended = 1;
   11860 let InputType = "imm";
   11861 let DecoderNamespace = "MustExtend";
   11862 let isExtendable = 1;
   11863 let opExtendable = 3;
   11864 let isExtentSigned = 0;
   11865 let opExtentBits = 6;
   11866 let opExtentAlign = 0;
   11867 }
   11868 def L4_loadd_locked : HInst<
   11869 (outs DoubleRegs:$Rdd32),
   11870 (ins IntRegs:$Rs32),
   11871 "$Rdd32 = memd_locked($Rs32)",
   11872 tc_6aa5711a, TypeLD>, Enc_3a3d62 {
   11873 let Inst{13-5} = 0b010000000;
   11874 let Inst{31-21} = 0b10010010000;
   11875 let accessSize = DoubleWordAccess;
   11876 let mayLoad = 1;
   11877 let isSoloAX = 1;
   11878 }
   11879 def L4_loadrb_ap : HInst<
   11880 (outs IntRegs:$Rd32, IntRegs:$Re32),
   11881 (ins u32_0Imm:$II),
   11882 "$Rd32 = memb($Re32=#$II)",
   11883 tc_b77c481f, TypeLD>, Enc_323f2d {
   11884 let Inst{7-7} = 0b0;
   11885 let Inst{13-12} = 0b01;
   11886 let Inst{31-21} = 0b10011011000;
   11887 let hasNewValue = 1;
   11888 let opNewValue = 0;
   11889 let addrMode = AbsoluteSet;
   11890 let accessSize = ByteAccess;
   11891 let mayLoad = 1;
   11892 let isExtended = 1;
   11893 let DecoderNamespace = "MustExtend";
   11894 let isExtendable = 1;
   11895 let opExtendable = 2;
   11896 let isExtentSigned = 0;
   11897 let opExtentBits = 6;
   11898 let opExtentAlign = 0;
   11899 }
   11900 def L4_loadrb_rr : HInst<
   11901 (outs IntRegs:$Rd32),
   11902 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   11903 "$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
   11904 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
   11905 let Inst{6-5} = 0b00;
   11906 let Inst{31-21} = 0b00111010000;
   11907 let hasNewValue = 1;
   11908 let opNewValue = 0;
   11909 let addrMode = BaseRegOffset;
   11910 let accessSize = ByteAccess;
   11911 let mayLoad = 1;
   11912 let CextOpcode = "L2_loadrb";
   11913 let InputType = "reg";
   11914 let BaseOpcode = "L4_loadrb_rr";
   11915 let isPredicable = 1;
   11916 }
   11917 def L4_loadrb_ur : HInst<
   11918 (outs IntRegs:$Rd32),
   11919 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11920 "$Rd32 = memb($Rt32<<#$Ii+#$II)",
   11921 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
   11922 let Inst{12-12} = 0b1;
   11923 let Inst{31-21} = 0b10011101000;
   11924 let hasNewValue = 1;
   11925 let opNewValue = 0;
   11926 let addrMode = BaseLongOffset;
   11927 let accessSize = ByteAccess;
   11928 let mayLoad = 1;
   11929 let isExtended = 1;
   11930 let CextOpcode = "L2_loadrb";
   11931 let InputType = "imm";
   11932 let DecoderNamespace = "MustExtend";
   11933 let isExtendable = 1;
   11934 let opExtendable = 3;
   11935 let isExtentSigned = 0;
   11936 let opExtentBits = 6;
   11937 let opExtentAlign = 0;
   11938 }
   11939 def L4_loadrd_ap : HInst<
   11940 (outs DoubleRegs:$Rdd32, IntRegs:$Re32),
   11941 (ins u32_0Imm:$II),
   11942 "$Rdd32 = memd($Re32=#$II)",
   11943 tc_b77c481f, TypeLD>, Enc_7fa7f6 {
   11944 let Inst{7-7} = 0b0;
   11945 let Inst{13-12} = 0b01;
   11946 let Inst{31-21} = 0b10011011110;
   11947 let addrMode = AbsoluteSet;
   11948 let accessSize = DoubleWordAccess;
   11949 let mayLoad = 1;
   11950 let isExtended = 1;
   11951 let DecoderNamespace = "MustExtend";
   11952 let isExtendable = 1;
   11953 let opExtendable = 2;
   11954 let isExtentSigned = 0;
   11955 let opExtentBits = 6;
   11956 let opExtentAlign = 0;
   11957 }
   11958 def L4_loadrd_rr : HInst<
   11959 (outs DoubleRegs:$Rdd32),
   11960 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   11961 "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
   11962 tc_f47d212f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
   11963 let Inst{6-5} = 0b00;
   11964 let Inst{31-21} = 0b00111010110;
   11965 let addrMode = BaseRegOffset;
   11966 let accessSize = DoubleWordAccess;
   11967 let mayLoad = 1;
   11968 let CextOpcode = "L2_loadrd";
   11969 let InputType = "reg";
   11970 let BaseOpcode = "L4_loadrd_rr";
   11971 let isPredicable = 1;
   11972 }
   11973 def L4_loadrd_ur : HInst<
   11974 (outs DoubleRegs:$Rdd32),
   11975 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   11976 "$Rdd32 = memd($Rt32<<#$Ii+#$II)",
   11977 tc_cf47a43f, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
   11978 let Inst{12-12} = 0b1;
   11979 let Inst{31-21} = 0b10011101110;
   11980 let addrMode = BaseLongOffset;
   11981 let accessSize = DoubleWordAccess;
   11982 let mayLoad = 1;
   11983 let isExtended = 1;
   11984 let CextOpcode = "L2_loadrd";
   11985 let InputType = "imm";
   11986 let DecoderNamespace = "MustExtend";
   11987 let isExtendable = 1;
   11988 let opExtendable = 3;
   11989 let isExtentSigned = 0;
   11990 let opExtentBits = 6;
   11991 let opExtentAlign = 0;
   11992 }
   11993 def L4_loadrh_ap : HInst<
   11994 (outs IntRegs:$Rd32, IntRegs:$Re32),
   11995 (ins u32_0Imm:$II),
   11996 "$Rd32 = memh($Re32=#$II)",
   11997 tc_b77c481f, TypeLD>, Enc_323f2d {
   11998 let Inst{7-7} = 0b0;
   11999 let Inst{13-12} = 0b01;
   12000 let Inst{31-21} = 0b10011011010;
   12001 let hasNewValue = 1;
   12002 let opNewValue = 0;
   12003 let addrMode = AbsoluteSet;
   12004 let accessSize = HalfWordAccess;
   12005 let mayLoad = 1;
   12006 let isExtended = 1;
   12007 let DecoderNamespace = "MustExtend";
   12008 let isExtendable = 1;
   12009 let opExtendable = 2;
   12010 let isExtentSigned = 0;
   12011 let opExtentBits = 6;
   12012 let opExtentAlign = 0;
   12013 }
   12014 def L4_loadrh_rr : HInst<
   12015 (outs IntRegs:$Rd32),
   12016 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12017 "$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
   12018 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
   12019 let Inst{6-5} = 0b00;
   12020 let Inst{31-21} = 0b00111010010;
   12021 let hasNewValue = 1;
   12022 let opNewValue = 0;
   12023 let addrMode = BaseRegOffset;
   12024 let accessSize = HalfWordAccess;
   12025 let mayLoad = 1;
   12026 let CextOpcode = "L2_loadrh";
   12027 let InputType = "reg";
   12028 let BaseOpcode = "L4_loadrh_rr";
   12029 let isPredicable = 1;
   12030 }
   12031 def L4_loadrh_ur : HInst<
   12032 (outs IntRegs:$Rd32),
   12033 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   12034 "$Rd32 = memh($Rt32<<#$Ii+#$II)",
   12035 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
   12036 let Inst{12-12} = 0b1;
   12037 let Inst{31-21} = 0b10011101010;
   12038 let hasNewValue = 1;
   12039 let opNewValue = 0;
   12040 let addrMode = BaseLongOffset;
   12041 let accessSize = HalfWordAccess;
   12042 let mayLoad = 1;
   12043 let isExtended = 1;
   12044 let CextOpcode = "L2_loadrh";
   12045 let InputType = "imm";
   12046 let DecoderNamespace = "MustExtend";
   12047 let isExtendable = 1;
   12048 let opExtendable = 3;
   12049 let isExtentSigned = 0;
   12050 let opExtentBits = 6;
   12051 let opExtentAlign = 0;
   12052 }
   12053 def L4_loadri_ap : HInst<
   12054 (outs IntRegs:$Rd32, IntRegs:$Re32),
   12055 (ins u32_0Imm:$II),
   12056 "$Rd32 = memw($Re32=#$II)",
   12057 tc_b77c481f, TypeLD>, Enc_323f2d {
   12058 let Inst{7-7} = 0b0;
   12059 let Inst{13-12} = 0b01;
   12060 let Inst{31-21} = 0b10011011100;
   12061 let hasNewValue = 1;
   12062 let opNewValue = 0;
   12063 let addrMode = AbsoluteSet;
   12064 let accessSize = WordAccess;
   12065 let mayLoad = 1;
   12066 let isExtended = 1;
   12067 let DecoderNamespace = "MustExtend";
   12068 let isExtendable = 1;
   12069 let opExtendable = 2;
   12070 let isExtentSigned = 0;
   12071 let opExtentBits = 6;
   12072 let opExtentAlign = 0;
   12073 }
   12074 def L4_loadri_rr : HInst<
   12075 (outs IntRegs:$Rd32),
   12076 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12077 "$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
   12078 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
   12079 let Inst{6-5} = 0b00;
   12080 let Inst{31-21} = 0b00111010100;
   12081 let hasNewValue = 1;
   12082 let opNewValue = 0;
   12083 let addrMode = BaseRegOffset;
   12084 let accessSize = WordAccess;
   12085 let mayLoad = 1;
   12086 let CextOpcode = "L2_loadri";
   12087 let InputType = "reg";
   12088 let BaseOpcode = "L4_loadri_rr";
   12089 let isPredicable = 1;
   12090 }
   12091 def L4_loadri_ur : HInst<
   12092 (outs IntRegs:$Rd32),
   12093 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   12094 "$Rd32 = memw($Rt32<<#$Ii+#$II)",
   12095 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
   12096 let Inst{12-12} = 0b1;
   12097 let Inst{31-21} = 0b10011101100;
   12098 let hasNewValue = 1;
   12099 let opNewValue = 0;
   12100 let addrMode = BaseLongOffset;
   12101 let accessSize = WordAccess;
   12102 let mayLoad = 1;
   12103 let isExtended = 1;
   12104 let CextOpcode = "L2_loadri";
   12105 let InputType = "imm";
   12106 let DecoderNamespace = "MustExtend";
   12107 let isExtendable = 1;
   12108 let opExtendable = 3;
   12109 let isExtentSigned = 0;
   12110 let opExtentBits = 6;
   12111 let opExtentAlign = 0;
   12112 }
   12113 def L4_loadrub_ap : HInst<
   12114 (outs IntRegs:$Rd32, IntRegs:$Re32),
   12115 (ins u32_0Imm:$II),
   12116 "$Rd32 = memub($Re32=#$II)",
   12117 tc_b77c481f, TypeLD>, Enc_323f2d {
   12118 let Inst{7-7} = 0b0;
   12119 let Inst{13-12} = 0b01;
   12120 let Inst{31-21} = 0b10011011001;
   12121 let hasNewValue = 1;
   12122 let opNewValue = 0;
   12123 let addrMode = AbsoluteSet;
   12124 let accessSize = ByteAccess;
   12125 let mayLoad = 1;
   12126 let isExtended = 1;
   12127 let DecoderNamespace = "MustExtend";
   12128 let isExtendable = 1;
   12129 let opExtendable = 2;
   12130 let isExtentSigned = 0;
   12131 let opExtentBits = 6;
   12132 let opExtentAlign = 0;
   12133 }
   12134 def L4_loadrub_rr : HInst<
   12135 (outs IntRegs:$Rd32),
   12136 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12137 "$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
   12138 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
   12139 let Inst{6-5} = 0b00;
   12140 let Inst{31-21} = 0b00111010001;
   12141 let hasNewValue = 1;
   12142 let opNewValue = 0;
   12143 let addrMode = BaseRegOffset;
   12144 let accessSize = ByteAccess;
   12145 let mayLoad = 1;
   12146 let CextOpcode = "L2_loadrub";
   12147 let InputType = "reg";
   12148 let BaseOpcode = "L4_loadrub_rr";
   12149 let isPredicable = 1;
   12150 }
   12151 def L4_loadrub_ur : HInst<
   12152 (outs IntRegs:$Rd32),
   12153 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   12154 "$Rd32 = memub($Rt32<<#$Ii+#$II)",
   12155 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
   12156 let Inst{12-12} = 0b1;
   12157 let Inst{31-21} = 0b10011101001;
   12158 let hasNewValue = 1;
   12159 let opNewValue = 0;
   12160 let addrMode = BaseLongOffset;
   12161 let accessSize = ByteAccess;
   12162 let mayLoad = 1;
   12163 let isExtended = 1;
   12164 let CextOpcode = "L2_loadrub";
   12165 let InputType = "imm";
   12166 let DecoderNamespace = "MustExtend";
   12167 let isExtendable = 1;
   12168 let opExtendable = 3;
   12169 let isExtentSigned = 0;
   12170 let opExtentBits = 6;
   12171 let opExtentAlign = 0;
   12172 }
   12173 def L4_loadruh_ap : HInst<
   12174 (outs IntRegs:$Rd32, IntRegs:$Re32),
   12175 (ins u32_0Imm:$II),
   12176 "$Rd32 = memuh($Re32=#$II)",
   12177 tc_b77c481f, TypeLD>, Enc_323f2d {
   12178 let Inst{7-7} = 0b0;
   12179 let Inst{13-12} = 0b01;
   12180 let Inst{31-21} = 0b10011011011;
   12181 let hasNewValue = 1;
   12182 let opNewValue = 0;
   12183 let addrMode = AbsoluteSet;
   12184 let accessSize = HalfWordAccess;
   12185 let mayLoad = 1;
   12186 let isExtended = 1;
   12187 let DecoderNamespace = "MustExtend";
   12188 let isExtendable = 1;
   12189 let opExtendable = 2;
   12190 let isExtentSigned = 0;
   12191 let opExtentBits = 6;
   12192 let opExtentAlign = 0;
   12193 }
   12194 def L4_loadruh_rr : HInst<
   12195 (outs IntRegs:$Rd32),
   12196 (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12197 "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
   12198 tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
   12199 let Inst{6-5} = 0b00;
   12200 let Inst{31-21} = 0b00111010011;
   12201 let hasNewValue = 1;
   12202 let opNewValue = 0;
   12203 let addrMode = BaseRegOffset;
   12204 let accessSize = HalfWordAccess;
   12205 let mayLoad = 1;
   12206 let CextOpcode = "L2_loadruh";
   12207 let InputType = "reg";
   12208 let BaseOpcode = "L4_loadruh_rr";
   12209 let isPredicable = 1;
   12210 }
   12211 def L4_loadruh_ur : HInst<
   12212 (outs IntRegs:$Rd32),
   12213 (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
   12214 "$Rd32 = memuh($Rt32<<#$Ii+#$II)",
   12215 tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
   12216 let Inst{12-12} = 0b1;
   12217 let Inst{31-21} = 0b10011101011;
   12218 let hasNewValue = 1;
   12219 let opNewValue = 0;
   12220 let addrMode = BaseLongOffset;
   12221 let accessSize = HalfWordAccess;
   12222 let mayLoad = 1;
   12223 let isExtended = 1;
   12224 let CextOpcode = "L2_loadruh";
   12225 let InputType = "imm";
   12226 let DecoderNamespace = "MustExtend";
   12227 let isExtendable = 1;
   12228 let opExtendable = 3;
   12229 let isExtentSigned = 0;
   12230 let opExtentBits = 6;
   12231 let opExtentAlign = 0;
   12232 }
   12233 def L4_or_memopb_io : HInst<
   12234 (outs),
   12235 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   12236 "memb($Rs32+#$Ii) |= $Rt32",
   12237 tc_44126683, TypeV4LDST>, Enc_d44e31 {
   12238 let Inst{6-5} = 0b11;
   12239 let Inst{13-13} = 0b0;
   12240 let Inst{31-21} = 0b00111110000;
   12241 let addrMode = BaseImmOffset;
   12242 let accessSize = ByteAccess;
   12243 let mayLoad = 1;
   12244 let isRestrictNoSlot1Store = 1;
   12245 let mayStore = 1;
   12246 let isExtendable = 1;
   12247 let opExtendable = 1;
   12248 let isExtentSigned = 0;
   12249 let opExtentBits = 6;
   12250 let opExtentAlign = 0;
   12251 }
   12252 def L4_or_memopb_zomap : HInst<
   12253 (outs),
   12254 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   12255 "memb($Rs32) |= $Rt32",
   12256 tc_44126683, TypeMAPPING> {
   12257 let isPseudo = 1;
   12258 let isCodeGenOnly = 1;
   12259 }
   12260 def L4_or_memoph_io : HInst<
   12261 (outs),
   12262 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   12263 "memh($Rs32+#$Ii) |= $Rt32",
   12264 tc_44126683, TypeV4LDST>, Enc_163a3c {
   12265 let Inst{6-5} = 0b11;
   12266 let Inst{13-13} = 0b0;
   12267 let Inst{31-21} = 0b00111110001;
   12268 let addrMode = BaseImmOffset;
   12269 let accessSize = HalfWordAccess;
   12270 let mayLoad = 1;
   12271 let isRestrictNoSlot1Store = 1;
   12272 let mayStore = 1;
   12273 let isExtendable = 1;
   12274 let opExtendable = 1;
   12275 let isExtentSigned = 0;
   12276 let opExtentBits = 7;
   12277 let opExtentAlign = 1;
   12278 }
   12279 def L4_or_memoph_zomap : HInst<
   12280 (outs),
   12281 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   12282 "memh($Rs32) |= $Rt32",
   12283 tc_44126683, TypeMAPPING> {
   12284 let isPseudo = 1;
   12285 let isCodeGenOnly = 1;
   12286 }
   12287 def L4_or_memopw_io : HInst<
   12288 (outs),
   12289 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   12290 "memw($Rs32+#$Ii) |= $Rt32",
   12291 tc_44126683, TypeV4LDST>, Enc_226535 {
   12292 let Inst{6-5} = 0b11;
   12293 let Inst{13-13} = 0b0;
   12294 let Inst{31-21} = 0b00111110010;
   12295 let addrMode = BaseImmOffset;
   12296 let accessSize = WordAccess;
   12297 let mayLoad = 1;
   12298 let isRestrictNoSlot1Store = 1;
   12299 let mayStore = 1;
   12300 let isExtendable = 1;
   12301 let opExtendable = 1;
   12302 let isExtentSigned = 0;
   12303 let opExtentBits = 8;
   12304 let opExtentAlign = 2;
   12305 }
   12306 def L4_or_memopw_zomap : HInst<
   12307 (outs),
   12308 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   12309 "memw($Rs32) |= $Rt32",
   12310 tc_44126683, TypeMAPPING> {
   12311 let isPseudo = 1;
   12312 let isCodeGenOnly = 1;
   12313 }
   12314 def L4_ploadrbf_abs : HInst<
   12315 (outs IntRegs:$Rd32),
   12316 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12317 "if (!$Pt4) $Rd32 = memb(#$Ii)",
   12318 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12319 let Inst{7-5} = 0b100;
   12320 let Inst{13-11} = 0b101;
   12321 let Inst{31-21} = 0b10011111000;
   12322 let isPredicated = 1;
   12323 let isPredicatedFalse = 1;
   12324 let hasNewValue = 1;
   12325 let opNewValue = 0;
   12326 let addrMode = Absolute;
   12327 let accessSize = ByteAccess;
   12328 let mayLoad = 1;
   12329 let isExtended = 1;
   12330 let CextOpcode = "L2_loadrb";
   12331 let BaseOpcode = "L4_loadrb_abs";
   12332 let DecoderNamespace = "MustExtend";
   12333 let isExtendable = 1;
   12334 let opExtendable = 2;
   12335 let isExtentSigned = 0;
   12336 let opExtentBits = 6;
   12337 let opExtentAlign = 0;
   12338 }
   12339 def L4_ploadrbf_rr : HInst<
   12340 (outs IntRegs:$Rd32),
   12341 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12342 "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
   12343 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12344 let Inst{31-21} = 0b00110001000;
   12345 let isPredicated = 1;
   12346 let isPredicatedFalse = 1;
   12347 let hasNewValue = 1;
   12348 let opNewValue = 0;
   12349 let addrMode = BaseRegOffset;
   12350 let accessSize = ByteAccess;
   12351 let mayLoad = 1;
   12352 let CextOpcode = "L2_loadrb";
   12353 let InputType = "reg";
   12354 let BaseOpcode = "L4_loadrb_rr";
   12355 }
   12356 def L4_ploadrbfnew_abs : HInst<
   12357 (outs IntRegs:$Rd32),
   12358 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12359 "if (!$Pt4.new) $Rd32 = memb(#$Ii)",
   12360 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12361 let Inst{7-5} = 0b100;
   12362 let Inst{13-11} = 0b111;
   12363 let Inst{31-21} = 0b10011111000;
   12364 let isPredicated = 1;
   12365 let isPredicatedFalse = 1;
   12366 let hasNewValue = 1;
   12367 let opNewValue = 0;
   12368 let addrMode = Absolute;
   12369 let accessSize = ByteAccess;
   12370 let isPredicatedNew = 1;
   12371 let mayLoad = 1;
   12372 let isExtended = 1;
   12373 let CextOpcode = "L2_loadrb";
   12374 let BaseOpcode = "L4_loadrb_abs";
   12375 let DecoderNamespace = "MustExtend";
   12376 let isExtendable = 1;
   12377 let opExtendable = 2;
   12378 let isExtentSigned = 0;
   12379 let opExtentBits = 6;
   12380 let opExtentAlign = 0;
   12381 }
   12382 def L4_ploadrbfnew_rr : HInst<
   12383 (outs IntRegs:$Rd32),
   12384 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12385 "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
   12386 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12387 let Inst{31-21} = 0b00110011000;
   12388 let isPredicated = 1;
   12389 let isPredicatedFalse = 1;
   12390 let hasNewValue = 1;
   12391 let opNewValue = 0;
   12392 let addrMode = BaseRegOffset;
   12393 let accessSize = ByteAccess;
   12394 let isPredicatedNew = 1;
   12395 let mayLoad = 1;
   12396 let CextOpcode = "L2_loadrb";
   12397 let InputType = "reg";
   12398 let BaseOpcode = "L4_loadrb_rr";
   12399 }
   12400 def L4_ploadrbt_abs : HInst<
   12401 (outs IntRegs:$Rd32),
   12402 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12403 "if ($Pt4) $Rd32 = memb(#$Ii)",
   12404 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12405 let Inst{7-5} = 0b100;
   12406 let Inst{13-11} = 0b100;
   12407 let Inst{31-21} = 0b10011111000;
   12408 let isPredicated = 1;
   12409 let hasNewValue = 1;
   12410 let opNewValue = 0;
   12411 let addrMode = Absolute;
   12412 let accessSize = ByteAccess;
   12413 let mayLoad = 1;
   12414 let isExtended = 1;
   12415 let CextOpcode = "L2_loadrb";
   12416 let BaseOpcode = "L4_loadrb_abs";
   12417 let DecoderNamespace = "MustExtend";
   12418 let isExtendable = 1;
   12419 let opExtendable = 2;
   12420 let isExtentSigned = 0;
   12421 let opExtentBits = 6;
   12422 let opExtentAlign = 0;
   12423 }
   12424 def L4_ploadrbt_rr : HInst<
   12425 (outs IntRegs:$Rd32),
   12426 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12427 "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
   12428 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12429 let Inst{31-21} = 0b00110000000;
   12430 let isPredicated = 1;
   12431 let hasNewValue = 1;
   12432 let opNewValue = 0;
   12433 let addrMode = BaseRegOffset;
   12434 let accessSize = ByteAccess;
   12435 let mayLoad = 1;
   12436 let CextOpcode = "L2_loadrb";
   12437 let InputType = "reg";
   12438 let BaseOpcode = "L4_loadrb_rr";
   12439 }
   12440 def L4_ploadrbtnew_abs : HInst<
   12441 (outs IntRegs:$Rd32),
   12442 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12443 "if ($Pt4.new) $Rd32 = memb(#$Ii)",
   12444 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12445 let Inst{7-5} = 0b100;
   12446 let Inst{13-11} = 0b110;
   12447 let Inst{31-21} = 0b10011111000;
   12448 let isPredicated = 1;
   12449 let hasNewValue = 1;
   12450 let opNewValue = 0;
   12451 let addrMode = Absolute;
   12452 let accessSize = ByteAccess;
   12453 let isPredicatedNew = 1;
   12454 let mayLoad = 1;
   12455 let isExtended = 1;
   12456 let CextOpcode = "L2_loadrb";
   12457 let BaseOpcode = "L4_loadrb_abs";
   12458 let DecoderNamespace = "MustExtend";
   12459 let isExtendable = 1;
   12460 let opExtendable = 2;
   12461 let isExtentSigned = 0;
   12462 let opExtentBits = 6;
   12463 let opExtentAlign = 0;
   12464 }
   12465 def L4_ploadrbtnew_rr : HInst<
   12466 (outs IntRegs:$Rd32),
   12467 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12468 "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
   12469 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12470 let Inst{31-21} = 0b00110010000;
   12471 let isPredicated = 1;
   12472 let hasNewValue = 1;
   12473 let opNewValue = 0;
   12474 let addrMode = BaseRegOffset;
   12475 let accessSize = ByteAccess;
   12476 let isPredicatedNew = 1;
   12477 let mayLoad = 1;
   12478 let CextOpcode = "L2_loadrb";
   12479 let InputType = "reg";
   12480 let BaseOpcode = "L4_loadrb_rr";
   12481 }
   12482 def L4_ploadrdf_abs : HInst<
   12483 (outs DoubleRegs:$Rdd32),
   12484 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12485 "if (!$Pt4) $Rdd32 = memd(#$Ii)",
   12486 tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
   12487 let Inst{7-5} = 0b100;
   12488 let Inst{13-11} = 0b101;
   12489 let Inst{31-21} = 0b10011111110;
   12490 let isPredicated = 1;
   12491 let isPredicatedFalse = 1;
   12492 let addrMode = Absolute;
   12493 let accessSize = DoubleWordAccess;
   12494 let mayLoad = 1;
   12495 let isExtended = 1;
   12496 let CextOpcode = "L2_loadrd";
   12497 let BaseOpcode = "L4_loadrd_abs";
   12498 let DecoderNamespace = "MustExtend";
   12499 let isExtendable = 1;
   12500 let opExtendable = 2;
   12501 let isExtentSigned = 0;
   12502 let opExtentBits = 6;
   12503 let opExtentAlign = 0;
   12504 }
   12505 def L4_ploadrdf_rr : HInst<
   12506 (outs DoubleRegs:$Rdd32),
   12507 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12508 "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
   12509 tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
   12510 let Inst{31-21} = 0b00110001110;
   12511 let isPredicated = 1;
   12512 let isPredicatedFalse = 1;
   12513 let addrMode = BaseRegOffset;
   12514 let accessSize = DoubleWordAccess;
   12515 let mayLoad = 1;
   12516 let CextOpcode = "L2_loadrd";
   12517 let InputType = "reg";
   12518 let BaseOpcode = "L4_loadrd_rr";
   12519 }
   12520 def L4_ploadrdfnew_abs : HInst<
   12521 (outs DoubleRegs:$Rdd32),
   12522 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12523 "if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
   12524 tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
   12525 let Inst{7-5} = 0b100;
   12526 let Inst{13-11} = 0b111;
   12527 let Inst{31-21} = 0b10011111110;
   12528 let isPredicated = 1;
   12529 let isPredicatedFalse = 1;
   12530 let addrMode = Absolute;
   12531 let accessSize = DoubleWordAccess;
   12532 let isPredicatedNew = 1;
   12533 let mayLoad = 1;
   12534 let isExtended = 1;
   12535 let CextOpcode = "L2_loadrd";
   12536 let BaseOpcode = "L4_loadrd_abs";
   12537 let DecoderNamespace = "MustExtend";
   12538 let isExtendable = 1;
   12539 let opExtendable = 2;
   12540 let isExtentSigned = 0;
   12541 let opExtentBits = 6;
   12542 let opExtentAlign = 0;
   12543 }
   12544 def L4_ploadrdfnew_rr : HInst<
   12545 (outs DoubleRegs:$Rdd32),
   12546 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12547 "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
   12548 tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
   12549 let Inst{31-21} = 0b00110011110;
   12550 let isPredicated = 1;
   12551 let isPredicatedFalse = 1;
   12552 let addrMode = BaseRegOffset;
   12553 let accessSize = DoubleWordAccess;
   12554 let isPredicatedNew = 1;
   12555 let mayLoad = 1;
   12556 let CextOpcode = "L2_loadrd";
   12557 let InputType = "reg";
   12558 let BaseOpcode = "L4_loadrd_rr";
   12559 }
   12560 def L4_ploadrdt_abs : HInst<
   12561 (outs DoubleRegs:$Rdd32),
   12562 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12563 "if ($Pt4) $Rdd32 = memd(#$Ii)",
   12564 tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel {
   12565 let Inst{7-5} = 0b100;
   12566 let Inst{13-11} = 0b100;
   12567 let Inst{31-21} = 0b10011111110;
   12568 let isPredicated = 1;
   12569 let addrMode = Absolute;
   12570 let accessSize = DoubleWordAccess;
   12571 let mayLoad = 1;
   12572 let isExtended = 1;
   12573 let CextOpcode = "L2_loadrd";
   12574 let BaseOpcode = "L4_loadrd_abs";
   12575 let DecoderNamespace = "MustExtend";
   12576 let isExtendable = 1;
   12577 let opExtendable = 2;
   12578 let isExtentSigned = 0;
   12579 let opExtentBits = 6;
   12580 let opExtentAlign = 0;
   12581 }
   12582 def L4_ploadrdt_rr : HInst<
   12583 (outs DoubleRegs:$Rdd32),
   12584 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12585 "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
   12586 tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel {
   12587 let Inst{31-21} = 0b00110000110;
   12588 let isPredicated = 1;
   12589 let addrMode = BaseRegOffset;
   12590 let accessSize = DoubleWordAccess;
   12591 let mayLoad = 1;
   12592 let CextOpcode = "L2_loadrd";
   12593 let InputType = "reg";
   12594 let BaseOpcode = "L4_loadrd_rr";
   12595 }
   12596 def L4_ploadrdtnew_abs : HInst<
   12597 (outs DoubleRegs:$Rdd32),
   12598 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12599 "if ($Pt4.new) $Rdd32 = memd(#$Ii)",
   12600 tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel {
   12601 let Inst{7-5} = 0b100;
   12602 let Inst{13-11} = 0b110;
   12603 let Inst{31-21} = 0b10011111110;
   12604 let isPredicated = 1;
   12605 let addrMode = Absolute;
   12606 let accessSize = DoubleWordAccess;
   12607 let isPredicatedNew = 1;
   12608 let mayLoad = 1;
   12609 let isExtended = 1;
   12610 let CextOpcode = "L2_loadrd";
   12611 let BaseOpcode = "L4_loadrd_abs";
   12612 let DecoderNamespace = "MustExtend";
   12613 let isExtendable = 1;
   12614 let opExtendable = 2;
   12615 let isExtentSigned = 0;
   12616 let opExtentBits = 6;
   12617 let opExtentAlign = 0;
   12618 }
   12619 def L4_ploadrdtnew_rr : HInst<
   12620 (outs DoubleRegs:$Rdd32),
   12621 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12622 "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
   12623 tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel {
   12624 let Inst{31-21} = 0b00110010110;
   12625 let isPredicated = 1;
   12626 let addrMode = BaseRegOffset;
   12627 let accessSize = DoubleWordAccess;
   12628 let isPredicatedNew = 1;
   12629 let mayLoad = 1;
   12630 let CextOpcode = "L2_loadrd";
   12631 let InputType = "reg";
   12632 let BaseOpcode = "L4_loadrd_rr";
   12633 }
   12634 def L4_ploadrhf_abs : HInst<
   12635 (outs IntRegs:$Rd32),
   12636 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12637 "if (!$Pt4) $Rd32 = memh(#$Ii)",
   12638 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12639 let Inst{7-5} = 0b100;
   12640 let Inst{13-11} = 0b101;
   12641 let Inst{31-21} = 0b10011111010;
   12642 let isPredicated = 1;
   12643 let isPredicatedFalse = 1;
   12644 let hasNewValue = 1;
   12645 let opNewValue = 0;
   12646 let addrMode = Absolute;
   12647 let accessSize = HalfWordAccess;
   12648 let mayLoad = 1;
   12649 let isExtended = 1;
   12650 let CextOpcode = "L2_loadrh";
   12651 let BaseOpcode = "L4_loadrh_abs";
   12652 let DecoderNamespace = "MustExtend";
   12653 let isExtendable = 1;
   12654 let opExtendable = 2;
   12655 let isExtentSigned = 0;
   12656 let opExtentBits = 6;
   12657 let opExtentAlign = 0;
   12658 }
   12659 def L4_ploadrhf_rr : HInst<
   12660 (outs IntRegs:$Rd32),
   12661 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12662 "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
   12663 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12664 let Inst{31-21} = 0b00110001010;
   12665 let isPredicated = 1;
   12666 let isPredicatedFalse = 1;
   12667 let hasNewValue = 1;
   12668 let opNewValue = 0;
   12669 let addrMode = BaseRegOffset;
   12670 let accessSize = HalfWordAccess;
   12671 let mayLoad = 1;
   12672 let CextOpcode = "L2_loadrh";
   12673 let InputType = "reg";
   12674 let BaseOpcode = "L4_loadrh_rr";
   12675 }
   12676 def L4_ploadrhfnew_abs : HInst<
   12677 (outs IntRegs:$Rd32),
   12678 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12679 "if (!$Pt4.new) $Rd32 = memh(#$Ii)",
   12680 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12681 let Inst{7-5} = 0b100;
   12682 let Inst{13-11} = 0b111;
   12683 let Inst{31-21} = 0b10011111010;
   12684 let isPredicated = 1;
   12685 let isPredicatedFalse = 1;
   12686 let hasNewValue = 1;
   12687 let opNewValue = 0;
   12688 let addrMode = Absolute;
   12689 let accessSize = HalfWordAccess;
   12690 let isPredicatedNew = 1;
   12691 let mayLoad = 1;
   12692 let isExtended = 1;
   12693 let CextOpcode = "L2_loadrh";
   12694 let BaseOpcode = "L4_loadrh_abs";
   12695 let DecoderNamespace = "MustExtend";
   12696 let isExtendable = 1;
   12697 let opExtendable = 2;
   12698 let isExtentSigned = 0;
   12699 let opExtentBits = 6;
   12700 let opExtentAlign = 0;
   12701 }
   12702 def L4_ploadrhfnew_rr : HInst<
   12703 (outs IntRegs:$Rd32),
   12704 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12705 "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
   12706 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12707 let Inst{31-21} = 0b00110011010;
   12708 let isPredicated = 1;
   12709 let isPredicatedFalse = 1;
   12710 let hasNewValue = 1;
   12711 let opNewValue = 0;
   12712 let addrMode = BaseRegOffset;
   12713 let accessSize = HalfWordAccess;
   12714 let isPredicatedNew = 1;
   12715 let mayLoad = 1;
   12716 let CextOpcode = "L2_loadrh";
   12717 let InputType = "reg";
   12718 let BaseOpcode = "L4_loadrh_rr";
   12719 }
   12720 def L4_ploadrht_abs : HInst<
   12721 (outs IntRegs:$Rd32),
   12722 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12723 "if ($Pt4) $Rd32 = memh(#$Ii)",
   12724 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12725 let Inst{7-5} = 0b100;
   12726 let Inst{13-11} = 0b100;
   12727 let Inst{31-21} = 0b10011111010;
   12728 let isPredicated = 1;
   12729 let hasNewValue = 1;
   12730 let opNewValue = 0;
   12731 let addrMode = Absolute;
   12732 let accessSize = HalfWordAccess;
   12733 let mayLoad = 1;
   12734 let isExtended = 1;
   12735 let CextOpcode = "L2_loadrh";
   12736 let BaseOpcode = "L4_loadrh_abs";
   12737 let DecoderNamespace = "MustExtend";
   12738 let isExtendable = 1;
   12739 let opExtendable = 2;
   12740 let isExtentSigned = 0;
   12741 let opExtentBits = 6;
   12742 let opExtentAlign = 0;
   12743 }
   12744 def L4_ploadrht_rr : HInst<
   12745 (outs IntRegs:$Rd32),
   12746 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12747 "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
   12748 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12749 let Inst{31-21} = 0b00110000010;
   12750 let isPredicated = 1;
   12751 let hasNewValue = 1;
   12752 let opNewValue = 0;
   12753 let addrMode = BaseRegOffset;
   12754 let accessSize = HalfWordAccess;
   12755 let mayLoad = 1;
   12756 let CextOpcode = "L2_loadrh";
   12757 let InputType = "reg";
   12758 let BaseOpcode = "L4_loadrh_rr";
   12759 }
   12760 def L4_ploadrhtnew_abs : HInst<
   12761 (outs IntRegs:$Rd32),
   12762 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12763 "if ($Pt4.new) $Rd32 = memh(#$Ii)",
   12764 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12765 let Inst{7-5} = 0b100;
   12766 let Inst{13-11} = 0b110;
   12767 let Inst{31-21} = 0b10011111010;
   12768 let isPredicated = 1;
   12769 let hasNewValue = 1;
   12770 let opNewValue = 0;
   12771 let addrMode = Absolute;
   12772 let accessSize = HalfWordAccess;
   12773 let isPredicatedNew = 1;
   12774 let mayLoad = 1;
   12775 let isExtended = 1;
   12776 let CextOpcode = "L2_loadrh";
   12777 let BaseOpcode = "L4_loadrh_abs";
   12778 let DecoderNamespace = "MustExtend";
   12779 let isExtendable = 1;
   12780 let opExtendable = 2;
   12781 let isExtentSigned = 0;
   12782 let opExtentBits = 6;
   12783 let opExtentAlign = 0;
   12784 }
   12785 def L4_ploadrhtnew_rr : HInst<
   12786 (outs IntRegs:$Rd32),
   12787 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12788 "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
   12789 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12790 let Inst{31-21} = 0b00110010010;
   12791 let isPredicated = 1;
   12792 let hasNewValue = 1;
   12793 let opNewValue = 0;
   12794 let addrMode = BaseRegOffset;
   12795 let accessSize = HalfWordAccess;
   12796 let isPredicatedNew = 1;
   12797 let mayLoad = 1;
   12798 let CextOpcode = "L2_loadrh";
   12799 let InputType = "reg";
   12800 let BaseOpcode = "L4_loadrh_rr";
   12801 }
   12802 def L4_ploadrif_abs : HInst<
   12803 (outs IntRegs:$Rd32),
   12804 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12805 "if (!$Pt4) $Rd32 = memw(#$Ii)",
   12806 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12807 let Inst{7-5} = 0b100;
   12808 let Inst{13-11} = 0b101;
   12809 let Inst{31-21} = 0b10011111100;
   12810 let isPredicated = 1;
   12811 let isPredicatedFalse = 1;
   12812 let hasNewValue = 1;
   12813 let opNewValue = 0;
   12814 let addrMode = Absolute;
   12815 let accessSize = WordAccess;
   12816 let mayLoad = 1;
   12817 let isExtended = 1;
   12818 let CextOpcode = "L2_loadri";
   12819 let BaseOpcode = "L4_loadri_abs";
   12820 let DecoderNamespace = "MustExtend";
   12821 let isExtendable = 1;
   12822 let opExtendable = 2;
   12823 let isExtentSigned = 0;
   12824 let opExtentBits = 6;
   12825 let opExtentAlign = 0;
   12826 }
   12827 def L4_ploadrif_rr : HInst<
   12828 (outs IntRegs:$Rd32),
   12829 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12830 "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
   12831 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12832 let Inst{31-21} = 0b00110001100;
   12833 let isPredicated = 1;
   12834 let isPredicatedFalse = 1;
   12835 let hasNewValue = 1;
   12836 let opNewValue = 0;
   12837 let addrMode = BaseRegOffset;
   12838 let accessSize = WordAccess;
   12839 let mayLoad = 1;
   12840 let CextOpcode = "L2_loadri";
   12841 let InputType = "reg";
   12842 let BaseOpcode = "L4_loadri_rr";
   12843 }
   12844 def L4_ploadrifnew_abs : HInst<
   12845 (outs IntRegs:$Rd32),
   12846 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12847 "if (!$Pt4.new) $Rd32 = memw(#$Ii)",
   12848 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12849 let Inst{7-5} = 0b100;
   12850 let Inst{13-11} = 0b111;
   12851 let Inst{31-21} = 0b10011111100;
   12852 let isPredicated = 1;
   12853 let isPredicatedFalse = 1;
   12854 let hasNewValue = 1;
   12855 let opNewValue = 0;
   12856 let addrMode = Absolute;
   12857 let accessSize = WordAccess;
   12858 let isPredicatedNew = 1;
   12859 let mayLoad = 1;
   12860 let isExtended = 1;
   12861 let CextOpcode = "L2_loadri";
   12862 let BaseOpcode = "L4_loadri_abs";
   12863 let DecoderNamespace = "MustExtend";
   12864 let isExtendable = 1;
   12865 let opExtendable = 2;
   12866 let isExtentSigned = 0;
   12867 let opExtentBits = 6;
   12868 let opExtentAlign = 0;
   12869 }
   12870 def L4_ploadrifnew_rr : HInst<
   12871 (outs IntRegs:$Rd32),
   12872 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12873 "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
   12874 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12875 let Inst{31-21} = 0b00110011100;
   12876 let isPredicated = 1;
   12877 let isPredicatedFalse = 1;
   12878 let hasNewValue = 1;
   12879 let opNewValue = 0;
   12880 let addrMode = BaseRegOffset;
   12881 let accessSize = WordAccess;
   12882 let isPredicatedNew = 1;
   12883 let mayLoad = 1;
   12884 let CextOpcode = "L2_loadri";
   12885 let InputType = "reg";
   12886 let BaseOpcode = "L4_loadri_rr";
   12887 }
   12888 def L4_ploadrit_abs : HInst<
   12889 (outs IntRegs:$Rd32),
   12890 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12891 "if ($Pt4) $Rd32 = memw(#$Ii)",
   12892 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12893 let Inst{7-5} = 0b100;
   12894 let Inst{13-11} = 0b100;
   12895 let Inst{31-21} = 0b10011111100;
   12896 let isPredicated = 1;
   12897 let hasNewValue = 1;
   12898 let opNewValue = 0;
   12899 let addrMode = Absolute;
   12900 let accessSize = WordAccess;
   12901 let mayLoad = 1;
   12902 let isExtended = 1;
   12903 let CextOpcode = "L2_loadri";
   12904 let BaseOpcode = "L4_loadri_abs";
   12905 let DecoderNamespace = "MustExtend";
   12906 let isExtendable = 1;
   12907 let opExtendable = 2;
   12908 let isExtentSigned = 0;
   12909 let opExtentBits = 6;
   12910 let opExtentAlign = 0;
   12911 }
   12912 def L4_ploadrit_rr : HInst<
   12913 (outs IntRegs:$Rd32),
   12914 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12915 "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
   12916 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   12917 let Inst{31-21} = 0b00110000100;
   12918 let isPredicated = 1;
   12919 let hasNewValue = 1;
   12920 let opNewValue = 0;
   12921 let addrMode = BaseRegOffset;
   12922 let accessSize = WordAccess;
   12923 let mayLoad = 1;
   12924 let CextOpcode = "L2_loadri";
   12925 let InputType = "reg";
   12926 let BaseOpcode = "L4_loadri_rr";
   12927 }
   12928 def L4_ploadritnew_abs : HInst<
   12929 (outs IntRegs:$Rd32),
   12930 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12931 "if ($Pt4.new) $Rd32 = memw(#$Ii)",
   12932 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   12933 let Inst{7-5} = 0b100;
   12934 let Inst{13-11} = 0b110;
   12935 let Inst{31-21} = 0b10011111100;
   12936 let isPredicated = 1;
   12937 let hasNewValue = 1;
   12938 let opNewValue = 0;
   12939 let addrMode = Absolute;
   12940 let accessSize = WordAccess;
   12941 let isPredicatedNew = 1;
   12942 let mayLoad = 1;
   12943 let isExtended = 1;
   12944 let CextOpcode = "L2_loadri";
   12945 let BaseOpcode = "L4_loadri_abs";
   12946 let DecoderNamespace = "MustExtend";
   12947 let isExtendable = 1;
   12948 let opExtendable = 2;
   12949 let isExtentSigned = 0;
   12950 let opExtentBits = 6;
   12951 let opExtentAlign = 0;
   12952 }
   12953 def L4_ploadritnew_rr : HInst<
   12954 (outs IntRegs:$Rd32),
   12955 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12956 "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
   12957 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   12958 let Inst{31-21} = 0b00110010100;
   12959 let isPredicated = 1;
   12960 let hasNewValue = 1;
   12961 let opNewValue = 0;
   12962 let addrMode = BaseRegOffset;
   12963 let accessSize = WordAccess;
   12964 let isPredicatedNew = 1;
   12965 let mayLoad = 1;
   12966 let CextOpcode = "L2_loadri";
   12967 let InputType = "reg";
   12968 let BaseOpcode = "L4_loadri_rr";
   12969 }
   12970 def L4_ploadrubf_abs : HInst<
   12971 (outs IntRegs:$Rd32),
   12972 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   12973 "if (!$Pt4) $Rd32 = memub(#$Ii)",
   12974 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   12975 let Inst{7-5} = 0b100;
   12976 let Inst{13-11} = 0b101;
   12977 let Inst{31-21} = 0b10011111001;
   12978 let isPredicated = 1;
   12979 let isPredicatedFalse = 1;
   12980 let hasNewValue = 1;
   12981 let opNewValue = 0;
   12982 let addrMode = Absolute;
   12983 let accessSize = ByteAccess;
   12984 let mayLoad = 1;
   12985 let isExtended = 1;
   12986 let CextOpcode = "L2_loadrub";
   12987 let BaseOpcode = "L4_loadrub_abs";
   12988 let DecoderNamespace = "MustExtend";
   12989 let isExtendable = 1;
   12990 let opExtendable = 2;
   12991 let isExtentSigned = 0;
   12992 let opExtentBits = 6;
   12993 let opExtentAlign = 0;
   12994 }
   12995 def L4_ploadrubf_rr : HInst<
   12996 (outs IntRegs:$Rd32),
   12997 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   12998 "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
   12999 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   13000 let Inst{31-21} = 0b00110001001;
   13001 let isPredicated = 1;
   13002 let isPredicatedFalse = 1;
   13003 let hasNewValue = 1;
   13004 let opNewValue = 0;
   13005 let addrMode = BaseRegOffset;
   13006 let accessSize = ByteAccess;
   13007 let mayLoad = 1;
   13008 let CextOpcode = "L2_loadrub";
   13009 let InputType = "reg";
   13010 let BaseOpcode = "L4_loadrub_rr";
   13011 }
   13012 def L4_ploadrubfnew_abs : HInst<
   13013 (outs IntRegs:$Rd32),
   13014 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13015 "if (!$Pt4.new) $Rd32 = memub(#$Ii)",
   13016 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   13017 let Inst{7-5} = 0b100;
   13018 let Inst{13-11} = 0b111;
   13019 let Inst{31-21} = 0b10011111001;
   13020 let isPredicated = 1;
   13021 let isPredicatedFalse = 1;
   13022 let hasNewValue = 1;
   13023 let opNewValue = 0;
   13024 let addrMode = Absolute;
   13025 let accessSize = ByteAccess;
   13026 let isPredicatedNew = 1;
   13027 let mayLoad = 1;
   13028 let isExtended = 1;
   13029 let CextOpcode = "L2_loadrub";
   13030 let BaseOpcode = "L4_loadrub_abs";
   13031 let DecoderNamespace = "MustExtend";
   13032 let isExtendable = 1;
   13033 let opExtendable = 2;
   13034 let isExtentSigned = 0;
   13035 let opExtentBits = 6;
   13036 let opExtentAlign = 0;
   13037 }
   13038 def L4_ploadrubfnew_rr : HInst<
   13039 (outs IntRegs:$Rd32),
   13040 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13041 "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
   13042 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   13043 let Inst{31-21} = 0b00110011001;
   13044 let isPredicated = 1;
   13045 let isPredicatedFalse = 1;
   13046 let hasNewValue = 1;
   13047 let opNewValue = 0;
   13048 let addrMode = BaseRegOffset;
   13049 let accessSize = ByteAccess;
   13050 let isPredicatedNew = 1;
   13051 let mayLoad = 1;
   13052 let CextOpcode = "L2_loadrub";
   13053 let InputType = "reg";
   13054 let BaseOpcode = "L4_loadrub_rr";
   13055 }
   13056 def L4_ploadrubt_abs : HInst<
   13057 (outs IntRegs:$Rd32),
   13058 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13059 "if ($Pt4) $Rd32 = memub(#$Ii)",
   13060 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   13061 let Inst{7-5} = 0b100;
   13062 let Inst{13-11} = 0b100;
   13063 let Inst{31-21} = 0b10011111001;
   13064 let isPredicated = 1;
   13065 let hasNewValue = 1;
   13066 let opNewValue = 0;
   13067 let addrMode = Absolute;
   13068 let accessSize = ByteAccess;
   13069 let mayLoad = 1;
   13070 let isExtended = 1;
   13071 let CextOpcode = "L2_loadrub";
   13072 let BaseOpcode = "L4_loadrub_abs";
   13073 let DecoderNamespace = "MustExtend";
   13074 let isExtendable = 1;
   13075 let opExtendable = 2;
   13076 let isExtentSigned = 0;
   13077 let opExtentBits = 6;
   13078 let opExtentAlign = 0;
   13079 }
   13080 def L4_ploadrubt_rr : HInst<
   13081 (outs IntRegs:$Rd32),
   13082 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13083 "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
   13084 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   13085 let Inst{31-21} = 0b00110000001;
   13086 let isPredicated = 1;
   13087 let hasNewValue = 1;
   13088 let opNewValue = 0;
   13089 let addrMode = BaseRegOffset;
   13090 let accessSize = ByteAccess;
   13091 let mayLoad = 1;
   13092 let CextOpcode = "L2_loadrub";
   13093 let InputType = "reg";
   13094 let BaseOpcode = "L4_loadrub_rr";
   13095 }
   13096 def L4_ploadrubtnew_abs : HInst<
   13097 (outs IntRegs:$Rd32),
   13098 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13099 "if ($Pt4.new) $Rd32 = memub(#$Ii)",
   13100 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   13101 let Inst{7-5} = 0b100;
   13102 let Inst{13-11} = 0b110;
   13103 let Inst{31-21} = 0b10011111001;
   13104 let isPredicated = 1;
   13105 let hasNewValue = 1;
   13106 let opNewValue = 0;
   13107 let addrMode = Absolute;
   13108 let accessSize = ByteAccess;
   13109 let isPredicatedNew = 1;
   13110 let mayLoad = 1;
   13111 let isExtended = 1;
   13112 let CextOpcode = "L2_loadrub";
   13113 let BaseOpcode = "L4_loadrub_abs";
   13114 let DecoderNamespace = "MustExtend";
   13115 let isExtendable = 1;
   13116 let opExtendable = 2;
   13117 let isExtentSigned = 0;
   13118 let opExtentBits = 6;
   13119 let opExtentAlign = 0;
   13120 }
   13121 def L4_ploadrubtnew_rr : HInst<
   13122 (outs IntRegs:$Rd32),
   13123 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13124 "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
   13125 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   13126 let Inst{31-21} = 0b00110010001;
   13127 let isPredicated = 1;
   13128 let hasNewValue = 1;
   13129 let opNewValue = 0;
   13130 let addrMode = BaseRegOffset;
   13131 let accessSize = ByteAccess;
   13132 let isPredicatedNew = 1;
   13133 let mayLoad = 1;
   13134 let CextOpcode = "L2_loadrub";
   13135 let InputType = "reg";
   13136 let BaseOpcode = "L4_loadrub_rr";
   13137 }
   13138 def L4_ploadruhf_abs : HInst<
   13139 (outs IntRegs:$Rd32),
   13140 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13141 "if (!$Pt4) $Rd32 = memuh(#$Ii)",
   13142 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   13143 let Inst{7-5} = 0b100;
   13144 let Inst{13-11} = 0b101;
   13145 let Inst{31-21} = 0b10011111011;
   13146 let isPredicated = 1;
   13147 let isPredicatedFalse = 1;
   13148 let hasNewValue = 1;
   13149 let opNewValue = 0;
   13150 let addrMode = Absolute;
   13151 let accessSize = HalfWordAccess;
   13152 let mayLoad = 1;
   13153 let isExtended = 1;
   13154 let CextOpcode = "L2_loadruh";
   13155 let BaseOpcode = "L4_loadruh_abs";
   13156 let DecoderNamespace = "MustExtend";
   13157 let isExtendable = 1;
   13158 let opExtendable = 2;
   13159 let isExtentSigned = 0;
   13160 let opExtentBits = 6;
   13161 let opExtentAlign = 0;
   13162 }
   13163 def L4_ploadruhf_rr : HInst<
   13164 (outs IntRegs:$Rd32),
   13165 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13166 "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
   13167 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   13168 let Inst{31-21} = 0b00110001011;
   13169 let isPredicated = 1;
   13170 let isPredicatedFalse = 1;
   13171 let hasNewValue = 1;
   13172 let opNewValue = 0;
   13173 let addrMode = BaseRegOffset;
   13174 let accessSize = HalfWordAccess;
   13175 let mayLoad = 1;
   13176 let CextOpcode = "L2_loadruh";
   13177 let InputType = "reg";
   13178 let BaseOpcode = "L4_loadruh_rr";
   13179 }
   13180 def L4_ploadruhfnew_abs : HInst<
   13181 (outs IntRegs:$Rd32),
   13182 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13183 "if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
   13184 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   13185 let Inst{7-5} = 0b100;
   13186 let Inst{13-11} = 0b111;
   13187 let Inst{31-21} = 0b10011111011;
   13188 let isPredicated = 1;
   13189 let isPredicatedFalse = 1;
   13190 let hasNewValue = 1;
   13191 let opNewValue = 0;
   13192 let addrMode = Absolute;
   13193 let accessSize = HalfWordAccess;
   13194 let isPredicatedNew = 1;
   13195 let mayLoad = 1;
   13196 let isExtended = 1;
   13197 let CextOpcode = "L2_loadruh";
   13198 let BaseOpcode = "L4_loadruh_abs";
   13199 let DecoderNamespace = "MustExtend";
   13200 let isExtendable = 1;
   13201 let opExtendable = 2;
   13202 let isExtentSigned = 0;
   13203 let opExtentBits = 6;
   13204 let opExtentAlign = 0;
   13205 }
   13206 def L4_ploadruhfnew_rr : HInst<
   13207 (outs IntRegs:$Rd32),
   13208 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13209 "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
   13210 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   13211 let Inst{31-21} = 0b00110011011;
   13212 let isPredicated = 1;
   13213 let isPredicatedFalse = 1;
   13214 let hasNewValue = 1;
   13215 let opNewValue = 0;
   13216 let addrMode = BaseRegOffset;
   13217 let accessSize = HalfWordAccess;
   13218 let isPredicatedNew = 1;
   13219 let mayLoad = 1;
   13220 let CextOpcode = "L2_loadruh";
   13221 let InputType = "reg";
   13222 let BaseOpcode = "L4_loadruh_rr";
   13223 }
   13224 def L4_ploadruht_abs : HInst<
   13225 (outs IntRegs:$Rd32),
   13226 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13227 "if ($Pt4) $Rd32 = memuh(#$Ii)",
   13228 tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel {
   13229 let Inst{7-5} = 0b100;
   13230 let Inst{13-11} = 0b100;
   13231 let Inst{31-21} = 0b10011111011;
   13232 let isPredicated = 1;
   13233 let hasNewValue = 1;
   13234 let opNewValue = 0;
   13235 let addrMode = Absolute;
   13236 let accessSize = HalfWordAccess;
   13237 let mayLoad = 1;
   13238 let isExtended = 1;
   13239 let CextOpcode = "L2_loadruh";
   13240 let BaseOpcode = "L4_loadruh_abs";
   13241 let DecoderNamespace = "MustExtend";
   13242 let isExtendable = 1;
   13243 let opExtendable = 2;
   13244 let isExtentSigned = 0;
   13245 let opExtentBits = 6;
   13246 let opExtentAlign = 0;
   13247 }
   13248 def L4_ploadruht_rr : HInst<
   13249 (outs IntRegs:$Rd32),
   13250 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13251 "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
   13252 tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel {
   13253 let Inst{31-21} = 0b00110000011;
   13254 let isPredicated = 1;
   13255 let hasNewValue = 1;
   13256 let opNewValue = 0;
   13257 let addrMode = BaseRegOffset;
   13258 let accessSize = HalfWordAccess;
   13259 let mayLoad = 1;
   13260 let CextOpcode = "L2_loadruh";
   13261 let InputType = "reg";
   13262 let BaseOpcode = "L4_loadruh_rr";
   13263 }
   13264 def L4_ploadruhtnew_abs : HInst<
   13265 (outs IntRegs:$Rd32),
   13266 (ins PredRegs:$Pt4, u32_0Imm:$Ii),
   13267 "if ($Pt4.new) $Rd32 = memuh(#$Ii)",
   13268 tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel {
   13269 let Inst{7-5} = 0b100;
   13270 let Inst{13-11} = 0b110;
   13271 let Inst{31-21} = 0b10011111011;
   13272 let isPredicated = 1;
   13273 let hasNewValue = 1;
   13274 let opNewValue = 0;
   13275 let addrMode = Absolute;
   13276 let accessSize = HalfWordAccess;
   13277 let isPredicatedNew = 1;
   13278 let mayLoad = 1;
   13279 let isExtended = 1;
   13280 let CextOpcode = "L2_loadruh";
   13281 let BaseOpcode = "L4_loadruh_abs";
   13282 let DecoderNamespace = "MustExtend";
   13283 let isExtendable = 1;
   13284 let opExtendable = 2;
   13285 let isExtentSigned = 0;
   13286 let opExtentBits = 6;
   13287 let opExtentAlign = 0;
   13288 }
   13289 def L4_ploadruhtnew_rr : HInst<
   13290 (outs IntRegs:$Rd32),
   13291 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
   13292 "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
   13293 tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel {
   13294 let Inst{31-21} = 0b00110010011;
   13295 let isPredicated = 1;
   13296 let hasNewValue = 1;
   13297 let opNewValue = 0;
   13298 let addrMode = BaseRegOffset;
   13299 let accessSize = HalfWordAccess;
   13300 let isPredicatedNew = 1;
   13301 let mayLoad = 1;
   13302 let CextOpcode = "L2_loadruh";
   13303 let InputType = "reg";
   13304 let BaseOpcode = "L4_loadruh_rr";
   13305 }
   13306 def L4_return : HInst<
   13307 (outs DoubleRegs:$Rdd32),
   13308 (ins IntRegs:$Rs32),
   13309 "$Rdd32 = dealloc_return($Rs32):raw",
   13310 tc_3d04548d, TypeLD>, Enc_3a3d62, PredNewRel {
   13311 let Inst{13-5} = 0b000000000;
   13312 let Inst{31-21} = 0b10010110000;
   13313 let isTerminator = 1;
   13314 let isIndirectBranch = 1;
   13315 let accessSize = DoubleWordAccess;
   13316 let mayLoad = 1;
   13317 let cofMax1 = 1;
   13318 let isRestrictNoSlot1Store = 1;
   13319 let isReturn = 1;
   13320 let Uses = [FRAMEKEY];
   13321 let Defs = [PC, R29];
   13322 let BaseOpcode = "L4_return";
   13323 let isBarrier = 1;
   13324 let isPredicable = 1;
   13325 let isTaken = 1;
   13326 }
   13327 def L4_return_f : HInst<
   13328 (outs DoubleRegs:$Rdd32),
   13329 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13330 "if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
   13331 tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
   13332 let Inst{7-5} = 0b000;
   13333 let Inst{13-10} = 0b1100;
   13334 let Inst{31-21} = 0b10010110000;
   13335 let isPredicated = 1;
   13336 let isPredicatedFalse = 1;
   13337 let isTerminator = 1;
   13338 let isIndirectBranch = 1;
   13339 let accessSize = DoubleWordAccess;
   13340 let mayLoad = 1;
   13341 let cofMax1 = 1;
   13342 let isRestrictNoSlot1Store = 1;
   13343 let isReturn = 1;
   13344 let Uses = [FRAMEKEY];
   13345 let Defs = [PC, R29];
   13346 let BaseOpcode = "L4_return";
   13347 let isTaken = Inst{12};
   13348 }
   13349 def L4_return_fnew_pnt : HInst<
   13350 (outs DoubleRegs:$Rdd32),
   13351 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13352 "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
   13353 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
   13354 let Inst{7-5} = 0b000;
   13355 let Inst{13-10} = 0b1010;
   13356 let Inst{31-21} = 0b10010110000;
   13357 let isPredicated = 1;
   13358 let isPredicatedFalse = 1;
   13359 let isTerminator = 1;
   13360 let isIndirectBranch = 1;
   13361 let accessSize = DoubleWordAccess;
   13362 let isPredicatedNew = 1;
   13363 let mayLoad = 1;
   13364 let cofMax1 = 1;
   13365 let isRestrictNoSlot1Store = 1;
   13366 let isReturn = 1;
   13367 let Uses = [FRAMEKEY];
   13368 let Defs = [PC, R29];
   13369 let BaseOpcode = "L4_return";
   13370 let isTaken = Inst{12};
   13371 }
   13372 def L4_return_fnew_pt : HInst<
   13373 (outs DoubleRegs:$Rdd32),
   13374 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13375 "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
   13376 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
   13377 let Inst{7-5} = 0b000;
   13378 let Inst{13-10} = 0b1110;
   13379 let Inst{31-21} = 0b10010110000;
   13380 let isPredicated = 1;
   13381 let isPredicatedFalse = 1;
   13382 let isTerminator = 1;
   13383 let isIndirectBranch = 1;
   13384 let accessSize = DoubleWordAccess;
   13385 let isPredicatedNew = 1;
   13386 let mayLoad = 1;
   13387 let cofMax1 = 1;
   13388 let isRestrictNoSlot1Store = 1;
   13389 let isReturn = 1;
   13390 let Uses = [FRAMEKEY];
   13391 let Defs = [PC, R29];
   13392 let BaseOpcode = "L4_return";
   13393 let isTaken = Inst{12};
   13394 }
   13395 def L4_return_map_to_raw_f : HInst<
   13396 (outs),
   13397 (ins PredRegs:$Pv4),
   13398 "if (!$Pv4) dealloc_return",
   13399 tc_513bef45, TypeMAPPING>, Requires<[HasV65]> {
   13400 let isPseudo = 1;
   13401 let isCodeGenOnly = 1;
   13402 }
   13403 def L4_return_map_to_raw_fnew_pnt : HInst<
   13404 (outs),
   13405 (ins PredRegs:$Pv4),
   13406 "if (!$Pv4.new) dealloc_return:nt",
   13407 tc_395dc00f, TypeMAPPING>, Requires<[HasV65]> {
   13408 let isPseudo = 1;
   13409 let isCodeGenOnly = 1;
   13410 }
   13411 def L4_return_map_to_raw_fnew_pt : HInst<
   13412 (outs),
   13413 (ins PredRegs:$Pv4),
   13414 "if (!$Pv4.new) dealloc_return:t",
   13415 tc_395dc00f, TypeMAPPING>, Requires<[HasV65]> {
   13416 let isPseudo = 1;
   13417 let isCodeGenOnly = 1;
   13418 }
   13419 def L4_return_map_to_raw_t : HInst<
   13420 (outs),
   13421 (ins PredRegs:$Pv4),
   13422 "if ($Pv4) dealloc_return",
   13423 tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65]> {
   13424 let isPseudo = 1;
   13425 let isCodeGenOnly = 1;
   13426 }
   13427 def L4_return_map_to_raw_tnew_pnt : HInst<
   13428 (outs),
   13429 (ins PredRegs:$Pv4),
   13430 "if ($Pv4.new) dealloc_return:nt",
   13431 tc_e7624c08, TypeMAPPING>, Requires<[HasV65]> {
   13432 let isPseudo = 1;
   13433 let isCodeGenOnly = 1;
   13434 }
   13435 def L4_return_map_to_raw_tnew_pt : HInst<
   13436 (outs),
   13437 (ins PredRegs:$Pv4),
   13438 "if ($Pv4.new) dealloc_return:t",
   13439 tc_e7624c08, TypeMAPPING>, Requires<[HasV65]> {
   13440 let isPseudo = 1;
   13441 let isCodeGenOnly = 1;
   13442 }
   13443 def L4_return_t : HInst<
   13444 (outs DoubleRegs:$Rdd32),
   13445 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13446 "if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
   13447 tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel {
   13448 let Inst{7-5} = 0b000;
   13449 let Inst{13-10} = 0b0100;
   13450 let Inst{31-21} = 0b10010110000;
   13451 let isPredicated = 1;
   13452 let isTerminator = 1;
   13453 let isIndirectBranch = 1;
   13454 let accessSize = DoubleWordAccess;
   13455 let mayLoad = 1;
   13456 let cofMax1 = 1;
   13457 let isRestrictNoSlot1Store = 1;
   13458 let isReturn = 1;
   13459 let Uses = [FRAMEKEY];
   13460 let Defs = [PC, R29];
   13461 let BaseOpcode = "L4_return";
   13462 let isTaken = Inst{12};
   13463 }
   13464 def L4_return_tnew_pnt : HInst<
   13465 (outs DoubleRegs:$Rdd32),
   13466 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13467 "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
   13468 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
   13469 let Inst{7-5} = 0b000;
   13470 let Inst{13-10} = 0b0010;
   13471 let Inst{31-21} = 0b10010110000;
   13472 let isPredicated = 1;
   13473 let isTerminator = 1;
   13474 let isIndirectBranch = 1;
   13475 let accessSize = DoubleWordAccess;
   13476 let isPredicatedNew = 1;
   13477 let mayLoad = 1;
   13478 let cofMax1 = 1;
   13479 let isRestrictNoSlot1Store = 1;
   13480 let isReturn = 1;
   13481 let Uses = [FRAMEKEY];
   13482 let Defs = [PC, R29];
   13483 let BaseOpcode = "L4_return";
   13484 let isTaken = Inst{12};
   13485 }
   13486 def L4_return_tnew_pt : HInst<
   13487 (outs DoubleRegs:$Rdd32),
   13488 (ins PredRegs:$Pv4, IntRegs:$Rs32),
   13489 "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
   13490 tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel {
   13491 let Inst{7-5} = 0b000;
   13492 let Inst{13-10} = 0b0110;
   13493 let Inst{31-21} = 0b10010110000;
   13494 let isPredicated = 1;
   13495 let isTerminator = 1;
   13496 let isIndirectBranch = 1;
   13497 let accessSize = DoubleWordAccess;
   13498 let isPredicatedNew = 1;
   13499 let mayLoad = 1;
   13500 let cofMax1 = 1;
   13501 let isRestrictNoSlot1Store = 1;
   13502 let isReturn = 1;
   13503 let Uses = [FRAMEKEY];
   13504 let Defs = [PC, R29];
   13505 let BaseOpcode = "L4_return";
   13506 let isTaken = Inst{12};
   13507 }
   13508 def L4_sub_memopb_io : HInst<
   13509 (outs),
   13510 (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   13511 "memb($Rs32+#$Ii) -= $Rt32",
   13512 tc_44126683, TypeV4LDST>, Enc_d44e31 {
   13513 let Inst{6-5} = 0b01;
   13514 let Inst{13-13} = 0b0;
   13515 let Inst{31-21} = 0b00111110000;
   13516 let addrMode = BaseImmOffset;
   13517 let accessSize = ByteAccess;
   13518 let mayLoad = 1;
   13519 let isRestrictNoSlot1Store = 1;
   13520 let mayStore = 1;
   13521 let isExtendable = 1;
   13522 let opExtendable = 1;
   13523 let isExtentSigned = 0;
   13524 let opExtentBits = 6;
   13525 let opExtentAlign = 0;
   13526 }
   13527 def L4_sub_memopb_zomap : HInst<
   13528 (outs),
   13529 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13530 "memb($Rs32) -= $Rt32",
   13531 tc_44126683, TypeMAPPING> {
   13532 let isPseudo = 1;
   13533 let isCodeGenOnly = 1;
   13534 }
   13535 def L4_sub_memoph_io : HInst<
   13536 (outs),
   13537 (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   13538 "memh($Rs32+#$Ii) -= $Rt32",
   13539 tc_44126683, TypeV4LDST>, Enc_163a3c {
   13540 let Inst{6-5} = 0b01;
   13541 let Inst{13-13} = 0b0;
   13542 let Inst{31-21} = 0b00111110001;
   13543 let addrMode = BaseImmOffset;
   13544 let accessSize = HalfWordAccess;
   13545 let mayLoad = 1;
   13546 let isRestrictNoSlot1Store = 1;
   13547 let mayStore = 1;
   13548 let isExtendable = 1;
   13549 let opExtendable = 1;
   13550 let isExtentSigned = 0;
   13551 let opExtentBits = 7;
   13552 let opExtentAlign = 1;
   13553 }
   13554 def L4_sub_memoph_zomap : HInst<
   13555 (outs),
   13556 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13557 "memh($Rs32) -= $Rt32",
   13558 tc_44126683, TypeMAPPING> {
   13559 let isPseudo = 1;
   13560 let isCodeGenOnly = 1;
   13561 }
   13562 def L4_sub_memopw_io : HInst<
   13563 (outs),
   13564 (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   13565 "memw($Rs32+#$Ii) -= $Rt32",
   13566 tc_44126683, TypeV4LDST>, Enc_226535 {
   13567 let Inst{6-5} = 0b01;
   13568 let Inst{13-13} = 0b0;
   13569 let Inst{31-21} = 0b00111110010;
   13570 let addrMode = BaseImmOffset;
   13571 let accessSize = WordAccess;
   13572 let mayLoad = 1;
   13573 let isRestrictNoSlot1Store = 1;
   13574 let mayStore = 1;
   13575 let isExtendable = 1;
   13576 let opExtendable = 1;
   13577 let isExtentSigned = 0;
   13578 let opExtentBits = 8;
   13579 let opExtentAlign = 2;
   13580 }
   13581 def L4_sub_memopw_zomap : HInst<
   13582 (outs),
   13583 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13584 "memw($Rs32) -= $Rt32",
   13585 tc_44126683, TypeMAPPING> {
   13586 let isPseudo = 1;
   13587 let isCodeGenOnly = 1;
   13588 }
   13589 def L6_deallocframe_map_to_raw : HInst<
   13590 (outs),
   13591 (ins),
   13592 "deallocframe",
   13593 tc_d1090e34, TypeMAPPING>, Requires<[HasV65]> {
   13594 let isPseudo = 1;
   13595 let isCodeGenOnly = 1;
   13596 }
   13597 def L6_return_map_to_raw : HInst<
   13598 (outs),
   13599 (ins),
   13600 "dealloc_return",
   13601 tc_3d04548d, TypeMAPPING>, Requires<[HasV65]> {
   13602 let isPseudo = 1;
   13603 let isCodeGenOnly = 1;
   13604 }
   13605 def M2_acci : HInst<
   13606 (outs IntRegs:$Rx32),
   13607 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13608 "$Rx32 += add($Rs32,$Rt32)",
   13609 tc_c74f796f, TypeM>, Enc_2ae154, ImmRegRel {
   13610 let Inst{7-5} = 0b001;
   13611 let Inst{13-13} = 0b0;
   13612 let Inst{31-21} = 0b11101111000;
   13613 let hasNewValue = 1;
   13614 let opNewValue = 0;
   13615 let prefersSlot3 = 1;
   13616 let CextOpcode = "M2_acci";
   13617 let InputType = "reg";
   13618 let Constraints = "$Rx32 = $Rx32in";
   13619 }
   13620 def M2_accii : HInst<
   13621 (outs IntRegs:$Rx32),
   13622 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
   13623 "$Rx32 += add($Rs32,#$Ii)",
   13624 tc_c74f796f, TypeM>, Enc_c90aca, ImmRegRel {
   13625 let Inst{13-13} = 0b0;
   13626 let Inst{31-21} = 0b11100010000;
   13627 let hasNewValue = 1;
   13628 let opNewValue = 0;
   13629 let prefersSlot3 = 1;
   13630 let CextOpcode = "M2_acci";
   13631 let InputType = "imm";
   13632 let isExtendable = 1;
   13633 let opExtendable = 3;
   13634 let isExtentSigned = 1;
   13635 let opExtentBits = 8;
   13636 let opExtentAlign = 0;
   13637 let Constraints = "$Rx32 = $Rx32in";
   13638 }
   13639 def M2_cmaci_s0 : HInst<
   13640 (outs DoubleRegs:$Rxx32),
   13641 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13642 "$Rxx32 += cmpyi($Rs32,$Rt32)",
   13643 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13644 let Inst{7-5} = 0b001;
   13645 let Inst{13-13} = 0b0;
   13646 let Inst{31-21} = 0b11100111000;
   13647 let prefersSlot3 = 1;
   13648 let Constraints = "$Rxx32 = $Rxx32in";
   13649 }
   13650 def M2_cmacr_s0 : HInst<
   13651 (outs DoubleRegs:$Rxx32),
   13652 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13653 "$Rxx32 += cmpyr($Rs32,$Rt32)",
   13654 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13655 let Inst{7-5} = 0b010;
   13656 let Inst{13-13} = 0b0;
   13657 let Inst{31-21} = 0b11100111000;
   13658 let prefersSlot3 = 1;
   13659 let Constraints = "$Rxx32 = $Rxx32in";
   13660 }
   13661 def M2_cmacs_s0 : HInst<
   13662 (outs DoubleRegs:$Rxx32),
   13663 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13664 "$Rxx32 += cmpy($Rs32,$Rt32):sat",
   13665 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13666 let Inst{7-5} = 0b110;
   13667 let Inst{13-13} = 0b0;
   13668 let Inst{31-21} = 0b11100111000;
   13669 let prefersSlot3 = 1;
   13670 let Defs = [USR_OVF];
   13671 let Constraints = "$Rxx32 = $Rxx32in";
   13672 }
   13673 def M2_cmacs_s1 : HInst<
   13674 (outs DoubleRegs:$Rxx32),
   13675 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13676 "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
   13677 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13678 let Inst{7-5} = 0b110;
   13679 let Inst{13-13} = 0b0;
   13680 let Inst{31-21} = 0b11100111100;
   13681 let prefersSlot3 = 1;
   13682 let Defs = [USR_OVF];
   13683 let Constraints = "$Rxx32 = $Rxx32in";
   13684 }
   13685 def M2_cmacsc_s0 : HInst<
   13686 (outs DoubleRegs:$Rxx32),
   13687 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13688 "$Rxx32 += cmpy($Rs32,$Rt32*):sat",
   13689 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13690 let Inst{7-5} = 0b110;
   13691 let Inst{13-13} = 0b0;
   13692 let Inst{31-21} = 0b11100111010;
   13693 let prefersSlot3 = 1;
   13694 let Defs = [USR_OVF];
   13695 let Constraints = "$Rxx32 = $Rxx32in";
   13696 }
   13697 def M2_cmacsc_s1 : HInst<
   13698 (outs DoubleRegs:$Rxx32),
   13699 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13700 "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
   13701 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13702 let Inst{7-5} = 0b110;
   13703 let Inst{13-13} = 0b0;
   13704 let Inst{31-21} = 0b11100111110;
   13705 let prefersSlot3 = 1;
   13706 let Defs = [USR_OVF];
   13707 let Constraints = "$Rxx32 = $Rxx32in";
   13708 }
   13709 def M2_cmpyi_s0 : HInst<
   13710 (outs DoubleRegs:$Rdd32),
   13711 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13712 "$Rdd32 = cmpyi($Rs32,$Rt32)",
   13713 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13714 let Inst{7-5} = 0b001;
   13715 let Inst{13-13} = 0b0;
   13716 let Inst{31-21} = 0b11100101000;
   13717 let prefersSlot3 = 1;
   13718 }
   13719 def M2_cmpyr_s0 : HInst<
   13720 (outs DoubleRegs:$Rdd32),
   13721 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13722 "$Rdd32 = cmpyr($Rs32,$Rt32)",
   13723 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13724 let Inst{7-5} = 0b010;
   13725 let Inst{13-13} = 0b0;
   13726 let Inst{31-21} = 0b11100101000;
   13727 let prefersSlot3 = 1;
   13728 }
   13729 def M2_cmpyrs_s0 : HInst<
   13730 (outs IntRegs:$Rd32),
   13731 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13732 "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
   13733 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13734 let Inst{7-5} = 0b110;
   13735 let Inst{13-13} = 0b0;
   13736 let Inst{31-21} = 0b11101101001;
   13737 let hasNewValue = 1;
   13738 let opNewValue = 0;
   13739 let prefersSlot3 = 1;
   13740 let Defs = [USR_OVF];
   13741 }
   13742 def M2_cmpyrs_s1 : HInst<
   13743 (outs IntRegs:$Rd32),
   13744 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13745 "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
   13746 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13747 let Inst{7-5} = 0b110;
   13748 let Inst{13-13} = 0b0;
   13749 let Inst{31-21} = 0b11101101101;
   13750 let hasNewValue = 1;
   13751 let opNewValue = 0;
   13752 let prefersSlot3 = 1;
   13753 let Defs = [USR_OVF];
   13754 }
   13755 def M2_cmpyrsc_s0 : HInst<
   13756 (outs IntRegs:$Rd32),
   13757 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13758 "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
   13759 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13760 let Inst{7-5} = 0b110;
   13761 let Inst{13-13} = 0b0;
   13762 let Inst{31-21} = 0b11101101011;
   13763 let hasNewValue = 1;
   13764 let opNewValue = 0;
   13765 let prefersSlot3 = 1;
   13766 let Defs = [USR_OVF];
   13767 }
   13768 def M2_cmpyrsc_s1 : HInst<
   13769 (outs IntRegs:$Rd32),
   13770 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13771 "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
   13772 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13773 let Inst{7-5} = 0b110;
   13774 let Inst{13-13} = 0b0;
   13775 let Inst{31-21} = 0b11101101111;
   13776 let hasNewValue = 1;
   13777 let opNewValue = 0;
   13778 let prefersSlot3 = 1;
   13779 let Defs = [USR_OVF];
   13780 }
   13781 def M2_cmpys_s0 : HInst<
   13782 (outs DoubleRegs:$Rdd32),
   13783 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13784 "$Rdd32 = cmpy($Rs32,$Rt32):sat",
   13785 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13786 let Inst{7-5} = 0b110;
   13787 let Inst{13-13} = 0b0;
   13788 let Inst{31-21} = 0b11100101000;
   13789 let prefersSlot3 = 1;
   13790 let Defs = [USR_OVF];
   13791 }
   13792 def M2_cmpys_s1 : HInst<
   13793 (outs DoubleRegs:$Rdd32),
   13794 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13795 "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
   13796 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13797 let Inst{7-5} = 0b110;
   13798 let Inst{13-13} = 0b0;
   13799 let Inst{31-21} = 0b11100101100;
   13800 let prefersSlot3 = 1;
   13801 let Defs = [USR_OVF];
   13802 }
   13803 def M2_cmpysc_s0 : HInst<
   13804 (outs DoubleRegs:$Rdd32),
   13805 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13806 "$Rdd32 = cmpy($Rs32,$Rt32*):sat",
   13807 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13808 let Inst{7-5} = 0b110;
   13809 let Inst{13-13} = 0b0;
   13810 let Inst{31-21} = 0b11100101010;
   13811 let prefersSlot3 = 1;
   13812 let Defs = [USR_OVF];
   13813 }
   13814 def M2_cmpysc_s1 : HInst<
   13815 (outs DoubleRegs:$Rdd32),
   13816 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13817 "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
   13818 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13819 let Inst{7-5} = 0b110;
   13820 let Inst{13-13} = 0b0;
   13821 let Inst{31-21} = 0b11100101110;
   13822 let prefersSlot3 = 1;
   13823 let Defs = [USR_OVF];
   13824 }
   13825 def M2_cnacs_s0 : HInst<
   13826 (outs DoubleRegs:$Rxx32),
   13827 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13828 "$Rxx32 -= cmpy($Rs32,$Rt32):sat",
   13829 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13830 let Inst{7-5} = 0b111;
   13831 let Inst{13-13} = 0b0;
   13832 let Inst{31-21} = 0b11100111000;
   13833 let prefersSlot3 = 1;
   13834 let Defs = [USR_OVF];
   13835 let Constraints = "$Rxx32 = $Rxx32in";
   13836 }
   13837 def M2_cnacs_s1 : HInst<
   13838 (outs DoubleRegs:$Rxx32),
   13839 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13840 "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
   13841 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13842 let Inst{7-5} = 0b111;
   13843 let Inst{13-13} = 0b0;
   13844 let Inst{31-21} = 0b11100111100;
   13845 let prefersSlot3 = 1;
   13846 let Defs = [USR_OVF];
   13847 let Constraints = "$Rxx32 = $Rxx32in";
   13848 }
   13849 def M2_cnacsc_s0 : HInst<
   13850 (outs DoubleRegs:$Rxx32),
   13851 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13852 "$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
   13853 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13854 let Inst{7-5} = 0b111;
   13855 let Inst{13-13} = 0b0;
   13856 let Inst{31-21} = 0b11100111010;
   13857 let prefersSlot3 = 1;
   13858 let Defs = [USR_OVF];
   13859 let Constraints = "$Rxx32 = $Rxx32in";
   13860 }
   13861 def M2_cnacsc_s1 : HInst<
   13862 (outs DoubleRegs:$Rxx32),
   13863 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13864 "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
   13865 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13866 let Inst{7-5} = 0b111;
   13867 let Inst{13-13} = 0b0;
   13868 let Inst{31-21} = 0b11100111110;
   13869 let prefersSlot3 = 1;
   13870 let Defs = [USR_OVF];
   13871 let Constraints = "$Rxx32 = $Rxx32in";
   13872 }
   13873 def M2_dpmpyss_acc_s0 : HInst<
   13874 (outs DoubleRegs:$Rxx32),
   13875 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13876 "$Rxx32 += mpy($Rs32,$Rt32)",
   13877 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13878 let Inst{7-5} = 0b000;
   13879 let Inst{13-13} = 0b0;
   13880 let Inst{31-21} = 0b11100111000;
   13881 let prefersSlot3 = 1;
   13882 let Constraints = "$Rxx32 = $Rxx32in";
   13883 }
   13884 def M2_dpmpyss_nac_s0 : HInst<
   13885 (outs DoubleRegs:$Rxx32),
   13886 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13887 "$Rxx32 -= mpy($Rs32,$Rt32)",
   13888 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13889 let Inst{7-5} = 0b000;
   13890 let Inst{13-13} = 0b0;
   13891 let Inst{31-21} = 0b11100111001;
   13892 let prefersSlot3 = 1;
   13893 let Constraints = "$Rxx32 = $Rxx32in";
   13894 }
   13895 def M2_dpmpyss_rnd_s0 : HInst<
   13896 (outs IntRegs:$Rd32),
   13897 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13898 "$Rd32 = mpy($Rs32,$Rt32):rnd",
   13899 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13900 let Inst{7-5} = 0b001;
   13901 let Inst{13-13} = 0b0;
   13902 let Inst{31-21} = 0b11101101001;
   13903 let hasNewValue = 1;
   13904 let opNewValue = 0;
   13905 let prefersSlot3 = 1;
   13906 }
   13907 def M2_dpmpyss_s0 : HInst<
   13908 (outs DoubleRegs:$Rdd32),
   13909 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13910 "$Rdd32 = mpy($Rs32,$Rt32)",
   13911 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13912 let Inst{7-5} = 0b000;
   13913 let Inst{13-13} = 0b0;
   13914 let Inst{31-21} = 0b11100101000;
   13915 let prefersSlot3 = 1;
   13916 }
   13917 def M2_dpmpyuu_acc_s0 : HInst<
   13918 (outs DoubleRegs:$Rxx32),
   13919 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13920 "$Rxx32 += mpyu($Rs32,$Rt32)",
   13921 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13922 let Inst{7-5} = 0b000;
   13923 let Inst{13-13} = 0b0;
   13924 let Inst{31-21} = 0b11100111010;
   13925 let prefersSlot3 = 1;
   13926 let Constraints = "$Rxx32 = $Rxx32in";
   13927 }
   13928 def M2_dpmpyuu_nac_s0 : HInst<
   13929 (outs DoubleRegs:$Rxx32),
   13930 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   13931 "$Rxx32 -= mpyu($Rs32,$Rt32)",
   13932 tc_e913dc32, TypeM>, Enc_61f0b0 {
   13933 let Inst{7-5} = 0b000;
   13934 let Inst{13-13} = 0b0;
   13935 let Inst{31-21} = 0b11100111011;
   13936 let prefersSlot3 = 1;
   13937 let Constraints = "$Rxx32 = $Rxx32in";
   13938 }
   13939 def M2_dpmpyuu_s0 : HInst<
   13940 (outs DoubleRegs:$Rdd32),
   13941 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13942 "$Rdd32 = mpyu($Rs32,$Rt32)",
   13943 tc_8fd5f294, TypeM>, Enc_be32a5 {
   13944 let Inst{7-5} = 0b000;
   13945 let Inst{13-13} = 0b0;
   13946 let Inst{31-21} = 0b11100101010;
   13947 let prefersSlot3 = 1;
   13948 }
   13949 def M2_hmmpyh_rs1 : HInst<
   13950 (outs IntRegs:$Rd32),
   13951 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13952 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
   13953 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13954 let Inst{7-5} = 0b100;
   13955 let Inst{13-13} = 0b0;
   13956 let Inst{31-21} = 0b11101101101;
   13957 let hasNewValue = 1;
   13958 let opNewValue = 0;
   13959 let prefersSlot3 = 1;
   13960 let Defs = [USR_OVF];
   13961 }
   13962 def M2_hmmpyh_s1 : HInst<
   13963 (outs IntRegs:$Rd32),
   13964 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13965 "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
   13966 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13967 let Inst{7-5} = 0b000;
   13968 let Inst{13-13} = 0b0;
   13969 let Inst{31-21} = 0b11101101101;
   13970 let hasNewValue = 1;
   13971 let opNewValue = 0;
   13972 let prefersSlot3 = 1;
   13973 let Defs = [USR_OVF];
   13974 }
   13975 def M2_hmmpyl_rs1 : HInst<
   13976 (outs IntRegs:$Rd32),
   13977 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13978 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
   13979 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13980 let Inst{7-5} = 0b100;
   13981 let Inst{13-13} = 0b0;
   13982 let Inst{31-21} = 0b11101101111;
   13983 let hasNewValue = 1;
   13984 let opNewValue = 0;
   13985 let prefersSlot3 = 1;
   13986 let Defs = [USR_OVF];
   13987 }
   13988 def M2_hmmpyl_s1 : HInst<
   13989 (outs IntRegs:$Rd32),
   13990 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   13991 "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
   13992 tc_8fd5f294, TypeM>, Enc_5ab2be {
   13993 let Inst{7-5} = 0b001;
   13994 let Inst{13-13} = 0b0;
   13995 let Inst{31-21} = 0b11101101101;
   13996 let hasNewValue = 1;
   13997 let opNewValue = 0;
   13998 let prefersSlot3 = 1;
   13999 let Defs = [USR_OVF];
   14000 }
   14001 def M2_maci : HInst<
   14002 (outs IntRegs:$Rx32),
   14003 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14004 "$Rx32 += mpyi($Rs32,$Rt32)",
   14005 tc_e913dc32, TypeM>, Enc_2ae154, ImmRegRel {
   14006 let Inst{7-5} = 0b000;
   14007 let Inst{13-13} = 0b0;
   14008 let Inst{31-21} = 0b11101111000;
   14009 let hasNewValue = 1;
   14010 let opNewValue = 0;
   14011 let prefersSlot3 = 1;
   14012 let CextOpcode = "M2_maci";
   14013 let InputType = "reg";
   14014 let Constraints = "$Rx32 = $Rx32in";
   14015 }
   14016 def M2_macsin : HInst<
   14017 (outs IntRegs:$Rx32),
   14018 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
   14019 "$Rx32 -= mpyi($Rs32,#$Ii)",
   14020 tc_16d0d8d5, TypeM>, Enc_c90aca {
   14021 let Inst{13-13} = 0b0;
   14022 let Inst{31-21} = 0b11100001100;
   14023 let hasNewValue = 1;
   14024 let opNewValue = 0;
   14025 let prefersSlot3 = 1;
   14026 let InputType = "imm";
   14027 let isExtendable = 1;
   14028 let opExtendable = 3;
   14029 let isExtentSigned = 0;
   14030 let opExtentBits = 8;
   14031 let opExtentAlign = 0;
   14032 let Constraints = "$Rx32 = $Rx32in";
   14033 }
   14034 def M2_macsip : HInst<
   14035 (outs IntRegs:$Rx32),
   14036 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
   14037 "$Rx32 += mpyi($Rs32,#$Ii)",
   14038 tc_16d0d8d5, TypeM>, Enc_c90aca, ImmRegRel {
   14039 let Inst{13-13} = 0b0;
   14040 let Inst{31-21} = 0b11100001000;
   14041 let hasNewValue = 1;
   14042 let opNewValue = 0;
   14043 let prefersSlot3 = 1;
   14044 let CextOpcode = "M2_maci";
   14045 let InputType = "imm";
   14046 let isExtendable = 1;
   14047 let opExtendable = 3;
   14048 let isExtentSigned = 0;
   14049 let opExtentBits = 8;
   14050 let opExtentAlign = 0;
   14051 let Constraints = "$Rx32 = $Rx32in";
   14052 }
   14053 def M2_mmachs_rs0 : HInst<
   14054 (outs DoubleRegs:$Rxx32),
   14055 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14056 "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
   14057 tc_e913dc32, TypeM>, Enc_88c16c {
   14058 let Inst{7-5} = 0b111;
   14059 let Inst{13-13} = 0b0;
   14060 let Inst{31-21} = 0b11101010001;
   14061 let prefersSlot3 = 1;
   14062 let Defs = [USR_OVF];
   14063 let Constraints = "$Rxx32 = $Rxx32in";
   14064 }
   14065 def M2_mmachs_rs1 : HInst<
   14066 (outs DoubleRegs:$Rxx32),
   14067 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14068 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
   14069 tc_e913dc32, TypeM>, Enc_88c16c {
   14070 let Inst{7-5} = 0b111;
   14071 let Inst{13-13} = 0b0;
   14072 let Inst{31-21} = 0b11101010101;
   14073 let prefersSlot3 = 1;
   14074 let Defs = [USR_OVF];
   14075 let Constraints = "$Rxx32 = $Rxx32in";
   14076 }
   14077 def M2_mmachs_s0 : HInst<
   14078 (outs DoubleRegs:$Rxx32),
   14079 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14080 "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
   14081 tc_e913dc32, TypeM>, Enc_88c16c {
   14082 let Inst{7-5} = 0b111;
   14083 let Inst{13-13} = 0b0;
   14084 let Inst{31-21} = 0b11101010000;
   14085 let prefersSlot3 = 1;
   14086 let Defs = [USR_OVF];
   14087 let Constraints = "$Rxx32 = $Rxx32in";
   14088 }
   14089 def M2_mmachs_s1 : HInst<
   14090 (outs DoubleRegs:$Rxx32),
   14091 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14092 "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
   14093 tc_e913dc32, TypeM>, Enc_88c16c {
   14094 let Inst{7-5} = 0b111;
   14095 let Inst{13-13} = 0b0;
   14096 let Inst{31-21} = 0b11101010100;
   14097 let prefersSlot3 = 1;
   14098 let Defs = [USR_OVF];
   14099 let Constraints = "$Rxx32 = $Rxx32in";
   14100 }
   14101 def M2_mmacls_rs0 : HInst<
   14102 (outs DoubleRegs:$Rxx32),
   14103 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14104 "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
   14105 tc_e913dc32, TypeM>, Enc_88c16c {
   14106 let Inst{7-5} = 0b101;
   14107 let Inst{13-13} = 0b0;
   14108 let Inst{31-21} = 0b11101010001;
   14109 let prefersSlot3 = 1;
   14110 let Defs = [USR_OVF];
   14111 let Constraints = "$Rxx32 = $Rxx32in";
   14112 }
   14113 def M2_mmacls_rs1 : HInst<
   14114 (outs DoubleRegs:$Rxx32),
   14115 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14116 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
   14117 tc_e913dc32, TypeM>, Enc_88c16c {
   14118 let Inst{7-5} = 0b101;
   14119 let Inst{13-13} = 0b0;
   14120 let Inst{31-21} = 0b11101010101;
   14121 let prefersSlot3 = 1;
   14122 let Defs = [USR_OVF];
   14123 let Constraints = "$Rxx32 = $Rxx32in";
   14124 }
   14125 def M2_mmacls_s0 : HInst<
   14126 (outs DoubleRegs:$Rxx32),
   14127 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14128 "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
   14129 tc_e913dc32, TypeM>, Enc_88c16c {
   14130 let Inst{7-5} = 0b101;
   14131 let Inst{13-13} = 0b0;
   14132 let Inst{31-21} = 0b11101010000;
   14133 let prefersSlot3 = 1;
   14134 let Defs = [USR_OVF];
   14135 let Constraints = "$Rxx32 = $Rxx32in";
   14136 }
   14137 def M2_mmacls_s1 : HInst<
   14138 (outs DoubleRegs:$Rxx32),
   14139 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14140 "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
   14141 tc_e913dc32, TypeM>, Enc_88c16c {
   14142 let Inst{7-5} = 0b101;
   14143 let Inst{13-13} = 0b0;
   14144 let Inst{31-21} = 0b11101010100;
   14145 let prefersSlot3 = 1;
   14146 let Defs = [USR_OVF];
   14147 let Constraints = "$Rxx32 = $Rxx32in";
   14148 }
   14149 def M2_mmacuhs_rs0 : HInst<
   14150 (outs DoubleRegs:$Rxx32),
   14151 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14152 "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
   14153 tc_e913dc32, TypeM>, Enc_88c16c {
   14154 let Inst{7-5} = 0b111;
   14155 let Inst{13-13} = 0b0;
   14156 let Inst{31-21} = 0b11101010011;
   14157 let prefersSlot3 = 1;
   14158 let Defs = [USR_OVF];
   14159 let Constraints = "$Rxx32 = $Rxx32in";
   14160 }
   14161 def M2_mmacuhs_rs1 : HInst<
   14162 (outs DoubleRegs:$Rxx32),
   14163 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14164 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
   14165 tc_e913dc32, TypeM>, Enc_88c16c {
   14166 let Inst{7-5} = 0b111;
   14167 let Inst{13-13} = 0b0;
   14168 let Inst{31-21} = 0b11101010111;
   14169 let prefersSlot3 = 1;
   14170 let Defs = [USR_OVF];
   14171 let Constraints = "$Rxx32 = $Rxx32in";
   14172 }
   14173 def M2_mmacuhs_s0 : HInst<
   14174 (outs DoubleRegs:$Rxx32),
   14175 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14176 "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
   14177 tc_e913dc32, TypeM>, Enc_88c16c {
   14178 let Inst{7-5} = 0b111;
   14179 let Inst{13-13} = 0b0;
   14180 let Inst{31-21} = 0b11101010010;
   14181 let prefersSlot3 = 1;
   14182 let Defs = [USR_OVF];
   14183 let Constraints = "$Rxx32 = $Rxx32in";
   14184 }
   14185 def M2_mmacuhs_s1 : HInst<
   14186 (outs DoubleRegs:$Rxx32),
   14187 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14188 "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
   14189 tc_e913dc32, TypeM>, Enc_88c16c {
   14190 let Inst{7-5} = 0b111;
   14191 let Inst{13-13} = 0b0;
   14192 let Inst{31-21} = 0b11101010110;
   14193 let prefersSlot3 = 1;
   14194 let Defs = [USR_OVF];
   14195 let Constraints = "$Rxx32 = $Rxx32in";
   14196 }
   14197 def M2_mmaculs_rs0 : HInst<
   14198 (outs DoubleRegs:$Rxx32),
   14199 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14200 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
   14201 tc_e913dc32, TypeM>, Enc_88c16c {
   14202 let Inst{7-5} = 0b101;
   14203 let Inst{13-13} = 0b0;
   14204 let Inst{31-21} = 0b11101010011;
   14205 let prefersSlot3 = 1;
   14206 let Defs = [USR_OVF];
   14207 let Constraints = "$Rxx32 = $Rxx32in";
   14208 }
   14209 def M2_mmaculs_rs1 : HInst<
   14210 (outs DoubleRegs:$Rxx32),
   14211 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14212 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
   14213 tc_e913dc32, TypeM>, Enc_88c16c {
   14214 let Inst{7-5} = 0b101;
   14215 let Inst{13-13} = 0b0;
   14216 let Inst{31-21} = 0b11101010111;
   14217 let prefersSlot3 = 1;
   14218 let Defs = [USR_OVF];
   14219 let Constraints = "$Rxx32 = $Rxx32in";
   14220 }
   14221 def M2_mmaculs_s0 : HInst<
   14222 (outs DoubleRegs:$Rxx32),
   14223 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14224 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
   14225 tc_e913dc32, TypeM>, Enc_88c16c {
   14226 let Inst{7-5} = 0b101;
   14227 let Inst{13-13} = 0b0;
   14228 let Inst{31-21} = 0b11101010010;
   14229 let prefersSlot3 = 1;
   14230 let Defs = [USR_OVF];
   14231 let Constraints = "$Rxx32 = $Rxx32in";
   14232 }
   14233 def M2_mmaculs_s1 : HInst<
   14234 (outs DoubleRegs:$Rxx32),
   14235 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14236 "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
   14237 tc_e913dc32, TypeM>, Enc_88c16c {
   14238 let Inst{7-5} = 0b101;
   14239 let Inst{13-13} = 0b0;
   14240 let Inst{31-21} = 0b11101010110;
   14241 let prefersSlot3 = 1;
   14242 let Defs = [USR_OVF];
   14243 let Constraints = "$Rxx32 = $Rxx32in";
   14244 }
   14245 def M2_mmpyh_rs0 : HInst<
   14246 (outs DoubleRegs:$Rdd32),
   14247 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14248 "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
   14249 tc_8fd5f294, TypeM>, Enc_a56825 {
   14250 let Inst{7-5} = 0b111;
   14251 let Inst{13-13} = 0b0;
   14252 let Inst{31-21} = 0b11101000001;
   14253 let prefersSlot3 = 1;
   14254 let Defs = [USR_OVF];
   14255 }
   14256 def M2_mmpyh_rs1 : HInst<
   14257 (outs DoubleRegs:$Rdd32),
   14258 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14259 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
   14260 tc_8fd5f294, TypeM>, Enc_a56825 {
   14261 let Inst{7-5} = 0b111;
   14262 let Inst{13-13} = 0b0;
   14263 let Inst{31-21} = 0b11101000101;
   14264 let prefersSlot3 = 1;
   14265 let Defs = [USR_OVF];
   14266 }
   14267 def M2_mmpyh_s0 : HInst<
   14268 (outs DoubleRegs:$Rdd32),
   14269 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14270 "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
   14271 tc_8fd5f294, TypeM>, Enc_a56825 {
   14272 let Inst{7-5} = 0b111;
   14273 let Inst{13-13} = 0b0;
   14274 let Inst{31-21} = 0b11101000000;
   14275 let prefersSlot3 = 1;
   14276 let Defs = [USR_OVF];
   14277 }
   14278 def M2_mmpyh_s1 : HInst<
   14279 (outs DoubleRegs:$Rdd32),
   14280 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14281 "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
   14282 tc_8fd5f294, TypeM>, Enc_a56825 {
   14283 let Inst{7-5} = 0b111;
   14284 let Inst{13-13} = 0b0;
   14285 let Inst{31-21} = 0b11101000100;
   14286 let prefersSlot3 = 1;
   14287 let Defs = [USR_OVF];
   14288 }
   14289 def M2_mmpyl_rs0 : HInst<
   14290 (outs DoubleRegs:$Rdd32),
   14291 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14292 "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
   14293 tc_8fd5f294, TypeM>, Enc_a56825 {
   14294 let Inst{7-5} = 0b101;
   14295 let Inst{13-13} = 0b0;
   14296 let Inst{31-21} = 0b11101000001;
   14297 let prefersSlot3 = 1;
   14298 let Defs = [USR_OVF];
   14299 }
   14300 def M2_mmpyl_rs1 : HInst<
   14301 (outs DoubleRegs:$Rdd32),
   14302 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14303 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
   14304 tc_8fd5f294, TypeM>, Enc_a56825 {
   14305 let Inst{7-5} = 0b101;
   14306 let Inst{13-13} = 0b0;
   14307 let Inst{31-21} = 0b11101000101;
   14308 let prefersSlot3 = 1;
   14309 let Defs = [USR_OVF];
   14310 }
   14311 def M2_mmpyl_s0 : HInst<
   14312 (outs DoubleRegs:$Rdd32),
   14313 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14314 "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
   14315 tc_8fd5f294, TypeM>, Enc_a56825 {
   14316 let Inst{7-5} = 0b101;
   14317 let Inst{13-13} = 0b0;
   14318 let Inst{31-21} = 0b11101000000;
   14319 let prefersSlot3 = 1;
   14320 let Defs = [USR_OVF];
   14321 }
   14322 def M2_mmpyl_s1 : HInst<
   14323 (outs DoubleRegs:$Rdd32),
   14324 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14325 "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
   14326 tc_8fd5f294, TypeM>, Enc_a56825 {
   14327 let Inst{7-5} = 0b101;
   14328 let Inst{13-13} = 0b0;
   14329 let Inst{31-21} = 0b11101000100;
   14330 let prefersSlot3 = 1;
   14331 let Defs = [USR_OVF];
   14332 }
   14333 def M2_mmpyuh_rs0 : HInst<
   14334 (outs DoubleRegs:$Rdd32),
   14335 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14336 "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
   14337 tc_8fd5f294, TypeM>, Enc_a56825 {
   14338 let Inst{7-5} = 0b111;
   14339 let Inst{13-13} = 0b0;
   14340 let Inst{31-21} = 0b11101000011;
   14341 let prefersSlot3 = 1;
   14342 let Defs = [USR_OVF];
   14343 }
   14344 def M2_mmpyuh_rs1 : HInst<
   14345 (outs DoubleRegs:$Rdd32),
   14346 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14347 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
   14348 tc_8fd5f294, TypeM>, Enc_a56825 {
   14349 let Inst{7-5} = 0b111;
   14350 let Inst{13-13} = 0b0;
   14351 let Inst{31-21} = 0b11101000111;
   14352 let prefersSlot3 = 1;
   14353 let Defs = [USR_OVF];
   14354 }
   14355 def M2_mmpyuh_s0 : HInst<
   14356 (outs DoubleRegs:$Rdd32),
   14357 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14358 "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
   14359 tc_8fd5f294, TypeM>, Enc_a56825 {
   14360 let Inst{7-5} = 0b111;
   14361 let Inst{13-13} = 0b0;
   14362 let Inst{31-21} = 0b11101000010;
   14363 let prefersSlot3 = 1;
   14364 let Defs = [USR_OVF];
   14365 }
   14366 def M2_mmpyuh_s1 : HInst<
   14367 (outs DoubleRegs:$Rdd32),
   14368 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14369 "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
   14370 tc_8fd5f294, TypeM>, Enc_a56825 {
   14371 let Inst{7-5} = 0b111;
   14372 let Inst{13-13} = 0b0;
   14373 let Inst{31-21} = 0b11101000110;
   14374 let prefersSlot3 = 1;
   14375 let Defs = [USR_OVF];
   14376 }
   14377 def M2_mmpyul_rs0 : HInst<
   14378 (outs DoubleRegs:$Rdd32),
   14379 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14380 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
   14381 tc_8fd5f294, TypeM>, Enc_a56825 {
   14382 let Inst{7-5} = 0b101;
   14383 let Inst{13-13} = 0b0;
   14384 let Inst{31-21} = 0b11101000011;
   14385 let prefersSlot3 = 1;
   14386 let Defs = [USR_OVF];
   14387 }
   14388 def M2_mmpyul_rs1 : HInst<
   14389 (outs DoubleRegs:$Rdd32),
   14390 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14391 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
   14392 tc_8fd5f294, TypeM>, Enc_a56825 {
   14393 let Inst{7-5} = 0b101;
   14394 let Inst{13-13} = 0b0;
   14395 let Inst{31-21} = 0b11101000111;
   14396 let prefersSlot3 = 1;
   14397 let Defs = [USR_OVF];
   14398 }
   14399 def M2_mmpyul_s0 : HInst<
   14400 (outs DoubleRegs:$Rdd32),
   14401 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14402 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
   14403 tc_8fd5f294, TypeM>, Enc_a56825 {
   14404 let Inst{7-5} = 0b101;
   14405 let Inst{13-13} = 0b0;
   14406 let Inst{31-21} = 0b11101000010;
   14407 let prefersSlot3 = 1;
   14408 let Defs = [USR_OVF];
   14409 }
   14410 def M2_mmpyul_s1 : HInst<
   14411 (outs DoubleRegs:$Rdd32),
   14412 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   14413 "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
   14414 tc_8fd5f294, TypeM>, Enc_a56825 {
   14415 let Inst{7-5} = 0b101;
   14416 let Inst{13-13} = 0b0;
   14417 let Inst{31-21} = 0b11101000110;
   14418 let prefersSlot3 = 1;
   14419 let Defs = [USR_OVF];
   14420 }
   14421 def M2_mpy_acc_hh_s0 : HInst<
   14422 (outs IntRegs:$Rx32),
   14423 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14424 "$Rx32 += mpy($Rs32.h,$Rt32.h)",
   14425 tc_e913dc32, TypeM>, Enc_2ae154 {
   14426 let Inst{7-5} = 0b011;
   14427 let Inst{13-13} = 0b0;
   14428 let Inst{31-21} = 0b11101110000;
   14429 let hasNewValue = 1;
   14430 let opNewValue = 0;
   14431 let prefersSlot3 = 1;
   14432 let Constraints = "$Rx32 = $Rx32in";
   14433 }
   14434 def M2_mpy_acc_hh_s1 : HInst<
   14435 (outs IntRegs:$Rx32),
   14436 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14437 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
   14438 tc_e913dc32, TypeM>, Enc_2ae154 {
   14439 let Inst{7-5} = 0b011;
   14440 let Inst{13-13} = 0b0;
   14441 let Inst{31-21} = 0b11101110100;
   14442 let hasNewValue = 1;
   14443 let opNewValue = 0;
   14444 let prefersSlot3 = 1;
   14445 let Constraints = "$Rx32 = $Rx32in";
   14446 }
   14447 def M2_mpy_acc_hl_s0 : HInst<
   14448 (outs IntRegs:$Rx32),
   14449 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14450 "$Rx32 += mpy($Rs32.h,$Rt32.l)",
   14451 tc_e913dc32, TypeM>, Enc_2ae154 {
   14452 let Inst{7-5} = 0b010;
   14453 let Inst{13-13} = 0b0;
   14454 let Inst{31-21} = 0b11101110000;
   14455 let hasNewValue = 1;
   14456 let opNewValue = 0;
   14457 let prefersSlot3 = 1;
   14458 let Constraints = "$Rx32 = $Rx32in";
   14459 }
   14460 def M2_mpy_acc_hl_s1 : HInst<
   14461 (outs IntRegs:$Rx32),
   14462 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14463 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
   14464 tc_e913dc32, TypeM>, Enc_2ae154 {
   14465 let Inst{7-5} = 0b010;
   14466 let Inst{13-13} = 0b0;
   14467 let Inst{31-21} = 0b11101110100;
   14468 let hasNewValue = 1;
   14469 let opNewValue = 0;
   14470 let prefersSlot3 = 1;
   14471 let Constraints = "$Rx32 = $Rx32in";
   14472 }
   14473 def M2_mpy_acc_lh_s0 : HInst<
   14474 (outs IntRegs:$Rx32),
   14475 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14476 "$Rx32 += mpy($Rs32.l,$Rt32.h)",
   14477 tc_e913dc32, TypeM>, Enc_2ae154 {
   14478 let Inst{7-5} = 0b001;
   14479 let Inst{13-13} = 0b0;
   14480 let Inst{31-21} = 0b11101110000;
   14481 let hasNewValue = 1;
   14482 let opNewValue = 0;
   14483 let prefersSlot3 = 1;
   14484 let Constraints = "$Rx32 = $Rx32in";
   14485 }
   14486 def M2_mpy_acc_lh_s1 : HInst<
   14487 (outs IntRegs:$Rx32),
   14488 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14489 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
   14490 tc_e913dc32, TypeM>, Enc_2ae154 {
   14491 let Inst{7-5} = 0b001;
   14492 let Inst{13-13} = 0b0;
   14493 let Inst{31-21} = 0b11101110100;
   14494 let hasNewValue = 1;
   14495 let opNewValue = 0;
   14496 let prefersSlot3 = 1;
   14497 let Constraints = "$Rx32 = $Rx32in";
   14498 }
   14499 def M2_mpy_acc_ll_s0 : HInst<
   14500 (outs IntRegs:$Rx32),
   14501 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14502 "$Rx32 += mpy($Rs32.l,$Rt32.l)",
   14503 tc_e913dc32, TypeM>, Enc_2ae154 {
   14504 let Inst{7-5} = 0b000;
   14505 let Inst{13-13} = 0b0;
   14506 let Inst{31-21} = 0b11101110000;
   14507 let hasNewValue = 1;
   14508 let opNewValue = 0;
   14509 let prefersSlot3 = 1;
   14510 let Constraints = "$Rx32 = $Rx32in";
   14511 }
   14512 def M2_mpy_acc_ll_s1 : HInst<
   14513 (outs IntRegs:$Rx32),
   14514 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14515 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
   14516 tc_e913dc32, TypeM>, Enc_2ae154 {
   14517 let Inst{7-5} = 0b000;
   14518 let Inst{13-13} = 0b0;
   14519 let Inst{31-21} = 0b11101110100;
   14520 let hasNewValue = 1;
   14521 let opNewValue = 0;
   14522 let prefersSlot3 = 1;
   14523 let Constraints = "$Rx32 = $Rx32in";
   14524 }
   14525 def M2_mpy_acc_sat_hh_s0 : HInst<
   14526 (outs IntRegs:$Rx32),
   14527 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14528 "$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
   14529 tc_e913dc32, TypeM>, Enc_2ae154 {
   14530 let Inst{7-5} = 0b111;
   14531 let Inst{13-13} = 0b0;
   14532 let Inst{31-21} = 0b11101110000;
   14533 let hasNewValue = 1;
   14534 let opNewValue = 0;
   14535 let prefersSlot3 = 1;
   14536 let Defs = [USR_OVF];
   14537 let Constraints = "$Rx32 = $Rx32in";
   14538 }
   14539 def M2_mpy_acc_sat_hh_s1 : HInst<
   14540 (outs IntRegs:$Rx32),
   14541 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14542 "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
   14543 tc_e913dc32, TypeM>, Enc_2ae154 {
   14544 let Inst{7-5} = 0b111;
   14545 let Inst{13-13} = 0b0;
   14546 let Inst{31-21} = 0b11101110100;
   14547 let hasNewValue = 1;
   14548 let opNewValue = 0;
   14549 let prefersSlot3 = 1;
   14550 let Defs = [USR_OVF];
   14551 let Constraints = "$Rx32 = $Rx32in";
   14552 }
   14553 def M2_mpy_acc_sat_hl_s0 : HInst<
   14554 (outs IntRegs:$Rx32),
   14555 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14556 "$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
   14557 tc_e913dc32, TypeM>, Enc_2ae154 {
   14558 let Inst{7-5} = 0b110;
   14559 let Inst{13-13} = 0b0;
   14560 let Inst{31-21} = 0b11101110000;
   14561 let hasNewValue = 1;
   14562 let opNewValue = 0;
   14563 let prefersSlot3 = 1;
   14564 let Defs = [USR_OVF];
   14565 let Constraints = "$Rx32 = $Rx32in";
   14566 }
   14567 def M2_mpy_acc_sat_hl_s1 : HInst<
   14568 (outs IntRegs:$Rx32),
   14569 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14570 "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
   14571 tc_e913dc32, TypeM>, Enc_2ae154 {
   14572 let Inst{7-5} = 0b110;
   14573 let Inst{13-13} = 0b0;
   14574 let Inst{31-21} = 0b11101110100;
   14575 let hasNewValue = 1;
   14576 let opNewValue = 0;
   14577 let prefersSlot3 = 1;
   14578 let Defs = [USR_OVF];
   14579 let Constraints = "$Rx32 = $Rx32in";
   14580 }
   14581 def M2_mpy_acc_sat_lh_s0 : HInst<
   14582 (outs IntRegs:$Rx32),
   14583 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14584 "$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
   14585 tc_e913dc32, TypeM>, Enc_2ae154 {
   14586 let Inst{7-5} = 0b101;
   14587 let Inst{13-13} = 0b0;
   14588 let Inst{31-21} = 0b11101110000;
   14589 let hasNewValue = 1;
   14590 let opNewValue = 0;
   14591 let prefersSlot3 = 1;
   14592 let Defs = [USR_OVF];
   14593 let Constraints = "$Rx32 = $Rx32in";
   14594 }
   14595 def M2_mpy_acc_sat_lh_s1 : HInst<
   14596 (outs IntRegs:$Rx32),
   14597 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14598 "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
   14599 tc_e913dc32, TypeM>, Enc_2ae154 {
   14600 let Inst{7-5} = 0b101;
   14601 let Inst{13-13} = 0b0;
   14602 let Inst{31-21} = 0b11101110100;
   14603 let hasNewValue = 1;
   14604 let opNewValue = 0;
   14605 let prefersSlot3 = 1;
   14606 let Defs = [USR_OVF];
   14607 let Constraints = "$Rx32 = $Rx32in";
   14608 }
   14609 def M2_mpy_acc_sat_ll_s0 : HInst<
   14610 (outs IntRegs:$Rx32),
   14611 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14612 "$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
   14613 tc_e913dc32, TypeM>, Enc_2ae154 {
   14614 let Inst{7-5} = 0b100;
   14615 let Inst{13-13} = 0b0;
   14616 let Inst{31-21} = 0b11101110000;
   14617 let hasNewValue = 1;
   14618 let opNewValue = 0;
   14619 let prefersSlot3 = 1;
   14620 let Defs = [USR_OVF];
   14621 let Constraints = "$Rx32 = $Rx32in";
   14622 }
   14623 def M2_mpy_acc_sat_ll_s1 : HInst<
   14624 (outs IntRegs:$Rx32),
   14625 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14626 "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
   14627 tc_e913dc32, TypeM>, Enc_2ae154 {
   14628 let Inst{7-5} = 0b100;
   14629 let Inst{13-13} = 0b0;
   14630 let Inst{31-21} = 0b11101110100;
   14631 let hasNewValue = 1;
   14632 let opNewValue = 0;
   14633 let prefersSlot3 = 1;
   14634 let Defs = [USR_OVF];
   14635 let Constraints = "$Rx32 = $Rx32in";
   14636 }
   14637 def M2_mpy_hh_s0 : HInst<
   14638 (outs IntRegs:$Rd32),
   14639 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14640 "$Rd32 = mpy($Rs32.h,$Rt32.h)",
   14641 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14642 let Inst{7-5} = 0b011;
   14643 let Inst{13-13} = 0b0;
   14644 let Inst{31-21} = 0b11101100000;
   14645 let hasNewValue = 1;
   14646 let opNewValue = 0;
   14647 let prefersSlot3 = 1;
   14648 }
   14649 def M2_mpy_hh_s1 : HInst<
   14650 (outs IntRegs:$Rd32),
   14651 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14652 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
   14653 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14654 let Inst{7-5} = 0b011;
   14655 let Inst{13-13} = 0b0;
   14656 let Inst{31-21} = 0b11101100100;
   14657 let hasNewValue = 1;
   14658 let opNewValue = 0;
   14659 let prefersSlot3 = 1;
   14660 }
   14661 def M2_mpy_hl_s0 : HInst<
   14662 (outs IntRegs:$Rd32),
   14663 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14664 "$Rd32 = mpy($Rs32.h,$Rt32.l)",
   14665 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14666 let Inst{7-5} = 0b010;
   14667 let Inst{13-13} = 0b0;
   14668 let Inst{31-21} = 0b11101100000;
   14669 let hasNewValue = 1;
   14670 let opNewValue = 0;
   14671 let prefersSlot3 = 1;
   14672 }
   14673 def M2_mpy_hl_s1 : HInst<
   14674 (outs IntRegs:$Rd32),
   14675 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14676 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
   14677 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14678 let Inst{7-5} = 0b010;
   14679 let Inst{13-13} = 0b0;
   14680 let Inst{31-21} = 0b11101100100;
   14681 let hasNewValue = 1;
   14682 let opNewValue = 0;
   14683 let prefersSlot3 = 1;
   14684 }
   14685 def M2_mpy_lh_s0 : HInst<
   14686 (outs IntRegs:$Rd32),
   14687 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14688 "$Rd32 = mpy($Rs32.l,$Rt32.h)",
   14689 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14690 let Inst{7-5} = 0b001;
   14691 let Inst{13-13} = 0b0;
   14692 let Inst{31-21} = 0b11101100000;
   14693 let hasNewValue = 1;
   14694 let opNewValue = 0;
   14695 let prefersSlot3 = 1;
   14696 }
   14697 def M2_mpy_lh_s1 : HInst<
   14698 (outs IntRegs:$Rd32),
   14699 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14700 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
   14701 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14702 let Inst{7-5} = 0b001;
   14703 let Inst{13-13} = 0b0;
   14704 let Inst{31-21} = 0b11101100100;
   14705 let hasNewValue = 1;
   14706 let opNewValue = 0;
   14707 let prefersSlot3 = 1;
   14708 }
   14709 def M2_mpy_ll_s0 : HInst<
   14710 (outs IntRegs:$Rd32),
   14711 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14712 "$Rd32 = mpy($Rs32.l,$Rt32.l)",
   14713 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14714 let Inst{7-5} = 0b000;
   14715 let Inst{13-13} = 0b0;
   14716 let Inst{31-21} = 0b11101100000;
   14717 let hasNewValue = 1;
   14718 let opNewValue = 0;
   14719 let prefersSlot3 = 1;
   14720 }
   14721 def M2_mpy_ll_s1 : HInst<
   14722 (outs IntRegs:$Rd32),
   14723 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14724 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
   14725 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14726 let Inst{7-5} = 0b000;
   14727 let Inst{13-13} = 0b0;
   14728 let Inst{31-21} = 0b11101100100;
   14729 let hasNewValue = 1;
   14730 let opNewValue = 0;
   14731 let prefersSlot3 = 1;
   14732 }
   14733 def M2_mpy_nac_hh_s0 : HInst<
   14734 (outs IntRegs:$Rx32),
   14735 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14736 "$Rx32 -= mpy($Rs32.h,$Rt32.h)",
   14737 tc_e913dc32, TypeM>, Enc_2ae154 {
   14738 let Inst{7-5} = 0b011;
   14739 let Inst{13-13} = 0b0;
   14740 let Inst{31-21} = 0b11101110001;
   14741 let hasNewValue = 1;
   14742 let opNewValue = 0;
   14743 let prefersSlot3 = 1;
   14744 let Constraints = "$Rx32 = $Rx32in";
   14745 }
   14746 def M2_mpy_nac_hh_s1 : HInst<
   14747 (outs IntRegs:$Rx32),
   14748 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14749 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
   14750 tc_e913dc32, TypeM>, Enc_2ae154 {
   14751 let Inst{7-5} = 0b011;
   14752 let Inst{13-13} = 0b0;
   14753 let Inst{31-21} = 0b11101110101;
   14754 let hasNewValue = 1;
   14755 let opNewValue = 0;
   14756 let prefersSlot3 = 1;
   14757 let Constraints = "$Rx32 = $Rx32in";
   14758 }
   14759 def M2_mpy_nac_hl_s0 : HInst<
   14760 (outs IntRegs:$Rx32),
   14761 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14762 "$Rx32 -= mpy($Rs32.h,$Rt32.l)",
   14763 tc_e913dc32, TypeM>, Enc_2ae154 {
   14764 let Inst{7-5} = 0b010;
   14765 let Inst{13-13} = 0b0;
   14766 let Inst{31-21} = 0b11101110001;
   14767 let hasNewValue = 1;
   14768 let opNewValue = 0;
   14769 let prefersSlot3 = 1;
   14770 let Constraints = "$Rx32 = $Rx32in";
   14771 }
   14772 def M2_mpy_nac_hl_s1 : HInst<
   14773 (outs IntRegs:$Rx32),
   14774 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14775 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
   14776 tc_e913dc32, TypeM>, Enc_2ae154 {
   14777 let Inst{7-5} = 0b010;
   14778 let Inst{13-13} = 0b0;
   14779 let Inst{31-21} = 0b11101110101;
   14780 let hasNewValue = 1;
   14781 let opNewValue = 0;
   14782 let prefersSlot3 = 1;
   14783 let Constraints = "$Rx32 = $Rx32in";
   14784 }
   14785 def M2_mpy_nac_lh_s0 : HInst<
   14786 (outs IntRegs:$Rx32),
   14787 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14788 "$Rx32 -= mpy($Rs32.l,$Rt32.h)",
   14789 tc_e913dc32, TypeM>, Enc_2ae154 {
   14790 let Inst{7-5} = 0b001;
   14791 let Inst{13-13} = 0b0;
   14792 let Inst{31-21} = 0b11101110001;
   14793 let hasNewValue = 1;
   14794 let opNewValue = 0;
   14795 let prefersSlot3 = 1;
   14796 let Constraints = "$Rx32 = $Rx32in";
   14797 }
   14798 def M2_mpy_nac_lh_s1 : HInst<
   14799 (outs IntRegs:$Rx32),
   14800 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14801 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
   14802 tc_e913dc32, TypeM>, Enc_2ae154 {
   14803 let Inst{7-5} = 0b001;
   14804 let Inst{13-13} = 0b0;
   14805 let Inst{31-21} = 0b11101110101;
   14806 let hasNewValue = 1;
   14807 let opNewValue = 0;
   14808 let prefersSlot3 = 1;
   14809 let Constraints = "$Rx32 = $Rx32in";
   14810 }
   14811 def M2_mpy_nac_ll_s0 : HInst<
   14812 (outs IntRegs:$Rx32),
   14813 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14814 "$Rx32 -= mpy($Rs32.l,$Rt32.l)",
   14815 tc_e913dc32, TypeM>, Enc_2ae154 {
   14816 let Inst{7-5} = 0b000;
   14817 let Inst{13-13} = 0b0;
   14818 let Inst{31-21} = 0b11101110001;
   14819 let hasNewValue = 1;
   14820 let opNewValue = 0;
   14821 let prefersSlot3 = 1;
   14822 let Constraints = "$Rx32 = $Rx32in";
   14823 }
   14824 def M2_mpy_nac_ll_s1 : HInst<
   14825 (outs IntRegs:$Rx32),
   14826 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14827 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
   14828 tc_e913dc32, TypeM>, Enc_2ae154 {
   14829 let Inst{7-5} = 0b000;
   14830 let Inst{13-13} = 0b0;
   14831 let Inst{31-21} = 0b11101110101;
   14832 let hasNewValue = 1;
   14833 let opNewValue = 0;
   14834 let prefersSlot3 = 1;
   14835 let Constraints = "$Rx32 = $Rx32in";
   14836 }
   14837 def M2_mpy_nac_sat_hh_s0 : HInst<
   14838 (outs IntRegs:$Rx32),
   14839 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14840 "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
   14841 tc_e913dc32, TypeM>, Enc_2ae154 {
   14842 let Inst{7-5} = 0b111;
   14843 let Inst{13-13} = 0b0;
   14844 let Inst{31-21} = 0b11101110001;
   14845 let hasNewValue = 1;
   14846 let opNewValue = 0;
   14847 let prefersSlot3 = 1;
   14848 let Defs = [USR_OVF];
   14849 let Constraints = "$Rx32 = $Rx32in";
   14850 }
   14851 def M2_mpy_nac_sat_hh_s1 : HInst<
   14852 (outs IntRegs:$Rx32),
   14853 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14854 "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
   14855 tc_e913dc32, TypeM>, Enc_2ae154 {
   14856 let Inst{7-5} = 0b111;
   14857 let Inst{13-13} = 0b0;
   14858 let Inst{31-21} = 0b11101110101;
   14859 let hasNewValue = 1;
   14860 let opNewValue = 0;
   14861 let prefersSlot3 = 1;
   14862 let Defs = [USR_OVF];
   14863 let Constraints = "$Rx32 = $Rx32in";
   14864 }
   14865 def M2_mpy_nac_sat_hl_s0 : HInst<
   14866 (outs IntRegs:$Rx32),
   14867 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14868 "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
   14869 tc_e913dc32, TypeM>, Enc_2ae154 {
   14870 let Inst{7-5} = 0b110;
   14871 let Inst{13-13} = 0b0;
   14872 let Inst{31-21} = 0b11101110001;
   14873 let hasNewValue = 1;
   14874 let opNewValue = 0;
   14875 let prefersSlot3 = 1;
   14876 let Defs = [USR_OVF];
   14877 let Constraints = "$Rx32 = $Rx32in";
   14878 }
   14879 def M2_mpy_nac_sat_hl_s1 : HInst<
   14880 (outs IntRegs:$Rx32),
   14881 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14882 "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
   14883 tc_e913dc32, TypeM>, Enc_2ae154 {
   14884 let Inst{7-5} = 0b110;
   14885 let Inst{13-13} = 0b0;
   14886 let Inst{31-21} = 0b11101110101;
   14887 let hasNewValue = 1;
   14888 let opNewValue = 0;
   14889 let prefersSlot3 = 1;
   14890 let Defs = [USR_OVF];
   14891 let Constraints = "$Rx32 = $Rx32in";
   14892 }
   14893 def M2_mpy_nac_sat_lh_s0 : HInst<
   14894 (outs IntRegs:$Rx32),
   14895 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14896 "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
   14897 tc_e913dc32, TypeM>, Enc_2ae154 {
   14898 let Inst{7-5} = 0b101;
   14899 let Inst{13-13} = 0b0;
   14900 let Inst{31-21} = 0b11101110001;
   14901 let hasNewValue = 1;
   14902 let opNewValue = 0;
   14903 let prefersSlot3 = 1;
   14904 let Defs = [USR_OVF];
   14905 let Constraints = "$Rx32 = $Rx32in";
   14906 }
   14907 def M2_mpy_nac_sat_lh_s1 : HInst<
   14908 (outs IntRegs:$Rx32),
   14909 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14910 "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
   14911 tc_e913dc32, TypeM>, Enc_2ae154 {
   14912 let Inst{7-5} = 0b101;
   14913 let Inst{13-13} = 0b0;
   14914 let Inst{31-21} = 0b11101110101;
   14915 let hasNewValue = 1;
   14916 let opNewValue = 0;
   14917 let prefersSlot3 = 1;
   14918 let Defs = [USR_OVF];
   14919 let Constraints = "$Rx32 = $Rx32in";
   14920 }
   14921 def M2_mpy_nac_sat_ll_s0 : HInst<
   14922 (outs IntRegs:$Rx32),
   14923 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14924 "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
   14925 tc_e913dc32, TypeM>, Enc_2ae154 {
   14926 let Inst{7-5} = 0b100;
   14927 let Inst{13-13} = 0b0;
   14928 let Inst{31-21} = 0b11101110001;
   14929 let hasNewValue = 1;
   14930 let opNewValue = 0;
   14931 let prefersSlot3 = 1;
   14932 let Defs = [USR_OVF];
   14933 let Constraints = "$Rx32 = $Rx32in";
   14934 }
   14935 def M2_mpy_nac_sat_ll_s1 : HInst<
   14936 (outs IntRegs:$Rx32),
   14937 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   14938 "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
   14939 tc_e913dc32, TypeM>, Enc_2ae154 {
   14940 let Inst{7-5} = 0b100;
   14941 let Inst{13-13} = 0b0;
   14942 let Inst{31-21} = 0b11101110101;
   14943 let hasNewValue = 1;
   14944 let opNewValue = 0;
   14945 let prefersSlot3 = 1;
   14946 let Defs = [USR_OVF];
   14947 let Constraints = "$Rx32 = $Rx32in";
   14948 }
   14949 def M2_mpy_rnd_hh_s0 : HInst<
   14950 (outs IntRegs:$Rd32),
   14951 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14952 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
   14953 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14954 let Inst{7-5} = 0b011;
   14955 let Inst{13-13} = 0b0;
   14956 let Inst{31-21} = 0b11101100001;
   14957 let hasNewValue = 1;
   14958 let opNewValue = 0;
   14959 let prefersSlot3 = 1;
   14960 }
   14961 def M2_mpy_rnd_hh_s1 : HInst<
   14962 (outs IntRegs:$Rd32),
   14963 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14964 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
   14965 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14966 let Inst{7-5} = 0b011;
   14967 let Inst{13-13} = 0b0;
   14968 let Inst{31-21} = 0b11101100101;
   14969 let hasNewValue = 1;
   14970 let opNewValue = 0;
   14971 let prefersSlot3 = 1;
   14972 }
   14973 def M2_mpy_rnd_hl_s0 : HInst<
   14974 (outs IntRegs:$Rd32),
   14975 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14976 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
   14977 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14978 let Inst{7-5} = 0b010;
   14979 let Inst{13-13} = 0b0;
   14980 let Inst{31-21} = 0b11101100001;
   14981 let hasNewValue = 1;
   14982 let opNewValue = 0;
   14983 let prefersSlot3 = 1;
   14984 }
   14985 def M2_mpy_rnd_hl_s1 : HInst<
   14986 (outs IntRegs:$Rd32),
   14987 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   14988 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
   14989 tc_8fd5f294, TypeM>, Enc_5ab2be {
   14990 let Inst{7-5} = 0b010;
   14991 let Inst{13-13} = 0b0;
   14992 let Inst{31-21} = 0b11101100101;
   14993 let hasNewValue = 1;
   14994 let opNewValue = 0;
   14995 let prefersSlot3 = 1;
   14996 }
   14997 def M2_mpy_rnd_lh_s0 : HInst<
   14998 (outs IntRegs:$Rd32),
   14999 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15000 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
   15001 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15002 let Inst{7-5} = 0b001;
   15003 let Inst{13-13} = 0b0;
   15004 let Inst{31-21} = 0b11101100001;
   15005 let hasNewValue = 1;
   15006 let opNewValue = 0;
   15007 let prefersSlot3 = 1;
   15008 }
   15009 def M2_mpy_rnd_lh_s1 : HInst<
   15010 (outs IntRegs:$Rd32),
   15011 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15012 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
   15013 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15014 let Inst{7-5} = 0b001;
   15015 let Inst{13-13} = 0b0;
   15016 let Inst{31-21} = 0b11101100101;
   15017 let hasNewValue = 1;
   15018 let opNewValue = 0;
   15019 let prefersSlot3 = 1;
   15020 }
   15021 def M2_mpy_rnd_ll_s0 : HInst<
   15022 (outs IntRegs:$Rd32),
   15023 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15024 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
   15025 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15026 let Inst{7-5} = 0b000;
   15027 let Inst{13-13} = 0b0;
   15028 let Inst{31-21} = 0b11101100001;
   15029 let hasNewValue = 1;
   15030 let opNewValue = 0;
   15031 let prefersSlot3 = 1;
   15032 }
   15033 def M2_mpy_rnd_ll_s1 : HInst<
   15034 (outs IntRegs:$Rd32),
   15035 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15036 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
   15037 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15038 let Inst{7-5} = 0b000;
   15039 let Inst{13-13} = 0b0;
   15040 let Inst{31-21} = 0b11101100101;
   15041 let hasNewValue = 1;
   15042 let opNewValue = 0;
   15043 let prefersSlot3 = 1;
   15044 }
   15045 def M2_mpy_sat_hh_s0 : HInst<
   15046 (outs IntRegs:$Rd32),
   15047 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15048 "$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
   15049 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15050 let Inst{7-5} = 0b111;
   15051 let Inst{13-13} = 0b0;
   15052 let Inst{31-21} = 0b11101100000;
   15053 let hasNewValue = 1;
   15054 let opNewValue = 0;
   15055 let prefersSlot3 = 1;
   15056 let Defs = [USR_OVF];
   15057 }
   15058 def M2_mpy_sat_hh_s1 : HInst<
   15059 (outs IntRegs:$Rd32),
   15060 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15061 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
   15062 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15063 let Inst{7-5} = 0b111;
   15064 let Inst{13-13} = 0b0;
   15065 let Inst{31-21} = 0b11101100100;
   15066 let hasNewValue = 1;
   15067 let opNewValue = 0;
   15068 let prefersSlot3 = 1;
   15069 let Defs = [USR_OVF];
   15070 }
   15071 def M2_mpy_sat_hl_s0 : HInst<
   15072 (outs IntRegs:$Rd32),
   15073 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15074 "$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
   15075 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15076 let Inst{7-5} = 0b110;
   15077 let Inst{13-13} = 0b0;
   15078 let Inst{31-21} = 0b11101100000;
   15079 let hasNewValue = 1;
   15080 let opNewValue = 0;
   15081 let prefersSlot3 = 1;
   15082 let Defs = [USR_OVF];
   15083 }
   15084 def M2_mpy_sat_hl_s1 : HInst<
   15085 (outs IntRegs:$Rd32),
   15086 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15087 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
   15088 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15089 let Inst{7-5} = 0b110;
   15090 let Inst{13-13} = 0b0;
   15091 let Inst{31-21} = 0b11101100100;
   15092 let hasNewValue = 1;
   15093 let opNewValue = 0;
   15094 let prefersSlot3 = 1;
   15095 let Defs = [USR_OVF];
   15096 }
   15097 def M2_mpy_sat_lh_s0 : HInst<
   15098 (outs IntRegs:$Rd32),
   15099 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15100 "$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
   15101 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15102 let Inst{7-5} = 0b101;
   15103 let Inst{13-13} = 0b0;
   15104 let Inst{31-21} = 0b11101100000;
   15105 let hasNewValue = 1;
   15106 let opNewValue = 0;
   15107 let prefersSlot3 = 1;
   15108 let Defs = [USR_OVF];
   15109 }
   15110 def M2_mpy_sat_lh_s1 : HInst<
   15111 (outs IntRegs:$Rd32),
   15112 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15113 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
   15114 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15115 let Inst{7-5} = 0b101;
   15116 let Inst{13-13} = 0b0;
   15117 let Inst{31-21} = 0b11101100100;
   15118 let hasNewValue = 1;
   15119 let opNewValue = 0;
   15120 let prefersSlot3 = 1;
   15121 let Defs = [USR_OVF];
   15122 }
   15123 def M2_mpy_sat_ll_s0 : HInst<
   15124 (outs IntRegs:$Rd32),
   15125 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15126 "$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
   15127 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15128 let Inst{7-5} = 0b100;
   15129 let Inst{13-13} = 0b0;
   15130 let Inst{31-21} = 0b11101100000;
   15131 let hasNewValue = 1;
   15132 let opNewValue = 0;
   15133 let prefersSlot3 = 1;
   15134 let Defs = [USR_OVF];
   15135 }
   15136 def M2_mpy_sat_ll_s1 : HInst<
   15137 (outs IntRegs:$Rd32),
   15138 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15139 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
   15140 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15141 let Inst{7-5} = 0b100;
   15142 let Inst{13-13} = 0b0;
   15143 let Inst{31-21} = 0b11101100100;
   15144 let hasNewValue = 1;
   15145 let opNewValue = 0;
   15146 let prefersSlot3 = 1;
   15147 let Defs = [USR_OVF];
   15148 }
   15149 def M2_mpy_sat_rnd_hh_s0 : HInst<
   15150 (outs IntRegs:$Rd32),
   15151 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15152 "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
   15153 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15154 let Inst{7-5} = 0b111;
   15155 let Inst{13-13} = 0b0;
   15156 let Inst{31-21} = 0b11101100001;
   15157 let hasNewValue = 1;
   15158 let opNewValue = 0;
   15159 let prefersSlot3 = 1;
   15160 let Defs = [USR_OVF];
   15161 }
   15162 def M2_mpy_sat_rnd_hh_s1 : HInst<
   15163 (outs IntRegs:$Rd32),
   15164 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15165 "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
   15166 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15167 let Inst{7-5} = 0b111;
   15168 let Inst{13-13} = 0b0;
   15169 let Inst{31-21} = 0b11101100101;
   15170 let hasNewValue = 1;
   15171 let opNewValue = 0;
   15172 let prefersSlot3 = 1;
   15173 let Defs = [USR_OVF];
   15174 }
   15175 def M2_mpy_sat_rnd_hl_s0 : HInst<
   15176 (outs IntRegs:$Rd32),
   15177 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15178 "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
   15179 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15180 let Inst{7-5} = 0b110;
   15181 let Inst{13-13} = 0b0;
   15182 let Inst{31-21} = 0b11101100001;
   15183 let hasNewValue = 1;
   15184 let opNewValue = 0;
   15185 let prefersSlot3 = 1;
   15186 let Defs = [USR_OVF];
   15187 }
   15188 def M2_mpy_sat_rnd_hl_s1 : HInst<
   15189 (outs IntRegs:$Rd32),
   15190 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15191 "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
   15192 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15193 let Inst{7-5} = 0b110;
   15194 let Inst{13-13} = 0b0;
   15195 let Inst{31-21} = 0b11101100101;
   15196 let hasNewValue = 1;
   15197 let opNewValue = 0;
   15198 let prefersSlot3 = 1;
   15199 let Defs = [USR_OVF];
   15200 }
   15201 def M2_mpy_sat_rnd_lh_s0 : HInst<
   15202 (outs IntRegs:$Rd32),
   15203 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15204 "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
   15205 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15206 let Inst{7-5} = 0b101;
   15207 let Inst{13-13} = 0b0;
   15208 let Inst{31-21} = 0b11101100001;
   15209 let hasNewValue = 1;
   15210 let opNewValue = 0;
   15211 let prefersSlot3 = 1;
   15212 let Defs = [USR_OVF];
   15213 }
   15214 def M2_mpy_sat_rnd_lh_s1 : HInst<
   15215 (outs IntRegs:$Rd32),
   15216 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15217 "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
   15218 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15219 let Inst{7-5} = 0b101;
   15220 let Inst{13-13} = 0b0;
   15221 let Inst{31-21} = 0b11101100101;
   15222 let hasNewValue = 1;
   15223 let opNewValue = 0;
   15224 let prefersSlot3 = 1;
   15225 let Defs = [USR_OVF];
   15226 }
   15227 def M2_mpy_sat_rnd_ll_s0 : HInst<
   15228 (outs IntRegs:$Rd32),
   15229 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15230 "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
   15231 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15232 let Inst{7-5} = 0b100;
   15233 let Inst{13-13} = 0b0;
   15234 let Inst{31-21} = 0b11101100001;
   15235 let hasNewValue = 1;
   15236 let opNewValue = 0;
   15237 let prefersSlot3 = 1;
   15238 let Defs = [USR_OVF];
   15239 }
   15240 def M2_mpy_sat_rnd_ll_s1 : HInst<
   15241 (outs IntRegs:$Rd32),
   15242 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15243 "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
   15244 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15245 let Inst{7-5} = 0b100;
   15246 let Inst{13-13} = 0b0;
   15247 let Inst{31-21} = 0b11101100101;
   15248 let hasNewValue = 1;
   15249 let opNewValue = 0;
   15250 let prefersSlot3 = 1;
   15251 let Defs = [USR_OVF];
   15252 }
   15253 def M2_mpy_up : HInst<
   15254 (outs IntRegs:$Rd32),
   15255 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15256 "$Rd32 = mpy($Rs32,$Rt32)",
   15257 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15258 let Inst{7-5} = 0b001;
   15259 let Inst{13-13} = 0b0;
   15260 let Inst{31-21} = 0b11101101000;
   15261 let hasNewValue = 1;
   15262 let opNewValue = 0;
   15263 let prefersSlot3 = 1;
   15264 }
   15265 def M2_mpy_up_s1 : HInst<
   15266 (outs IntRegs:$Rd32),
   15267 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15268 "$Rd32 = mpy($Rs32,$Rt32):<<1",
   15269 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15270 let Inst{7-5} = 0b010;
   15271 let Inst{13-13} = 0b0;
   15272 let Inst{31-21} = 0b11101101101;
   15273 let hasNewValue = 1;
   15274 let opNewValue = 0;
   15275 let prefersSlot3 = 1;
   15276 }
   15277 def M2_mpy_up_s1_sat : HInst<
   15278 (outs IntRegs:$Rd32),
   15279 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15280 "$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
   15281 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15282 let Inst{7-5} = 0b000;
   15283 let Inst{13-13} = 0b0;
   15284 let Inst{31-21} = 0b11101101111;
   15285 let hasNewValue = 1;
   15286 let opNewValue = 0;
   15287 let prefersSlot3 = 1;
   15288 let Defs = [USR_OVF];
   15289 }
   15290 def M2_mpyd_acc_hh_s0 : HInst<
   15291 (outs DoubleRegs:$Rxx32),
   15292 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15293 "$Rxx32 += mpy($Rs32.h,$Rt32.h)",
   15294 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15295 let Inst{7-5} = 0b011;
   15296 let Inst{13-13} = 0b0;
   15297 let Inst{31-21} = 0b11100110000;
   15298 let prefersSlot3 = 1;
   15299 let Constraints = "$Rxx32 = $Rxx32in";
   15300 }
   15301 def M2_mpyd_acc_hh_s1 : HInst<
   15302 (outs DoubleRegs:$Rxx32),
   15303 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15304 "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
   15305 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15306 let Inst{7-5} = 0b011;
   15307 let Inst{13-13} = 0b0;
   15308 let Inst{31-21} = 0b11100110100;
   15309 let prefersSlot3 = 1;
   15310 let Constraints = "$Rxx32 = $Rxx32in";
   15311 }
   15312 def M2_mpyd_acc_hl_s0 : HInst<
   15313 (outs DoubleRegs:$Rxx32),
   15314 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15315 "$Rxx32 += mpy($Rs32.h,$Rt32.l)",
   15316 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15317 let Inst{7-5} = 0b010;
   15318 let Inst{13-13} = 0b0;
   15319 let Inst{31-21} = 0b11100110000;
   15320 let prefersSlot3 = 1;
   15321 let Constraints = "$Rxx32 = $Rxx32in";
   15322 }
   15323 def M2_mpyd_acc_hl_s1 : HInst<
   15324 (outs DoubleRegs:$Rxx32),
   15325 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15326 "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
   15327 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15328 let Inst{7-5} = 0b010;
   15329 let Inst{13-13} = 0b0;
   15330 let Inst{31-21} = 0b11100110100;
   15331 let prefersSlot3 = 1;
   15332 let Constraints = "$Rxx32 = $Rxx32in";
   15333 }
   15334 def M2_mpyd_acc_lh_s0 : HInst<
   15335 (outs DoubleRegs:$Rxx32),
   15336 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15337 "$Rxx32 += mpy($Rs32.l,$Rt32.h)",
   15338 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15339 let Inst{7-5} = 0b001;
   15340 let Inst{13-13} = 0b0;
   15341 let Inst{31-21} = 0b11100110000;
   15342 let prefersSlot3 = 1;
   15343 let Constraints = "$Rxx32 = $Rxx32in";
   15344 }
   15345 def M2_mpyd_acc_lh_s1 : HInst<
   15346 (outs DoubleRegs:$Rxx32),
   15347 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15348 "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
   15349 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15350 let Inst{7-5} = 0b001;
   15351 let Inst{13-13} = 0b0;
   15352 let Inst{31-21} = 0b11100110100;
   15353 let prefersSlot3 = 1;
   15354 let Constraints = "$Rxx32 = $Rxx32in";
   15355 }
   15356 def M2_mpyd_acc_ll_s0 : HInst<
   15357 (outs DoubleRegs:$Rxx32),
   15358 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15359 "$Rxx32 += mpy($Rs32.l,$Rt32.l)",
   15360 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15361 let Inst{7-5} = 0b000;
   15362 let Inst{13-13} = 0b0;
   15363 let Inst{31-21} = 0b11100110000;
   15364 let prefersSlot3 = 1;
   15365 let Constraints = "$Rxx32 = $Rxx32in";
   15366 }
   15367 def M2_mpyd_acc_ll_s1 : HInst<
   15368 (outs DoubleRegs:$Rxx32),
   15369 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15370 "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
   15371 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15372 let Inst{7-5} = 0b000;
   15373 let Inst{13-13} = 0b0;
   15374 let Inst{31-21} = 0b11100110100;
   15375 let prefersSlot3 = 1;
   15376 let Constraints = "$Rxx32 = $Rxx32in";
   15377 }
   15378 def M2_mpyd_hh_s0 : HInst<
   15379 (outs DoubleRegs:$Rdd32),
   15380 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15381 "$Rdd32 = mpy($Rs32.h,$Rt32.h)",
   15382 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15383 let Inst{7-5} = 0b011;
   15384 let Inst{13-13} = 0b0;
   15385 let Inst{31-21} = 0b11100100000;
   15386 let prefersSlot3 = 1;
   15387 }
   15388 def M2_mpyd_hh_s1 : HInst<
   15389 (outs DoubleRegs:$Rdd32),
   15390 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15391 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
   15392 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15393 let Inst{7-5} = 0b011;
   15394 let Inst{13-13} = 0b0;
   15395 let Inst{31-21} = 0b11100100100;
   15396 let prefersSlot3 = 1;
   15397 }
   15398 def M2_mpyd_hl_s0 : HInst<
   15399 (outs DoubleRegs:$Rdd32),
   15400 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15401 "$Rdd32 = mpy($Rs32.h,$Rt32.l)",
   15402 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15403 let Inst{7-5} = 0b010;
   15404 let Inst{13-13} = 0b0;
   15405 let Inst{31-21} = 0b11100100000;
   15406 let prefersSlot3 = 1;
   15407 }
   15408 def M2_mpyd_hl_s1 : HInst<
   15409 (outs DoubleRegs:$Rdd32),
   15410 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15411 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
   15412 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15413 let Inst{7-5} = 0b010;
   15414 let Inst{13-13} = 0b0;
   15415 let Inst{31-21} = 0b11100100100;
   15416 let prefersSlot3 = 1;
   15417 }
   15418 def M2_mpyd_lh_s0 : HInst<
   15419 (outs DoubleRegs:$Rdd32),
   15420 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15421 "$Rdd32 = mpy($Rs32.l,$Rt32.h)",
   15422 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15423 let Inst{7-5} = 0b001;
   15424 let Inst{13-13} = 0b0;
   15425 let Inst{31-21} = 0b11100100000;
   15426 let prefersSlot3 = 1;
   15427 }
   15428 def M2_mpyd_lh_s1 : HInst<
   15429 (outs DoubleRegs:$Rdd32),
   15430 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15431 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
   15432 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15433 let Inst{7-5} = 0b001;
   15434 let Inst{13-13} = 0b0;
   15435 let Inst{31-21} = 0b11100100100;
   15436 let prefersSlot3 = 1;
   15437 }
   15438 def M2_mpyd_ll_s0 : HInst<
   15439 (outs DoubleRegs:$Rdd32),
   15440 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15441 "$Rdd32 = mpy($Rs32.l,$Rt32.l)",
   15442 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15443 let Inst{7-5} = 0b000;
   15444 let Inst{13-13} = 0b0;
   15445 let Inst{31-21} = 0b11100100000;
   15446 let prefersSlot3 = 1;
   15447 }
   15448 def M2_mpyd_ll_s1 : HInst<
   15449 (outs DoubleRegs:$Rdd32),
   15450 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15451 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
   15452 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15453 let Inst{7-5} = 0b000;
   15454 let Inst{13-13} = 0b0;
   15455 let Inst{31-21} = 0b11100100100;
   15456 let prefersSlot3 = 1;
   15457 }
   15458 def M2_mpyd_nac_hh_s0 : HInst<
   15459 (outs DoubleRegs:$Rxx32),
   15460 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15461 "$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
   15462 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15463 let Inst{7-5} = 0b011;
   15464 let Inst{13-13} = 0b0;
   15465 let Inst{31-21} = 0b11100110001;
   15466 let prefersSlot3 = 1;
   15467 let Constraints = "$Rxx32 = $Rxx32in";
   15468 }
   15469 def M2_mpyd_nac_hh_s1 : HInst<
   15470 (outs DoubleRegs:$Rxx32),
   15471 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15472 "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
   15473 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15474 let Inst{7-5} = 0b011;
   15475 let Inst{13-13} = 0b0;
   15476 let Inst{31-21} = 0b11100110101;
   15477 let prefersSlot3 = 1;
   15478 let Constraints = "$Rxx32 = $Rxx32in";
   15479 }
   15480 def M2_mpyd_nac_hl_s0 : HInst<
   15481 (outs DoubleRegs:$Rxx32),
   15482 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15483 "$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
   15484 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15485 let Inst{7-5} = 0b010;
   15486 let Inst{13-13} = 0b0;
   15487 let Inst{31-21} = 0b11100110001;
   15488 let prefersSlot3 = 1;
   15489 let Constraints = "$Rxx32 = $Rxx32in";
   15490 }
   15491 def M2_mpyd_nac_hl_s1 : HInst<
   15492 (outs DoubleRegs:$Rxx32),
   15493 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15494 "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
   15495 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15496 let Inst{7-5} = 0b010;
   15497 let Inst{13-13} = 0b0;
   15498 let Inst{31-21} = 0b11100110101;
   15499 let prefersSlot3 = 1;
   15500 let Constraints = "$Rxx32 = $Rxx32in";
   15501 }
   15502 def M2_mpyd_nac_lh_s0 : HInst<
   15503 (outs DoubleRegs:$Rxx32),
   15504 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15505 "$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
   15506 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15507 let Inst{7-5} = 0b001;
   15508 let Inst{13-13} = 0b0;
   15509 let Inst{31-21} = 0b11100110001;
   15510 let prefersSlot3 = 1;
   15511 let Constraints = "$Rxx32 = $Rxx32in";
   15512 }
   15513 def M2_mpyd_nac_lh_s1 : HInst<
   15514 (outs DoubleRegs:$Rxx32),
   15515 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15516 "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
   15517 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15518 let Inst{7-5} = 0b001;
   15519 let Inst{13-13} = 0b0;
   15520 let Inst{31-21} = 0b11100110101;
   15521 let prefersSlot3 = 1;
   15522 let Constraints = "$Rxx32 = $Rxx32in";
   15523 }
   15524 def M2_mpyd_nac_ll_s0 : HInst<
   15525 (outs DoubleRegs:$Rxx32),
   15526 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15527 "$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
   15528 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15529 let Inst{7-5} = 0b000;
   15530 let Inst{13-13} = 0b0;
   15531 let Inst{31-21} = 0b11100110001;
   15532 let prefersSlot3 = 1;
   15533 let Constraints = "$Rxx32 = $Rxx32in";
   15534 }
   15535 def M2_mpyd_nac_ll_s1 : HInst<
   15536 (outs DoubleRegs:$Rxx32),
   15537 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15538 "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
   15539 tc_e913dc32, TypeM>, Enc_61f0b0 {
   15540 let Inst{7-5} = 0b000;
   15541 let Inst{13-13} = 0b0;
   15542 let Inst{31-21} = 0b11100110101;
   15543 let prefersSlot3 = 1;
   15544 let Constraints = "$Rxx32 = $Rxx32in";
   15545 }
   15546 def M2_mpyd_rnd_hh_s0 : HInst<
   15547 (outs DoubleRegs:$Rdd32),
   15548 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15549 "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
   15550 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15551 let Inst{7-5} = 0b011;
   15552 let Inst{13-13} = 0b0;
   15553 let Inst{31-21} = 0b11100100001;
   15554 let prefersSlot3 = 1;
   15555 }
   15556 def M2_mpyd_rnd_hh_s1 : HInst<
   15557 (outs DoubleRegs:$Rdd32),
   15558 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15559 "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
   15560 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15561 let Inst{7-5} = 0b011;
   15562 let Inst{13-13} = 0b0;
   15563 let Inst{31-21} = 0b11100100101;
   15564 let prefersSlot3 = 1;
   15565 }
   15566 def M2_mpyd_rnd_hl_s0 : HInst<
   15567 (outs DoubleRegs:$Rdd32),
   15568 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15569 "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
   15570 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15571 let Inst{7-5} = 0b010;
   15572 let Inst{13-13} = 0b0;
   15573 let Inst{31-21} = 0b11100100001;
   15574 let prefersSlot3 = 1;
   15575 }
   15576 def M2_mpyd_rnd_hl_s1 : HInst<
   15577 (outs DoubleRegs:$Rdd32),
   15578 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15579 "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
   15580 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15581 let Inst{7-5} = 0b010;
   15582 let Inst{13-13} = 0b0;
   15583 let Inst{31-21} = 0b11100100101;
   15584 let prefersSlot3 = 1;
   15585 }
   15586 def M2_mpyd_rnd_lh_s0 : HInst<
   15587 (outs DoubleRegs:$Rdd32),
   15588 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15589 "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
   15590 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15591 let Inst{7-5} = 0b001;
   15592 let Inst{13-13} = 0b0;
   15593 let Inst{31-21} = 0b11100100001;
   15594 let prefersSlot3 = 1;
   15595 }
   15596 def M2_mpyd_rnd_lh_s1 : HInst<
   15597 (outs DoubleRegs:$Rdd32),
   15598 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15599 "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
   15600 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15601 let Inst{7-5} = 0b001;
   15602 let Inst{13-13} = 0b0;
   15603 let Inst{31-21} = 0b11100100101;
   15604 let prefersSlot3 = 1;
   15605 }
   15606 def M2_mpyd_rnd_ll_s0 : HInst<
   15607 (outs DoubleRegs:$Rdd32),
   15608 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15609 "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
   15610 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15611 let Inst{7-5} = 0b000;
   15612 let Inst{13-13} = 0b0;
   15613 let Inst{31-21} = 0b11100100001;
   15614 let prefersSlot3 = 1;
   15615 }
   15616 def M2_mpyd_rnd_ll_s1 : HInst<
   15617 (outs DoubleRegs:$Rdd32),
   15618 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15619 "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
   15620 tc_8fd5f294, TypeM>, Enc_be32a5 {
   15621 let Inst{7-5} = 0b000;
   15622 let Inst{13-13} = 0b0;
   15623 let Inst{31-21} = 0b11100100101;
   15624 let prefersSlot3 = 1;
   15625 }
   15626 def M2_mpyi : HInst<
   15627 (outs IntRegs:$Rd32),
   15628 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15629 "$Rd32 = mpyi($Rs32,$Rt32)",
   15630 tc_8fd5f294, TypeM>, Enc_5ab2be, ImmRegRel {
   15631 let Inst{7-5} = 0b000;
   15632 let Inst{13-13} = 0b0;
   15633 let Inst{31-21} = 0b11101101000;
   15634 let hasNewValue = 1;
   15635 let opNewValue = 0;
   15636 let prefersSlot3 = 1;
   15637 let CextOpcode = "M2_mpyi";
   15638 let InputType = "reg";
   15639 }
   15640 def M2_mpysin : HInst<
   15641 (outs IntRegs:$Rd32),
   15642 (ins IntRegs:$Rs32, u8_0Imm:$Ii),
   15643 "$Rd32 = -mpyi($Rs32,#$Ii)",
   15644 tc_1853ea6d, TypeM>, Enc_b8c967 {
   15645 let Inst{13-13} = 0b0;
   15646 let Inst{31-21} = 0b11100000100;
   15647 let hasNewValue = 1;
   15648 let opNewValue = 0;
   15649 let prefersSlot3 = 1;
   15650 }
   15651 def M2_mpysip : HInst<
   15652 (outs IntRegs:$Rd32),
   15653 (ins IntRegs:$Rs32, u32_0Imm:$Ii),
   15654 "$Rd32 = +mpyi($Rs32,#$Ii)",
   15655 tc_1853ea6d, TypeM>, Enc_b8c967 {
   15656 let Inst{13-13} = 0b0;
   15657 let Inst{31-21} = 0b11100000000;
   15658 let hasNewValue = 1;
   15659 let opNewValue = 0;
   15660 let prefersSlot3 = 1;
   15661 let isExtendable = 1;
   15662 let opExtendable = 2;
   15663 let isExtentSigned = 0;
   15664 let opExtentBits = 8;
   15665 let opExtentAlign = 0;
   15666 }
   15667 def M2_mpysmi : HInst<
   15668 (outs IntRegs:$Rd32),
   15669 (ins IntRegs:$Rs32, m32_0Imm:$Ii),
   15670 "$Rd32 = mpyi($Rs32,#$Ii)",
   15671 tc_1853ea6d, TypeM>, ImmRegRel {
   15672 let hasNewValue = 1;
   15673 let opNewValue = 0;
   15674 let CextOpcode = "M2_mpyi";
   15675 let InputType = "imm";
   15676 let isPseudo = 1;
   15677 let isExtendable = 1;
   15678 let opExtendable = 2;
   15679 let isExtentSigned = 1;
   15680 let opExtentBits = 9;
   15681 let opExtentAlign = 0;
   15682 }
   15683 def M2_mpysu_up : HInst<
   15684 (outs IntRegs:$Rd32),
   15685 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15686 "$Rd32 = mpysu($Rs32,$Rt32)",
   15687 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15688 let Inst{7-5} = 0b001;
   15689 let Inst{13-13} = 0b0;
   15690 let Inst{31-21} = 0b11101101011;
   15691 let hasNewValue = 1;
   15692 let opNewValue = 0;
   15693 let prefersSlot3 = 1;
   15694 }
   15695 def M2_mpyu_acc_hh_s0 : HInst<
   15696 (outs IntRegs:$Rx32),
   15697 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15698 "$Rx32 += mpyu($Rs32.h,$Rt32.h)",
   15699 tc_e913dc32, TypeM>, Enc_2ae154 {
   15700 let Inst{7-5} = 0b011;
   15701 let Inst{13-13} = 0b0;
   15702 let Inst{31-21} = 0b11101110010;
   15703 let hasNewValue = 1;
   15704 let opNewValue = 0;
   15705 let prefersSlot3 = 1;
   15706 let Constraints = "$Rx32 = $Rx32in";
   15707 }
   15708 def M2_mpyu_acc_hh_s1 : HInst<
   15709 (outs IntRegs:$Rx32),
   15710 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15711 "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
   15712 tc_e913dc32, TypeM>, Enc_2ae154 {
   15713 let Inst{7-5} = 0b011;
   15714 let Inst{13-13} = 0b0;
   15715 let Inst{31-21} = 0b11101110110;
   15716 let hasNewValue = 1;
   15717 let opNewValue = 0;
   15718 let prefersSlot3 = 1;
   15719 let Constraints = "$Rx32 = $Rx32in";
   15720 }
   15721 def M2_mpyu_acc_hl_s0 : HInst<
   15722 (outs IntRegs:$Rx32),
   15723 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15724 "$Rx32 += mpyu($Rs32.h,$Rt32.l)",
   15725 tc_e913dc32, TypeM>, Enc_2ae154 {
   15726 let Inst{7-5} = 0b010;
   15727 let Inst{13-13} = 0b0;
   15728 let Inst{31-21} = 0b11101110010;
   15729 let hasNewValue = 1;
   15730 let opNewValue = 0;
   15731 let prefersSlot3 = 1;
   15732 let Constraints = "$Rx32 = $Rx32in";
   15733 }
   15734 def M2_mpyu_acc_hl_s1 : HInst<
   15735 (outs IntRegs:$Rx32),
   15736 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15737 "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
   15738 tc_e913dc32, TypeM>, Enc_2ae154 {
   15739 let Inst{7-5} = 0b010;
   15740 let Inst{13-13} = 0b0;
   15741 let Inst{31-21} = 0b11101110110;
   15742 let hasNewValue = 1;
   15743 let opNewValue = 0;
   15744 let prefersSlot3 = 1;
   15745 let Constraints = "$Rx32 = $Rx32in";
   15746 }
   15747 def M2_mpyu_acc_lh_s0 : HInst<
   15748 (outs IntRegs:$Rx32),
   15749 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15750 "$Rx32 += mpyu($Rs32.l,$Rt32.h)",
   15751 tc_e913dc32, TypeM>, Enc_2ae154 {
   15752 let Inst{7-5} = 0b001;
   15753 let Inst{13-13} = 0b0;
   15754 let Inst{31-21} = 0b11101110010;
   15755 let hasNewValue = 1;
   15756 let opNewValue = 0;
   15757 let prefersSlot3 = 1;
   15758 let Constraints = "$Rx32 = $Rx32in";
   15759 }
   15760 def M2_mpyu_acc_lh_s1 : HInst<
   15761 (outs IntRegs:$Rx32),
   15762 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15763 "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
   15764 tc_e913dc32, TypeM>, Enc_2ae154 {
   15765 let Inst{7-5} = 0b001;
   15766 let Inst{13-13} = 0b0;
   15767 let Inst{31-21} = 0b11101110110;
   15768 let hasNewValue = 1;
   15769 let opNewValue = 0;
   15770 let prefersSlot3 = 1;
   15771 let Constraints = "$Rx32 = $Rx32in";
   15772 }
   15773 def M2_mpyu_acc_ll_s0 : HInst<
   15774 (outs IntRegs:$Rx32),
   15775 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15776 "$Rx32 += mpyu($Rs32.l,$Rt32.l)",
   15777 tc_e913dc32, TypeM>, Enc_2ae154 {
   15778 let Inst{7-5} = 0b000;
   15779 let Inst{13-13} = 0b0;
   15780 let Inst{31-21} = 0b11101110010;
   15781 let hasNewValue = 1;
   15782 let opNewValue = 0;
   15783 let prefersSlot3 = 1;
   15784 let Constraints = "$Rx32 = $Rx32in";
   15785 }
   15786 def M2_mpyu_acc_ll_s1 : HInst<
   15787 (outs IntRegs:$Rx32),
   15788 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15789 "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
   15790 tc_e913dc32, TypeM>, Enc_2ae154 {
   15791 let Inst{7-5} = 0b000;
   15792 let Inst{13-13} = 0b0;
   15793 let Inst{31-21} = 0b11101110110;
   15794 let hasNewValue = 1;
   15795 let opNewValue = 0;
   15796 let prefersSlot3 = 1;
   15797 let Constraints = "$Rx32 = $Rx32in";
   15798 }
   15799 def M2_mpyu_hh_s0 : HInst<
   15800 (outs IntRegs:$Rd32),
   15801 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15802 "$Rd32 = mpyu($Rs32.h,$Rt32.h)",
   15803 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15804 let Inst{7-5} = 0b011;
   15805 let Inst{13-13} = 0b0;
   15806 let Inst{31-21} = 0b11101100010;
   15807 let hasNewValue = 1;
   15808 let opNewValue = 0;
   15809 let prefersSlot3 = 1;
   15810 }
   15811 def M2_mpyu_hh_s1 : HInst<
   15812 (outs IntRegs:$Rd32),
   15813 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15814 "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
   15815 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15816 let Inst{7-5} = 0b011;
   15817 let Inst{13-13} = 0b0;
   15818 let Inst{31-21} = 0b11101100110;
   15819 let hasNewValue = 1;
   15820 let opNewValue = 0;
   15821 let prefersSlot3 = 1;
   15822 }
   15823 def M2_mpyu_hl_s0 : HInst<
   15824 (outs IntRegs:$Rd32),
   15825 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15826 "$Rd32 = mpyu($Rs32.h,$Rt32.l)",
   15827 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15828 let Inst{7-5} = 0b010;
   15829 let Inst{13-13} = 0b0;
   15830 let Inst{31-21} = 0b11101100010;
   15831 let hasNewValue = 1;
   15832 let opNewValue = 0;
   15833 let prefersSlot3 = 1;
   15834 }
   15835 def M2_mpyu_hl_s1 : HInst<
   15836 (outs IntRegs:$Rd32),
   15837 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15838 "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
   15839 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15840 let Inst{7-5} = 0b010;
   15841 let Inst{13-13} = 0b0;
   15842 let Inst{31-21} = 0b11101100110;
   15843 let hasNewValue = 1;
   15844 let opNewValue = 0;
   15845 let prefersSlot3 = 1;
   15846 }
   15847 def M2_mpyu_lh_s0 : HInst<
   15848 (outs IntRegs:$Rd32),
   15849 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15850 "$Rd32 = mpyu($Rs32.l,$Rt32.h)",
   15851 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15852 let Inst{7-5} = 0b001;
   15853 let Inst{13-13} = 0b0;
   15854 let Inst{31-21} = 0b11101100010;
   15855 let hasNewValue = 1;
   15856 let opNewValue = 0;
   15857 let prefersSlot3 = 1;
   15858 }
   15859 def M2_mpyu_lh_s1 : HInst<
   15860 (outs IntRegs:$Rd32),
   15861 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15862 "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
   15863 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15864 let Inst{7-5} = 0b001;
   15865 let Inst{13-13} = 0b0;
   15866 let Inst{31-21} = 0b11101100110;
   15867 let hasNewValue = 1;
   15868 let opNewValue = 0;
   15869 let prefersSlot3 = 1;
   15870 }
   15871 def M2_mpyu_ll_s0 : HInst<
   15872 (outs IntRegs:$Rd32),
   15873 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15874 "$Rd32 = mpyu($Rs32.l,$Rt32.l)",
   15875 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15876 let Inst{7-5} = 0b000;
   15877 let Inst{13-13} = 0b0;
   15878 let Inst{31-21} = 0b11101100010;
   15879 let hasNewValue = 1;
   15880 let opNewValue = 0;
   15881 let prefersSlot3 = 1;
   15882 }
   15883 def M2_mpyu_ll_s1 : HInst<
   15884 (outs IntRegs:$Rd32),
   15885 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   15886 "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
   15887 tc_8fd5f294, TypeM>, Enc_5ab2be {
   15888 let Inst{7-5} = 0b000;
   15889 let Inst{13-13} = 0b0;
   15890 let Inst{31-21} = 0b11101100110;
   15891 let hasNewValue = 1;
   15892 let opNewValue = 0;
   15893 let prefersSlot3 = 1;
   15894 }
   15895 def M2_mpyu_nac_hh_s0 : HInst<
   15896 (outs IntRegs:$Rx32),
   15897 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15898 "$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
   15899 tc_e913dc32, TypeM>, Enc_2ae154 {
   15900 let Inst{7-5} = 0b011;
   15901 let Inst{13-13} = 0b0;
   15902 let Inst{31-21} = 0b11101110011;
   15903 let hasNewValue = 1;
   15904 let opNewValue = 0;
   15905 let prefersSlot3 = 1;
   15906 let Constraints = "$Rx32 = $Rx32in";
   15907 }
   15908 def M2_mpyu_nac_hh_s1 : HInst<
   15909 (outs IntRegs:$Rx32),
   15910 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15911 "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
   15912 tc_e913dc32, TypeM>, Enc_2ae154 {
   15913 let Inst{7-5} = 0b011;
   15914 let Inst{13-13} = 0b0;
   15915 let Inst{31-21} = 0b11101110111;
   15916 let hasNewValue = 1;
   15917 let opNewValue = 0;
   15918 let prefersSlot3 = 1;
   15919 let Constraints = "$Rx32 = $Rx32in";
   15920 }
   15921 def M2_mpyu_nac_hl_s0 : HInst<
   15922 (outs IntRegs:$Rx32),
   15923 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15924 "$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
   15925 tc_e913dc32, TypeM>, Enc_2ae154 {
   15926 let Inst{7-5} = 0b010;
   15927 let Inst{13-13} = 0b0;
   15928 let Inst{31-21} = 0b11101110011;
   15929 let hasNewValue = 1;
   15930 let opNewValue = 0;
   15931 let prefersSlot3 = 1;
   15932 let Constraints = "$Rx32 = $Rx32in";
   15933 }
   15934 def M2_mpyu_nac_hl_s1 : HInst<
   15935 (outs IntRegs:$Rx32),
   15936 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15937 "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
   15938 tc_e913dc32, TypeM>, Enc_2ae154 {
   15939 let Inst{7-5} = 0b010;
   15940 let Inst{13-13} = 0b0;
   15941 let Inst{31-21} = 0b11101110111;
   15942 let hasNewValue = 1;
   15943 let opNewValue = 0;
   15944 let prefersSlot3 = 1;
   15945 let Constraints = "$Rx32 = $Rx32in";
   15946 }
   15947 def M2_mpyu_nac_lh_s0 : HInst<
   15948 (outs IntRegs:$Rx32),
   15949 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15950 "$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
   15951 tc_e913dc32, TypeM>, Enc_2ae154 {
   15952 let Inst{7-5} = 0b001;
   15953 let Inst{13-13} = 0b0;
   15954 let Inst{31-21} = 0b11101110011;
   15955 let hasNewValue = 1;
   15956 let opNewValue = 0;
   15957 let prefersSlot3 = 1;
   15958 let Constraints = "$Rx32 = $Rx32in";
   15959 }
   15960 def M2_mpyu_nac_lh_s1 : HInst<
   15961 (outs IntRegs:$Rx32),
   15962 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15963 "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
   15964 tc_e913dc32, TypeM>, Enc_2ae154 {
   15965 let Inst{7-5} = 0b001;
   15966 let Inst{13-13} = 0b0;
   15967 let Inst{31-21} = 0b11101110111;
   15968 let hasNewValue = 1;
   15969 let opNewValue = 0;
   15970 let prefersSlot3 = 1;
   15971 let Constraints = "$Rx32 = $Rx32in";
   15972 }
   15973 def M2_mpyu_nac_ll_s0 : HInst<
   15974 (outs IntRegs:$Rx32),
   15975 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15976 "$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
   15977 tc_e913dc32, TypeM>, Enc_2ae154 {
   15978 let Inst{7-5} = 0b000;
   15979 let Inst{13-13} = 0b0;
   15980 let Inst{31-21} = 0b11101110011;
   15981 let hasNewValue = 1;
   15982 let opNewValue = 0;
   15983 let prefersSlot3 = 1;
   15984 let Constraints = "$Rx32 = $Rx32in";
   15985 }
   15986 def M2_mpyu_nac_ll_s1 : HInst<
   15987 (outs IntRegs:$Rx32),
   15988 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   15989 "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
   15990 tc_e913dc32, TypeM>, Enc_2ae154 {
   15991 let Inst{7-5} = 0b000;
   15992 let Inst{13-13} = 0b0;
   15993 let Inst{31-21} = 0b11101110111;
   15994 let hasNewValue = 1;
   15995 let opNewValue = 0;
   15996 let prefersSlot3 = 1;
   15997 let Constraints = "$Rx32 = $Rx32in";
   15998 }
   15999 def M2_mpyu_up : HInst<
   16000 (outs IntRegs:$Rd32),
   16001 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16002 "$Rd32 = mpyu($Rs32,$Rt32)",
   16003 tc_8fd5f294, TypeM>, Enc_5ab2be {
   16004 let Inst{7-5} = 0b001;
   16005 let Inst{13-13} = 0b0;
   16006 let Inst{31-21} = 0b11101101010;
   16007 let hasNewValue = 1;
   16008 let opNewValue = 0;
   16009 let prefersSlot3 = 1;
   16010 }
   16011 def M2_mpyud_acc_hh_s0 : HInst<
   16012 (outs DoubleRegs:$Rxx32),
   16013 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16014 "$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
   16015 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16016 let Inst{7-5} = 0b011;
   16017 let Inst{13-13} = 0b0;
   16018 let Inst{31-21} = 0b11100110010;
   16019 let prefersSlot3 = 1;
   16020 let Constraints = "$Rxx32 = $Rxx32in";
   16021 }
   16022 def M2_mpyud_acc_hh_s1 : HInst<
   16023 (outs DoubleRegs:$Rxx32),
   16024 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16025 "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
   16026 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16027 let Inst{7-5} = 0b011;
   16028 let Inst{13-13} = 0b0;
   16029 let Inst{31-21} = 0b11100110110;
   16030 let prefersSlot3 = 1;
   16031 let Constraints = "$Rxx32 = $Rxx32in";
   16032 }
   16033 def M2_mpyud_acc_hl_s0 : HInst<
   16034 (outs DoubleRegs:$Rxx32),
   16035 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16036 "$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
   16037 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16038 let Inst{7-5} = 0b010;
   16039 let Inst{13-13} = 0b0;
   16040 let Inst{31-21} = 0b11100110010;
   16041 let prefersSlot3 = 1;
   16042 let Constraints = "$Rxx32 = $Rxx32in";
   16043 }
   16044 def M2_mpyud_acc_hl_s1 : HInst<
   16045 (outs DoubleRegs:$Rxx32),
   16046 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16047 "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
   16048 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16049 let Inst{7-5} = 0b010;
   16050 let Inst{13-13} = 0b0;
   16051 let Inst{31-21} = 0b11100110110;
   16052 let prefersSlot3 = 1;
   16053 let Constraints = "$Rxx32 = $Rxx32in";
   16054 }
   16055 def M2_mpyud_acc_lh_s0 : HInst<
   16056 (outs DoubleRegs:$Rxx32),
   16057 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16058 "$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
   16059 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16060 let Inst{7-5} = 0b001;
   16061 let Inst{13-13} = 0b0;
   16062 let Inst{31-21} = 0b11100110010;
   16063 let prefersSlot3 = 1;
   16064 let Constraints = "$Rxx32 = $Rxx32in";
   16065 }
   16066 def M2_mpyud_acc_lh_s1 : HInst<
   16067 (outs DoubleRegs:$Rxx32),
   16068 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16069 "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
   16070 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16071 let Inst{7-5} = 0b001;
   16072 let Inst{13-13} = 0b0;
   16073 let Inst{31-21} = 0b11100110110;
   16074 let prefersSlot3 = 1;
   16075 let Constraints = "$Rxx32 = $Rxx32in";
   16076 }
   16077 def M2_mpyud_acc_ll_s0 : HInst<
   16078 (outs DoubleRegs:$Rxx32),
   16079 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16080 "$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
   16081 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16082 let Inst{7-5} = 0b000;
   16083 let Inst{13-13} = 0b0;
   16084 let Inst{31-21} = 0b11100110010;
   16085 let prefersSlot3 = 1;
   16086 let Constraints = "$Rxx32 = $Rxx32in";
   16087 }
   16088 def M2_mpyud_acc_ll_s1 : HInst<
   16089 (outs DoubleRegs:$Rxx32),
   16090 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16091 "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
   16092 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16093 let Inst{7-5} = 0b000;
   16094 let Inst{13-13} = 0b0;
   16095 let Inst{31-21} = 0b11100110110;
   16096 let prefersSlot3 = 1;
   16097 let Constraints = "$Rxx32 = $Rxx32in";
   16098 }
   16099 def M2_mpyud_hh_s0 : HInst<
   16100 (outs DoubleRegs:$Rdd32),
   16101 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16102 "$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
   16103 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16104 let Inst{7-5} = 0b011;
   16105 let Inst{13-13} = 0b0;
   16106 let Inst{31-21} = 0b11100100010;
   16107 let prefersSlot3 = 1;
   16108 }
   16109 def M2_mpyud_hh_s1 : HInst<
   16110 (outs DoubleRegs:$Rdd32),
   16111 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16112 "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
   16113 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16114 let Inst{7-5} = 0b011;
   16115 let Inst{13-13} = 0b0;
   16116 let Inst{31-21} = 0b11100100110;
   16117 let prefersSlot3 = 1;
   16118 }
   16119 def M2_mpyud_hl_s0 : HInst<
   16120 (outs DoubleRegs:$Rdd32),
   16121 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16122 "$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
   16123 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16124 let Inst{7-5} = 0b010;
   16125 let Inst{13-13} = 0b0;
   16126 let Inst{31-21} = 0b11100100010;
   16127 let prefersSlot3 = 1;
   16128 }
   16129 def M2_mpyud_hl_s1 : HInst<
   16130 (outs DoubleRegs:$Rdd32),
   16131 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16132 "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
   16133 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16134 let Inst{7-5} = 0b010;
   16135 let Inst{13-13} = 0b0;
   16136 let Inst{31-21} = 0b11100100110;
   16137 let prefersSlot3 = 1;
   16138 }
   16139 def M2_mpyud_lh_s0 : HInst<
   16140 (outs DoubleRegs:$Rdd32),
   16141 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16142 "$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
   16143 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16144 let Inst{7-5} = 0b001;
   16145 let Inst{13-13} = 0b0;
   16146 let Inst{31-21} = 0b11100100010;
   16147 let prefersSlot3 = 1;
   16148 }
   16149 def M2_mpyud_lh_s1 : HInst<
   16150 (outs DoubleRegs:$Rdd32),
   16151 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16152 "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
   16153 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16154 let Inst{7-5} = 0b001;
   16155 let Inst{13-13} = 0b0;
   16156 let Inst{31-21} = 0b11100100110;
   16157 let prefersSlot3 = 1;
   16158 }
   16159 def M2_mpyud_ll_s0 : HInst<
   16160 (outs DoubleRegs:$Rdd32),
   16161 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16162 "$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
   16163 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16164 let Inst{7-5} = 0b000;
   16165 let Inst{13-13} = 0b0;
   16166 let Inst{31-21} = 0b11100100010;
   16167 let prefersSlot3 = 1;
   16168 }
   16169 def M2_mpyud_ll_s1 : HInst<
   16170 (outs DoubleRegs:$Rdd32),
   16171 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16172 "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
   16173 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16174 let Inst{7-5} = 0b000;
   16175 let Inst{13-13} = 0b0;
   16176 let Inst{31-21} = 0b11100100110;
   16177 let prefersSlot3 = 1;
   16178 }
   16179 def M2_mpyud_nac_hh_s0 : HInst<
   16180 (outs DoubleRegs:$Rxx32),
   16181 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16182 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
   16183 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16184 let Inst{7-5} = 0b011;
   16185 let Inst{13-13} = 0b0;
   16186 let Inst{31-21} = 0b11100110011;
   16187 let prefersSlot3 = 1;
   16188 let Constraints = "$Rxx32 = $Rxx32in";
   16189 }
   16190 def M2_mpyud_nac_hh_s1 : HInst<
   16191 (outs DoubleRegs:$Rxx32),
   16192 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16193 "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
   16194 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16195 let Inst{7-5} = 0b011;
   16196 let Inst{13-13} = 0b0;
   16197 let Inst{31-21} = 0b11100110111;
   16198 let prefersSlot3 = 1;
   16199 let Constraints = "$Rxx32 = $Rxx32in";
   16200 }
   16201 def M2_mpyud_nac_hl_s0 : HInst<
   16202 (outs DoubleRegs:$Rxx32),
   16203 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16204 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
   16205 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16206 let Inst{7-5} = 0b010;
   16207 let Inst{13-13} = 0b0;
   16208 let Inst{31-21} = 0b11100110011;
   16209 let prefersSlot3 = 1;
   16210 let Constraints = "$Rxx32 = $Rxx32in";
   16211 }
   16212 def M2_mpyud_nac_hl_s1 : HInst<
   16213 (outs DoubleRegs:$Rxx32),
   16214 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16215 "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
   16216 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16217 let Inst{7-5} = 0b010;
   16218 let Inst{13-13} = 0b0;
   16219 let Inst{31-21} = 0b11100110111;
   16220 let prefersSlot3 = 1;
   16221 let Constraints = "$Rxx32 = $Rxx32in";
   16222 }
   16223 def M2_mpyud_nac_lh_s0 : HInst<
   16224 (outs DoubleRegs:$Rxx32),
   16225 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16226 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
   16227 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16228 let Inst{7-5} = 0b001;
   16229 let Inst{13-13} = 0b0;
   16230 let Inst{31-21} = 0b11100110011;
   16231 let prefersSlot3 = 1;
   16232 let Constraints = "$Rxx32 = $Rxx32in";
   16233 }
   16234 def M2_mpyud_nac_lh_s1 : HInst<
   16235 (outs DoubleRegs:$Rxx32),
   16236 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16237 "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
   16238 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16239 let Inst{7-5} = 0b001;
   16240 let Inst{13-13} = 0b0;
   16241 let Inst{31-21} = 0b11100110111;
   16242 let prefersSlot3 = 1;
   16243 let Constraints = "$Rxx32 = $Rxx32in";
   16244 }
   16245 def M2_mpyud_nac_ll_s0 : HInst<
   16246 (outs DoubleRegs:$Rxx32),
   16247 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16248 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
   16249 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16250 let Inst{7-5} = 0b000;
   16251 let Inst{13-13} = 0b0;
   16252 let Inst{31-21} = 0b11100110011;
   16253 let prefersSlot3 = 1;
   16254 let Constraints = "$Rxx32 = $Rxx32in";
   16255 }
   16256 def M2_mpyud_nac_ll_s1 : HInst<
   16257 (outs DoubleRegs:$Rxx32),
   16258 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16259 "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
   16260 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16261 let Inst{7-5} = 0b000;
   16262 let Inst{13-13} = 0b0;
   16263 let Inst{31-21} = 0b11100110111;
   16264 let prefersSlot3 = 1;
   16265 let Constraints = "$Rxx32 = $Rxx32in";
   16266 }
   16267 def M2_mpyui : HInst<
   16268 (outs IntRegs:$Rd32),
   16269 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16270 "$Rd32 = mpyui($Rs32,$Rt32)",
   16271 tc_8fd5f294, TypeM> {
   16272 let hasNewValue = 1;
   16273 let opNewValue = 0;
   16274 let isPseudo = 1;
   16275 let isCodeGenOnly = 1;
   16276 }
   16277 def M2_nacci : HInst<
   16278 (outs IntRegs:$Rx32),
   16279 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16280 "$Rx32 -= add($Rs32,$Rt32)",
   16281 tc_c74f796f, TypeM>, Enc_2ae154 {
   16282 let Inst{7-5} = 0b001;
   16283 let Inst{13-13} = 0b0;
   16284 let Inst{31-21} = 0b11101111100;
   16285 let hasNewValue = 1;
   16286 let opNewValue = 0;
   16287 let prefersSlot3 = 1;
   16288 let InputType = "reg";
   16289 let Constraints = "$Rx32 = $Rx32in";
   16290 }
   16291 def M2_naccii : HInst<
   16292 (outs IntRegs:$Rx32),
   16293 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
   16294 "$Rx32 -= add($Rs32,#$Ii)",
   16295 tc_c74f796f, TypeM>, Enc_c90aca {
   16296 let Inst{13-13} = 0b0;
   16297 let Inst{31-21} = 0b11100010100;
   16298 let hasNewValue = 1;
   16299 let opNewValue = 0;
   16300 let prefersSlot3 = 1;
   16301 let InputType = "imm";
   16302 let isExtendable = 1;
   16303 let opExtendable = 3;
   16304 let isExtentSigned = 1;
   16305 let opExtentBits = 8;
   16306 let opExtentAlign = 0;
   16307 let Constraints = "$Rx32 = $Rx32in";
   16308 }
   16309 def M2_subacc : HInst<
   16310 (outs IntRegs:$Rx32),
   16311 (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
   16312 "$Rx32 += sub($Rt32,$Rs32)",
   16313 tc_c74f796f, TypeM>, Enc_a568d4 {
   16314 let Inst{7-5} = 0b011;
   16315 let Inst{13-13} = 0b0;
   16316 let Inst{31-21} = 0b11101111000;
   16317 let hasNewValue = 1;
   16318 let opNewValue = 0;
   16319 let prefersSlot3 = 1;
   16320 let InputType = "reg";
   16321 let Constraints = "$Rx32 = $Rx32in";
   16322 }
   16323 def M2_vabsdiffh : HInst<
   16324 (outs DoubleRegs:$Rdd32),
   16325 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   16326 "$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
   16327 tc_2b6f77c6, TypeM>, Enc_ea23e4 {
   16328 let Inst{7-5} = 0b000;
   16329 let Inst{13-13} = 0b0;
   16330 let Inst{31-21} = 0b11101000011;
   16331 let prefersSlot3 = 1;
   16332 }
   16333 def M2_vabsdiffw : HInst<
   16334 (outs DoubleRegs:$Rdd32),
   16335 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   16336 "$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
   16337 tc_2b6f77c6, TypeM>, Enc_ea23e4 {
   16338 let Inst{7-5} = 0b000;
   16339 let Inst{13-13} = 0b0;
   16340 let Inst{31-21} = 0b11101000001;
   16341 let prefersSlot3 = 1;
   16342 }
   16343 def M2_vcmac_s0_sat_i : HInst<
   16344 (outs DoubleRegs:$Rxx32),
   16345 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16346 "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
   16347 tc_e913dc32, TypeM>, Enc_88c16c {
   16348 let Inst{7-5} = 0b100;
   16349 let Inst{13-13} = 0b0;
   16350 let Inst{31-21} = 0b11101010010;
   16351 let prefersSlot3 = 1;
   16352 let Defs = [USR_OVF];
   16353 let Constraints = "$Rxx32 = $Rxx32in";
   16354 }
   16355 def M2_vcmac_s0_sat_r : HInst<
   16356 (outs DoubleRegs:$Rxx32),
   16357 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16358 "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
   16359 tc_e913dc32, TypeM>, Enc_88c16c {
   16360 let Inst{7-5} = 0b100;
   16361 let Inst{13-13} = 0b0;
   16362 let Inst{31-21} = 0b11101010001;
   16363 let prefersSlot3 = 1;
   16364 let Defs = [USR_OVF];
   16365 let Constraints = "$Rxx32 = $Rxx32in";
   16366 }
   16367 def M2_vcmpy_s0_sat_i : HInst<
   16368 (outs DoubleRegs:$Rdd32),
   16369 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16370 "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
   16371 tc_8fd5f294, TypeM>, Enc_a56825 {
   16372 let Inst{7-5} = 0b110;
   16373 let Inst{13-13} = 0b0;
   16374 let Inst{31-21} = 0b11101000010;
   16375 let prefersSlot3 = 1;
   16376 let Defs = [USR_OVF];
   16377 }
   16378 def M2_vcmpy_s0_sat_r : HInst<
   16379 (outs DoubleRegs:$Rdd32),
   16380 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16381 "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
   16382 tc_8fd5f294, TypeM>, Enc_a56825 {
   16383 let Inst{7-5} = 0b110;
   16384 let Inst{13-13} = 0b0;
   16385 let Inst{31-21} = 0b11101000001;
   16386 let prefersSlot3 = 1;
   16387 let Defs = [USR_OVF];
   16388 }
   16389 def M2_vcmpy_s1_sat_i : HInst<
   16390 (outs DoubleRegs:$Rdd32),
   16391 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16392 "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
   16393 tc_8fd5f294, TypeM>, Enc_a56825 {
   16394 let Inst{7-5} = 0b110;
   16395 let Inst{13-13} = 0b0;
   16396 let Inst{31-21} = 0b11101000110;
   16397 let prefersSlot3 = 1;
   16398 let Defs = [USR_OVF];
   16399 }
   16400 def M2_vcmpy_s1_sat_r : HInst<
   16401 (outs DoubleRegs:$Rdd32),
   16402 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16403 "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
   16404 tc_8fd5f294, TypeM>, Enc_a56825 {
   16405 let Inst{7-5} = 0b110;
   16406 let Inst{13-13} = 0b0;
   16407 let Inst{31-21} = 0b11101000101;
   16408 let prefersSlot3 = 1;
   16409 let Defs = [USR_OVF];
   16410 }
   16411 def M2_vdmacs_s0 : HInst<
   16412 (outs DoubleRegs:$Rxx32),
   16413 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16414 "$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
   16415 tc_e913dc32, TypeM>, Enc_88c16c {
   16416 let Inst{7-5} = 0b100;
   16417 let Inst{13-13} = 0b0;
   16418 let Inst{31-21} = 0b11101010000;
   16419 let prefersSlot3 = 1;
   16420 let Defs = [USR_OVF];
   16421 let Constraints = "$Rxx32 = $Rxx32in";
   16422 }
   16423 def M2_vdmacs_s1 : HInst<
   16424 (outs DoubleRegs:$Rxx32),
   16425 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16426 "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
   16427 tc_e913dc32, TypeM>, Enc_88c16c {
   16428 let Inst{7-5} = 0b100;
   16429 let Inst{13-13} = 0b0;
   16430 let Inst{31-21} = 0b11101010100;
   16431 let prefersSlot3 = 1;
   16432 let Defs = [USR_OVF];
   16433 let Constraints = "$Rxx32 = $Rxx32in";
   16434 }
   16435 def M2_vdmpyrs_s0 : HInst<
   16436 (outs IntRegs:$Rd32),
   16437 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16438 "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
   16439 tc_8fd5f294, TypeM>, Enc_d2216a {
   16440 let Inst{7-5} = 0b000;
   16441 let Inst{13-13} = 0b0;
   16442 let Inst{31-21} = 0b11101001000;
   16443 let hasNewValue = 1;
   16444 let opNewValue = 0;
   16445 let prefersSlot3 = 1;
   16446 let Defs = [USR_OVF];
   16447 }
   16448 def M2_vdmpyrs_s1 : HInst<
   16449 (outs IntRegs:$Rd32),
   16450 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16451 "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
   16452 tc_8fd5f294, TypeM>, Enc_d2216a {
   16453 let Inst{7-5} = 0b000;
   16454 let Inst{13-13} = 0b0;
   16455 let Inst{31-21} = 0b11101001100;
   16456 let hasNewValue = 1;
   16457 let opNewValue = 0;
   16458 let prefersSlot3 = 1;
   16459 let Defs = [USR_OVF];
   16460 }
   16461 def M2_vdmpys_s0 : HInst<
   16462 (outs DoubleRegs:$Rdd32),
   16463 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16464 "$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
   16465 tc_8fd5f294, TypeM>, Enc_a56825 {
   16466 let Inst{7-5} = 0b100;
   16467 let Inst{13-13} = 0b0;
   16468 let Inst{31-21} = 0b11101000000;
   16469 let prefersSlot3 = 1;
   16470 let Defs = [USR_OVF];
   16471 }
   16472 def M2_vdmpys_s1 : HInst<
   16473 (outs DoubleRegs:$Rdd32),
   16474 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16475 "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
   16476 tc_8fd5f294, TypeM>, Enc_a56825 {
   16477 let Inst{7-5} = 0b100;
   16478 let Inst{13-13} = 0b0;
   16479 let Inst{31-21} = 0b11101000100;
   16480 let prefersSlot3 = 1;
   16481 let Defs = [USR_OVF];
   16482 }
   16483 def M2_vmac2 : HInst<
   16484 (outs DoubleRegs:$Rxx32),
   16485 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16486 "$Rxx32 += vmpyh($Rs32,$Rt32)",
   16487 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16488 let Inst{7-5} = 0b001;
   16489 let Inst{13-13} = 0b0;
   16490 let Inst{31-21} = 0b11100111001;
   16491 let prefersSlot3 = 1;
   16492 let Constraints = "$Rxx32 = $Rxx32in";
   16493 }
   16494 def M2_vmac2es : HInst<
   16495 (outs DoubleRegs:$Rxx32),
   16496 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16497 "$Rxx32 += vmpyeh($Rss32,$Rtt32)",
   16498 tc_e913dc32, TypeM>, Enc_88c16c {
   16499 let Inst{7-5} = 0b010;
   16500 let Inst{13-13} = 0b0;
   16501 let Inst{31-21} = 0b11101010001;
   16502 let prefersSlot3 = 1;
   16503 let Constraints = "$Rxx32 = $Rxx32in";
   16504 }
   16505 def M2_vmac2es_s0 : HInst<
   16506 (outs DoubleRegs:$Rxx32),
   16507 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16508 "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
   16509 tc_e913dc32, TypeM>, Enc_88c16c {
   16510 let Inst{7-5} = 0b110;
   16511 let Inst{13-13} = 0b0;
   16512 let Inst{31-21} = 0b11101010000;
   16513 let prefersSlot3 = 1;
   16514 let Defs = [USR_OVF];
   16515 let Constraints = "$Rxx32 = $Rxx32in";
   16516 }
   16517 def M2_vmac2es_s1 : HInst<
   16518 (outs DoubleRegs:$Rxx32),
   16519 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16520 "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
   16521 tc_e913dc32, TypeM>, Enc_88c16c {
   16522 let Inst{7-5} = 0b110;
   16523 let Inst{13-13} = 0b0;
   16524 let Inst{31-21} = 0b11101010100;
   16525 let prefersSlot3 = 1;
   16526 let Defs = [USR_OVF];
   16527 let Constraints = "$Rxx32 = $Rxx32in";
   16528 }
   16529 def M2_vmac2s_s0 : HInst<
   16530 (outs DoubleRegs:$Rxx32),
   16531 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16532 "$Rxx32 += vmpyh($Rs32,$Rt32):sat",
   16533 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16534 let Inst{7-5} = 0b101;
   16535 let Inst{13-13} = 0b0;
   16536 let Inst{31-21} = 0b11100111000;
   16537 let prefersSlot3 = 1;
   16538 let Defs = [USR_OVF];
   16539 let Constraints = "$Rxx32 = $Rxx32in";
   16540 }
   16541 def M2_vmac2s_s1 : HInst<
   16542 (outs DoubleRegs:$Rxx32),
   16543 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16544 "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
   16545 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16546 let Inst{7-5} = 0b101;
   16547 let Inst{13-13} = 0b0;
   16548 let Inst{31-21} = 0b11100111100;
   16549 let prefersSlot3 = 1;
   16550 let Defs = [USR_OVF];
   16551 let Constraints = "$Rxx32 = $Rxx32in";
   16552 }
   16553 def M2_vmac2su_s0 : HInst<
   16554 (outs DoubleRegs:$Rxx32),
   16555 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16556 "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
   16557 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16558 let Inst{7-5} = 0b101;
   16559 let Inst{13-13} = 0b0;
   16560 let Inst{31-21} = 0b11100111011;
   16561 let prefersSlot3 = 1;
   16562 let Defs = [USR_OVF];
   16563 let Constraints = "$Rxx32 = $Rxx32in";
   16564 }
   16565 def M2_vmac2su_s1 : HInst<
   16566 (outs DoubleRegs:$Rxx32),
   16567 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16568 "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
   16569 tc_e913dc32, TypeM>, Enc_61f0b0 {
   16570 let Inst{7-5} = 0b101;
   16571 let Inst{13-13} = 0b0;
   16572 let Inst{31-21} = 0b11100111111;
   16573 let prefersSlot3 = 1;
   16574 let Defs = [USR_OVF];
   16575 let Constraints = "$Rxx32 = $Rxx32in";
   16576 }
   16577 def M2_vmpy2es_s0 : HInst<
   16578 (outs DoubleRegs:$Rdd32),
   16579 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16580 "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
   16581 tc_8fd5f294, TypeM>, Enc_a56825 {
   16582 let Inst{7-5} = 0b110;
   16583 let Inst{13-13} = 0b0;
   16584 let Inst{31-21} = 0b11101000000;
   16585 let prefersSlot3 = 1;
   16586 let Defs = [USR_OVF];
   16587 }
   16588 def M2_vmpy2es_s1 : HInst<
   16589 (outs DoubleRegs:$Rdd32),
   16590 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16591 "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
   16592 tc_8fd5f294, TypeM>, Enc_a56825 {
   16593 let Inst{7-5} = 0b110;
   16594 let Inst{13-13} = 0b0;
   16595 let Inst{31-21} = 0b11101000100;
   16596 let prefersSlot3 = 1;
   16597 let Defs = [USR_OVF];
   16598 }
   16599 def M2_vmpy2s_s0 : HInst<
   16600 (outs DoubleRegs:$Rdd32),
   16601 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16602 "$Rdd32 = vmpyh($Rs32,$Rt32):sat",
   16603 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16604 let Inst{7-5} = 0b101;
   16605 let Inst{13-13} = 0b0;
   16606 let Inst{31-21} = 0b11100101000;
   16607 let prefersSlot3 = 1;
   16608 let Defs = [USR_OVF];
   16609 }
   16610 def M2_vmpy2s_s0pack : HInst<
   16611 (outs IntRegs:$Rd32),
   16612 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16613 "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
   16614 tc_8fd5f294, TypeM>, Enc_5ab2be {
   16615 let Inst{7-5} = 0b111;
   16616 let Inst{13-13} = 0b0;
   16617 let Inst{31-21} = 0b11101101001;
   16618 let hasNewValue = 1;
   16619 let opNewValue = 0;
   16620 let prefersSlot3 = 1;
   16621 let Defs = [USR_OVF];
   16622 }
   16623 def M2_vmpy2s_s1 : HInst<
   16624 (outs DoubleRegs:$Rdd32),
   16625 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16626 "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
   16627 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16628 let Inst{7-5} = 0b101;
   16629 let Inst{13-13} = 0b0;
   16630 let Inst{31-21} = 0b11100101100;
   16631 let prefersSlot3 = 1;
   16632 let Defs = [USR_OVF];
   16633 }
   16634 def M2_vmpy2s_s1pack : HInst<
   16635 (outs IntRegs:$Rd32),
   16636 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16637 "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
   16638 tc_8fd5f294, TypeM>, Enc_5ab2be {
   16639 let Inst{7-5} = 0b111;
   16640 let Inst{13-13} = 0b0;
   16641 let Inst{31-21} = 0b11101101101;
   16642 let hasNewValue = 1;
   16643 let opNewValue = 0;
   16644 let prefersSlot3 = 1;
   16645 let Defs = [USR_OVF];
   16646 }
   16647 def M2_vmpy2su_s0 : HInst<
   16648 (outs DoubleRegs:$Rdd32),
   16649 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16650 "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
   16651 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16652 let Inst{7-5} = 0b111;
   16653 let Inst{13-13} = 0b0;
   16654 let Inst{31-21} = 0b11100101000;
   16655 let prefersSlot3 = 1;
   16656 let Defs = [USR_OVF];
   16657 }
   16658 def M2_vmpy2su_s1 : HInst<
   16659 (outs DoubleRegs:$Rdd32),
   16660 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   16661 "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
   16662 tc_8fd5f294, TypeM>, Enc_be32a5 {
   16663 let Inst{7-5} = 0b111;
   16664 let Inst{13-13} = 0b0;
   16665 let Inst{31-21} = 0b11100101100;
   16666 let prefersSlot3 = 1;
   16667 let Defs = [USR_OVF];
   16668 }
   16669 def M2_vraddh : HInst<
   16670 (outs IntRegs:$Rd32),
   16671 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16672 "$Rd32 = vraddh($Rss32,$Rtt32)",
   16673 tc_8fd5f294, TypeM>, Enc_d2216a {
   16674 let Inst{7-5} = 0b111;
   16675 let Inst{13-13} = 0b0;
   16676 let Inst{31-21} = 0b11101001001;
   16677 let hasNewValue = 1;
   16678 let opNewValue = 0;
   16679 let prefersSlot3 = 1;
   16680 }
   16681 def M2_vradduh : HInst<
   16682 (outs IntRegs:$Rd32),
   16683 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16684 "$Rd32 = vradduh($Rss32,$Rtt32)",
   16685 tc_8fd5f294, TypeM>, Enc_d2216a {
   16686 let Inst{7-5} = 0b001;
   16687 let Inst{13-13} = 0b0;
   16688 let Inst{31-21} = 0b11101001000;
   16689 let hasNewValue = 1;
   16690 let opNewValue = 0;
   16691 let prefersSlot3 = 1;
   16692 }
   16693 def M2_vrcmaci_s0 : HInst<
   16694 (outs DoubleRegs:$Rxx32),
   16695 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16696 "$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
   16697 tc_e913dc32, TypeM>, Enc_88c16c {
   16698 let Inst{7-5} = 0b000;
   16699 let Inst{13-13} = 0b0;
   16700 let Inst{31-21} = 0b11101010000;
   16701 let prefersSlot3 = 1;
   16702 let Constraints = "$Rxx32 = $Rxx32in";
   16703 }
   16704 def M2_vrcmaci_s0c : HInst<
   16705 (outs DoubleRegs:$Rxx32),
   16706 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16707 "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
   16708 tc_e913dc32, TypeM>, Enc_88c16c {
   16709 let Inst{7-5} = 0b000;
   16710 let Inst{13-13} = 0b0;
   16711 let Inst{31-21} = 0b11101010010;
   16712 let prefersSlot3 = 1;
   16713 let Constraints = "$Rxx32 = $Rxx32in";
   16714 }
   16715 def M2_vrcmacr_s0 : HInst<
   16716 (outs DoubleRegs:$Rxx32),
   16717 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16718 "$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
   16719 tc_e913dc32, TypeM>, Enc_88c16c {
   16720 let Inst{7-5} = 0b001;
   16721 let Inst{13-13} = 0b0;
   16722 let Inst{31-21} = 0b11101010000;
   16723 let prefersSlot3 = 1;
   16724 let Constraints = "$Rxx32 = $Rxx32in";
   16725 }
   16726 def M2_vrcmacr_s0c : HInst<
   16727 (outs DoubleRegs:$Rxx32),
   16728 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16729 "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
   16730 tc_e913dc32, TypeM>, Enc_88c16c {
   16731 let Inst{7-5} = 0b001;
   16732 let Inst{13-13} = 0b0;
   16733 let Inst{31-21} = 0b11101010011;
   16734 let prefersSlot3 = 1;
   16735 let Constraints = "$Rxx32 = $Rxx32in";
   16736 }
   16737 def M2_vrcmpyi_s0 : HInst<
   16738 (outs DoubleRegs:$Rdd32),
   16739 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16740 "$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
   16741 tc_8fd5f294, TypeM>, Enc_a56825 {
   16742 let Inst{7-5} = 0b000;
   16743 let Inst{13-13} = 0b0;
   16744 let Inst{31-21} = 0b11101000000;
   16745 let prefersSlot3 = 1;
   16746 }
   16747 def M2_vrcmpyi_s0c : HInst<
   16748 (outs DoubleRegs:$Rdd32),
   16749 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16750 "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
   16751 tc_8fd5f294, TypeM>, Enc_a56825 {
   16752 let Inst{7-5} = 0b000;
   16753 let Inst{13-13} = 0b0;
   16754 let Inst{31-21} = 0b11101000010;
   16755 let prefersSlot3 = 1;
   16756 }
   16757 def M2_vrcmpyr_s0 : HInst<
   16758 (outs DoubleRegs:$Rdd32),
   16759 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16760 "$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
   16761 tc_8fd5f294, TypeM>, Enc_a56825 {
   16762 let Inst{7-5} = 0b001;
   16763 let Inst{13-13} = 0b0;
   16764 let Inst{31-21} = 0b11101000000;
   16765 let prefersSlot3 = 1;
   16766 }
   16767 def M2_vrcmpyr_s0c : HInst<
   16768 (outs DoubleRegs:$Rdd32),
   16769 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16770 "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
   16771 tc_8fd5f294, TypeM>, Enc_a56825 {
   16772 let Inst{7-5} = 0b001;
   16773 let Inst{13-13} = 0b0;
   16774 let Inst{31-21} = 0b11101000011;
   16775 let prefersSlot3 = 1;
   16776 }
   16777 def M2_vrcmpys_acc_s1 : HInst<
   16778 (outs DoubleRegs:$Rxx32),
   16779 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   16780 "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
   16781 tc_e913dc32, TypeM> {
   16782 let isPseudo = 1;
   16783 let Constraints = "$Rxx32 = $Rxx32in";
   16784 }
   16785 def M2_vrcmpys_acc_s1_h : HInst<
   16786 (outs DoubleRegs:$Rxx32),
   16787 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16788 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
   16789 tc_e913dc32, TypeM>, Enc_88c16c {
   16790 let Inst{7-5} = 0b100;
   16791 let Inst{13-13} = 0b0;
   16792 let Inst{31-21} = 0b11101010101;
   16793 let prefersSlot3 = 1;
   16794 let Defs = [USR_OVF];
   16795 let Constraints = "$Rxx32 = $Rxx32in";
   16796 }
   16797 def M2_vrcmpys_acc_s1_l : HInst<
   16798 (outs DoubleRegs:$Rxx32),
   16799 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16800 "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
   16801 tc_e913dc32, TypeM>, Enc_88c16c {
   16802 let Inst{7-5} = 0b100;
   16803 let Inst{13-13} = 0b0;
   16804 let Inst{31-21} = 0b11101010111;
   16805 let prefersSlot3 = 1;
   16806 let Defs = [USR_OVF];
   16807 let Constraints = "$Rxx32 = $Rxx32in";
   16808 }
   16809 def M2_vrcmpys_s1 : HInst<
   16810 (outs DoubleRegs:$Rdd32),
   16811 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   16812 "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
   16813 tc_8fd5f294, TypeM> {
   16814 let isPseudo = 1;
   16815 }
   16816 def M2_vrcmpys_s1_h : HInst<
   16817 (outs DoubleRegs:$Rdd32),
   16818 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16819 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
   16820 tc_8fd5f294, TypeM>, Enc_a56825 {
   16821 let Inst{7-5} = 0b100;
   16822 let Inst{13-13} = 0b0;
   16823 let Inst{31-21} = 0b11101000101;
   16824 let prefersSlot3 = 1;
   16825 let Defs = [USR_OVF];
   16826 }
   16827 def M2_vrcmpys_s1_l : HInst<
   16828 (outs DoubleRegs:$Rdd32),
   16829 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16830 "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
   16831 tc_8fd5f294, TypeM>, Enc_a56825 {
   16832 let Inst{7-5} = 0b100;
   16833 let Inst{13-13} = 0b0;
   16834 let Inst{31-21} = 0b11101000111;
   16835 let prefersSlot3 = 1;
   16836 let Defs = [USR_OVF];
   16837 }
   16838 def M2_vrcmpys_s1rp : HInst<
   16839 (outs IntRegs:$Rd32),
   16840 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   16841 "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
   16842 tc_8fd5f294, TypeM> {
   16843 let hasNewValue = 1;
   16844 let opNewValue = 0;
   16845 let isPseudo = 1;
   16846 }
   16847 def M2_vrcmpys_s1rp_h : HInst<
   16848 (outs IntRegs:$Rd32),
   16849 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16850 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
   16851 tc_8fd5f294, TypeM>, Enc_d2216a {
   16852 let Inst{7-5} = 0b110;
   16853 let Inst{13-13} = 0b0;
   16854 let Inst{31-21} = 0b11101001101;
   16855 let hasNewValue = 1;
   16856 let opNewValue = 0;
   16857 let prefersSlot3 = 1;
   16858 let Defs = [USR_OVF];
   16859 }
   16860 def M2_vrcmpys_s1rp_l : HInst<
   16861 (outs IntRegs:$Rd32),
   16862 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16863 "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
   16864 tc_8fd5f294, TypeM>, Enc_d2216a {
   16865 let Inst{7-5} = 0b111;
   16866 let Inst{13-13} = 0b0;
   16867 let Inst{31-21} = 0b11101001101;
   16868 let hasNewValue = 1;
   16869 let opNewValue = 0;
   16870 let prefersSlot3 = 1;
   16871 let Defs = [USR_OVF];
   16872 }
   16873 def M2_vrmac_s0 : HInst<
   16874 (outs DoubleRegs:$Rxx32),
   16875 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16876 "$Rxx32 += vrmpyh($Rss32,$Rtt32)",
   16877 tc_e913dc32, TypeM>, Enc_88c16c {
   16878 let Inst{7-5} = 0b010;
   16879 let Inst{13-13} = 0b0;
   16880 let Inst{31-21} = 0b11101010000;
   16881 let prefersSlot3 = 1;
   16882 let Constraints = "$Rxx32 = $Rxx32in";
   16883 }
   16884 def M2_vrmpy_s0 : HInst<
   16885 (outs DoubleRegs:$Rdd32),
   16886 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   16887 "$Rdd32 = vrmpyh($Rss32,$Rtt32)",
   16888 tc_8fd5f294, TypeM>, Enc_a56825 {
   16889 let Inst{7-5} = 0b010;
   16890 let Inst{13-13} = 0b0;
   16891 let Inst{31-21} = 0b11101000000;
   16892 let prefersSlot3 = 1;
   16893 }
   16894 def M2_xor_xacc : HInst<
   16895 (outs IntRegs:$Rx32),
   16896 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16897 "$Rx32 ^= xor($Rs32,$Rt32)",
   16898 tc_84df2cd3, TypeM>, Enc_2ae154 {
   16899 let Inst{7-5} = 0b011;
   16900 let Inst{13-13} = 0b0;
   16901 let Inst{31-21} = 0b11101111100;
   16902 let hasNewValue = 1;
   16903 let opNewValue = 0;
   16904 let prefersSlot3 = 1;
   16905 let InputType = "reg";
   16906 let Constraints = "$Rx32 = $Rx32in";
   16907 }
   16908 def M4_and_and : HInst<
   16909 (outs IntRegs:$Rx32),
   16910 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16911 "$Rx32 &= and($Rs32,$Rt32)",
   16912 tc_84df2cd3, TypeM>, Enc_2ae154 {
   16913 let Inst{7-5} = 0b000;
   16914 let Inst{13-13} = 0b0;
   16915 let Inst{31-21} = 0b11101111010;
   16916 let hasNewValue = 1;
   16917 let opNewValue = 0;
   16918 let prefersSlot3 = 1;
   16919 let InputType = "reg";
   16920 let Constraints = "$Rx32 = $Rx32in";
   16921 }
   16922 def M4_and_andn : HInst<
   16923 (outs IntRegs:$Rx32),
   16924 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16925 "$Rx32 &= and($Rs32,~$Rt32)",
   16926 tc_84df2cd3, TypeM>, Enc_2ae154 {
   16927 let Inst{7-5} = 0b001;
   16928 let Inst{13-13} = 0b0;
   16929 let Inst{31-21} = 0b11101111001;
   16930 let hasNewValue = 1;
   16931 let opNewValue = 0;
   16932 let prefersSlot3 = 1;
   16933 let InputType = "reg";
   16934 let Constraints = "$Rx32 = $Rx32in";
   16935 }
   16936 def M4_and_or : HInst<
   16937 (outs IntRegs:$Rx32),
   16938 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16939 "$Rx32 &= or($Rs32,$Rt32)",
   16940 tc_84df2cd3, TypeM>, Enc_2ae154 {
   16941 let Inst{7-5} = 0b001;
   16942 let Inst{13-13} = 0b0;
   16943 let Inst{31-21} = 0b11101111010;
   16944 let hasNewValue = 1;
   16945 let opNewValue = 0;
   16946 let prefersSlot3 = 1;
   16947 let InputType = "reg";
   16948 let Constraints = "$Rx32 = $Rx32in";
   16949 }
   16950 def M4_and_xor : HInst<
   16951 (outs IntRegs:$Rx32),
   16952 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   16953 "$Rx32 &= xor($Rs32,$Rt32)",
   16954 tc_84df2cd3, TypeM>, Enc_2ae154 {
   16955 let Inst{7-5} = 0b010;
   16956 let Inst{13-13} = 0b0;
   16957 let Inst{31-21} = 0b11101111010;
   16958 let hasNewValue = 1;
   16959 let opNewValue = 0;
   16960 let prefersSlot3 = 1;
   16961 let InputType = "reg";
   16962 let Constraints = "$Rx32 = $Rx32in";
   16963 }
   16964 def M4_cmpyi_wh : HInst<
   16965 (outs IntRegs:$Rd32),
   16966 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   16967 "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
   16968 tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
   16969 let Inst{7-5} = 0b100;
   16970 let Inst{13-13} = 0b0;
   16971 let Inst{31-21} = 0b11000101000;
   16972 let hasNewValue = 1;
   16973 let opNewValue = 0;
   16974 let prefersSlot3 = 1;
   16975 let Defs = [USR_OVF];
   16976 }
   16977 def M4_cmpyi_whc : HInst<
   16978 (outs IntRegs:$Rd32),
   16979 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   16980 "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
   16981 tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> {
   16982 let Inst{7-5} = 0b101;
   16983 let Inst{13-13} = 0b0;
   16984 let Inst{31-21} = 0b11000101000;
   16985 let hasNewValue = 1;
   16986 let opNewValue = 0;
   16987 let prefersSlot3 = 1;
   16988 let Defs = [USR_OVF];
   16989 }
   16990 def M4_cmpyr_wh : HInst<
   16991 (outs IntRegs:$Rd32),
   16992 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   16993 "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
   16994 tc_8fd5f294, TypeS_3op>, Enc_3d5b28 {
   16995 let Inst{7-5} = 0b110;
   16996 let Inst{13-13} = 0b0;
   16997 let Inst{31-21} = 0b11000101000;
   16998 let hasNewValue = 1;
   16999 let opNewValue = 0;
   17000 let prefersSlot3 = 1;
   17001 let Defs = [USR_OVF];
   17002 }
   17003 def M4_cmpyr_whc : HInst<
   17004 (outs IntRegs:$Rd32),
   17005 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   17006 "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
   17007 tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> {
   17008 let Inst{7-5} = 0b111;
   17009 let Inst{13-13} = 0b0;
   17010 let Inst{31-21} = 0b11000101000;
   17011 let hasNewValue = 1;
   17012 let opNewValue = 0;
   17013 let prefersSlot3 = 1;
   17014 let Defs = [USR_OVF];
   17015 }
   17016 def M4_mac_up_s1_sat : HInst<
   17017 (outs IntRegs:$Rx32),
   17018 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17019 "$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
   17020 tc_e913dc32, TypeM>, Enc_2ae154 {
   17021 let Inst{7-5} = 0b000;
   17022 let Inst{13-13} = 0b0;
   17023 let Inst{31-21} = 0b11101111011;
   17024 let hasNewValue = 1;
   17025 let opNewValue = 0;
   17026 let prefersSlot3 = 1;
   17027 let Defs = [USR_OVF];
   17028 let InputType = "reg";
   17029 let Constraints = "$Rx32 = $Rx32in";
   17030 }
   17031 def M4_mpyri_addi : HInst<
   17032 (outs IntRegs:$Rd32),
   17033 (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
   17034 "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
   17035 tc_16d0d8d5, TypeALU64>, Enc_322e1b, ImmRegRel {
   17036 let Inst{31-24} = 0b11011000;
   17037 let hasNewValue = 1;
   17038 let opNewValue = 0;
   17039 let prefersSlot3 = 1;
   17040 let CextOpcode = "M4_mpyri_addr";
   17041 let isExtendable = 1;
   17042 let opExtendable = 1;
   17043 let isExtentSigned = 0;
   17044 let opExtentBits = 6;
   17045 let opExtentAlign = 0;
   17046 }
   17047 def M4_mpyri_addr : HInst<
   17048 (outs IntRegs:$Rd32),
   17049 (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
   17050 "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
   17051 tc_16d0d8d5, TypeALU64>, Enc_420cf3, ImmRegRel {
   17052 let Inst{31-23} = 0b110111111;
   17053 let hasNewValue = 1;
   17054 let opNewValue = 0;
   17055 let prefersSlot3 = 1;
   17056 let CextOpcode = "M4_mpyri_addr";
   17057 let InputType = "imm";
   17058 let isExtendable = 1;
   17059 let opExtendable = 3;
   17060 let isExtentSigned = 0;
   17061 let opExtentBits = 6;
   17062 let opExtentAlign = 0;
   17063 }
   17064 def M4_mpyri_addr_u2 : HInst<
   17065 (outs IntRegs:$Rd32),
   17066 (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
   17067 "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
   17068 tc_bcc96cee, TypeALU64>, Enc_277737 {
   17069 let Inst{31-23} = 0b110111110;
   17070 let hasNewValue = 1;
   17071 let opNewValue = 0;
   17072 let prefersSlot3 = 1;
   17073 }
   17074 def M4_mpyrr_addi : HInst<
   17075 (outs IntRegs:$Rd32),
   17076 (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
   17077 "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
   17078 tc_e913dc32, TypeALU64>, Enc_a7b8e8, ImmRegRel {
   17079 let Inst{31-23} = 0b110101110;
   17080 let hasNewValue = 1;
   17081 let opNewValue = 0;
   17082 let prefersSlot3 = 1;
   17083 let CextOpcode = "M4_mpyrr_addr";
   17084 let InputType = "imm";
   17085 let isExtendable = 1;
   17086 let opExtendable = 1;
   17087 let isExtentSigned = 0;
   17088 let opExtentBits = 6;
   17089 let opExtentAlign = 0;
   17090 }
   17091 def M4_mpyrr_addr : HInst<
   17092 (outs IntRegs:$Ry32),
   17093 (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
   17094 "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
   17095 tc_e913dc32, TypeM>, Enc_7f1a05, ImmRegRel {
   17096 let Inst{7-5} = 0b000;
   17097 let Inst{13-13} = 0b0;
   17098 let Inst{31-21} = 0b11100011000;
   17099 let hasNewValue = 1;
   17100 let opNewValue = 0;
   17101 let prefersSlot3 = 1;
   17102 let CextOpcode = "M4_mpyrr_addr";
   17103 let InputType = "reg";
   17104 let Constraints = "$Ry32 = $Ry32in";
   17105 }
   17106 def M4_nac_up_s1_sat : HInst<
   17107 (outs IntRegs:$Rx32),
   17108 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17109 "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
   17110 tc_e913dc32, TypeM>, Enc_2ae154 {
   17111 let Inst{7-5} = 0b001;
   17112 let Inst{13-13} = 0b0;
   17113 let Inst{31-21} = 0b11101111011;
   17114 let hasNewValue = 1;
   17115 let opNewValue = 0;
   17116 let prefersSlot3 = 1;
   17117 let Defs = [USR_OVF];
   17118 let InputType = "reg";
   17119 let Constraints = "$Rx32 = $Rx32in";
   17120 }
   17121 def M4_or_and : HInst<
   17122 (outs IntRegs:$Rx32),
   17123 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17124 "$Rx32 |= and($Rs32,$Rt32)",
   17125 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17126 let Inst{7-5} = 0b011;
   17127 let Inst{13-13} = 0b0;
   17128 let Inst{31-21} = 0b11101111010;
   17129 let hasNewValue = 1;
   17130 let opNewValue = 0;
   17131 let prefersSlot3 = 1;
   17132 let InputType = "reg";
   17133 let Constraints = "$Rx32 = $Rx32in";
   17134 }
   17135 def M4_or_andn : HInst<
   17136 (outs IntRegs:$Rx32),
   17137 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17138 "$Rx32 |= and($Rs32,~$Rt32)",
   17139 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17140 let Inst{7-5} = 0b000;
   17141 let Inst{13-13} = 0b0;
   17142 let Inst{31-21} = 0b11101111001;
   17143 let hasNewValue = 1;
   17144 let opNewValue = 0;
   17145 let prefersSlot3 = 1;
   17146 let InputType = "reg";
   17147 let Constraints = "$Rx32 = $Rx32in";
   17148 }
   17149 def M4_or_or : HInst<
   17150 (outs IntRegs:$Rx32),
   17151 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17152 "$Rx32 |= or($Rs32,$Rt32)",
   17153 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17154 let Inst{7-5} = 0b000;
   17155 let Inst{13-13} = 0b0;
   17156 let Inst{31-21} = 0b11101111110;
   17157 let hasNewValue = 1;
   17158 let opNewValue = 0;
   17159 let prefersSlot3 = 1;
   17160 let InputType = "reg";
   17161 let Constraints = "$Rx32 = $Rx32in";
   17162 }
   17163 def M4_or_xor : HInst<
   17164 (outs IntRegs:$Rx32),
   17165 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17166 "$Rx32 |= xor($Rs32,$Rt32)",
   17167 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17168 let Inst{7-5} = 0b001;
   17169 let Inst{13-13} = 0b0;
   17170 let Inst{31-21} = 0b11101111110;
   17171 let hasNewValue = 1;
   17172 let opNewValue = 0;
   17173 let prefersSlot3 = 1;
   17174 let InputType = "reg";
   17175 let Constraints = "$Rx32 = $Rx32in";
   17176 }
   17177 def M4_pmpyw : HInst<
   17178 (outs DoubleRegs:$Rdd32),
   17179 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   17180 "$Rdd32 = pmpyw($Rs32,$Rt32)",
   17181 tc_8fd5f294, TypeM>, Enc_be32a5 {
   17182 let Inst{7-5} = 0b111;
   17183 let Inst{13-13} = 0b0;
   17184 let Inst{31-21} = 0b11100101010;
   17185 let prefersSlot3 = 1;
   17186 }
   17187 def M4_pmpyw_acc : HInst<
   17188 (outs DoubleRegs:$Rxx32),
   17189 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17190 "$Rxx32 ^= pmpyw($Rs32,$Rt32)",
   17191 tc_e913dc32, TypeM>, Enc_61f0b0 {
   17192 let Inst{7-5} = 0b111;
   17193 let Inst{13-13} = 0b0;
   17194 let Inst{31-21} = 0b11100111001;
   17195 let prefersSlot3 = 1;
   17196 let Constraints = "$Rxx32 = $Rxx32in";
   17197 }
   17198 def M4_vpmpyh : HInst<
   17199 (outs DoubleRegs:$Rdd32),
   17200 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   17201 "$Rdd32 = vpmpyh($Rs32,$Rt32)",
   17202 tc_8fd5f294, TypeM>, Enc_be32a5 {
   17203 let Inst{7-5} = 0b111;
   17204 let Inst{13-13} = 0b0;
   17205 let Inst{31-21} = 0b11100101110;
   17206 let prefersSlot3 = 1;
   17207 }
   17208 def M4_vpmpyh_acc : HInst<
   17209 (outs DoubleRegs:$Rxx32),
   17210 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17211 "$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
   17212 tc_e913dc32, TypeM>, Enc_61f0b0 {
   17213 let Inst{7-5} = 0b111;
   17214 let Inst{13-13} = 0b0;
   17215 let Inst{31-21} = 0b11100111101;
   17216 let prefersSlot3 = 1;
   17217 let Constraints = "$Rxx32 = $Rxx32in";
   17218 }
   17219 def M4_vrmpyeh_acc_s0 : HInst<
   17220 (outs DoubleRegs:$Rxx32),
   17221 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17222 "$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
   17223 tc_e913dc32, TypeM>, Enc_88c16c {
   17224 let Inst{7-5} = 0b110;
   17225 let Inst{13-13} = 0b0;
   17226 let Inst{31-21} = 0b11101010001;
   17227 let prefersSlot3 = 1;
   17228 let Constraints = "$Rxx32 = $Rxx32in";
   17229 }
   17230 def M4_vrmpyeh_acc_s1 : HInst<
   17231 (outs DoubleRegs:$Rxx32),
   17232 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17233 "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
   17234 tc_e913dc32, TypeM>, Enc_88c16c {
   17235 let Inst{7-5} = 0b110;
   17236 let Inst{13-13} = 0b0;
   17237 let Inst{31-21} = 0b11101010101;
   17238 let prefersSlot3 = 1;
   17239 let Constraints = "$Rxx32 = $Rxx32in";
   17240 }
   17241 def M4_vrmpyeh_s0 : HInst<
   17242 (outs DoubleRegs:$Rdd32),
   17243 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17244 "$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
   17245 tc_8fd5f294, TypeM>, Enc_a56825 {
   17246 let Inst{7-5} = 0b100;
   17247 let Inst{13-13} = 0b0;
   17248 let Inst{31-21} = 0b11101000010;
   17249 let prefersSlot3 = 1;
   17250 }
   17251 def M4_vrmpyeh_s1 : HInst<
   17252 (outs DoubleRegs:$Rdd32),
   17253 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17254 "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
   17255 tc_8fd5f294, TypeM>, Enc_a56825 {
   17256 let Inst{7-5} = 0b100;
   17257 let Inst{13-13} = 0b0;
   17258 let Inst{31-21} = 0b11101000110;
   17259 let prefersSlot3 = 1;
   17260 }
   17261 def M4_vrmpyoh_acc_s0 : HInst<
   17262 (outs DoubleRegs:$Rxx32),
   17263 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17264 "$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
   17265 tc_e913dc32, TypeM>, Enc_88c16c {
   17266 let Inst{7-5} = 0b110;
   17267 let Inst{13-13} = 0b0;
   17268 let Inst{31-21} = 0b11101010011;
   17269 let prefersSlot3 = 1;
   17270 let Constraints = "$Rxx32 = $Rxx32in";
   17271 }
   17272 def M4_vrmpyoh_acc_s1 : HInst<
   17273 (outs DoubleRegs:$Rxx32),
   17274 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17275 "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
   17276 tc_e913dc32, TypeM>, Enc_88c16c {
   17277 let Inst{7-5} = 0b110;
   17278 let Inst{13-13} = 0b0;
   17279 let Inst{31-21} = 0b11101010111;
   17280 let prefersSlot3 = 1;
   17281 let Constraints = "$Rxx32 = $Rxx32in";
   17282 }
   17283 def M4_vrmpyoh_s0 : HInst<
   17284 (outs DoubleRegs:$Rdd32),
   17285 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17286 "$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
   17287 tc_8fd5f294, TypeM>, Enc_a56825 {
   17288 let Inst{7-5} = 0b010;
   17289 let Inst{13-13} = 0b0;
   17290 let Inst{31-21} = 0b11101000001;
   17291 let prefersSlot3 = 1;
   17292 }
   17293 def M4_vrmpyoh_s1 : HInst<
   17294 (outs DoubleRegs:$Rdd32),
   17295 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17296 "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
   17297 tc_8fd5f294, TypeM>, Enc_a56825 {
   17298 let Inst{7-5} = 0b010;
   17299 let Inst{13-13} = 0b0;
   17300 let Inst{31-21} = 0b11101000101;
   17301 let prefersSlot3 = 1;
   17302 }
   17303 def M4_xor_and : HInst<
   17304 (outs IntRegs:$Rx32),
   17305 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17306 "$Rx32 ^= and($Rs32,$Rt32)",
   17307 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17308 let Inst{7-5} = 0b010;
   17309 let Inst{13-13} = 0b0;
   17310 let Inst{31-21} = 0b11101111110;
   17311 let hasNewValue = 1;
   17312 let opNewValue = 0;
   17313 let prefersSlot3 = 1;
   17314 let InputType = "reg";
   17315 let Constraints = "$Rx32 = $Rx32in";
   17316 }
   17317 def M4_xor_andn : HInst<
   17318 (outs IntRegs:$Rx32),
   17319 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17320 "$Rx32 ^= and($Rs32,~$Rt32)",
   17321 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17322 let Inst{7-5} = 0b010;
   17323 let Inst{13-13} = 0b0;
   17324 let Inst{31-21} = 0b11101111001;
   17325 let hasNewValue = 1;
   17326 let opNewValue = 0;
   17327 let prefersSlot3 = 1;
   17328 let InputType = "reg";
   17329 let Constraints = "$Rx32 = $Rx32in";
   17330 }
   17331 def M4_xor_or : HInst<
   17332 (outs IntRegs:$Rx32),
   17333 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17334 "$Rx32 ^= or($Rs32,$Rt32)",
   17335 tc_84df2cd3, TypeM>, Enc_2ae154 {
   17336 let Inst{7-5} = 0b011;
   17337 let Inst{13-13} = 0b0;
   17338 let Inst{31-21} = 0b11101111110;
   17339 let hasNewValue = 1;
   17340 let opNewValue = 0;
   17341 let prefersSlot3 = 1;
   17342 let InputType = "reg";
   17343 let Constraints = "$Rx32 = $Rx32in";
   17344 }
   17345 def M4_xor_xacc : HInst<
   17346 (outs DoubleRegs:$Rxx32),
   17347 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17348 "$Rxx32 ^= xor($Rss32,$Rtt32)",
   17349 tc_84df2cd3, TypeS_3op>, Enc_88c16c {
   17350 let Inst{7-5} = 0b000;
   17351 let Inst{13-13} = 0b0;
   17352 let Inst{31-21} = 0b11001010100;
   17353 let prefersSlot3 = 1;
   17354 let Constraints = "$Rxx32 = $Rxx32in";
   17355 }
   17356 def M5_vdmacbsu : HInst<
   17357 (outs DoubleRegs:$Rxx32),
   17358 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17359 "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
   17360 tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5]> {
   17361 let Inst{7-5} = 0b001;
   17362 let Inst{13-13} = 0b0;
   17363 let Inst{31-21} = 0b11101010001;
   17364 let prefersSlot3 = 1;
   17365 let Defs = [USR_OVF];
   17366 let Constraints = "$Rxx32 = $Rxx32in";
   17367 }
   17368 def M5_vdmpybsu : HInst<
   17369 (outs DoubleRegs:$Rdd32),
   17370 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17371 "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
   17372 tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5]> {
   17373 let Inst{7-5} = 0b001;
   17374 let Inst{13-13} = 0b0;
   17375 let Inst{31-21} = 0b11101000101;
   17376 let prefersSlot3 = 1;
   17377 let Defs = [USR_OVF];
   17378 }
   17379 def M5_vmacbsu : HInst<
   17380 (outs DoubleRegs:$Rxx32),
   17381 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17382 "$Rxx32 += vmpybsu($Rs32,$Rt32)",
   17383 tc_e913dc32, TypeM>, Enc_61f0b0 {
   17384 let Inst{7-5} = 0b001;
   17385 let Inst{13-13} = 0b0;
   17386 let Inst{31-21} = 0b11100111110;
   17387 let prefersSlot3 = 1;
   17388 let Constraints = "$Rxx32 = $Rxx32in";
   17389 }
   17390 def M5_vmacbuu : HInst<
   17391 (outs DoubleRegs:$Rxx32),
   17392 (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   17393 "$Rxx32 += vmpybu($Rs32,$Rt32)",
   17394 tc_e913dc32, TypeM>, Enc_61f0b0 {
   17395 let Inst{7-5} = 0b001;
   17396 let Inst{13-13} = 0b0;
   17397 let Inst{31-21} = 0b11100111100;
   17398 let prefersSlot3 = 1;
   17399 let Constraints = "$Rxx32 = $Rxx32in";
   17400 }
   17401 def M5_vmpybsu : HInst<
   17402 (outs DoubleRegs:$Rdd32),
   17403 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   17404 "$Rdd32 = vmpybsu($Rs32,$Rt32)",
   17405 tc_8fd5f294, TypeM>, Enc_be32a5 {
   17406 let Inst{7-5} = 0b001;
   17407 let Inst{13-13} = 0b0;
   17408 let Inst{31-21} = 0b11100101010;
   17409 let prefersSlot3 = 1;
   17410 }
   17411 def M5_vmpybuu : HInst<
   17412 (outs DoubleRegs:$Rdd32),
   17413 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   17414 "$Rdd32 = vmpybu($Rs32,$Rt32)",
   17415 tc_8fd5f294, TypeM>, Enc_be32a5 {
   17416 let Inst{7-5} = 0b001;
   17417 let Inst{13-13} = 0b0;
   17418 let Inst{31-21} = 0b11100101100;
   17419 let prefersSlot3 = 1;
   17420 }
   17421 def M5_vrmacbsu : HInst<
   17422 (outs DoubleRegs:$Rxx32),
   17423 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17424 "$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
   17425 tc_e913dc32, TypeM>, Enc_88c16c {
   17426 let Inst{7-5} = 0b001;
   17427 let Inst{13-13} = 0b0;
   17428 let Inst{31-21} = 0b11101010110;
   17429 let prefersSlot3 = 1;
   17430 let Constraints = "$Rxx32 = $Rxx32in";
   17431 }
   17432 def M5_vrmacbuu : HInst<
   17433 (outs DoubleRegs:$Rxx32),
   17434 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17435 "$Rxx32 += vrmpybu($Rss32,$Rtt32)",
   17436 tc_e913dc32, TypeM>, Enc_88c16c {
   17437 let Inst{7-5} = 0b001;
   17438 let Inst{13-13} = 0b0;
   17439 let Inst{31-21} = 0b11101010100;
   17440 let prefersSlot3 = 1;
   17441 let Constraints = "$Rxx32 = $Rxx32in";
   17442 }
   17443 def M5_vrmpybsu : HInst<
   17444 (outs DoubleRegs:$Rdd32),
   17445 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17446 "$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
   17447 tc_8fd5f294, TypeM>, Enc_a56825 {
   17448 let Inst{7-5} = 0b001;
   17449 let Inst{13-13} = 0b0;
   17450 let Inst{31-21} = 0b11101000110;
   17451 let prefersSlot3 = 1;
   17452 }
   17453 def M5_vrmpybuu : HInst<
   17454 (outs DoubleRegs:$Rdd32),
   17455 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   17456 "$Rdd32 = vrmpybu($Rss32,$Rtt32)",
   17457 tc_8fd5f294, TypeM>, Enc_a56825 {
   17458 let Inst{7-5} = 0b001;
   17459 let Inst{13-13} = 0b0;
   17460 let Inst{31-21} = 0b11101000100;
   17461 let prefersSlot3 = 1;
   17462 }
   17463 def M6_vabsdiffb : HInst<
   17464 (outs DoubleRegs:$Rdd32),
   17465 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   17466 "$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
   17467 tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
   17468 let Inst{7-5} = 0b000;
   17469 let Inst{13-13} = 0b0;
   17470 let Inst{31-21} = 0b11101000111;
   17471 let prefersSlot3 = 1;
   17472 }
   17473 def M6_vabsdiffub : HInst<
   17474 (outs DoubleRegs:$Rdd32),
   17475 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   17476 "$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
   17477 tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
   17478 let Inst{7-5} = 0b000;
   17479 let Inst{13-13} = 0b0;
   17480 let Inst{31-21} = 0b11101000101;
   17481 let prefersSlot3 = 1;
   17482 }
   17483 def PS_loadrbabs : HInst<
   17484 (outs IntRegs:$Rd32),
   17485 (ins u32_0Imm:$Ii),
   17486 "$Rd32 = memb(#$Ii)",
   17487 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
   17488 let Inst{24-21} = 0b1000;
   17489 let Inst{31-27} = 0b01001;
   17490 let hasNewValue = 1;
   17491 let opNewValue = 0;
   17492 let addrMode = Absolute;
   17493 let accessSize = ByteAccess;
   17494 let mayLoad = 1;
   17495 let isExtended = 1;
   17496 let CextOpcode = "L2_loadrb";
   17497 let BaseOpcode = "L4_loadrb_abs";
   17498 let isPredicable = 1;
   17499 let DecoderNamespace = "MustExtend";
   17500 let isExtended = 1;
   17501 let opExtendable = 1;
   17502 let isExtentSigned = 0;
   17503 let opExtentBits = 16;
   17504 let opExtentAlign = 0;
   17505 }
   17506 def PS_loadrdabs : HInst<
   17507 (outs DoubleRegs:$Rdd32),
   17508 (ins u29_3Imm:$Ii),
   17509 "$Rdd32 = memd(#$Ii)",
   17510 tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel {
   17511 let Inst{24-21} = 0b1110;
   17512 let Inst{31-27} = 0b01001;
   17513 let addrMode = Absolute;
   17514 let accessSize = DoubleWordAccess;
   17515 let mayLoad = 1;
   17516 let isExtended = 1;
   17517 let CextOpcode = "L2_loadrd";
   17518 let BaseOpcode = "L4_loadrd_abs";
   17519 let isPredicable = 1;
   17520 let DecoderNamespace = "MustExtend";
   17521 let isExtended = 1;
   17522 let opExtendable = 1;
   17523 let isExtentSigned = 0;
   17524 let opExtentBits = 19;
   17525 let opExtentAlign = 3;
   17526 }
   17527 def PS_loadrhabs : HInst<
   17528 (outs IntRegs:$Rd32),
   17529 (ins u31_1Imm:$Ii),
   17530 "$Rd32 = memh(#$Ii)",
   17531 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
   17532 let Inst{24-21} = 0b1010;
   17533 let Inst{31-27} = 0b01001;
   17534 let hasNewValue = 1;
   17535 let opNewValue = 0;
   17536 let addrMode = Absolute;
   17537 let accessSize = HalfWordAccess;
   17538 let mayLoad = 1;
   17539 let isExtended = 1;
   17540 let CextOpcode = "L2_loadrh";
   17541 let BaseOpcode = "L4_loadrh_abs";
   17542 let isPredicable = 1;
   17543 let DecoderNamespace = "MustExtend";
   17544 let isExtended = 1;
   17545 let opExtendable = 1;
   17546 let isExtentSigned = 0;
   17547 let opExtentBits = 17;
   17548 let opExtentAlign = 1;
   17549 }
   17550 def PS_loadriabs : HInst<
   17551 (outs IntRegs:$Rd32),
   17552 (ins u30_2Imm:$Ii),
   17553 "$Rd32 = memw(#$Ii)",
   17554 tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
   17555 let Inst{24-21} = 0b1100;
   17556 let Inst{31-27} = 0b01001;
   17557 let hasNewValue = 1;
   17558 let opNewValue = 0;
   17559 let addrMode = Absolute;
   17560 let accessSize = WordAccess;
   17561 let mayLoad = 1;
   17562 let isExtended = 1;
   17563 let CextOpcode = "L2_loadri";
   17564 let BaseOpcode = "L4_loadri_abs";
   17565 let isPredicable = 1;
   17566 let DecoderNamespace = "MustExtend";
   17567 let isExtended = 1;
   17568 let opExtendable = 1;
   17569 let isExtentSigned = 0;
   17570 let opExtentBits = 18;
   17571 let opExtentAlign = 2;
   17572 }
   17573 def PS_loadrubabs : HInst<
   17574 (outs IntRegs:$Rd32),
   17575 (ins u32_0Imm:$Ii),
   17576 "$Rd32 = memub(#$Ii)",
   17577 tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel {
   17578 let Inst{24-21} = 0b1001;
   17579 let Inst{31-27} = 0b01001;
   17580 let hasNewValue = 1;
   17581 let opNewValue = 0;
   17582 let addrMode = Absolute;
   17583 let accessSize = ByteAccess;
   17584 let mayLoad = 1;
   17585 let isExtended = 1;
   17586 let CextOpcode = "L2_loadrub";
   17587 let BaseOpcode = "L4_loadrub_abs";
   17588 let isPredicable = 1;
   17589 let DecoderNamespace = "MustExtend";
   17590 let isExtended = 1;
   17591 let opExtendable = 1;
   17592 let isExtentSigned = 0;
   17593 let opExtentBits = 16;
   17594 let opExtentAlign = 0;
   17595 }
   17596 def PS_loadruhabs : HInst<
   17597 (outs IntRegs:$Rd32),
   17598 (ins u31_1Imm:$Ii),
   17599 "$Rd32 = memuh(#$Ii)",
   17600 tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel {
   17601 let Inst{24-21} = 0b1011;
   17602 let Inst{31-27} = 0b01001;
   17603 let hasNewValue = 1;
   17604 let opNewValue = 0;
   17605 let addrMode = Absolute;
   17606 let accessSize = HalfWordAccess;
   17607 let mayLoad = 1;
   17608 let isExtended = 1;
   17609 let CextOpcode = "L2_loadruh";
   17610 let BaseOpcode = "L4_loadruh_abs";
   17611 let isPredicable = 1;
   17612 let DecoderNamespace = "MustExtend";
   17613 let isExtended = 1;
   17614 let opExtendable = 1;
   17615 let isExtentSigned = 0;
   17616 let opExtentBits = 17;
   17617 let opExtentAlign = 1;
   17618 }
   17619 def PS_storerbabs : HInst<
   17620 (outs),
   17621 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
   17622 "memb(#$Ii) = $Rt32",
   17623 tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
   17624 let Inst{24-21} = 0b0000;
   17625 let Inst{31-27} = 0b01001;
   17626 let addrMode = Absolute;
   17627 let accessSize = ByteAccess;
   17628 let isExtended = 1;
   17629 let mayStore = 1;
   17630 let CextOpcode = "S2_storerb";
   17631 let BaseOpcode = "S2_storerbabs";
   17632 let isPredicable = 1;
   17633 let isNVStorable = 1;
   17634 let DecoderNamespace = "MustExtend";
   17635 let isExtended = 1;
   17636 let opExtendable = 0;
   17637 let isExtentSigned = 0;
   17638 let opExtentBits = 16;
   17639 let opExtentAlign = 0;
   17640 }
   17641 def PS_storerbnewabs : HInst<
   17642 (outs),
   17643 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
   17644 "memb(#$Ii) = $Nt8.new",
   17645 tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
   17646 let Inst{12-11} = 0b00;
   17647 let Inst{24-21} = 0b0101;
   17648 let Inst{31-27} = 0b01001;
   17649 let addrMode = Absolute;
   17650 let accessSize = ByteAccess;
   17651 let isNVStore = 1;
   17652 let isNewValue = 1;
   17653 let isExtended = 1;
   17654 let isRestrictNoSlot1Store = 1;
   17655 let mayStore = 1;
   17656 let CextOpcode = "S2_storerb";
   17657 let BaseOpcode = "S2_storerbabs";
   17658 let isPredicable = 1;
   17659 let DecoderNamespace = "MustExtend";
   17660 let isExtended = 1;
   17661 let opExtendable = 0;
   17662 let isExtentSigned = 0;
   17663 let opExtentBits = 16;
   17664 let opExtentAlign = 0;
   17665 let opNewValue = 1;
   17666 }
   17667 def PS_storerdabs : HInst<
   17668 (outs),
   17669 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   17670 "memd(#$Ii) = $Rtt32",
   17671 tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
   17672 let Inst{24-21} = 0b0110;
   17673 let Inst{31-27} = 0b01001;
   17674 let addrMode = Absolute;
   17675 let accessSize = DoubleWordAccess;
   17676 let isExtended = 1;
   17677 let mayStore = 1;
   17678 let CextOpcode = "S2_storerd";
   17679 let BaseOpcode = "S2_storerdabs";
   17680 let isPredicable = 1;
   17681 let DecoderNamespace = "MustExtend";
   17682 let isExtended = 1;
   17683 let opExtendable = 0;
   17684 let isExtentSigned = 0;
   17685 let opExtentBits = 19;
   17686 let opExtentAlign = 3;
   17687 }
   17688 def PS_storerfabs : HInst<
   17689 (outs),
   17690 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
   17691 "memh(#$Ii) = $Rt32.h",
   17692 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
   17693 let Inst{24-21} = 0b0011;
   17694 let Inst{31-27} = 0b01001;
   17695 let addrMode = Absolute;
   17696 let accessSize = HalfWordAccess;
   17697 let isExtended = 1;
   17698 let mayStore = 1;
   17699 let CextOpcode = "S2_storerf";
   17700 let BaseOpcode = "S2_storerfabs";
   17701 let isPredicable = 1;
   17702 let DecoderNamespace = "MustExtend";
   17703 let isExtended = 1;
   17704 let opExtendable = 0;
   17705 let isExtentSigned = 0;
   17706 let opExtentBits = 17;
   17707 let opExtentAlign = 1;
   17708 }
   17709 def PS_storerhabs : HInst<
   17710 (outs),
   17711 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
   17712 "memh(#$Ii) = $Rt32",
   17713 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
   17714 let Inst{24-21} = 0b0010;
   17715 let Inst{31-27} = 0b01001;
   17716 let addrMode = Absolute;
   17717 let accessSize = HalfWordAccess;
   17718 let isExtended = 1;
   17719 let mayStore = 1;
   17720 let CextOpcode = "S2_storerh";
   17721 let BaseOpcode = "S2_storerhabs";
   17722 let isPredicable = 1;
   17723 let isNVStorable = 1;
   17724 let DecoderNamespace = "MustExtend";
   17725 let isExtended = 1;
   17726 let opExtendable = 0;
   17727 let isExtentSigned = 0;
   17728 let opExtentBits = 17;
   17729 let opExtentAlign = 1;
   17730 }
   17731 def PS_storerhnewabs : HInst<
   17732 (outs),
   17733 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
   17734 "memh(#$Ii) = $Nt8.new",
   17735 tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
   17736 let Inst{12-11} = 0b01;
   17737 let Inst{24-21} = 0b0101;
   17738 let Inst{31-27} = 0b01001;
   17739 let addrMode = Absolute;
   17740 let accessSize = HalfWordAccess;
   17741 let isNVStore = 1;
   17742 let isNewValue = 1;
   17743 let isExtended = 1;
   17744 let isRestrictNoSlot1Store = 1;
   17745 let mayStore = 1;
   17746 let CextOpcode = "S2_storerh";
   17747 let BaseOpcode = "S2_storerhabs";
   17748 let isPredicable = 1;
   17749 let DecoderNamespace = "MustExtend";
   17750 let isExtended = 1;
   17751 let opExtendable = 0;
   17752 let isExtentSigned = 0;
   17753 let opExtentBits = 17;
   17754 let opExtentAlign = 1;
   17755 let opNewValue = 1;
   17756 }
   17757 def PS_storeriabs : HInst<
   17758 (outs),
   17759 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
   17760 "memw(#$Ii) = $Rt32",
   17761 tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
   17762 let Inst{24-21} = 0b0100;
   17763 let Inst{31-27} = 0b01001;
   17764 let addrMode = Absolute;
   17765 let accessSize = WordAccess;
   17766 let isExtended = 1;
   17767 let mayStore = 1;
   17768 let CextOpcode = "S2_storeri";
   17769 let BaseOpcode = "S2_storeriabs";
   17770 let isPredicable = 1;
   17771 let isNVStorable = 1;
   17772 let DecoderNamespace = "MustExtend";
   17773 let isExtended = 1;
   17774 let opExtendable = 0;
   17775 let isExtentSigned = 0;
   17776 let opExtentBits = 18;
   17777 let opExtentAlign = 2;
   17778 }
   17779 def PS_storerinewabs : HInst<
   17780 (outs),
   17781 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
   17782 "memw(#$Ii) = $Nt8.new",
   17783 tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
   17784 let Inst{12-11} = 0b10;
   17785 let Inst{24-21} = 0b0101;
   17786 let Inst{31-27} = 0b01001;
   17787 let addrMode = Absolute;
   17788 let accessSize = WordAccess;
   17789 let isNVStore = 1;
   17790 let isNewValue = 1;
   17791 let isExtended = 1;
   17792 let isRestrictNoSlot1Store = 1;
   17793 let mayStore = 1;
   17794 let CextOpcode = "S2_storeri";
   17795 let BaseOpcode = "S2_storeriabs";
   17796 let isPredicable = 1;
   17797 let DecoderNamespace = "MustExtend";
   17798 let isExtended = 1;
   17799 let opExtendable = 0;
   17800 let isExtentSigned = 0;
   17801 let opExtentBits = 18;
   17802 let opExtentAlign = 2;
   17803 let opNewValue = 1;
   17804 }
   17805 def S2_addasl_rrri : HInst<
   17806 (outs IntRegs:$Rd32),
   17807 (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
   17808 "$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
   17809 tc_c74f796f, TypeS_3op>, Enc_47ef61 {
   17810 let Inst{13-13} = 0b0;
   17811 let Inst{31-21} = 0b11000100000;
   17812 let hasNewValue = 1;
   17813 let opNewValue = 0;
   17814 let prefersSlot3 = 1;
   17815 }
   17816 def S2_allocframe : HInst<
   17817 (outs IntRegs:$Rx32),
   17818 (ins IntRegs:$Rx32in, u11_3Imm:$Ii),
   17819 "allocframe($Rx32,#$Ii):raw",
   17820 tc_e216a5db, TypeST>, Enc_22c845 {
   17821 let Inst{13-11} = 0b000;
   17822 let Inst{31-21} = 0b10100000100;
   17823 let hasNewValue = 1;
   17824 let opNewValue = 0;
   17825 let addrMode = BaseImmOffset;
   17826 let accessSize = DoubleWordAccess;
   17827 let mayStore = 1;
   17828 let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
   17829 let Defs = [R30];
   17830 let Constraints = "$Rx32 = $Rx32in";
   17831 }
   17832 def S2_asl_i_p : HInst<
   17833 (outs DoubleRegs:$Rdd32),
   17834 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17835 "$Rdd32 = asl($Rss32,#$Ii)",
   17836 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
   17837 let Inst{7-5} = 0b010;
   17838 let Inst{31-21} = 0b10000000000;
   17839 }
   17840 def S2_asl_i_p_acc : HInst<
   17841 (outs DoubleRegs:$Rxx32),
   17842 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17843 "$Rxx32 += asl($Rss32,#$Ii)",
   17844 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   17845 let Inst{7-5} = 0b110;
   17846 let Inst{31-21} = 0b10000010000;
   17847 let prefersSlot3 = 1;
   17848 let Constraints = "$Rxx32 = $Rxx32in";
   17849 }
   17850 def S2_asl_i_p_and : HInst<
   17851 (outs DoubleRegs:$Rxx32),
   17852 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17853 "$Rxx32 &= asl($Rss32,#$Ii)",
   17854 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   17855 let Inst{7-5} = 0b010;
   17856 let Inst{31-21} = 0b10000010010;
   17857 let prefersSlot3 = 1;
   17858 let Constraints = "$Rxx32 = $Rxx32in";
   17859 }
   17860 def S2_asl_i_p_nac : HInst<
   17861 (outs DoubleRegs:$Rxx32),
   17862 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17863 "$Rxx32 -= asl($Rss32,#$Ii)",
   17864 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   17865 let Inst{7-5} = 0b010;
   17866 let Inst{31-21} = 0b10000010000;
   17867 let prefersSlot3 = 1;
   17868 let Constraints = "$Rxx32 = $Rxx32in";
   17869 }
   17870 def S2_asl_i_p_or : HInst<
   17871 (outs DoubleRegs:$Rxx32),
   17872 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17873 "$Rxx32 |= asl($Rss32,#$Ii)",
   17874 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   17875 let Inst{7-5} = 0b110;
   17876 let Inst{31-21} = 0b10000010010;
   17877 let prefersSlot3 = 1;
   17878 let Constraints = "$Rxx32 = $Rxx32in";
   17879 }
   17880 def S2_asl_i_p_xacc : HInst<
   17881 (outs DoubleRegs:$Rxx32),
   17882 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   17883 "$Rxx32 ^= asl($Rss32,#$Ii)",
   17884 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   17885 let Inst{7-5} = 0b010;
   17886 let Inst{31-21} = 0b10000010100;
   17887 let prefersSlot3 = 1;
   17888 let Constraints = "$Rxx32 = $Rxx32in";
   17889 }
   17890 def S2_asl_i_r : HInst<
   17891 (outs IntRegs:$Rd32),
   17892 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   17893 "$Rd32 = asl($Rs32,#$Ii)",
   17894 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   17895 let Inst{7-5} = 0b010;
   17896 let Inst{13-13} = 0b0;
   17897 let Inst{31-21} = 0b10001100000;
   17898 let hasNewValue = 1;
   17899 let opNewValue = 0;
   17900 }
   17901 def S2_asl_i_r_acc : HInst<
   17902 (outs IntRegs:$Rx32),
   17903 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   17904 "$Rx32 += asl($Rs32,#$Ii)",
   17905 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   17906 let Inst{7-5} = 0b110;
   17907 let Inst{13-13} = 0b0;
   17908 let Inst{31-21} = 0b10001110000;
   17909 let hasNewValue = 1;
   17910 let opNewValue = 0;
   17911 let prefersSlot3 = 1;
   17912 let Constraints = "$Rx32 = $Rx32in";
   17913 }
   17914 def S2_asl_i_r_and : HInst<
   17915 (outs IntRegs:$Rx32),
   17916 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   17917 "$Rx32 &= asl($Rs32,#$Ii)",
   17918 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   17919 let Inst{7-5} = 0b010;
   17920 let Inst{13-13} = 0b0;
   17921 let Inst{31-21} = 0b10001110010;
   17922 let hasNewValue = 1;
   17923 let opNewValue = 0;
   17924 let prefersSlot3 = 1;
   17925 let Constraints = "$Rx32 = $Rx32in";
   17926 }
   17927 def S2_asl_i_r_nac : HInst<
   17928 (outs IntRegs:$Rx32),
   17929 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   17930 "$Rx32 -= asl($Rs32,#$Ii)",
   17931 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   17932 let Inst{7-5} = 0b010;
   17933 let Inst{13-13} = 0b0;
   17934 let Inst{31-21} = 0b10001110000;
   17935 let hasNewValue = 1;
   17936 let opNewValue = 0;
   17937 let prefersSlot3 = 1;
   17938 let Constraints = "$Rx32 = $Rx32in";
   17939 }
   17940 def S2_asl_i_r_or : HInst<
   17941 (outs IntRegs:$Rx32),
   17942 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   17943 "$Rx32 |= asl($Rs32,#$Ii)",
   17944 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   17945 let Inst{7-5} = 0b110;
   17946 let Inst{13-13} = 0b0;
   17947 let Inst{31-21} = 0b10001110010;
   17948 let hasNewValue = 1;
   17949 let opNewValue = 0;
   17950 let prefersSlot3 = 1;
   17951 let Constraints = "$Rx32 = $Rx32in";
   17952 }
   17953 def S2_asl_i_r_sat : HInst<
   17954 (outs IntRegs:$Rd32),
   17955 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   17956 "$Rd32 = asl($Rs32,#$Ii):sat",
   17957 tc_b44c6e2a, TypeS_2op>, Enc_a05677 {
   17958 let Inst{7-5} = 0b010;
   17959 let Inst{13-13} = 0b0;
   17960 let Inst{31-21} = 0b10001100010;
   17961 let hasNewValue = 1;
   17962 let opNewValue = 0;
   17963 let prefersSlot3 = 1;
   17964 let Defs = [USR_OVF];
   17965 }
   17966 def S2_asl_i_r_xacc : HInst<
   17967 (outs IntRegs:$Rx32),
   17968 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   17969 "$Rx32 ^= asl($Rs32,#$Ii)",
   17970 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   17971 let Inst{7-5} = 0b010;
   17972 let Inst{13-13} = 0b0;
   17973 let Inst{31-21} = 0b10001110100;
   17974 let hasNewValue = 1;
   17975 let opNewValue = 0;
   17976 let prefersSlot3 = 1;
   17977 let Constraints = "$Rx32 = $Rx32in";
   17978 }
   17979 def S2_asl_i_vh : HInst<
   17980 (outs DoubleRegs:$Rdd32),
   17981 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   17982 "$Rdd32 = vaslh($Rss32,#$Ii)",
   17983 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
   17984 let Inst{7-5} = 0b010;
   17985 let Inst{13-12} = 0b00;
   17986 let Inst{31-21} = 0b10000000100;
   17987 }
   17988 def S2_asl_i_vw : HInst<
   17989 (outs DoubleRegs:$Rdd32),
   17990 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
   17991 "$Rdd32 = vaslw($Rss32,#$Ii)",
   17992 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
   17993 let Inst{7-5} = 0b010;
   17994 let Inst{13-13} = 0b0;
   17995 let Inst{31-21} = 0b10000000010;
   17996 }
   17997 def S2_asl_r_p : HInst<
   17998 (outs DoubleRegs:$Rdd32),
   17999 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18000 "$Rdd32 = asl($Rss32,$Rt32)",
   18001 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18002 let Inst{7-5} = 0b100;
   18003 let Inst{13-13} = 0b0;
   18004 let Inst{31-21} = 0b11000011100;
   18005 }
   18006 def S2_asl_r_p_acc : HInst<
   18007 (outs DoubleRegs:$Rxx32),
   18008 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18009 "$Rxx32 += asl($Rss32,$Rt32)",
   18010 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18011 let Inst{7-5} = 0b100;
   18012 let Inst{13-13} = 0b0;
   18013 let Inst{31-21} = 0b11001011110;
   18014 let prefersSlot3 = 1;
   18015 let Constraints = "$Rxx32 = $Rxx32in";
   18016 }
   18017 def S2_asl_r_p_and : HInst<
   18018 (outs DoubleRegs:$Rxx32),
   18019 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18020 "$Rxx32 &= asl($Rss32,$Rt32)",
   18021 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18022 let Inst{7-5} = 0b100;
   18023 let Inst{13-13} = 0b0;
   18024 let Inst{31-21} = 0b11001011010;
   18025 let prefersSlot3 = 1;
   18026 let Constraints = "$Rxx32 = $Rxx32in";
   18027 }
   18028 def S2_asl_r_p_nac : HInst<
   18029 (outs DoubleRegs:$Rxx32),
   18030 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18031 "$Rxx32 -= asl($Rss32,$Rt32)",
   18032 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18033 let Inst{7-5} = 0b100;
   18034 let Inst{13-13} = 0b0;
   18035 let Inst{31-21} = 0b11001011100;
   18036 let prefersSlot3 = 1;
   18037 let Constraints = "$Rxx32 = $Rxx32in";
   18038 }
   18039 def S2_asl_r_p_or : HInst<
   18040 (outs DoubleRegs:$Rxx32),
   18041 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18042 "$Rxx32 |= asl($Rss32,$Rt32)",
   18043 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18044 let Inst{7-5} = 0b100;
   18045 let Inst{13-13} = 0b0;
   18046 let Inst{31-21} = 0b11001011000;
   18047 let prefersSlot3 = 1;
   18048 let Constraints = "$Rxx32 = $Rxx32in";
   18049 }
   18050 def S2_asl_r_p_xor : HInst<
   18051 (outs DoubleRegs:$Rxx32),
   18052 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18053 "$Rxx32 ^= asl($Rss32,$Rt32)",
   18054 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18055 let Inst{7-5} = 0b100;
   18056 let Inst{13-13} = 0b0;
   18057 let Inst{31-21} = 0b11001011011;
   18058 let prefersSlot3 = 1;
   18059 let Constraints = "$Rxx32 = $Rxx32in";
   18060 }
   18061 def S2_asl_r_r : HInst<
   18062 (outs IntRegs:$Rd32),
   18063 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18064 "$Rd32 = asl($Rs32,$Rt32)",
   18065 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   18066 let Inst{7-5} = 0b100;
   18067 let Inst{13-13} = 0b0;
   18068 let Inst{31-21} = 0b11000110010;
   18069 let hasNewValue = 1;
   18070 let opNewValue = 0;
   18071 }
   18072 def S2_asl_r_r_acc : HInst<
   18073 (outs IntRegs:$Rx32),
   18074 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18075 "$Rx32 += asl($Rs32,$Rt32)",
   18076 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18077 let Inst{7-5} = 0b100;
   18078 let Inst{13-13} = 0b0;
   18079 let Inst{31-21} = 0b11001100110;
   18080 let hasNewValue = 1;
   18081 let opNewValue = 0;
   18082 let prefersSlot3 = 1;
   18083 let Constraints = "$Rx32 = $Rx32in";
   18084 }
   18085 def S2_asl_r_r_and : HInst<
   18086 (outs IntRegs:$Rx32),
   18087 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18088 "$Rx32 &= asl($Rs32,$Rt32)",
   18089 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18090 let Inst{7-5} = 0b100;
   18091 let Inst{13-13} = 0b0;
   18092 let Inst{31-21} = 0b11001100010;
   18093 let hasNewValue = 1;
   18094 let opNewValue = 0;
   18095 let prefersSlot3 = 1;
   18096 let Constraints = "$Rx32 = $Rx32in";
   18097 }
   18098 def S2_asl_r_r_nac : HInst<
   18099 (outs IntRegs:$Rx32),
   18100 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18101 "$Rx32 -= asl($Rs32,$Rt32)",
   18102 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18103 let Inst{7-5} = 0b100;
   18104 let Inst{13-13} = 0b0;
   18105 let Inst{31-21} = 0b11001100100;
   18106 let hasNewValue = 1;
   18107 let opNewValue = 0;
   18108 let prefersSlot3 = 1;
   18109 let Constraints = "$Rx32 = $Rx32in";
   18110 }
   18111 def S2_asl_r_r_or : HInst<
   18112 (outs IntRegs:$Rx32),
   18113 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18114 "$Rx32 |= asl($Rs32,$Rt32)",
   18115 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18116 let Inst{7-5} = 0b100;
   18117 let Inst{13-13} = 0b0;
   18118 let Inst{31-21} = 0b11001100000;
   18119 let hasNewValue = 1;
   18120 let opNewValue = 0;
   18121 let prefersSlot3 = 1;
   18122 let Constraints = "$Rx32 = $Rx32in";
   18123 }
   18124 def S2_asl_r_r_sat : HInst<
   18125 (outs IntRegs:$Rd32),
   18126 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18127 "$Rd32 = asl($Rs32,$Rt32):sat",
   18128 tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
   18129 let Inst{7-5} = 0b100;
   18130 let Inst{13-13} = 0b0;
   18131 let Inst{31-21} = 0b11000110000;
   18132 let hasNewValue = 1;
   18133 let opNewValue = 0;
   18134 let prefersSlot3 = 1;
   18135 let Defs = [USR_OVF];
   18136 }
   18137 def S2_asl_r_vh : HInst<
   18138 (outs DoubleRegs:$Rdd32),
   18139 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18140 "$Rdd32 = vaslh($Rss32,$Rt32)",
   18141 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18142 let Inst{7-5} = 0b100;
   18143 let Inst{13-13} = 0b0;
   18144 let Inst{31-21} = 0b11000011010;
   18145 }
   18146 def S2_asl_r_vw : HInst<
   18147 (outs DoubleRegs:$Rdd32),
   18148 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18149 "$Rdd32 = vaslw($Rss32,$Rt32)",
   18150 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18151 let Inst{7-5} = 0b100;
   18152 let Inst{13-13} = 0b0;
   18153 let Inst{31-21} = 0b11000011000;
   18154 }
   18155 def S2_asr_i_p : HInst<
   18156 (outs DoubleRegs:$Rdd32),
   18157 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18158 "$Rdd32 = asr($Rss32,#$Ii)",
   18159 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
   18160 let Inst{7-5} = 0b000;
   18161 let Inst{31-21} = 0b10000000000;
   18162 }
   18163 def S2_asr_i_p_acc : HInst<
   18164 (outs DoubleRegs:$Rxx32),
   18165 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18166 "$Rxx32 += asr($Rss32,#$Ii)",
   18167 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   18168 let Inst{7-5} = 0b100;
   18169 let Inst{31-21} = 0b10000010000;
   18170 let prefersSlot3 = 1;
   18171 let Constraints = "$Rxx32 = $Rxx32in";
   18172 }
   18173 def S2_asr_i_p_and : HInst<
   18174 (outs DoubleRegs:$Rxx32),
   18175 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18176 "$Rxx32 &= asr($Rss32,#$Ii)",
   18177 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   18178 let Inst{7-5} = 0b000;
   18179 let Inst{31-21} = 0b10000010010;
   18180 let prefersSlot3 = 1;
   18181 let Constraints = "$Rxx32 = $Rxx32in";
   18182 }
   18183 def S2_asr_i_p_nac : HInst<
   18184 (outs DoubleRegs:$Rxx32),
   18185 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18186 "$Rxx32 -= asr($Rss32,#$Ii)",
   18187 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   18188 let Inst{7-5} = 0b000;
   18189 let Inst{31-21} = 0b10000010000;
   18190 let prefersSlot3 = 1;
   18191 let Constraints = "$Rxx32 = $Rxx32in";
   18192 }
   18193 def S2_asr_i_p_or : HInst<
   18194 (outs DoubleRegs:$Rxx32),
   18195 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18196 "$Rxx32 |= asr($Rss32,#$Ii)",
   18197 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   18198 let Inst{7-5} = 0b100;
   18199 let Inst{31-21} = 0b10000010010;
   18200 let prefersSlot3 = 1;
   18201 let Constraints = "$Rxx32 = $Rxx32in";
   18202 }
   18203 def S2_asr_i_p_rnd : HInst<
   18204 (outs DoubleRegs:$Rdd32),
   18205 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18206 "$Rdd32 = asr($Rss32,#$Ii):rnd",
   18207 tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5]> {
   18208 let Inst{7-5} = 0b111;
   18209 let Inst{31-21} = 0b10000000110;
   18210 let prefersSlot3 = 1;
   18211 }
   18212 def S2_asr_i_p_rnd_goodsyntax : HInst<
   18213 (outs DoubleRegs:$Rdd32),
   18214 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18215 "$Rdd32 = asrrnd($Rss32,#$Ii)",
   18216 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> {
   18217 let isPseudo = 1;
   18218 }
   18219 def S2_asr_i_r : HInst<
   18220 (outs IntRegs:$Rd32),
   18221 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   18222 "$Rd32 = asr($Rs32,#$Ii)",
   18223 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   18224 let Inst{7-5} = 0b000;
   18225 let Inst{13-13} = 0b0;
   18226 let Inst{31-21} = 0b10001100000;
   18227 let hasNewValue = 1;
   18228 let opNewValue = 0;
   18229 }
   18230 def S2_asr_i_r_acc : HInst<
   18231 (outs IntRegs:$Rx32),
   18232 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   18233 "$Rx32 += asr($Rs32,#$Ii)",
   18234 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   18235 let Inst{7-5} = 0b100;
   18236 let Inst{13-13} = 0b0;
   18237 let Inst{31-21} = 0b10001110000;
   18238 let hasNewValue = 1;
   18239 let opNewValue = 0;
   18240 let prefersSlot3 = 1;
   18241 let Constraints = "$Rx32 = $Rx32in";
   18242 }
   18243 def S2_asr_i_r_and : HInst<
   18244 (outs IntRegs:$Rx32),
   18245 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   18246 "$Rx32 &= asr($Rs32,#$Ii)",
   18247 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   18248 let Inst{7-5} = 0b000;
   18249 let Inst{13-13} = 0b0;
   18250 let Inst{31-21} = 0b10001110010;
   18251 let hasNewValue = 1;
   18252 let opNewValue = 0;
   18253 let prefersSlot3 = 1;
   18254 let Constraints = "$Rx32 = $Rx32in";
   18255 }
   18256 def S2_asr_i_r_nac : HInst<
   18257 (outs IntRegs:$Rx32),
   18258 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   18259 "$Rx32 -= asr($Rs32,#$Ii)",
   18260 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   18261 let Inst{7-5} = 0b000;
   18262 let Inst{13-13} = 0b0;
   18263 let Inst{31-21} = 0b10001110000;
   18264 let hasNewValue = 1;
   18265 let opNewValue = 0;
   18266 let prefersSlot3 = 1;
   18267 let Constraints = "$Rx32 = $Rx32in";
   18268 }
   18269 def S2_asr_i_r_or : HInst<
   18270 (outs IntRegs:$Rx32),
   18271 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   18272 "$Rx32 |= asr($Rs32,#$Ii)",
   18273 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   18274 let Inst{7-5} = 0b100;
   18275 let Inst{13-13} = 0b0;
   18276 let Inst{31-21} = 0b10001110010;
   18277 let hasNewValue = 1;
   18278 let opNewValue = 0;
   18279 let prefersSlot3 = 1;
   18280 let Constraints = "$Rx32 = $Rx32in";
   18281 }
   18282 def S2_asr_i_r_rnd : HInst<
   18283 (outs IntRegs:$Rd32),
   18284 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   18285 "$Rd32 = asr($Rs32,#$Ii):rnd",
   18286 tc_2b6f77c6, TypeS_2op>, Enc_a05677 {
   18287 let Inst{7-5} = 0b000;
   18288 let Inst{13-13} = 0b0;
   18289 let Inst{31-21} = 0b10001100010;
   18290 let hasNewValue = 1;
   18291 let opNewValue = 0;
   18292 let prefersSlot3 = 1;
   18293 }
   18294 def S2_asr_i_r_rnd_goodsyntax : HInst<
   18295 (outs IntRegs:$Rd32),
   18296 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   18297 "$Rd32 = asrrnd($Rs32,#$Ii)",
   18298 tc_2b6f77c6, TypeS_2op> {
   18299 let hasNewValue = 1;
   18300 let opNewValue = 0;
   18301 let isPseudo = 1;
   18302 }
   18303 def S2_asr_i_svw_trun : HInst<
   18304 (outs IntRegs:$Rd32),
   18305 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
   18306 "$Rd32 = vasrw($Rss32,#$Ii)",
   18307 tc_1b9c9ee5, TypeS_2op>, Enc_8dec2e {
   18308 let Inst{7-5} = 0b010;
   18309 let Inst{13-13} = 0b0;
   18310 let Inst{31-21} = 0b10001000110;
   18311 let hasNewValue = 1;
   18312 let opNewValue = 0;
   18313 let prefersSlot3 = 1;
   18314 }
   18315 def S2_asr_i_vh : HInst<
   18316 (outs DoubleRegs:$Rdd32),
   18317 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   18318 "$Rdd32 = vasrh($Rss32,#$Ii)",
   18319 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
   18320 let Inst{7-5} = 0b000;
   18321 let Inst{13-12} = 0b00;
   18322 let Inst{31-21} = 0b10000000100;
   18323 }
   18324 def S2_asr_i_vw : HInst<
   18325 (outs DoubleRegs:$Rdd32),
   18326 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
   18327 "$Rdd32 = vasrw($Rss32,#$Ii)",
   18328 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
   18329 let Inst{7-5} = 0b000;
   18330 let Inst{13-13} = 0b0;
   18331 let Inst{31-21} = 0b10000000010;
   18332 }
   18333 def S2_asr_r_p : HInst<
   18334 (outs DoubleRegs:$Rdd32),
   18335 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18336 "$Rdd32 = asr($Rss32,$Rt32)",
   18337 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18338 let Inst{7-5} = 0b000;
   18339 let Inst{13-13} = 0b0;
   18340 let Inst{31-21} = 0b11000011100;
   18341 }
   18342 def S2_asr_r_p_acc : HInst<
   18343 (outs DoubleRegs:$Rxx32),
   18344 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18345 "$Rxx32 += asr($Rss32,$Rt32)",
   18346 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18347 let Inst{7-5} = 0b000;
   18348 let Inst{13-13} = 0b0;
   18349 let Inst{31-21} = 0b11001011110;
   18350 let prefersSlot3 = 1;
   18351 let Constraints = "$Rxx32 = $Rxx32in";
   18352 }
   18353 def S2_asr_r_p_and : HInst<
   18354 (outs DoubleRegs:$Rxx32),
   18355 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18356 "$Rxx32 &= asr($Rss32,$Rt32)",
   18357 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18358 let Inst{7-5} = 0b000;
   18359 let Inst{13-13} = 0b0;
   18360 let Inst{31-21} = 0b11001011010;
   18361 let prefersSlot3 = 1;
   18362 let Constraints = "$Rxx32 = $Rxx32in";
   18363 }
   18364 def S2_asr_r_p_nac : HInst<
   18365 (outs DoubleRegs:$Rxx32),
   18366 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18367 "$Rxx32 -= asr($Rss32,$Rt32)",
   18368 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18369 let Inst{7-5} = 0b000;
   18370 let Inst{13-13} = 0b0;
   18371 let Inst{31-21} = 0b11001011100;
   18372 let prefersSlot3 = 1;
   18373 let Constraints = "$Rxx32 = $Rxx32in";
   18374 }
   18375 def S2_asr_r_p_or : HInst<
   18376 (outs DoubleRegs:$Rxx32),
   18377 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18378 "$Rxx32 |= asr($Rss32,$Rt32)",
   18379 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18380 let Inst{7-5} = 0b000;
   18381 let Inst{13-13} = 0b0;
   18382 let Inst{31-21} = 0b11001011000;
   18383 let prefersSlot3 = 1;
   18384 let Constraints = "$Rxx32 = $Rxx32in";
   18385 }
   18386 def S2_asr_r_p_xor : HInst<
   18387 (outs DoubleRegs:$Rxx32),
   18388 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18389 "$Rxx32 ^= asr($Rss32,$Rt32)",
   18390 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18391 let Inst{7-5} = 0b000;
   18392 let Inst{13-13} = 0b0;
   18393 let Inst{31-21} = 0b11001011011;
   18394 let prefersSlot3 = 1;
   18395 let Constraints = "$Rxx32 = $Rxx32in";
   18396 }
   18397 def S2_asr_r_r : HInst<
   18398 (outs IntRegs:$Rd32),
   18399 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18400 "$Rd32 = asr($Rs32,$Rt32)",
   18401 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   18402 let Inst{7-5} = 0b000;
   18403 let Inst{13-13} = 0b0;
   18404 let Inst{31-21} = 0b11000110010;
   18405 let hasNewValue = 1;
   18406 let opNewValue = 0;
   18407 }
   18408 def S2_asr_r_r_acc : HInst<
   18409 (outs IntRegs:$Rx32),
   18410 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18411 "$Rx32 += asr($Rs32,$Rt32)",
   18412 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18413 let Inst{7-5} = 0b000;
   18414 let Inst{13-13} = 0b0;
   18415 let Inst{31-21} = 0b11001100110;
   18416 let hasNewValue = 1;
   18417 let opNewValue = 0;
   18418 let prefersSlot3 = 1;
   18419 let Constraints = "$Rx32 = $Rx32in";
   18420 }
   18421 def S2_asr_r_r_and : HInst<
   18422 (outs IntRegs:$Rx32),
   18423 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18424 "$Rx32 &= asr($Rs32,$Rt32)",
   18425 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18426 let Inst{7-5} = 0b000;
   18427 let Inst{13-13} = 0b0;
   18428 let Inst{31-21} = 0b11001100010;
   18429 let hasNewValue = 1;
   18430 let opNewValue = 0;
   18431 let prefersSlot3 = 1;
   18432 let Constraints = "$Rx32 = $Rx32in";
   18433 }
   18434 def S2_asr_r_r_nac : HInst<
   18435 (outs IntRegs:$Rx32),
   18436 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18437 "$Rx32 -= asr($Rs32,$Rt32)",
   18438 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18439 let Inst{7-5} = 0b000;
   18440 let Inst{13-13} = 0b0;
   18441 let Inst{31-21} = 0b11001100100;
   18442 let hasNewValue = 1;
   18443 let opNewValue = 0;
   18444 let prefersSlot3 = 1;
   18445 let Constraints = "$Rx32 = $Rx32in";
   18446 }
   18447 def S2_asr_r_r_or : HInst<
   18448 (outs IntRegs:$Rx32),
   18449 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18450 "$Rx32 |= asr($Rs32,$Rt32)",
   18451 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18452 let Inst{7-5} = 0b000;
   18453 let Inst{13-13} = 0b0;
   18454 let Inst{31-21} = 0b11001100000;
   18455 let hasNewValue = 1;
   18456 let opNewValue = 0;
   18457 let prefersSlot3 = 1;
   18458 let Constraints = "$Rx32 = $Rx32in";
   18459 }
   18460 def S2_asr_r_r_sat : HInst<
   18461 (outs IntRegs:$Rd32),
   18462 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18463 "$Rd32 = asr($Rs32,$Rt32):sat",
   18464 tc_b44c6e2a, TypeS_3op>, Enc_5ab2be {
   18465 let Inst{7-5} = 0b000;
   18466 let Inst{13-13} = 0b0;
   18467 let Inst{31-21} = 0b11000110000;
   18468 let hasNewValue = 1;
   18469 let opNewValue = 0;
   18470 let prefersSlot3 = 1;
   18471 let Defs = [USR_OVF];
   18472 }
   18473 def S2_asr_r_svw_trun : HInst<
   18474 (outs IntRegs:$Rd32),
   18475 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18476 "$Rd32 = vasrw($Rss32,$Rt32)",
   18477 tc_1b9c9ee5, TypeS_3op>, Enc_3d5b28 {
   18478 let Inst{7-5} = 0b010;
   18479 let Inst{13-13} = 0b0;
   18480 let Inst{31-21} = 0b11000101000;
   18481 let hasNewValue = 1;
   18482 let opNewValue = 0;
   18483 let prefersSlot3 = 1;
   18484 }
   18485 def S2_asr_r_vh : HInst<
   18486 (outs DoubleRegs:$Rdd32),
   18487 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18488 "$Rdd32 = vasrh($Rss32,$Rt32)",
   18489 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18490 let Inst{7-5} = 0b000;
   18491 let Inst{13-13} = 0b0;
   18492 let Inst{31-21} = 0b11000011010;
   18493 }
   18494 def S2_asr_r_vw : HInst<
   18495 (outs DoubleRegs:$Rdd32),
   18496 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18497 "$Rdd32 = vasrw($Rss32,$Rt32)",
   18498 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18499 let Inst{7-5} = 0b000;
   18500 let Inst{13-13} = 0b0;
   18501 let Inst{31-21} = 0b11000011000;
   18502 }
   18503 def S2_brev : HInst<
   18504 (outs IntRegs:$Rd32),
   18505 (ins IntRegs:$Rs32),
   18506 "$Rd32 = brev($Rs32)",
   18507 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18508 let Inst{13-5} = 0b000000110;
   18509 let Inst{31-21} = 0b10001100010;
   18510 let hasNewValue = 1;
   18511 let opNewValue = 0;
   18512 let prefersSlot3 = 1;
   18513 }
   18514 def S2_brevp : HInst<
   18515 (outs DoubleRegs:$Rdd32),
   18516 (ins DoubleRegs:$Rss32),
   18517 "$Rdd32 = brev($Rss32)",
   18518 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
   18519 let Inst{13-5} = 0b000000110;
   18520 let Inst{31-21} = 0b10000000110;
   18521 let prefersSlot3 = 1;
   18522 }
   18523 def S2_cabacdecbin : HInst<
   18524 (outs DoubleRegs:$Rdd32),
   18525 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   18526 "$Rdd32 = decbin($Rss32,$Rtt32)",
   18527 tc_c6ebf8dd, TypeS_3op>, Enc_a56825 {
   18528 let Inst{7-5} = 0b110;
   18529 let Inst{13-13} = 0b0;
   18530 let Inst{31-21} = 0b11000001110;
   18531 let isPredicateLate = 1;
   18532 let prefersSlot3 = 1;
   18533 let Defs = [P0];
   18534 }
   18535 def S2_cl0 : HInst<
   18536 (outs IntRegs:$Rd32),
   18537 (ins IntRegs:$Rs32),
   18538 "$Rd32 = cl0($Rs32)",
   18539 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18540 let Inst{13-5} = 0b000000101;
   18541 let Inst{31-21} = 0b10001100000;
   18542 let hasNewValue = 1;
   18543 let opNewValue = 0;
   18544 let prefersSlot3 = 1;
   18545 }
   18546 def S2_cl0p : HInst<
   18547 (outs IntRegs:$Rd32),
   18548 (ins DoubleRegs:$Rss32),
   18549 "$Rd32 = cl0($Rss32)",
   18550 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   18551 let Inst{13-5} = 0b000000010;
   18552 let Inst{31-21} = 0b10001000010;
   18553 let hasNewValue = 1;
   18554 let opNewValue = 0;
   18555 let prefersSlot3 = 1;
   18556 }
   18557 def S2_cl1 : HInst<
   18558 (outs IntRegs:$Rd32),
   18559 (ins IntRegs:$Rs32),
   18560 "$Rd32 = cl1($Rs32)",
   18561 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18562 let Inst{13-5} = 0b000000110;
   18563 let Inst{31-21} = 0b10001100000;
   18564 let hasNewValue = 1;
   18565 let opNewValue = 0;
   18566 let prefersSlot3 = 1;
   18567 }
   18568 def S2_cl1p : HInst<
   18569 (outs IntRegs:$Rd32),
   18570 (ins DoubleRegs:$Rss32),
   18571 "$Rd32 = cl1($Rss32)",
   18572 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   18573 let Inst{13-5} = 0b000000100;
   18574 let Inst{31-21} = 0b10001000010;
   18575 let hasNewValue = 1;
   18576 let opNewValue = 0;
   18577 let prefersSlot3 = 1;
   18578 }
   18579 def S2_clb : HInst<
   18580 (outs IntRegs:$Rd32),
   18581 (ins IntRegs:$Rs32),
   18582 "$Rd32 = clb($Rs32)",
   18583 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18584 let Inst{13-5} = 0b000000100;
   18585 let Inst{31-21} = 0b10001100000;
   18586 let hasNewValue = 1;
   18587 let opNewValue = 0;
   18588 let prefersSlot3 = 1;
   18589 }
   18590 def S2_clbnorm : HInst<
   18591 (outs IntRegs:$Rd32),
   18592 (ins IntRegs:$Rs32),
   18593 "$Rd32 = normamt($Rs32)",
   18594 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18595 let Inst{13-5} = 0b000000111;
   18596 let Inst{31-21} = 0b10001100000;
   18597 let hasNewValue = 1;
   18598 let opNewValue = 0;
   18599 let prefersSlot3 = 1;
   18600 }
   18601 def S2_clbp : HInst<
   18602 (outs IntRegs:$Rd32),
   18603 (ins DoubleRegs:$Rss32),
   18604 "$Rd32 = clb($Rss32)",
   18605 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   18606 let Inst{13-5} = 0b000000000;
   18607 let Inst{31-21} = 0b10001000010;
   18608 let hasNewValue = 1;
   18609 let opNewValue = 0;
   18610 let prefersSlot3 = 1;
   18611 }
   18612 def S2_clrbit_i : HInst<
   18613 (outs IntRegs:$Rd32),
   18614 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   18615 "$Rd32 = clrbit($Rs32,#$Ii)",
   18616 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   18617 let Inst{7-5} = 0b001;
   18618 let Inst{13-13} = 0b0;
   18619 let Inst{31-21} = 0b10001100110;
   18620 let hasNewValue = 1;
   18621 let opNewValue = 0;
   18622 }
   18623 def S2_clrbit_r : HInst<
   18624 (outs IntRegs:$Rd32),
   18625 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18626 "$Rd32 = clrbit($Rs32,$Rt32)",
   18627 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   18628 let Inst{7-5} = 0b010;
   18629 let Inst{13-13} = 0b0;
   18630 let Inst{31-21} = 0b11000110100;
   18631 let hasNewValue = 1;
   18632 let opNewValue = 0;
   18633 }
   18634 def S2_ct0 : HInst<
   18635 (outs IntRegs:$Rd32),
   18636 (ins IntRegs:$Rs32),
   18637 "$Rd32 = ct0($Rs32)",
   18638 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18639 let Inst{13-5} = 0b000000100;
   18640 let Inst{31-21} = 0b10001100010;
   18641 let hasNewValue = 1;
   18642 let opNewValue = 0;
   18643 let prefersSlot3 = 1;
   18644 }
   18645 def S2_ct0p : HInst<
   18646 (outs IntRegs:$Rd32),
   18647 (ins DoubleRegs:$Rss32),
   18648 "$Rd32 = ct0($Rss32)",
   18649 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   18650 let Inst{13-5} = 0b000000010;
   18651 let Inst{31-21} = 0b10001000111;
   18652 let hasNewValue = 1;
   18653 let opNewValue = 0;
   18654 let prefersSlot3 = 1;
   18655 }
   18656 def S2_ct1 : HInst<
   18657 (outs IntRegs:$Rd32),
   18658 (ins IntRegs:$Rs32),
   18659 "$Rd32 = ct1($Rs32)",
   18660 tc_d088982c, TypeS_2op>, Enc_5e2823 {
   18661 let Inst{13-5} = 0b000000101;
   18662 let Inst{31-21} = 0b10001100010;
   18663 let hasNewValue = 1;
   18664 let opNewValue = 0;
   18665 let prefersSlot3 = 1;
   18666 }
   18667 def S2_ct1p : HInst<
   18668 (outs IntRegs:$Rd32),
   18669 (ins DoubleRegs:$Rss32),
   18670 "$Rd32 = ct1($Rss32)",
   18671 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   18672 let Inst{13-5} = 0b000000100;
   18673 let Inst{31-21} = 0b10001000111;
   18674 let hasNewValue = 1;
   18675 let opNewValue = 0;
   18676 let prefersSlot3 = 1;
   18677 }
   18678 def S2_deinterleave : HInst<
   18679 (outs DoubleRegs:$Rdd32),
   18680 (ins DoubleRegs:$Rss32),
   18681 "$Rdd32 = deinterleave($Rss32)",
   18682 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
   18683 let Inst{13-5} = 0b000000100;
   18684 let Inst{31-21} = 0b10000000110;
   18685 let prefersSlot3 = 1;
   18686 }
   18687 def S2_extractu : HInst<
   18688 (outs IntRegs:$Rd32),
   18689 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
   18690 "$Rd32 = extractu($Rs32,#$Ii,#$II)",
   18691 tc_c74f796f, TypeS_2op>, Enc_b388cf {
   18692 let Inst{13-13} = 0b0;
   18693 let Inst{31-23} = 0b100011010;
   18694 let hasNewValue = 1;
   18695 let opNewValue = 0;
   18696 let prefersSlot3 = 1;
   18697 }
   18698 def S2_extractu_rp : HInst<
   18699 (outs IntRegs:$Rd32),
   18700 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   18701 "$Rd32 = extractu($Rs32,$Rtt32)",
   18702 tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
   18703 let Inst{7-5} = 0b000;
   18704 let Inst{13-13} = 0b0;
   18705 let Inst{31-21} = 0b11001001000;
   18706 let hasNewValue = 1;
   18707 let opNewValue = 0;
   18708 let prefersSlot3 = 1;
   18709 }
   18710 def S2_extractup : HInst<
   18711 (outs DoubleRegs:$Rdd32),
   18712 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
   18713 "$Rdd32 = extractu($Rss32,#$Ii,#$II)",
   18714 tc_c74f796f, TypeS_2op>, Enc_b84c4c {
   18715 let Inst{31-24} = 0b10000001;
   18716 let prefersSlot3 = 1;
   18717 }
   18718 def S2_extractup_rp : HInst<
   18719 (outs DoubleRegs:$Rdd32),
   18720 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   18721 "$Rdd32 = extractu($Rss32,$Rtt32)",
   18722 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
   18723 let Inst{7-5} = 0b000;
   18724 let Inst{13-13} = 0b0;
   18725 let Inst{31-21} = 0b11000001000;
   18726 let prefersSlot3 = 1;
   18727 }
   18728 def S2_insert : HInst<
   18729 (outs IntRegs:$Rx32),
   18730 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
   18731 "$Rx32 = insert($Rs32,#$Ii,#$II)",
   18732 tc_87735c3b, TypeS_2op>, Enc_a1e29d {
   18733 let Inst{13-13} = 0b0;
   18734 let Inst{31-23} = 0b100011110;
   18735 let hasNewValue = 1;
   18736 let opNewValue = 0;
   18737 let prefersSlot3 = 1;
   18738 let Constraints = "$Rx32 = $Rx32in";
   18739 }
   18740 def S2_insert_rp : HInst<
   18741 (outs IntRegs:$Rx32),
   18742 (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
   18743 "$Rx32 = insert($Rs32,$Rtt32)",
   18744 tc_84df2cd3, TypeS_3op>, Enc_179b35 {
   18745 let Inst{7-5} = 0b000;
   18746 let Inst{13-13} = 0b0;
   18747 let Inst{31-21} = 0b11001000000;
   18748 let hasNewValue = 1;
   18749 let opNewValue = 0;
   18750 let prefersSlot3 = 1;
   18751 let Constraints = "$Rx32 = $Rx32in";
   18752 }
   18753 def S2_insertp : HInst<
   18754 (outs DoubleRegs:$Rxx32),
   18755 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
   18756 "$Rxx32 = insert($Rss32,#$Ii,#$II)",
   18757 tc_87735c3b, TypeS_2op>, Enc_143a3c {
   18758 let Inst{31-24} = 0b10000011;
   18759 let prefersSlot3 = 1;
   18760 let Constraints = "$Rxx32 = $Rxx32in";
   18761 }
   18762 def S2_insertp_rp : HInst<
   18763 (outs DoubleRegs:$Rxx32),
   18764 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   18765 "$Rxx32 = insert($Rss32,$Rtt32)",
   18766 tc_84df2cd3, TypeS_3op>, Enc_88c16c {
   18767 let Inst{7-5} = 0b000;
   18768 let Inst{13-13} = 0b0;
   18769 let Inst{31-21} = 0b11001010000;
   18770 let prefersSlot3 = 1;
   18771 let Constraints = "$Rxx32 = $Rxx32in";
   18772 }
   18773 def S2_interleave : HInst<
   18774 (outs DoubleRegs:$Rdd32),
   18775 (ins DoubleRegs:$Rss32),
   18776 "$Rdd32 = interleave($Rss32)",
   18777 tc_d088982c, TypeS_2op>, Enc_b9c5fb {
   18778 let Inst{13-5} = 0b000000101;
   18779 let Inst{31-21} = 0b10000000110;
   18780 let prefersSlot3 = 1;
   18781 }
   18782 def S2_lfsp : HInst<
   18783 (outs DoubleRegs:$Rdd32),
   18784 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   18785 "$Rdd32 = lfs($Rss32,$Rtt32)",
   18786 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
   18787 let Inst{7-5} = 0b110;
   18788 let Inst{13-13} = 0b0;
   18789 let Inst{31-21} = 0b11000001100;
   18790 let prefersSlot3 = 1;
   18791 }
   18792 def S2_lsl_r_p : HInst<
   18793 (outs DoubleRegs:$Rdd32),
   18794 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18795 "$Rdd32 = lsl($Rss32,$Rt32)",
   18796 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18797 let Inst{7-5} = 0b110;
   18798 let Inst{13-13} = 0b0;
   18799 let Inst{31-21} = 0b11000011100;
   18800 }
   18801 def S2_lsl_r_p_acc : HInst<
   18802 (outs DoubleRegs:$Rxx32),
   18803 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18804 "$Rxx32 += lsl($Rss32,$Rt32)",
   18805 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18806 let Inst{7-5} = 0b110;
   18807 let Inst{13-13} = 0b0;
   18808 let Inst{31-21} = 0b11001011110;
   18809 let prefersSlot3 = 1;
   18810 let Constraints = "$Rxx32 = $Rxx32in";
   18811 }
   18812 def S2_lsl_r_p_and : HInst<
   18813 (outs DoubleRegs:$Rxx32),
   18814 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18815 "$Rxx32 &= lsl($Rss32,$Rt32)",
   18816 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18817 let Inst{7-5} = 0b110;
   18818 let Inst{13-13} = 0b0;
   18819 let Inst{31-21} = 0b11001011010;
   18820 let prefersSlot3 = 1;
   18821 let Constraints = "$Rxx32 = $Rxx32in";
   18822 }
   18823 def S2_lsl_r_p_nac : HInst<
   18824 (outs DoubleRegs:$Rxx32),
   18825 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18826 "$Rxx32 -= lsl($Rss32,$Rt32)",
   18827 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   18828 let Inst{7-5} = 0b110;
   18829 let Inst{13-13} = 0b0;
   18830 let Inst{31-21} = 0b11001011100;
   18831 let prefersSlot3 = 1;
   18832 let Constraints = "$Rxx32 = $Rxx32in";
   18833 }
   18834 def S2_lsl_r_p_or : HInst<
   18835 (outs DoubleRegs:$Rxx32),
   18836 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18837 "$Rxx32 |= lsl($Rss32,$Rt32)",
   18838 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18839 let Inst{7-5} = 0b110;
   18840 let Inst{13-13} = 0b0;
   18841 let Inst{31-21} = 0b11001011000;
   18842 let prefersSlot3 = 1;
   18843 let Constraints = "$Rxx32 = $Rxx32in";
   18844 }
   18845 def S2_lsl_r_p_xor : HInst<
   18846 (outs DoubleRegs:$Rxx32),
   18847 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   18848 "$Rxx32 ^= lsl($Rss32,$Rt32)",
   18849 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   18850 let Inst{7-5} = 0b110;
   18851 let Inst{13-13} = 0b0;
   18852 let Inst{31-21} = 0b11001011011;
   18853 let prefersSlot3 = 1;
   18854 let Constraints = "$Rxx32 = $Rxx32in";
   18855 }
   18856 def S2_lsl_r_r : HInst<
   18857 (outs IntRegs:$Rd32),
   18858 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   18859 "$Rd32 = lsl($Rs32,$Rt32)",
   18860 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   18861 let Inst{7-5} = 0b110;
   18862 let Inst{13-13} = 0b0;
   18863 let Inst{31-21} = 0b11000110010;
   18864 let hasNewValue = 1;
   18865 let opNewValue = 0;
   18866 }
   18867 def S2_lsl_r_r_acc : HInst<
   18868 (outs IntRegs:$Rx32),
   18869 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18870 "$Rx32 += lsl($Rs32,$Rt32)",
   18871 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18872 let Inst{7-5} = 0b110;
   18873 let Inst{13-13} = 0b0;
   18874 let Inst{31-21} = 0b11001100110;
   18875 let hasNewValue = 1;
   18876 let opNewValue = 0;
   18877 let prefersSlot3 = 1;
   18878 let Constraints = "$Rx32 = $Rx32in";
   18879 }
   18880 def S2_lsl_r_r_and : HInst<
   18881 (outs IntRegs:$Rx32),
   18882 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18883 "$Rx32 &= lsl($Rs32,$Rt32)",
   18884 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18885 let Inst{7-5} = 0b110;
   18886 let Inst{13-13} = 0b0;
   18887 let Inst{31-21} = 0b11001100010;
   18888 let hasNewValue = 1;
   18889 let opNewValue = 0;
   18890 let prefersSlot3 = 1;
   18891 let Constraints = "$Rx32 = $Rx32in";
   18892 }
   18893 def S2_lsl_r_r_nac : HInst<
   18894 (outs IntRegs:$Rx32),
   18895 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18896 "$Rx32 -= lsl($Rs32,$Rt32)",
   18897 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   18898 let Inst{7-5} = 0b110;
   18899 let Inst{13-13} = 0b0;
   18900 let Inst{31-21} = 0b11001100100;
   18901 let hasNewValue = 1;
   18902 let opNewValue = 0;
   18903 let prefersSlot3 = 1;
   18904 let Constraints = "$Rx32 = $Rx32in";
   18905 }
   18906 def S2_lsl_r_r_or : HInst<
   18907 (outs IntRegs:$Rx32),
   18908 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   18909 "$Rx32 |= lsl($Rs32,$Rt32)",
   18910 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   18911 let Inst{7-5} = 0b110;
   18912 let Inst{13-13} = 0b0;
   18913 let Inst{31-21} = 0b11001100000;
   18914 let hasNewValue = 1;
   18915 let opNewValue = 0;
   18916 let prefersSlot3 = 1;
   18917 let Constraints = "$Rx32 = $Rx32in";
   18918 }
   18919 def S2_lsl_r_vh : HInst<
   18920 (outs DoubleRegs:$Rdd32),
   18921 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18922 "$Rdd32 = vlslh($Rss32,$Rt32)",
   18923 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18924 let Inst{7-5} = 0b110;
   18925 let Inst{13-13} = 0b0;
   18926 let Inst{31-21} = 0b11000011010;
   18927 }
   18928 def S2_lsl_r_vw : HInst<
   18929 (outs DoubleRegs:$Rdd32),
   18930 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   18931 "$Rdd32 = vlslw($Rss32,$Rt32)",
   18932 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   18933 let Inst{7-5} = 0b110;
   18934 let Inst{13-13} = 0b0;
   18935 let Inst{31-21} = 0b11000011000;
   18936 }
   18937 def S2_lsr_i_p : HInst<
   18938 (outs DoubleRegs:$Rdd32),
   18939 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18940 "$Rdd32 = lsr($Rss32,#$Ii)",
   18941 tc_540fdfbc, TypeS_2op>, Enc_5eac98 {
   18942 let Inst{7-5} = 0b001;
   18943 let Inst{31-21} = 0b10000000000;
   18944 }
   18945 def S2_lsr_i_p_acc : HInst<
   18946 (outs DoubleRegs:$Rxx32),
   18947 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18948 "$Rxx32 += lsr($Rss32,#$Ii)",
   18949 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   18950 let Inst{7-5} = 0b101;
   18951 let Inst{31-21} = 0b10000010000;
   18952 let prefersSlot3 = 1;
   18953 let Constraints = "$Rxx32 = $Rxx32in";
   18954 }
   18955 def S2_lsr_i_p_and : HInst<
   18956 (outs DoubleRegs:$Rxx32),
   18957 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18958 "$Rxx32 &= lsr($Rss32,#$Ii)",
   18959 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   18960 let Inst{7-5} = 0b001;
   18961 let Inst{31-21} = 0b10000010010;
   18962 let prefersSlot3 = 1;
   18963 let Constraints = "$Rxx32 = $Rxx32in";
   18964 }
   18965 def S2_lsr_i_p_nac : HInst<
   18966 (outs DoubleRegs:$Rxx32),
   18967 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18968 "$Rxx32 -= lsr($Rss32,#$Ii)",
   18969 tc_c74f796f, TypeS_2op>, Enc_70fb07 {
   18970 let Inst{7-5} = 0b001;
   18971 let Inst{31-21} = 0b10000010000;
   18972 let prefersSlot3 = 1;
   18973 let Constraints = "$Rxx32 = $Rxx32in";
   18974 }
   18975 def S2_lsr_i_p_or : HInst<
   18976 (outs DoubleRegs:$Rxx32),
   18977 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18978 "$Rxx32 |= lsr($Rss32,#$Ii)",
   18979 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   18980 let Inst{7-5} = 0b101;
   18981 let Inst{31-21} = 0b10000010010;
   18982 let prefersSlot3 = 1;
   18983 let Constraints = "$Rxx32 = $Rxx32in";
   18984 }
   18985 def S2_lsr_i_p_xacc : HInst<
   18986 (outs DoubleRegs:$Rxx32),
   18987 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   18988 "$Rxx32 ^= lsr($Rss32,#$Ii)",
   18989 tc_84df2cd3, TypeS_2op>, Enc_70fb07 {
   18990 let Inst{7-5} = 0b001;
   18991 let Inst{31-21} = 0b10000010100;
   18992 let prefersSlot3 = 1;
   18993 let Constraints = "$Rxx32 = $Rxx32in";
   18994 }
   18995 def S2_lsr_i_r : HInst<
   18996 (outs IntRegs:$Rd32),
   18997 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   18998 "$Rd32 = lsr($Rs32,#$Ii)",
   18999 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   19000 let Inst{7-5} = 0b001;
   19001 let Inst{13-13} = 0b0;
   19002 let Inst{31-21} = 0b10001100000;
   19003 let hasNewValue = 1;
   19004 let opNewValue = 0;
   19005 }
   19006 def S2_lsr_i_r_acc : HInst<
   19007 (outs IntRegs:$Rx32),
   19008 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   19009 "$Rx32 += lsr($Rs32,#$Ii)",
   19010 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   19011 let Inst{7-5} = 0b101;
   19012 let Inst{13-13} = 0b0;
   19013 let Inst{31-21} = 0b10001110000;
   19014 let hasNewValue = 1;
   19015 let opNewValue = 0;
   19016 let prefersSlot3 = 1;
   19017 let Constraints = "$Rx32 = $Rx32in";
   19018 }
   19019 def S2_lsr_i_r_and : HInst<
   19020 (outs IntRegs:$Rx32),
   19021 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   19022 "$Rx32 &= lsr($Rs32,#$Ii)",
   19023 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   19024 let Inst{7-5} = 0b001;
   19025 let Inst{13-13} = 0b0;
   19026 let Inst{31-21} = 0b10001110010;
   19027 let hasNewValue = 1;
   19028 let opNewValue = 0;
   19029 let prefersSlot3 = 1;
   19030 let Constraints = "$Rx32 = $Rx32in";
   19031 }
   19032 def S2_lsr_i_r_nac : HInst<
   19033 (outs IntRegs:$Rx32),
   19034 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   19035 "$Rx32 -= lsr($Rs32,#$Ii)",
   19036 tc_c74f796f, TypeS_2op>, Enc_28a2dc {
   19037 let Inst{7-5} = 0b001;
   19038 let Inst{13-13} = 0b0;
   19039 let Inst{31-21} = 0b10001110000;
   19040 let hasNewValue = 1;
   19041 let opNewValue = 0;
   19042 let prefersSlot3 = 1;
   19043 let Constraints = "$Rx32 = $Rx32in";
   19044 }
   19045 def S2_lsr_i_r_or : HInst<
   19046 (outs IntRegs:$Rx32),
   19047 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   19048 "$Rx32 |= lsr($Rs32,#$Ii)",
   19049 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   19050 let Inst{7-5} = 0b101;
   19051 let Inst{13-13} = 0b0;
   19052 let Inst{31-21} = 0b10001110010;
   19053 let hasNewValue = 1;
   19054 let opNewValue = 0;
   19055 let prefersSlot3 = 1;
   19056 let Constraints = "$Rx32 = $Rx32in";
   19057 }
   19058 def S2_lsr_i_r_xacc : HInst<
   19059 (outs IntRegs:$Rx32),
   19060 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   19061 "$Rx32 ^= lsr($Rs32,#$Ii)",
   19062 tc_84df2cd3, TypeS_2op>, Enc_28a2dc {
   19063 let Inst{7-5} = 0b001;
   19064 let Inst{13-13} = 0b0;
   19065 let Inst{31-21} = 0b10001110100;
   19066 let hasNewValue = 1;
   19067 let opNewValue = 0;
   19068 let prefersSlot3 = 1;
   19069 let Constraints = "$Rx32 = $Rx32in";
   19070 }
   19071 def S2_lsr_i_vh : HInst<
   19072 (outs DoubleRegs:$Rdd32),
   19073 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   19074 "$Rdd32 = vlsrh($Rss32,#$Ii)",
   19075 tc_540fdfbc, TypeS_2op>, Enc_12b6e9 {
   19076 let Inst{7-5} = 0b001;
   19077 let Inst{13-12} = 0b00;
   19078 let Inst{31-21} = 0b10000000100;
   19079 }
   19080 def S2_lsr_i_vw : HInst<
   19081 (outs DoubleRegs:$Rdd32),
   19082 (ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
   19083 "$Rdd32 = vlsrw($Rss32,#$Ii)",
   19084 tc_540fdfbc, TypeS_2op>, Enc_7e5a82 {
   19085 let Inst{7-5} = 0b001;
   19086 let Inst{13-13} = 0b0;
   19087 let Inst{31-21} = 0b10000000010;
   19088 }
   19089 def S2_lsr_r_p : HInst<
   19090 (outs DoubleRegs:$Rdd32),
   19091 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   19092 "$Rdd32 = lsr($Rss32,$Rt32)",
   19093 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   19094 let Inst{7-5} = 0b010;
   19095 let Inst{13-13} = 0b0;
   19096 let Inst{31-21} = 0b11000011100;
   19097 }
   19098 def S2_lsr_r_p_acc : HInst<
   19099 (outs DoubleRegs:$Rxx32),
   19100 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   19101 "$Rxx32 += lsr($Rss32,$Rt32)",
   19102 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   19103 let Inst{7-5} = 0b010;
   19104 let Inst{13-13} = 0b0;
   19105 let Inst{31-21} = 0b11001011110;
   19106 let prefersSlot3 = 1;
   19107 let Constraints = "$Rxx32 = $Rxx32in";
   19108 }
   19109 def S2_lsr_r_p_and : HInst<
   19110 (outs DoubleRegs:$Rxx32),
   19111 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   19112 "$Rxx32 &= lsr($Rss32,$Rt32)",
   19113 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   19114 let Inst{7-5} = 0b010;
   19115 let Inst{13-13} = 0b0;
   19116 let Inst{31-21} = 0b11001011010;
   19117 let prefersSlot3 = 1;
   19118 let Constraints = "$Rxx32 = $Rxx32in";
   19119 }
   19120 def S2_lsr_r_p_nac : HInst<
   19121 (outs DoubleRegs:$Rxx32),
   19122 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   19123 "$Rxx32 -= lsr($Rss32,$Rt32)",
   19124 tc_c74f796f, TypeS_3op>, Enc_1aa186 {
   19125 let Inst{7-5} = 0b010;
   19126 let Inst{13-13} = 0b0;
   19127 let Inst{31-21} = 0b11001011100;
   19128 let prefersSlot3 = 1;
   19129 let Constraints = "$Rxx32 = $Rxx32in";
   19130 }
   19131 def S2_lsr_r_p_or : HInst<
   19132 (outs DoubleRegs:$Rxx32),
   19133 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   19134 "$Rxx32 |= lsr($Rss32,$Rt32)",
   19135 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   19136 let Inst{7-5} = 0b010;
   19137 let Inst{13-13} = 0b0;
   19138 let Inst{31-21} = 0b11001011000;
   19139 let prefersSlot3 = 1;
   19140 let Constraints = "$Rxx32 = $Rxx32in";
   19141 }
   19142 def S2_lsr_r_p_xor : HInst<
   19143 (outs DoubleRegs:$Rxx32),
   19144 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   19145 "$Rxx32 ^= lsr($Rss32,$Rt32)",
   19146 tc_84df2cd3, TypeS_3op>, Enc_1aa186 {
   19147 let Inst{7-5} = 0b010;
   19148 let Inst{13-13} = 0b0;
   19149 let Inst{31-21} = 0b11001011011;
   19150 let prefersSlot3 = 1;
   19151 let Constraints = "$Rxx32 = $Rxx32in";
   19152 }
   19153 def S2_lsr_r_r : HInst<
   19154 (outs IntRegs:$Rd32),
   19155 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   19156 "$Rd32 = lsr($Rs32,$Rt32)",
   19157 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   19158 let Inst{7-5} = 0b010;
   19159 let Inst{13-13} = 0b0;
   19160 let Inst{31-21} = 0b11000110010;
   19161 let hasNewValue = 1;
   19162 let opNewValue = 0;
   19163 }
   19164 def S2_lsr_r_r_acc : HInst<
   19165 (outs IntRegs:$Rx32),
   19166 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   19167 "$Rx32 += lsr($Rs32,$Rt32)",
   19168 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   19169 let Inst{7-5} = 0b010;
   19170 let Inst{13-13} = 0b0;
   19171 let Inst{31-21} = 0b11001100110;
   19172 let hasNewValue = 1;
   19173 let opNewValue = 0;
   19174 let prefersSlot3 = 1;
   19175 let Constraints = "$Rx32 = $Rx32in";
   19176 }
   19177 def S2_lsr_r_r_and : HInst<
   19178 (outs IntRegs:$Rx32),
   19179 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   19180 "$Rx32 &= lsr($Rs32,$Rt32)",
   19181 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   19182 let Inst{7-5} = 0b010;
   19183 let Inst{13-13} = 0b0;
   19184 let Inst{31-21} = 0b11001100010;
   19185 let hasNewValue = 1;
   19186 let opNewValue = 0;
   19187 let prefersSlot3 = 1;
   19188 let Constraints = "$Rx32 = $Rx32in";
   19189 }
   19190 def S2_lsr_r_r_nac : HInst<
   19191 (outs IntRegs:$Rx32),
   19192 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   19193 "$Rx32 -= lsr($Rs32,$Rt32)",
   19194 tc_c74f796f, TypeS_3op>, Enc_2ae154 {
   19195 let Inst{7-5} = 0b010;
   19196 let Inst{13-13} = 0b0;
   19197 let Inst{31-21} = 0b11001100100;
   19198 let hasNewValue = 1;
   19199 let opNewValue = 0;
   19200 let prefersSlot3 = 1;
   19201 let Constraints = "$Rx32 = $Rx32in";
   19202 }
   19203 def S2_lsr_r_r_or : HInst<
   19204 (outs IntRegs:$Rx32),
   19205 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
   19206 "$Rx32 |= lsr($Rs32,$Rt32)",
   19207 tc_84df2cd3, TypeS_3op>, Enc_2ae154 {
   19208 let Inst{7-5} = 0b010;
   19209 let Inst{13-13} = 0b0;
   19210 let Inst{31-21} = 0b11001100000;
   19211 let hasNewValue = 1;
   19212 let opNewValue = 0;
   19213 let prefersSlot3 = 1;
   19214 let Constraints = "$Rx32 = $Rx32in";
   19215 }
   19216 def S2_lsr_r_vh : HInst<
   19217 (outs DoubleRegs:$Rdd32),
   19218 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   19219 "$Rdd32 = vlsrh($Rss32,$Rt32)",
   19220 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   19221 let Inst{7-5} = 0b010;
   19222 let Inst{13-13} = 0b0;
   19223 let Inst{31-21} = 0b11000011010;
   19224 }
   19225 def S2_lsr_r_vw : HInst<
   19226 (outs DoubleRegs:$Rdd32),
   19227 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   19228 "$Rdd32 = vlsrw($Rss32,$Rt32)",
   19229 tc_540fdfbc, TypeS_3op>, Enc_927852 {
   19230 let Inst{7-5} = 0b010;
   19231 let Inst{13-13} = 0b0;
   19232 let Inst{31-21} = 0b11000011000;
   19233 }
   19234 def S2_packhl : HInst<
   19235 (outs DoubleRegs:$Rdd32),
   19236 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   19237 "$Rdd32 = packhl($Rs32,$Rt32)",
   19238 tc_b9488031, TypeALU32_3op>, Enc_be32a5 {
   19239 let Inst{7-5} = 0b000;
   19240 let Inst{13-13} = 0b0;
   19241 let Inst{31-21} = 0b11110101100;
   19242 let InputType = "reg";
   19243 }
   19244 def S2_parityp : HInst<
   19245 (outs IntRegs:$Rd32),
   19246 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   19247 "$Rd32 = parity($Rss32,$Rtt32)",
   19248 tc_2b6f77c6, TypeALU64>, Enc_d2216a {
   19249 let Inst{7-5} = 0b000;
   19250 let Inst{13-13} = 0b0;
   19251 let Inst{31-21} = 0b11010000000;
   19252 let hasNewValue = 1;
   19253 let opNewValue = 0;
   19254 let prefersSlot3 = 1;
   19255 }
   19256 def S2_pstorerbf_io : HInst<
   19257 (outs),
   19258 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   19259 "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
   19260 tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
   19261 let Inst{2-2} = 0b0;
   19262 let Inst{31-21} = 0b01000100000;
   19263 let isPredicated = 1;
   19264 let isPredicatedFalse = 1;
   19265 let addrMode = BaseImmOffset;
   19266 let accessSize = ByteAccess;
   19267 let mayStore = 1;
   19268 let CextOpcode = "S2_storerb";
   19269 let InputType = "imm";
   19270 let BaseOpcode = "S2_storerb_io";
   19271 let isNVStorable = 1;
   19272 let isExtendable = 1;
   19273 let opExtendable = 2;
   19274 let isExtentSigned = 0;
   19275 let opExtentBits = 6;
   19276 let opExtentAlign = 0;
   19277 }
   19278 def S2_pstorerbf_pi : HInst<
   19279 (outs IntRegs:$Rx32),
   19280 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
   19281 "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
   19282 tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
   19283 let Inst{2-2} = 0b1;
   19284 let Inst{7-7} = 0b0;
   19285 let Inst{13-13} = 0b1;
   19286 let Inst{31-21} = 0b10101011000;
   19287 let isPredicated = 1;
   19288 let isPredicatedFalse = 1;
   19289 let addrMode = PostInc;
   19290 let accessSize = ByteAccess;
   19291 let mayStore = 1;
   19292 let BaseOpcode = "S2_storerb_pi";
   19293 let isNVStorable = 1;
   19294 let Constraints = "$Rx32 = $Rx32in";
   19295 }
   19296 def S2_pstorerbf_zomap : HInst<
   19297 (outs),
   19298 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   19299 "if (!$Pv4) memb($Rs32) = $Rt32",
   19300 tc_8b15472a, TypeMAPPING> {
   19301 let isPseudo = 1;
   19302 let isCodeGenOnly = 1;
   19303 }
   19304 def S2_pstorerbfnew_pi : HInst<
   19305 (outs IntRegs:$Rx32),
   19306 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
   19307 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
   19308 tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
   19309 let Inst{2-2} = 0b1;
   19310 let Inst{7-7} = 0b1;
   19311 let Inst{13-13} = 0b1;
   19312 let Inst{31-21} = 0b10101011000;
   19313 let isPredicated = 1;
   19314 let isPredicatedFalse = 1;
   19315 let addrMode = PostInc;
   19316 let accessSize = ByteAccess;
   19317 let isPredicatedNew = 1;
   19318 let mayStore = 1;
   19319 let BaseOpcode = "S2_storerb_pi";
   19320 let isNVStorable = 1;
   19321 let Constraints = "$Rx32 = $Rx32in";
   19322 }
   19323 def S2_pstorerbnewf_io : HInst<
   19324 (outs),
   19325 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
   19326 "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
   19327 tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
   19328 let Inst{2-2} = 0b0;
   19329 let Inst{12-11} = 0b00;
   19330 let Inst{31-21} = 0b01000100101;
   19331 let isPredicated = 1;
   19332 let isPredicatedFalse = 1;
   19333 let addrMode = BaseImmOffset;
   19334 let accessSize = ByteAccess;
   19335 let isNVStore = 1;
   19336 let isNewValue = 1;
   19337 let isRestrictNoSlot1Store = 1;
   19338 let mayStore = 1;
   19339 let CextOpcode = "S2_storerb";
   19340 let InputType = "imm";
   19341 let BaseOpcode = "S2_storerb_io";
   19342 let isExtendable = 1;
   19343 let opExtendable = 2;
   19344 let isExtentSigned = 0;
   19345 let opExtentBits = 6;
   19346 let opExtentAlign = 0;
   19347 let opNewValue = 3;
   19348 }
   19349 def S2_pstorerbnewf_pi : HInst<
   19350 (outs IntRegs:$Rx32),
   19351 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
   19352 "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
   19353 tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
   19354 let Inst{2-2} = 0b1;
   19355 let Inst{7-7} = 0b0;
   19356 let Inst{13-11} = 0b100;
   19357 let Inst{31-21} = 0b10101011101;
   19358 let isPredicated = 1;
   19359 let isPredicatedFalse = 1;
   19360 let addrMode = PostInc;
   19361 let accessSize = ByteAccess;
   19362 let isNVStore = 1;
   19363 let isNewValue = 1;
   19364 let isRestrictNoSlot1Store = 1;
   19365 let mayStore = 1;
   19366 let CextOpcode = "S2_storerb";
   19367 let BaseOpcode = "S2_storerb_pi";
   19368 let opNewValue = 4;
   19369 let Constraints = "$Rx32 = $Rx32in";
   19370 }
   19371 def S2_pstorerbnewf_zomap : HInst<
   19372 (outs),
   19373 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   19374 "if (!$Pv4) memb($Rs32) = $Nt8.new",
   19375 tc_594ab548, TypeMAPPING> {
   19376 let isPseudo = 1;
   19377 let isCodeGenOnly = 1;
   19378 let opNewValue = 2;
   19379 }
   19380 def S2_pstorerbnewfnew_pi : HInst<
   19381 (outs IntRegs:$Rx32),
   19382 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
   19383 "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
   19384 tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
   19385 let Inst{2-2} = 0b1;
   19386 let Inst{7-7} = 0b1;
   19387 let Inst{13-11} = 0b100;
   19388 let Inst{31-21} = 0b10101011101;
   19389 let isPredicated = 1;
   19390 let isPredicatedFalse = 1;
   19391 let addrMode = PostInc;
   19392 let accessSize = ByteAccess;
   19393 let isNVStore = 1;
   19394 let isPredicatedNew = 1;
   19395 let isNewValue = 1;
   19396 let isRestrictNoSlot1Store = 1;
   19397 let mayStore = 1;
   19398 let CextOpcode = "S2_storerb";
   19399 let BaseOpcode = "S2_storerb_pi";
   19400 let opNewValue = 4;
   19401 let Constraints = "$Rx32 = $Rx32in";
   19402 }
   19403 def S2_pstorerbnewt_io : HInst<
   19404 (outs),
   19405 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
   19406 "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
   19407 tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel {
   19408 let Inst{2-2} = 0b0;
   19409 let Inst{12-11} = 0b00;
   19410 let Inst{31-21} = 0b01000000101;
   19411 let isPredicated = 1;
   19412 let addrMode = BaseImmOffset;
   19413 let accessSize = ByteAccess;
   19414 let isNVStore = 1;
   19415 let isNewValue = 1;
   19416 let isRestrictNoSlot1Store = 1;
   19417 let mayStore = 1;
   19418 let CextOpcode = "S2_storerb";
   19419 let InputType = "imm";
   19420 let BaseOpcode = "S2_storerb_io";
   19421 let isExtendable = 1;
   19422 let opExtendable = 2;
   19423 let isExtentSigned = 0;
   19424 let opExtentBits = 6;
   19425 let opExtentAlign = 0;
   19426 let opNewValue = 3;
   19427 }
   19428 def S2_pstorerbnewt_pi : HInst<
   19429 (outs IntRegs:$Rx32),
   19430 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
   19431 "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
   19432 tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel {
   19433 let Inst{2-2} = 0b0;
   19434 let Inst{7-7} = 0b0;
   19435 let Inst{13-11} = 0b100;
   19436 let Inst{31-21} = 0b10101011101;
   19437 let isPredicated = 1;
   19438 let addrMode = PostInc;
   19439 let accessSize = ByteAccess;
   19440 let isNVStore = 1;
   19441 let isNewValue = 1;
   19442 let isRestrictNoSlot1Store = 1;
   19443 let mayStore = 1;
   19444 let CextOpcode = "S2_storerb";
   19445 let BaseOpcode = "S2_storerb_pi";
   19446 let opNewValue = 4;
   19447 let Constraints = "$Rx32 = $Rx32in";
   19448 }
   19449 def S2_pstorerbnewt_zomap : HInst<
   19450 (outs),
   19451 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   19452 "if ($Pv4) memb($Rs32) = $Nt8.new",
   19453 tc_594ab548, TypeMAPPING> {
   19454 let isPseudo = 1;
   19455 let isCodeGenOnly = 1;
   19456 let opNewValue = 2;
   19457 }
   19458 def S2_pstorerbnewtnew_pi : HInst<
   19459 (outs IntRegs:$Rx32),
   19460 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
   19461 "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
   19462 tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel {
   19463 let Inst{2-2} = 0b0;
   19464 let Inst{7-7} = 0b1;
   19465 let Inst{13-11} = 0b100;
   19466 let Inst{31-21} = 0b10101011101;
   19467 let isPredicated = 1;
   19468 let addrMode = PostInc;
   19469 let accessSize = ByteAccess;
   19470 let isNVStore = 1;
   19471 let isPredicatedNew = 1;
   19472 let isNewValue = 1;
   19473 let isRestrictNoSlot1Store = 1;
   19474 let mayStore = 1;
   19475 let CextOpcode = "S2_storerb";
   19476 let BaseOpcode = "S2_storerb_pi";
   19477 let opNewValue = 4;
   19478 let Constraints = "$Rx32 = $Rx32in";
   19479 }
   19480 def S2_pstorerbt_io : HInst<
   19481 (outs),
   19482 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   19483 "if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
   19484 tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
   19485 let Inst{2-2} = 0b0;
   19486 let Inst{31-21} = 0b01000000000;
   19487 let isPredicated = 1;
   19488 let addrMode = BaseImmOffset;
   19489 let accessSize = ByteAccess;
   19490 let mayStore = 1;
   19491 let CextOpcode = "S2_storerb";
   19492 let InputType = "imm";
   19493 let BaseOpcode = "S2_storerb_io";
   19494 let isNVStorable = 1;
   19495 let isExtendable = 1;
   19496 let opExtendable = 2;
   19497 let isExtentSigned = 0;
   19498 let opExtentBits = 6;
   19499 let opExtentAlign = 0;
   19500 }
   19501 def S2_pstorerbt_pi : HInst<
   19502 (outs IntRegs:$Rx32),
   19503 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
   19504 "if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
   19505 tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel {
   19506 let Inst{2-2} = 0b0;
   19507 let Inst{7-7} = 0b0;
   19508 let Inst{13-13} = 0b1;
   19509 let Inst{31-21} = 0b10101011000;
   19510 let isPredicated = 1;
   19511 let addrMode = PostInc;
   19512 let accessSize = ByteAccess;
   19513 let mayStore = 1;
   19514 let BaseOpcode = "S2_storerb_pi";
   19515 let isNVStorable = 1;
   19516 let Constraints = "$Rx32 = $Rx32in";
   19517 }
   19518 def S2_pstorerbt_zomap : HInst<
   19519 (outs),
   19520 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   19521 "if ($Pv4) memb($Rs32) = $Rt32",
   19522 tc_8b15472a, TypeMAPPING> {
   19523 let isPseudo = 1;
   19524 let isCodeGenOnly = 1;
   19525 }
   19526 def S2_pstorerbtnew_pi : HInst<
   19527 (outs IntRegs:$Rx32),
   19528 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
   19529 "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
   19530 tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel {
   19531 let Inst{2-2} = 0b0;
   19532 let Inst{7-7} = 0b1;
   19533 let Inst{13-13} = 0b1;
   19534 let Inst{31-21} = 0b10101011000;
   19535 let isPredicated = 1;
   19536 let addrMode = PostInc;
   19537 let accessSize = ByteAccess;
   19538 let isPredicatedNew = 1;
   19539 let mayStore = 1;
   19540 let BaseOpcode = "S2_storerb_pi";
   19541 let isNVStorable = 1;
   19542 let Constraints = "$Rx32 = $Rx32in";
   19543 }
   19544 def S2_pstorerdf_io : HInst<
   19545 (outs),
   19546 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   19547 "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
   19548 tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
   19549 let Inst{2-2} = 0b0;
   19550 let Inst{31-21} = 0b01000100110;
   19551 let isPredicated = 1;
   19552 let isPredicatedFalse = 1;
   19553 let addrMode = BaseImmOffset;
   19554 let accessSize = DoubleWordAccess;
   19555 let mayStore = 1;
   19556 let CextOpcode = "S2_storerd";
   19557 let InputType = "imm";
   19558 let BaseOpcode = "S2_storerd_io";
   19559 let isExtendable = 1;
   19560 let opExtendable = 2;
   19561 let isExtentSigned = 0;
   19562 let opExtentBits = 9;
   19563 let opExtentAlign = 3;
   19564 }
   19565 def S2_pstorerdf_pi : HInst<
   19566 (outs IntRegs:$Rx32),
   19567 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
   19568 "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
   19569 tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
   19570 let Inst{2-2} = 0b1;
   19571 let Inst{7-7} = 0b0;
   19572 let Inst{13-13} = 0b1;
   19573 let Inst{31-21} = 0b10101011110;
   19574 let isPredicated = 1;
   19575 let isPredicatedFalse = 1;
   19576 let addrMode = PostInc;
   19577 let accessSize = DoubleWordAccess;
   19578 let mayStore = 1;
   19579 let CextOpcode = "S2_storerd";
   19580 let BaseOpcode = "S2_storerd_pi";
   19581 let Constraints = "$Rx32 = $Rx32in";
   19582 }
   19583 def S2_pstorerdf_zomap : HInst<
   19584 (outs),
   19585 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
   19586 "if (!$Pv4) memd($Rs32) = $Rtt32",
   19587 tc_8b15472a, TypeMAPPING> {
   19588 let isPseudo = 1;
   19589 let isCodeGenOnly = 1;
   19590 }
   19591 def S2_pstorerdfnew_pi : HInst<
   19592 (outs IntRegs:$Rx32),
   19593 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
   19594 "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
   19595 tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
   19596 let Inst{2-2} = 0b1;
   19597 let Inst{7-7} = 0b1;
   19598 let Inst{13-13} = 0b1;
   19599 let Inst{31-21} = 0b10101011110;
   19600 let isPredicated = 1;
   19601 let isPredicatedFalse = 1;
   19602 let addrMode = PostInc;
   19603 let accessSize = DoubleWordAccess;
   19604 let isPredicatedNew = 1;
   19605 let mayStore = 1;
   19606 let CextOpcode = "S2_storerd";
   19607 let BaseOpcode = "S2_storerd_pi";
   19608 let Constraints = "$Rx32 = $Rx32in";
   19609 }
   19610 def S2_pstorerdt_io : HInst<
   19611 (outs),
   19612 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   19613 "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
   19614 tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
   19615 let Inst{2-2} = 0b0;
   19616 let Inst{31-21} = 0b01000000110;
   19617 let isPredicated = 1;
   19618 let addrMode = BaseImmOffset;
   19619 let accessSize = DoubleWordAccess;
   19620 let mayStore = 1;
   19621 let CextOpcode = "S2_storerd";
   19622 let InputType = "imm";
   19623 let BaseOpcode = "S2_storerd_io";
   19624 let isExtendable = 1;
   19625 let opExtendable = 2;
   19626 let isExtentSigned = 0;
   19627 let opExtentBits = 9;
   19628 let opExtentAlign = 3;
   19629 }
   19630 def S2_pstorerdt_pi : HInst<
   19631 (outs IntRegs:$Rx32),
   19632 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
   19633 "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
   19634 tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel {
   19635 let Inst{2-2} = 0b0;
   19636 let Inst{7-7} = 0b0;
   19637 let Inst{13-13} = 0b1;
   19638 let Inst{31-21} = 0b10101011110;
   19639 let isPredicated = 1;
   19640 let addrMode = PostInc;
   19641 let accessSize = DoubleWordAccess;
   19642 let mayStore = 1;
   19643 let CextOpcode = "S2_storerd";
   19644 let BaseOpcode = "S2_storerd_pi";
   19645 let Constraints = "$Rx32 = $Rx32in";
   19646 }
   19647 def S2_pstorerdt_zomap : HInst<
   19648 (outs),
   19649 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
   19650 "if ($Pv4) memd($Rs32) = $Rtt32",
   19651 tc_8b15472a, TypeMAPPING> {
   19652 let isPseudo = 1;
   19653 let isCodeGenOnly = 1;
   19654 }
   19655 def S2_pstorerdtnew_pi : HInst<
   19656 (outs IntRegs:$Rx32),
   19657 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
   19658 "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
   19659 tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel {
   19660 let Inst{2-2} = 0b0;
   19661 let Inst{7-7} = 0b1;
   19662 let Inst{13-13} = 0b1;
   19663 let Inst{31-21} = 0b10101011110;
   19664 let isPredicated = 1;
   19665 let addrMode = PostInc;
   19666 let accessSize = DoubleWordAccess;
   19667 let isPredicatedNew = 1;
   19668 let mayStore = 1;
   19669 let CextOpcode = "S2_storerd";
   19670 let BaseOpcode = "S2_storerd_pi";
   19671 let Constraints = "$Rx32 = $Rx32in";
   19672 }
   19673 def S2_pstorerff_io : HInst<
   19674 (outs),
   19675 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   19676 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
   19677 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   19678 let Inst{2-2} = 0b0;
   19679 let Inst{31-21} = 0b01000100011;
   19680 let isPredicated = 1;
   19681 let isPredicatedFalse = 1;
   19682 let addrMode = BaseImmOffset;
   19683 let accessSize = HalfWordAccess;
   19684 let mayStore = 1;
   19685 let CextOpcode = "S2_storerf";
   19686 let InputType = "imm";
   19687 let BaseOpcode = "S2_storerf_io";
   19688 let isExtendable = 1;
   19689 let opExtendable = 2;
   19690 let isExtentSigned = 0;
   19691 let opExtentBits = 7;
   19692 let opExtentAlign = 1;
   19693 }
   19694 def S2_pstorerff_pi : HInst<
   19695 (outs IntRegs:$Rx32),
   19696 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19697 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
   19698 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
   19699 let Inst{2-2} = 0b1;
   19700 let Inst{7-7} = 0b0;
   19701 let Inst{13-13} = 0b1;
   19702 let Inst{31-21} = 0b10101011011;
   19703 let isPredicated = 1;
   19704 let isPredicatedFalse = 1;
   19705 let addrMode = PostInc;
   19706 let accessSize = HalfWordAccess;
   19707 let mayStore = 1;
   19708 let CextOpcode = "S2_storerf";
   19709 let BaseOpcode = "S2_storerf_pi";
   19710 let Constraints = "$Rx32 = $Rx32in";
   19711 }
   19712 def S2_pstorerff_zomap : HInst<
   19713 (outs),
   19714 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   19715 "if (!$Pv4) memh($Rs32) = $Rt32.h",
   19716 tc_8b15472a, TypeMAPPING> {
   19717 let isPseudo = 1;
   19718 let isCodeGenOnly = 1;
   19719 }
   19720 def S2_pstorerffnew_pi : HInst<
   19721 (outs IntRegs:$Rx32),
   19722 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19723 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
   19724 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
   19725 let Inst{2-2} = 0b1;
   19726 let Inst{7-7} = 0b1;
   19727 let Inst{13-13} = 0b1;
   19728 let Inst{31-21} = 0b10101011011;
   19729 let isPredicated = 1;
   19730 let isPredicatedFalse = 1;
   19731 let addrMode = PostInc;
   19732 let accessSize = HalfWordAccess;
   19733 let isPredicatedNew = 1;
   19734 let mayStore = 1;
   19735 let CextOpcode = "S2_storerf";
   19736 let BaseOpcode = "S2_storerf_pi";
   19737 let Constraints = "$Rx32 = $Rx32in";
   19738 }
   19739 def S2_pstorerft_io : HInst<
   19740 (outs),
   19741 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   19742 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
   19743 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   19744 let Inst{2-2} = 0b0;
   19745 let Inst{31-21} = 0b01000000011;
   19746 let isPredicated = 1;
   19747 let addrMode = BaseImmOffset;
   19748 let accessSize = HalfWordAccess;
   19749 let mayStore = 1;
   19750 let CextOpcode = "S2_storerf";
   19751 let InputType = "imm";
   19752 let BaseOpcode = "S2_storerf_io";
   19753 let isExtendable = 1;
   19754 let opExtendable = 2;
   19755 let isExtentSigned = 0;
   19756 let opExtentBits = 7;
   19757 let opExtentAlign = 1;
   19758 }
   19759 def S2_pstorerft_pi : HInst<
   19760 (outs IntRegs:$Rx32),
   19761 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19762 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
   19763 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
   19764 let Inst{2-2} = 0b0;
   19765 let Inst{7-7} = 0b0;
   19766 let Inst{13-13} = 0b1;
   19767 let Inst{31-21} = 0b10101011011;
   19768 let isPredicated = 1;
   19769 let addrMode = PostInc;
   19770 let accessSize = HalfWordAccess;
   19771 let mayStore = 1;
   19772 let CextOpcode = "S2_storerf";
   19773 let BaseOpcode = "S2_storerf_pi";
   19774 let Constraints = "$Rx32 = $Rx32in";
   19775 }
   19776 def S2_pstorerft_zomap : HInst<
   19777 (outs),
   19778 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   19779 "if ($Pv4) memh($Rs32) = $Rt32.h",
   19780 tc_8b15472a, TypeMAPPING> {
   19781 let isPseudo = 1;
   19782 let isCodeGenOnly = 1;
   19783 }
   19784 def S2_pstorerftnew_pi : HInst<
   19785 (outs IntRegs:$Rx32),
   19786 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19787 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
   19788 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
   19789 let Inst{2-2} = 0b0;
   19790 let Inst{7-7} = 0b1;
   19791 let Inst{13-13} = 0b1;
   19792 let Inst{31-21} = 0b10101011011;
   19793 let isPredicated = 1;
   19794 let addrMode = PostInc;
   19795 let accessSize = HalfWordAccess;
   19796 let isPredicatedNew = 1;
   19797 let mayStore = 1;
   19798 let CextOpcode = "S2_storerf";
   19799 let BaseOpcode = "S2_storerf_pi";
   19800 let Constraints = "$Rx32 = $Rx32in";
   19801 }
   19802 def S2_pstorerhf_io : HInst<
   19803 (outs),
   19804 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   19805 "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
   19806 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   19807 let Inst{2-2} = 0b0;
   19808 let Inst{31-21} = 0b01000100010;
   19809 let isPredicated = 1;
   19810 let isPredicatedFalse = 1;
   19811 let addrMode = BaseImmOffset;
   19812 let accessSize = HalfWordAccess;
   19813 let mayStore = 1;
   19814 let CextOpcode = "S2_storerh";
   19815 let InputType = "imm";
   19816 let BaseOpcode = "S2_storerh_io";
   19817 let isNVStorable = 1;
   19818 let isExtendable = 1;
   19819 let opExtendable = 2;
   19820 let isExtentSigned = 0;
   19821 let opExtentBits = 7;
   19822 let opExtentAlign = 1;
   19823 }
   19824 def S2_pstorerhf_pi : HInst<
   19825 (outs IntRegs:$Rx32),
   19826 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19827 "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
   19828 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
   19829 let Inst{2-2} = 0b1;
   19830 let Inst{7-7} = 0b0;
   19831 let Inst{13-13} = 0b1;
   19832 let Inst{31-21} = 0b10101011010;
   19833 let isPredicated = 1;
   19834 let isPredicatedFalse = 1;
   19835 let addrMode = PostInc;
   19836 let accessSize = HalfWordAccess;
   19837 let mayStore = 1;
   19838 let BaseOpcode = "S2_storerh_pi";
   19839 let isNVStorable = 1;
   19840 let Constraints = "$Rx32 = $Rx32in";
   19841 }
   19842 def S2_pstorerhf_zomap : HInst<
   19843 (outs),
   19844 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   19845 "if (!$Pv4) memh($Rs32) = $Rt32",
   19846 tc_8b15472a, TypeMAPPING> {
   19847 let isPseudo = 1;
   19848 let isCodeGenOnly = 1;
   19849 }
   19850 def S2_pstorerhfnew_pi : HInst<
   19851 (outs IntRegs:$Rx32),
   19852 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   19853 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
   19854 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
   19855 let Inst{2-2} = 0b1;
   19856 let Inst{7-7} = 0b1;
   19857 let Inst{13-13} = 0b1;
   19858 let Inst{31-21} = 0b10101011010;
   19859 let isPredicated = 1;
   19860 let isPredicatedFalse = 1;
   19861 let addrMode = PostInc;
   19862 let accessSize = HalfWordAccess;
   19863 let isPredicatedNew = 1;
   19864 let mayStore = 1;
   19865 let BaseOpcode = "S2_storerh_pi";
   19866 let isNVStorable = 1;
   19867 let Constraints = "$Rx32 = $Rx32in";
   19868 }
   19869 def S2_pstorerhnewf_io : HInst<
   19870 (outs),
   19871 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
   19872 "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
   19873 tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
   19874 let Inst{2-2} = 0b0;
   19875 let Inst{12-11} = 0b01;
   19876 let Inst{31-21} = 0b01000100101;
   19877 let isPredicated = 1;
   19878 let isPredicatedFalse = 1;
   19879 let addrMode = BaseImmOffset;
   19880 let accessSize = HalfWordAccess;
   19881 let isNVStore = 1;
   19882 let isNewValue = 1;
   19883 let isRestrictNoSlot1Store = 1;
   19884 let mayStore = 1;
   19885 let CextOpcode = "S2_storerh";
   19886 let InputType = "imm";
   19887 let BaseOpcode = "S2_storerh_io";
   19888 let isExtendable = 1;
   19889 let opExtendable = 2;
   19890 let isExtentSigned = 0;
   19891 let opExtentBits = 7;
   19892 let opExtentAlign = 1;
   19893 let opNewValue = 3;
   19894 }
   19895 def S2_pstorerhnewf_pi : HInst<
   19896 (outs IntRegs:$Rx32),
   19897 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
   19898 "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
   19899 tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
   19900 let Inst{2-2} = 0b1;
   19901 let Inst{7-7} = 0b0;
   19902 let Inst{13-11} = 0b101;
   19903 let Inst{31-21} = 0b10101011101;
   19904 let isPredicated = 1;
   19905 let isPredicatedFalse = 1;
   19906 let addrMode = PostInc;
   19907 let accessSize = HalfWordAccess;
   19908 let isNVStore = 1;
   19909 let isNewValue = 1;
   19910 let isRestrictNoSlot1Store = 1;
   19911 let mayStore = 1;
   19912 let CextOpcode = "S2_storerh";
   19913 let BaseOpcode = "S2_storerh_pi";
   19914 let opNewValue = 4;
   19915 let Constraints = "$Rx32 = $Rx32in";
   19916 }
   19917 def S2_pstorerhnewf_zomap : HInst<
   19918 (outs),
   19919 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   19920 "if (!$Pv4) memh($Rs32) = $Nt8.new",
   19921 tc_594ab548, TypeMAPPING> {
   19922 let isPseudo = 1;
   19923 let isCodeGenOnly = 1;
   19924 let opNewValue = 2;
   19925 }
   19926 def S2_pstorerhnewfnew_pi : HInst<
   19927 (outs IntRegs:$Rx32),
   19928 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
   19929 "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
   19930 tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
   19931 let Inst{2-2} = 0b1;
   19932 let Inst{7-7} = 0b1;
   19933 let Inst{13-11} = 0b101;
   19934 let Inst{31-21} = 0b10101011101;
   19935 let isPredicated = 1;
   19936 let isPredicatedFalse = 1;
   19937 let addrMode = PostInc;
   19938 let accessSize = HalfWordAccess;
   19939 let isNVStore = 1;
   19940 let isPredicatedNew = 1;
   19941 let isNewValue = 1;
   19942 let isRestrictNoSlot1Store = 1;
   19943 let mayStore = 1;
   19944 let CextOpcode = "S2_storerh";
   19945 let BaseOpcode = "S2_storerh_pi";
   19946 let opNewValue = 4;
   19947 let Constraints = "$Rx32 = $Rx32in";
   19948 }
   19949 def S2_pstorerhnewt_io : HInst<
   19950 (outs),
   19951 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
   19952 "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
   19953 tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel {
   19954 let Inst{2-2} = 0b0;
   19955 let Inst{12-11} = 0b01;
   19956 let Inst{31-21} = 0b01000000101;
   19957 let isPredicated = 1;
   19958 let addrMode = BaseImmOffset;
   19959 let accessSize = HalfWordAccess;
   19960 let isNVStore = 1;
   19961 let isNewValue = 1;
   19962 let isRestrictNoSlot1Store = 1;
   19963 let mayStore = 1;
   19964 let CextOpcode = "S2_storerh";
   19965 let InputType = "imm";
   19966 let BaseOpcode = "S2_storerh_io";
   19967 let isExtendable = 1;
   19968 let opExtendable = 2;
   19969 let isExtentSigned = 0;
   19970 let opExtentBits = 7;
   19971 let opExtentAlign = 1;
   19972 let opNewValue = 3;
   19973 }
   19974 def S2_pstorerhnewt_pi : HInst<
   19975 (outs IntRegs:$Rx32),
   19976 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
   19977 "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
   19978 tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel {
   19979 let Inst{2-2} = 0b0;
   19980 let Inst{7-7} = 0b0;
   19981 let Inst{13-11} = 0b101;
   19982 let Inst{31-21} = 0b10101011101;
   19983 let isPredicated = 1;
   19984 let addrMode = PostInc;
   19985 let accessSize = HalfWordAccess;
   19986 let isNVStore = 1;
   19987 let isNewValue = 1;
   19988 let isRestrictNoSlot1Store = 1;
   19989 let mayStore = 1;
   19990 let CextOpcode = "S2_storerh";
   19991 let BaseOpcode = "S2_storerh_pi";
   19992 let opNewValue = 4;
   19993 let Constraints = "$Rx32 = $Rx32in";
   19994 }
   19995 def S2_pstorerhnewt_zomap : HInst<
   19996 (outs),
   19997 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   19998 "if ($Pv4) memh($Rs32) = $Nt8.new",
   19999 tc_594ab548, TypeMAPPING> {
   20000 let isPseudo = 1;
   20001 let isCodeGenOnly = 1;
   20002 let opNewValue = 2;
   20003 }
   20004 def S2_pstorerhnewtnew_pi : HInst<
   20005 (outs IntRegs:$Rx32),
   20006 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
   20007 "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
   20008 tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel {
   20009 let Inst{2-2} = 0b0;
   20010 let Inst{7-7} = 0b1;
   20011 let Inst{13-11} = 0b101;
   20012 let Inst{31-21} = 0b10101011101;
   20013 let isPredicated = 1;
   20014 let addrMode = PostInc;
   20015 let accessSize = HalfWordAccess;
   20016 let isNVStore = 1;
   20017 let isPredicatedNew = 1;
   20018 let isNewValue = 1;
   20019 let isRestrictNoSlot1Store = 1;
   20020 let mayStore = 1;
   20021 let CextOpcode = "S2_storerh";
   20022 let BaseOpcode = "S2_storerh_pi";
   20023 let opNewValue = 4;
   20024 let Constraints = "$Rx32 = $Rx32in";
   20025 }
   20026 def S2_pstorerht_io : HInst<
   20027 (outs),
   20028 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   20029 "if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
   20030 tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   20031 let Inst{2-2} = 0b0;
   20032 let Inst{31-21} = 0b01000000010;
   20033 let isPredicated = 1;
   20034 let addrMode = BaseImmOffset;
   20035 let accessSize = HalfWordAccess;
   20036 let mayStore = 1;
   20037 let CextOpcode = "S2_storerh";
   20038 let InputType = "imm";
   20039 let BaseOpcode = "S2_storerh_io";
   20040 let isNVStorable = 1;
   20041 let isExtendable = 1;
   20042 let opExtendable = 2;
   20043 let isExtentSigned = 0;
   20044 let opExtentBits = 7;
   20045 let opExtentAlign = 1;
   20046 }
   20047 def S2_pstorerht_pi : HInst<
   20048 (outs IntRegs:$Rx32),
   20049 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   20050 "if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
   20051 tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel {
   20052 let Inst{2-2} = 0b0;
   20053 let Inst{7-7} = 0b0;
   20054 let Inst{13-13} = 0b1;
   20055 let Inst{31-21} = 0b10101011010;
   20056 let isPredicated = 1;
   20057 let addrMode = PostInc;
   20058 let accessSize = HalfWordAccess;
   20059 let mayStore = 1;
   20060 let BaseOpcode = "S2_storerh_pi";
   20061 let isNVStorable = 1;
   20062 let Constraints = "$Rx32 = $Rx32in";
   20063 }
   20064 def S2_pstorerht_zomap : HInst<
   20065 (outs),
   20066 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   20067 "if ($Pv4) memh($Rs32) = $Rt32",
   20068 tc_8b15472a, TypeMAPPING> {
   20069 let isPseudo = 1;
   20070 let isCodeGenOnly = 1;
   20071 }
   20072 def S2_pstorerhtnew_pi : HInst<
   20073 (outs IntRegs:$Rx32),
   20074 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   20075 "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
   20076 tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel {
   20077 let Inst{2-2} = 0b0;
   20078 let Inst{7-7} = 0b1;
   20079 let Inst{13-13} = 0b1;
   20080 let Inst{31-21} = 0b10101011010;
   20081 let isPredicated = 1;
   20082 let addrMode = PostInc;
   20083 let accessSize = HalfWordAccess;
   20084 let isPredicatedNew = 1;
   20085 let mayStore = 1;
   20086 let BaseOpcode = "S2_storerh_pi";
   20087 let isNVStorable = 1;
   20088 let Constraints = "$Rx32 = $Rx32in";
   20089 }
   20090 def S2_pstorerif_io : HInst<
   20091 (outs),
   20092 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   20093 "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
   20094 tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
   20095 let Inst{2-2} = 0b0;
   20096 let Inst{31-21} = 0b01000100100;
   20097 let isPredicated = 1;
   20098 let isPredicatedFalse = 1;
   20099 let addrMode = BaseImmOffset;
   20100 let accessSize = WordAccess;
   20101 let mayStore = 1;
   20102 let CextOpcode = "S2_storeri";
   20103 let InputType = "imm";
   20104 let BaseOpcode = "S2_storeri_io";
   20105 let isNVStorable = 1;
   20106 let isExtendable = 1;
   20107 let opExtendable = 2;
   20108 let isExtentSigned = 0;
   20109 let opExtentBits = 8;
   20110 let opExtentAlign = 2;
   20111 }
   20112 def S2_pstorerif_pi : HInst<
   20113 (outs IntRegs:$Rx32),
   20114 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
   20115 "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
   20116 tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
   20117 let Inst{2-2} = 0b1;
   20118 let Inst{7-7} = 0b0;
   20119 let Inst{13-13} = 0b1;
   20120 let Inst{31-21} = 0b10101011100;
   20121 let isPredicated = 1;
   20122 let isPredicatedFalse = 1;
   20123 let addrMode = PostInc;
   20124 let accessSize = WordAccess;
   20125 let mayStore = 1;
   20126 let BaseOpcode = "S2_storeri_pi";
   20127 let isNVStorable = 1;
   20128 let Constraints = "$Rx32 = $Rx32in";
   20129 }
   20130 def S2_pstorerif_zomap : HInst<
   20131 (outs),
   20132 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   20133 "if (!$Pv4) memw($Rs32) = $Rt32",
   20134 tc_8b15472a, TypeMAPPING> {
   20135 let isPseudo = 1;
   20136 let isCodeGenOnly = 1;
   20137 }
   20138 def S2_pstorerifnew_pi : HInst<
   20139 (outs IntRegs:$Rx32),
   20140 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
   20141 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
   20142 tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
   20143 let Inst{2-2} = 0b1;
   20144 let Inst{7-7} = 0b1;
   20145 let Inst{13-13} = 0b1;
   20146 let Inst{31-21} = 0b10101011100;
   20147 let isPredicated = 1;
   20148 let isPredicatedFalse = 1;
   20149 let addrMode = PostInc;
   20150 let accessSize = WordAccess;
   20151 let isPredicatedNew = 1;
   20152 let mayStore = 1;
   20153 let CextOpcode = "S2_storeri";
   20154 let BaseOpcode = "S2_storeri_pi";
   20155 let isNVStorable = 1;
   20156 let Constraints = "$Rx32 = $Rx32in";
   20157 }
   20158 def S2_pstorerinewf_io : HInst<
   20159 (outs),
   20160 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
   20161 "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
   20162 tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
   20163 let Inst{2-2} = 0b0;
   20164 let Inst{12-11} = 0b10;
   20165 let Inst{31-21} = 0b01000100101;
   20166 let isPredicated = 1;
   20167 let isPredicatedFalse = 1;
   20168 let addrMode = BaseImmOffset;
   20169 let accessSize = WordAccess;
   20170 let isNVStore = 1;
   20171 let isNewValue = 1;
   20172 let isRestrictNoSlot1Store = 1;
   20173 let mayStore = 1;
   20174 let CextOpcode = "S2_storeri";
   20175 let InputType = "imm";
   20176 let BaseOpcode = "S2_storeri_io";
   20177 let isExtendable = 1;
   20178 let opExtendable = 2;
   20179 let isExtentSigned = 0;
   20180 let opExtentBits = 8;
   20181 let opExtentAlign = 2;
   20182 let opNewValue = 3;
   20183 }
   20184 def S2_pstorerinewf_pi : HInst<
   20185 (outs IntRegs:$Rx32),
   20186 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
   20187 "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
   20188 tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
   20189 let Inst{2-2} = 0b1;
   20190 let Inst{7-7} = 0b0;
   20191 let Inst{13-11} = 0b110;
   20192 let Inst{31-21} = 0b10101011101;
   20193 let isPredicated = 1;
   20194 let isPredicatedFalse = 1;
   20195 let addrMode = PostInc;
   20196 let accessSize = WordAccess;
   20197 let isNVStore = 1;
   20198 let isNewValue = 1;
   20199 let isRestrictNoSlot1Store = 1;
   20200 let mayStore = 1;
   20201 let CextOpcode = "S2_storeri";
   20202 let BaseOpcode = "S2_storeri_pi";
   20203 let opNewValue = 4;
   20204 let Constraints = "$Rx32 = $Rx32in";
   20205 }
   20206 def S2_pstorerinewf_zomap : HInst<
   20207 (outs),
   20208 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   20209 "if (!$Pv4) memw($Rs32) = $Nt8.new",
   20210 tc_594ab548, TypeMAPPING> {
   20211 let isPseudo = 1;
   20212 let isCodeGenOnly = 1;
   20213 let opNewValue = 2;
   20214 }
   20215 def S2_pstorerinewfnew_pi : HInst<
   20216 (outs IntRegs:$Rx32),
   20217 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
   20218 "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
   20219 tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
   20220 let Inst{2-2} = 0b1;
   20221 let Inst{7-7} = 0b1;
   20222 let Inst{13-11} = 0b110;
   20223 let Inst{31-21} = 0b10101011101;
   20224 let isPredicated = 1;
   20225 let isPredicatedFalse = 1;
   20226 let addrMode = PostInc;
   20227 let accessSize = WordAccess;
   20228 let isNVStore = 1;
   20229 let isPredicatedNew = 1;
   20230 let isNewValue = 1;
   20231 let isRestrictNoSlot1Store = 1;
   20232 let mayStore = 1;
   20233 let CextOpcode = "S2_storeri";
   20234 let BaseOpcode = "S2_storeri_pi";
   20235 let opNewValue = 4;
   20236 let Constraints = "$Rx32 = $Rx32in";
   20237 }
   20238 def S2_pstorerinewt_io : HInst<
   20239 (outs),
   20240 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
   20241 "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
   20242 tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
   20243 let Inst{2-2} = 0b0;
   20244 let Inst{12-11} = 0b10;
   20245 let Inst{31-21} = 0b01000000101;
   20246 let isPredicated = 1;
   20247 let addrMode = BaseImmOffset;
   20248 let accessSize = WordAccess;
   20249 let isNVStore = 1;
   20250 let isNewValue = 1;
   20251 let isRestrictNoSlot1Store = 1;
   20252 let mayStore = 1;
   20253 let CextOpcode = "S2_storeri";
   20254 let InputType = "imm";
   20255 let BaseOpcode = "S2_storeri_io";
   20256 let isExtendable = 1;
   20257 let opExtendable = 2;
   20258 let isExtentSigned = 0;
   20259 let opExtentBits = 8;
   20260 let opExtentAlign = 2;
   20261 let opNewValue = 3;
   20262 }
   20263 def S2_pstorerinewt_pi : HInst<
   20264 (outs IntRegs:$Rx32),
   20265 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
   20266 "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
   20267 tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel {
   20268 let Inst{2-2} = 0b0;
   20269 let Inst{7-7} = 0b0;
   20270 let Inst{13-11} = 0b110;
   20271 let Inst{31-21} = 0b10101011101;
   20272 let isPredicated = 1;
   20273 let addrMode = PostInc;
   20274 let accessSize = WordAccess;
   20275 let isNVStore = 1;
   20276 let isNewValue = 1;
   20277 let isRestrictNoSlot1Store = 1;
   20278 let mayStore = 1;
   20279 let CextOpcode = "S2_storeri";
   20280 let BaseOpcode = "S2_storeri_pi";
   20281 let opNewValue = 4;
   20282 let Constraints = "$Rx32 = $Rx32in";
   20283 }
   20284 def S2_pstorerinewt_zomap : HInst<
   20285 (outs),
   20286 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   20287 "if ($Pv4) memw($Rs32) = $Nt8.new",
   20288 tc_594ab548, TypeMAPPING> {
   20289 let isPseudo = 1;
   20290 let isCodeGenOnly = 1;
   20291 let opNewValue = 2;
   20292 }
   20293 def S2_pstorerinewtnew_pi : HInst<
   20294 (outs IntRegs:$Rx32),
   20295 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
   20296 "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
   20297 tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel {
   20298 let Inst{2-2} = 0b0;
   20299 let Inst{7-7} = 0b1;
   20300 let Inst{13-11} = 0b110;
   20301 let Inst{31-21} = 0b10101011101;
   20302 let isPredicated = 1;
   20303 let addrMode = PostInc;
   20304 let accessSize = WordAccess;
   20305 let isNVStore = 1;
   20306 let isPredicatedNew = 1;
   20307 let isNewValue = 1;
   20308 let isRestrictNoSlot1Store = 1;
   20309 let mayStore = 1;
   20310 let CextOpcode = "S2_storeri";
   20311 let BaseOpcode = "S2_storeri_pi";
   20312 let opNewValue = 4;
   20313 let Constraints = "$Rx32 = $Rx32in";
   20314 }
   20315 def S2_pstorerit_io : HInst<
   20316 (outs),
   20317 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   20318 "if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
   20319 tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel {
   20320 let Inst{2-2} = 0b0;
   20321 let Inst{31-21} = 0b01000000100;
   20322 let isPredicated = 1;
   20323 let addrMode = BaseImmOffset;
   20324 let accessSize = WordAccess;
   20325 let mayStore = 1;
   20326 let CextOpcode = "S2_storeri";
   20327 let InputType = "imm";
   20328 let BaseOpcode = "S2_storeri_io";
   20329 let isNVStorable = 1;
   20330 let isExtendable = 1;
   20331 let opExtendable = 2;
   20332 let isExtentSigned = 0;
   20333 let opExtentBits = 8;
   20334 let opExtentAlign = 2;
   20335 }
   20336 def S2_pstorerit_pi : HInst<
   20337 (outs IntRegs:$Rx32),
   20338 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
   20339 "if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
   20340 tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel {
   20341 let Inst{2-2} = 0b0;
   20342 let Inst{7-7} = 0b0;
   20343 let Inst{13-13} = 0b1;
   20344 let Inst{31-21} = 0b10101011100;
   20345 let isPredicated = 1;
   20346 let addrMode = PostInc;
   20347 let accessSize = WordAccess;
   20348 let mayStore = 1;
   20349 let BaseOpcode = "S2_storeri_pi";
   20350 let isNVStorable = 1;
   20351 let Constraints = "$Rx32 = $Rx32in";
   20352 }
   20353 def S2_pstorerit_zomap : HInst<
   20354 (outs),
   20355 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   20356 "if ($Pv4) memw($Rs32) = $Rt32",
   20357 tc_8b15472a, TypeMAPPING> {
   20358 let isPseudo = 1;
   20359 let isCodeGenOnly = 1;
   20360 }
   20361 def S2_pstoreritnew_pi : HInst<
   20362 (outs IntRegs:$Rx32),
   20363 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
   20364 "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
   20365 tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel {
   20366 let Inst{2-2} = 0b0;
   20367 let Inst{7-7} = 0b1;
   20368 let Inst{13-13} = 0b1;
   20369 let Inst{31-21} = 0b10101011100;
   20370 let isPredicated = 1;
   20371 let addrMode = PostInc;
   20372 let accessSize = WordAccess;
   20373 let isPredicatedNew = 1;
   20374 let mayStore = 1;
   20375 let BaseOpcode = "S2_storeri_pi";
   20376 let isNVStorable = 1;
   20377 let Constraints = "$Rx32 = $Rx32in";
   20378 }
   20379 def S2_setbit_i : HInst<
   20380 (outs IntRegs:$Rd32),
   20381 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   20382 "$Rd32 = setbit($Rs32,#$Ii)",
   20383 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   20384 let Inst{7-5} = 0b000;
   20385 let Inst{13-13} = 0b0;
   20386 let Inst{31-21} = 0b10001100110;
   20387 let hasNewValue = 1;
   20388 let opNewValue = 0;
   20389 }
   20390 def S2_setbit_r : HInst<
   20391 (outs IntRegs:$Rd32),
   20392 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   20393 "$Rd32 = setbit($Rs32,$Rt32)",
   20394 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   20395 let Inst{7-5} = 0b000;
   20396 let Inst{13-13} = 0b0;
   20397 let Inst{31-21} = 0b11000110100;
   20398 let hasNewValue = 1;
   20399 let opNewValue = 0;
   20400 }
   20401 def S2_shuffeb : HInst<
   20402 (outs DoubleRegs:$Rdd32),
   20403 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   20404 "$Rdd32 = shuffeb($Rss32,$Rtt32)",
   20405 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
   20406 let Inst{7-5} = 0b010;
   20407 let Inst{13-13} = 0b0;
   20408 let Inst{31-21} = 0b11000001000;
   20409 }
   20410 def S2_shuffeh : HInst<
   20411 (outs DoubleRegs:$Rdd32),
   20412 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   20413 "$Rdd32 = shuffeh($Rss32,$Rtt32)",
   20414 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
   20415 let Inst{7-5} = 0b110;
   20416 let Inst{13-13} = 0b0;
   20417 let Inst{31-21} = 0b11000001000;
   20418 }
   20419 def S2_shuffob : HInst<
   20420 (outs DoubleRegs:$Rdd32),
   20421 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   20422 "$Rdd32 = shuffob($Rtt32,$Rss32)",
   20423 tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
   20424 let Inst{7-5} = 0b100;
   20425 let Inst{13-13} = 0b0;
   20426 let Inst{31-21} = 0b11000001000;
   20427 }
   20428 def S2_shuffoh : HInst<
   20429 (outs DoubleRegs:$Rdd32),
   20430 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
   20431 "$Rdd32 = shuffoh($Rtt32,$Rss32)",
   20432 tc_540fdfbc, TypeS_3op>, Enc_ea23e4 {
   20433 let Inst{7-5} = 0b000;
   20434 let Inst{13-13} = 0b0;
   20435 let Inst{31-21} = 0b11000001100;
   20436 }
   20437 def S2_storerb_io : HInst<
   20438 (outs),
   20439 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
   20440 "memb($Rs32+#$Ii) = $Rt32",
   20441 tc_05b6c987, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
   20442 let Inst{24-21} = 0b1000;
   20443 let Inst{31-27} = 0b10100;
   20444 let addrMode = BaseImmOffset;
   20445 let accessSize = ByteAccess;
   20446 let mayStore = 1;
   20447 let CextOpcode = "S2_storerb";
   20448 let InputType = "imm";
   20449 let BaseOpcode = "S2_storerb_io";
   20450 let isPredicable = 1;
   20451 let isNVStorable = 1;
   20452 let isExtendable = 1;
   20453 let opExtendable = 1;
   20454 let isExtentSigned = 1;
   20455 let opExtentBits = 11;
   20456 let opExtentAlign = 0;
   20457 }
   20458 def S2_storerb_pbr : HInst<
   20459 (outs IntRegs:$Rx32),
   20460 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20461 "memb($Rx32++$Mu2:brev) = $Rt32",
   20462 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   20463 let Inst{7-0} = 0b00000000;
   20464 let Inst{31-21} = 0b10101111000;
   20465 let accessSize = ByteAccess;
   20466 let mayStore = 1;
   20467 let BaseOpcode = "S2_storerb_pbr";
   20468 let isNVStorable = 1;
   20469 let Constraints = "$Rx32 = $Rx32in";
   20470 }
   20471 def S2_storerb_pci : HInst<
   20472 (outs IntRegs:$Rx32),
   20473 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
   20474 "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
   20475 tc_9fdb5406, TypeST>, Enc_b15941, AddrModeRel {
   20476 let Inst{2-0} = 0b000;
   20477 let Inst{7-7} = 0b0;
   20478 let Inst{31-21} = 0b10101001000;
   20479 let addrMode = PostInc;
   20480 let accessSize = ByteAccess;
   20481 let mayStore = 1;
   20482 let Uses = [CS];
   20483 let BaseOpcode = "S2_storerb_pci";
   20484 let isNVStorable = 1;
   20485 let Constraints = "$Rx32 = $Rx32in";
   20486 }
   20487 def S2_storerb_pcr : HInst<
   20488 (outs IntRegs:$Rx32),
   20489 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20490 "memb($Rx32++I:circ($Mu2)) = $Rt32",
   20491 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   20492 let Inst{7-0} = 0b00000010;
   20493 let Inst{31-21} = 0b10101001000;
   20494 let addrMode = PostInc;
   20495 let accessSize = ByteAccess;
   20496 let mayStore = 1;
   20497 let Uses = [CS];
   20498 let BaseOpcode = "S2_storerb_pcr";
   20499 let isNVStorable = 1;
   20500 let Constraints = "$Rx32 = $Rx32in";
   20501 }
   20502 def S2_storerb_pi : HInst<
   20503 (outs IntRegs:$Rx32),
   20504 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
   20505 "memb($Rx32++#$Ii) = $Rt32",
   20506 tc_f86c328a, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
   20507 let Inst{2-0} = 0b000;
   20508 let Inst{7-7} = 0b0;
   20509 let Inst{13-13} = 0b0;
   20510 let Inst{31-21} = 0b10101011000;
   20511 let addrMode = PostInc;
   20512 let accessSize = ByteAccess;
   20513 let mayStore = 1;
   20514 let CextOpcode = "S2_storerb";
   20515 let BaseOpcode = "S2_storerb_pi";
   20516 let isPredicable = 1;
   20517 let isNVStorable = 1;
   20518 let Constraints = "$Rx32 = $Rx32in";
   20519 }
   20520 def S2_storerb_pr : HInst<
   20521 (outs IntRegs:$Rx32),
   20522 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20523 "memb($Rx32++$Mu2) = $Rt32",
   20524 tc_f86c328a, TypeST>, Enc_d5c73f {
   20525 let Inst{7-0} = 0b00000000;
   20526 let Inst{31-21} = 0b10101101000;
   20527 let addrMode = PostInc;
   20528 let accessSize = ByteAccess;
   20529 let mayStore = 1;
   20530 let isNVStorable = 1;
   20531 let Constraints = "$Rx32 = $Rx32in";
   20532 }
   20533 def S2_storerb_zomap : HInst<
   20534 (outs),
   20535 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   20536 "memb($Rs32) = $Rt32",
   20537 tc_05b6c987, TypeMAPPING> {
   20538 let isPseudo = 1;
   20539 let isCodeGenOnly = 1;
   20540 }
   20541 def S2_storerbgp : HInst<
   20542 (outs),
   20543 (ins u32_0Imm:$Ii, IntRegs:$Rt32),
   20544 "memb(gp+#$Ii) = $Rt32",
   20545 tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
   20546 let Inst{24-21} = 0b0000;
   20547 let Inst{31-27} = 0b01001;
   20548 let accessSize = ByteAccess;
   20549 let mayStore = 1;
   20550 let Uses = [GP];
   20551 let BaseOpcode = "S2_storerbabs";
   20552 let isPredicable = 1;
   20553 let isNVStorable = 1;
   20554 let opExtendable = 0;
   20555 let isExtentSigned = 0;
   20556 let opExtentBits = 16;
   20557 let opExtentAlign = 0;
   20558 }
   20559 def S2_storerbnew_io : HInst<
   20560 (outs),
   20561 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
   20562 "memb($Rs32+#$Ii) = $Nt8.new",
   20563 tc_f7dd9c9f, TypeST>, Enc_4df4e9, AddrModeRel {
   20564 let Inst{12-11} = 0b00;
   20565 let Inst{24-21} = 0b1101;
   20566 let Inst{31-27} = 0b10100;
   20567 let addrMode = BaseImmOffset;
   20568 let accessSize = ByteAccess;
   20569 let isNVStore = 1;
   20570 let isNewValue = 1;
   20571 let isRestrictNoSlot1Store = 1;
   20572 let mayStore = 1;
   20573 let CextOpcode = "S2_storerb";
   20574 let InputType = "imm";
   20575 let BaseOpcode = "S2_storerb_io";
   20576 let isPredicable = 1;
   20577 let isExtendable = 1;
   20578 let opExtendable = 1;
   20579 let isExtentSigned = 1;
   20580 let opExtentBits = 11;
   20581 let opExtentAlign = 0;
   20582 let opNewValue = 2;
   20583 }
   20584 def S2_storerbnew_pbr : HInst<
   20585 (outs IntRegs:$Rx32),
   20586 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   20587 "memb($Rx32++$Mu2:brev) = $Nt8.new",
   20588 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   20589 let Inst{7-0} = 0b00000000;
   20590 let Inst{12-11} = 0b00;
   20591 let Inst{31-21} = 0b10101111101;
   20592 let accessSize = ByteAccess;
   20593 let isNVStore = 1;
   20594 let isNewValue = 1;
   20595 let isRestrictNoSlot1Store = 1;
   20596 let mayStore = 1;
   20597 let BaseOpcode = "S2_storerb_pbr";
   20598 let opNewValue = 3;
   20599 let Constraints = "$Rx32 = $Rx32in";
   20600 }
   20601 def S2_storerbnew_pci : HInst<
   20602 (outs IntRegs:$Rx32),
   20603 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
   20604 "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
   20605 tc_9d5941c7, TypeST>, Enc_96ce4f, AddrModeRel {
   20606 let Inst{2-0} = 0b000;
   20607 let Inst{7-7} = 0b0;
   20608 let Inst{12-11} = 0b00;
   20609 let Inst{31-21} = 0b10101001101;
   20610 let addrMode = PostInc;
   20611 let accessSize = ByteAccess;
   20612 let isNVStore = 1;
   20613 let isNewValue = 1;
   20614 let isRestrictNoSlot1Store = 1;
   20615 let mayStore = 1;
   20616 let Uses = [CS];
   20617 let BaseOpcode = "S2_storerb_pci";
   20618 let opNewValue = 4;
   20619 let Constraints = "$Rx32 = $Rx32in";
   20620 }
   20621 def S2_storerbnew_pcr : HInst<
   20622 (outs IntRegs:$Rx32),
   20623 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   20624 "memb($Rx32++I:circ($Mu2)) = $Nt8.new",
   20625 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   20626 let Inst{7-0} = 0b00000010;
   20627 let Inst{12-11} = 0b00;
   20628 let Inst{31-21} = 0b10101001101;
   20629 let addrMode = PostInc;
   20630 let accessSize = ByteAccess;
   20631 let isNVStore = 1;
   20632 let isNewValue = 1;
   20633 let isRestrictNoSlot1Store = 1;
   20634 let mayStore = 1;
   20635 let Uses = [CS];
   20636 let BaseOpcode = "S2_storerb_pcr";
   20637 let opNewValue = 3;
   20638 let Constraints = "$Rx32 = $Rx32in";
   20639 }
   20640 def S2_storerbnew_pi : HInst<
   20641 (outs IntRegs:$Rx32),
   20642 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
   20643 "memb($Rx32++#$Ii) = $Nt8.new",
   20644 tc_e7d02c66, TypeST>, Enc_c7cd90, AddrModeRel {
   20645 let Inst{2-0} = 0b000;
   20646 let Inst{7-7} = 0b0;
   20647 let Inst{13-11} = 0b000;
   20648 let Inst{31-21} = 0b10101011101;
   20649 let addrMode = PostInc;
   20650 let accessSize = ByteAccess;
   20651 let isNVStore = 1;
   20652 let isNewValue = 1;
   20653 let isRestrictNoSlot1Store = 1;
   20654 let mayStore = 1;
   20655 let BaseOpcode = "S2_storerb_pi";
   20656 let isPredicable = 1;
   20657 let isNVStorable = 1;
   20658 let opNewValue = 3;
   20659 let Constraints = "$Rx32 = $Rx32in";
   20660 }
   20661 def S2_storerbnew_pr : HInst<
   20662 (outs IntRegs:$Rx32),
   20663 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   20664 "memb($Rx32++$Mu2) = $Nt8.new",
   20665 tc_e7d02c66, TypeST>, Enc_8dbe85 {
   20666 let Inst{7-0} = 0b00000000;
   20667 let Inst{12-11} = 0b00;
   20668 let Inst{31-21} = 0b10101101101;
   20669 let addrMode = PostInc;
   20670 let accessSize = ByteAccess;
   20671 let isNVStore = 1;
   20672 let isNewValue = 1;
   20673 let isRestrictNoSlot1Store = 1;
   20674 let mayStore = 1;
   20675 let opNewValue = 3;
   20676 let Constraints = "$Rx32 = $Rx32in";
   20677 }
   20678 def S2_storerbnew_zomap : HInst<
   20679 (outs),
   20680 (ins IntRegs:$Rs32, IntRegs:$Nt8),
   20681 "memb($Rs32) = $Nt8.new",
   20682 tc_f7dd9c9f, TypeMAPPING> {
   20683 let isPseudo = 1;
   20684 let isCodeGenOnly = 1;
   20685 let opNewValue = 1;
   20686 }
   20687 def S2_storerbnewgp : HInst<
   20688 (outs),
   20689 (ins u32_0Imm:$Ii, IntRegs:$Nt8),
   20690 "memb(gp+#$Ii) = $Nt8.new",
   20691 tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel {
   20692 let Inst{12-11} = 0b00;
   20693 let Inst{24-21} = 0b0101;
   20694 let Inst{31-27} = 0b01001;
   20695 let accessSize = ByteAccess;
   20696 let isNVStore = 1;
   20697 let isNewValue = 1;
   20698 let isRestrictNoSlot1Store = 1;
   20699 let mayStore = 1;
   20700 let Uses = [GP];
   20701 let BaseOpcode = "S2_storerbabs";
   20702 let isPredicable = 1;
   20703 let opExtendable = 0;
   20704 let isExtentSigned = 0;
   20705 let opExtentBits = 16;
   20706 let opExtentAlign = 0;
   20707 let opNewValue = 1;
   20708 }
   20709 def S2_storerd_io : HInst<
   20710 (outs),
   20711 (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
   20712 "memd($Rs32+#$Ii) = $Rtt32",
   20713 tc_05b6c987, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
   20714 let Inst{24-21} = 0b1110;
   20715 let Inst{31-27} = 0b10100;
   20716 let addrMode = BaseImmOffset;
   20717 let accessSize = DoubleWordAccess;
   20718 let mayStore = 1;
   20719 let CextOpcode = "S2_storerd";
   20720 let InputType = "imm";
   20721 let BaseOpcode = "S2_storerd_io";
   20722 let isPredicable = 1;
   20723 let isExtendable = 1;
   20724 let opExtendable = 1;
   20725 let isExtentSigned = 1;
   20726 let opExtentBits = 14;
   20727 let opExtentAlign = 3;
   20728 }
   20729 def S2_storerd_pbr : HInst<
   20730 (outs IntRegs:$Rx32),
   20731 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
   20732 "memd($Rx32++$Mu2:brev) = $Rtt32",
   20733 tc_f86c328a, TypeST>, Enc_928ca1 {
   20734 let Inst{7-0} = 0b00000000;
   20735 let Inst{31-21} = 0b10101111110;
   20736 let accessSize = DoubleWordAccess;
   20737 let mayStore = 1;
   20738 let Constraints = "$Rx32 = $Rx32in";
   20739 }
   20740 def S2_storerd_pci : HInst<
   20741 (outs IntRegs:$Rx32),
   20742 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
   20743 "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
   20744 tc_9fdb5406, TypeST>, Enc_395cc4 {
   20745 let Inst{2-0} = 0b000;
   20746 let Inst{7-7} = 0b0;
   20747 let Inst{31-21} = 0b10101001110;
   20748 let addrMode = PostInc;
   20749 let accessSize = DoubleWordAccess;
   20750 let mayStore = 1;
   20751 let Uses = [CS];
   20752 let Constraints = "$Rx32 = $Rx32in";
   20753 }
   20754 def S2_storerd_pcr : HInst<
   20755 (outs IntRegs:$Rx32),
   20756 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
   20757 "memd($Rx32++I:circ($Mu2)) = $Rtt32",
   20758 tc_f86c328a, TypeST>, Enc_928ca1 {
   20759 let Inst{7-0} = 0b00000010;
   20760 let Inst{31-21} = 0b10101001110;
   20761 let addrMode = PostInc;
   20762 let accessSize = DoubleWordAccess;
   20763 let mayStore = 1;
   20764 let Uses = [CS];
   20765 let Constraints = "$Rx32 = $Rx32in";
   20766 }
   20767 def S2_storerd_pi : HInst<
   20768 (outs IntRegs:$Rx32),
   20769 (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
   20770 "memd($Rx32++#$Ii) = $Rtt32",
   20771 tc_f86c328a, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
   20772 let Inst{2-0} = 0b000;
   20773 let Inst{7-7} = 0b0;
   20774 let Inst{13-13} = 0b0;
   20775 let Inst{31-21} = 0b10101011110;
   20776 let addrMode = PostInc;
   20777 let accessSize = DoubleWordAccess;
   20778 let mayStore = 1;
   20779 let CextOpcode = "S2_storerd";
   20780 let BaseOpcode = "S2_storerd_pi";
   20781 let isPredicable = 1;
   20782 let Constraints = "$Rx32 = $Rx32in";
   20783 }
   20784 def S2_storerd_pr : HInst<
   20785 (outs IntRegs:$Rx32),
   20786 (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
   20787 "memd($Rx32++$Mu2) = $Rtt32",
   20788 tc_f86c328a, TypeST>, Enc_928ca1 {
   20789 let Inst{7-0} = 0b00000000;
   20790 let Inst{31-21} = 0b10101101110;
   20791 let addrMode = PostInc;
   20792 let accessSize = DoubleWordAccess;
   20793 let mayStore = 1;
   20794 let Constraints = "$Rx32 = $Rx32in";
   20795 }
   20796 def S2_storerd_zomap : HInst<
   20797 (outs),
   20798 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   20799 "memd($Rs32) = $Rtt32",
   20800 tc_05b6c987, TypeMAPPING> {
   20801 let isPseudo = 1;
   20802 let isCodeGenOnly = 1;
   20803 }
   20804 def S2_storerdgp : HInst<
   20805 (outs),
   20806 (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   20807 "memd(gp+#$Ii) = $Rtt32",
   20808 tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel {
   20809 let Inst{24-21} = 0b0110;
   20810 let Inst{31-27} = 0b01001;
   20811 let accessSize = DoubleWordAccess;
   20812 let mayStore = 1;
   20813 let Uses = [GP];
   20814 let BaseOpcode = "S2_storerdabs";
   20815 let isPredicable = 1;
   20816 let opExtendable = 0;
   20817 let isExtentSigned = 0;
   20818 let opExtentBits = 19;
   20819 let opExtentAlign = 3;
   20820 }
   20821 def S2_storerf_io : HInst<
   20822 (outs),
   20823 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
   20824 "memh($Rs32+#$Ii) = $Rt32.h",
   20825 tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
   20826 let Inst{24-21} = 0b1011;
   20827 let Inst{31-27} = 0b10100;
   20828 let addrMode = BaseImmOffset;
   20829 let accessSize = HalfWordAccess;
   20830 let mayStore = 1;
   20831 let CextOpcode = "S2_storerf";
   20832 let InputType = "imm";
   20833 let BaseOpcode = "S2_storerf_io";
   20834 let isPredicable = 1;
   20835 let isExtendable = 1;
   20836 let opExtendable = 1;
   20837 let isExtentSigned = 1;
   20838 let opExtentBits = 12;
   20839 let opExtentAlign = 1;
   20840 }
   20841 def S2_storerf_pbr : HInst<
   20842 (outs IntRegs:$Rx32),
   20843 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20844 "memh($Rx32++$Mu2:brev) = $Rt32.h",
   20845 tc_f86c328a, TypeST>, Enc_d5c73f {
   20846 let Inst{7-0} = 0b00000000;
   20847 let Inst{31-21} = 0b10101111011;
   20848 let accessSize = HalfWordAccess;
   20849 let mayStore = 1;
   20850 let Constraints = "$Rx32 = $Rx32in";
   20851 }
   20852 def S2_storerf_pci : HInst<
   20853 (outs IntRegs:$Rx32),
   20854 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
   20855 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
   20856 tc_9fdb5406, TypeST>, Enc_935d9b {
   20857 let Inst{2-0} = 0b000;
   20858 let Inst{7-7} = 0b0;
   20859 let Inst{31-21} = 0b10101001011;
   20860 let addrMode = PostInc;
   20861 let accessSize = HalfWordAccess;
   20862 let mayStore = 1;
   20863 let Uses = [CS];
   20864 let Constraints = "$Rx32 = $Rx32in";
   20865 }
   20866 def S2_storerf_pcr : HInst<
   20867 (outs IntRegs:$Rx32),
   20868 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20869 "memh($Rx32++I:circ($Mu2)) = $Rt32.h",
   20870 tc_f86c328a, TypeST>, Enc_d5c73f {
   20871 let Inst{7-0} = 0b00000010;
   20872 let Inst{31-21} = 0b10101001011;
   20873 let addrMode = PostInc;
   20874 let accessSize = HalfWordAccess;
   20875 let mayStore = 1;
   20876 let Uses = [CS];
   20877 let Constraints = "$Rx32 = $Rx32in";
   20878 }
   20879 def S2_storerf_pi : HInst<
   20880 (outs IntRegs:$Rx32),
   20881 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   20882 "memh($Rx32++#$Ii) = $Rt32.h",
   20883 tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
   20884 let Inst{2-0} = 0b000;
   20885 let Inst{7-7} = 0b0;
   20886 let Inst{13-13} = 0b0;
   20887 let Inst{31-21} = 0b10101011011;
   20888 let addrMode = PostInc;
   20889 let accessSize = HalfWordAccess;
   20890 let mayStore = 1;
   20891 let CextOpcode = "S2_storerf";
   20892 let BaseOpcode = "S2_storerf_pi";
   20893 let isPredicable = 1;
   20894 let Constraints = "$Rx32 = $Rx32in";
   20895 }
   20896 def S2_storerf_pr : HInst<
   20897 (outs IntRegs:$Rx32),
   20898 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20899 "memh($Rx32++$Mu2) = $Rt32.h",
   20900 tc_f86c328a, TypeST>, Enc_d5c73f {
   20901 let Inst{7-0} = 0b00000000;
   20902 let Inst{31-21} = 0b10101101011;
   20903 let addrMode = PostInc;
   20904 let accessSize = HalfWordAccess;
   20905 let mayStore = 1;
   20906 let Constraints = "$Rx32 = $Rx32in";
   20907 }
   20908 def S2_storerf_zomap : HInst<
   20909 (outs),
   20910 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   20911 "memh($Rs32) = $Rt32.h",
   20912 tc_05b6c987, TypeMAPPING> {
   20913 let isPseudo = 1;
   20914 let isCodeGenOnly = 1;
   20915 }
   20916 def S2_storerfgp : HInst<
   20917 (outs),
   20918 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
   20919 "memh(gp+#$Ii) = $Rt32.h",
   20920 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
   20921 let Inst{24-21} = 0b0011;
   20922 let Inst{31-27} = 0b01001;
   20923 let accessSize = HalfWordAccess;
   20924 let mayStore = 1;
   20925 let Uses = [GP];
   20926 let BaseOpcode = "S2_storerfabs";
   20927 let isPredicable = 1;
   20928 let opExtendable = 0;
   20929 let isExtentSigned = 0;
   20930 let opExtentBits = 17;
   20931 let opExtentAlign = 1;
   20932 }
   20933 def S2_storerh_io : HInst<
   20934 (outs),
   20935 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
   20936 "memh($Rs32+#$Ii) = $Rt32",
   20937 tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
   20938 let Inst{24-21} = 0b1010;
   20939 let Inst{31-27} = 0b10100;
   20940 let addrMode = BaseImmOffset;
   20941 let accessSize = HalfWordAccess;
   20942 let mayStore = 1;
   20943 let CextOpcode = "S2_storerh";
   20944 let InputType = "imm";
   20945 let BaseOpcode = "S2_storerh_io";
   20946 let isPredicable = 1;
   20947 let isNVStorable = 1;
   20948 let isExtendable = 1;
   20949 let opExtendable = 1;
   20950 let isExtentSigned = 1;
   20951 let opExtentBits = 12;
   20952 let opExtentAlign = 1;
   20953 }
   20954 def S2_storerh_pbr : HInst<
   20955 (outs IntRegs:$Rx32),
   20956 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20957 "memh($Rx32++$Mu2:brev) = $Rt32",
   20958 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   20959 let Inst{7-0} = 0b00000000;
   20960 let Inst{31-21} = 0b10101111010;
   20961 let accessSize = HalfWordAccess;
   20962 let mayStore = 1;
   20963 let BaseOpcode = "S2_storerh_pbr";
   20964 let isNVStorable = 1;
   20965 let Constraints = "$Rx32 = $Rx32in";
   20966 }
   20967 def S2_storerh_pci : HInst<
   20968 (outs IntRegs:$Rx32),
   20969 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
   20970 "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
   20971 tc_9fdb5406, TypeST>, Enc_935d9b, AddrModeRel {
   20972 let Inst{2-0} = 0b000;
   20973 let Inst{7-7} = 0b0;
   20974 let Inst{31-21} = 0b10101001010;
   20975 let addrMode = PostInc;
   20976 let accessSize = HalfWordAccess;
   20977 let mayStore = 1;
   20978 let Uses = [CS];
   20979 let BaseOpcode = "S2_storerh_pci";
   20980 let isNVStorable = 1;
   20981 let Constraints = "$Rx32 = $Rx32in";
   20982 }
   20983 def S2_storerh_pcr : HInst<
   20984 (outs IntRegs:$Rx32),
   20985 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   20986 "memh($Rx32++I:circ($Mu2)) = $Rt32",
   20987 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   20988 let Inst{7-0} = 0b00000010;
   20989 let Inst{31-21} = 0b10101001010;
   20990 let addrMode = PostInc;
   20991 let accessSize = HalfWordAccess;
   20992 let mayStore = 1;
   20993 let Uses = [CS];
   20994 let BaseOpcode = "S2_storerh_pcr";
   20995 let isNVStorable = 1;
   20996 let Constraints = "$Rx32 = $Rx32in";
   20997 }
   20998 def S2_storerh_pi : HInst<
   20999 (outs IntRegs:$Rx32),
   21000 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
   21001 "memh($Rx32++#$Ii) = $Rt32",
   21002 tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
   21003 let Inst{2-0} = 0b000;
   21004 let Inst{7-7} = 0b0;
   21005 let Inst{13-13} = 0b0;
   21006 let Inst{31-21} = 0b10101011010;
   21007 let addrMode = PostInc;
   21008 let accessSize = HalfWordAccess;
   21009 let mayStore = 1;
   21010 let CextOpcode = "S2_storerh";
   21011 let BaseOpcode = "S2_storerh_pi";
   21012 let isPredicable = 1;
   21013 let isNVStorable = 1;
   21014 let Constraints = "$Rx32 = $Rx32in";
   21015 }
   21016 def S2_storerh_pr : HInst<
   21017 (outs IntRegs:$Rx32),
   21018 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   21019 "memh($Rx32++$Mu2) = $Rt32",
   21020 tc_f86c328a, TypeST>, Enc_d5c73f {
   21021 let Inst{7-0} = 0b00000000;
   21022 let Inst{31-21} = 0b10101101010;
   21023 let addrMode = PostInc;
   21024 let accessSize = HalfWordAccess;
   21025 let mayStore = 1;
   21026 let isNVStorable = 1;
   21027 let Constraints = "$Rx32 = $Rx32in";
   21028 }
   21029 def S2_storerh_zomap : HInst<
   21030 (outs),
   21031 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   21032 "memh($Rs32) = $Rt32",
   21033 tc_05b6c987, TypeMAPPING> {
   21034 let isPseudo = 1;
   21035 let isCodeGenOnly = 1;
   21036 }
   21037 def S2_storerhgp : HInst<
   21038 (outs),
   21039 (ins u31_1Imm:$Ii, IntRegs:$Rt32),
   21040 "memh(gp+#$Ii) = $Rt32",
   21041 tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel {
   21042 let Inst{24-21} = 0b0010;
   21043 let Inst{31-27} = 0b01001;
   21044 let accessSize = HalfWordAccess;
   21045 let mayStore = 1;
   21046 let Uses = [GP];
   21047 let BaseOpcode = "S2_storerhabs";
   21048 let isPredicable = 1;
   21049 let isNVStorable = 1;
   21050 let opExtendable = 0;
   21051 let isExtentSigned = 0;
   21052 let opExtentBits = 17;
   21053 let opExtentAlign = 1;
   21054 }
   21055 def S2_storerhnew_io : HInst<
   21056 (outs),
   21057 (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
   21058 "memh($Rs32+#$Ii) = $Nt8.new",
   21059 tc_f7dd9c9f, TypeST>, Enc_0d8870, AddrModeRel {
   21060 let Inst{12-11} = 0b01;
   21061 let Inst{24-21} = 0b1101;
   21062 let Inst{31-27} = 0b10100;
   21063 let addrMode = BaseImmOffset;
   21064 let accessSize = HalfWordAccess;
   21065 let isNVStore = 1;
   21066 let isNewValue = 1;
   21067 let isRestrictNoSlot1Store = 1;
   21068 let mayStore = 1;
   21069 let CextOpcode = "S2_storerh";
   21070 let InputType = "imm";
   21071 let BaseOpcode = "S2_storerh_io";
   21072 let isPredicable = 1;
   21073 let isExtendable = 1;
   21074 let opExtendable = 1;
   21075 let isExtentSigned = 1;
   21076 let opExtentBits = 12;
   21077 let opExtentAlign = 1;
   21078 let opNewValue = 2;
   21079 }
   21080 def S2_storerhnew_pbr : HInst<
   21081 (outs IntRegs:$Rx32),
   21082 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21083 "memh($Rx32++$Mu2:brev) = $Nt8.new",
   21084 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   21085 let Inst{7-0} = 0b00000000;
   21086 let Inst{12-11} = 0b01;
   21087 let Inst{31-21} = 0b10101111101;
   21088 let accessSize = HalfWordAccess;
   21089 let isNVStore = 1;
   21090 let isNewValue = 1;
   21091 let isRestrictNoSlot1Store = 1;
   21092 let mayStore = 1;
   21093 let BaseOpcode = "S2_storerh_pbr";
   21094 let opNewValue = 3;
   21095 let Constraints = "$Rx32 = $Rx32in";
   21096 }
   21097 def S2_storerhnew_pci : HInst<
   21098 (outs IntRegs:$Rx32),
   21099 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
   21100 "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
   21101 tc_9d5941c7, TypeST>, Enc_91b9fe, AddrModeRel {
   21102 let Inst{2-0} = 0b000;
   21103 let Inst{7-7} = 0b0;
   21104 let Inst{12-11} = 0b01;
   21105 let Inst{31-21} = 0b10101001101;
   21106 let addrMode = PostInc;
   21107 let accessSize = HalfWordAccess;
   21108 let isNVStore = 1;
   21109 let isNewValue = 1;
   21110 let isRestrictNoSlot1Store = 1;
   21111 let mayStore = 1;
   21112 let Uses = [CS];
   21113 let BaseOpcode = "S2_storerh_pci";
   21114 let opNewValue = 4;
   21115 let Constraints = "$Rx32 = $Rx32in";
   21116 }
   21117 def S2_storerhnew_pcr : HInst<
   21118 (outs IntRegs:$Rx32),
   21119 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21120 "memh($Rx32++I:circ($Mu2)) = $Nt8.new",
   21121 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   21122 let Inst{7-0} = 0b00000010;
   21123 let Inst{12-11} = 0b01;
   21124 let Inst{31-21} = 0b10101001101;
   21125 let addrMode = PostInc;
   21126 let accessSize = HalfWordAccess;
   21127 let isNVStore = 1;
   21128 let isNewValue = 1;
   21129 let isRestrictNoSlot1Store = 1;
   21130 let mayStore = 1;
   21131 let Uses = [CS];
   21132 let BaseOpcode = "S2_storerh_pcr";
   21133 let opNewValue = 3;
   21134 let Constraints = "$Rx32 = $Rx32in";
   21135 }
   21136 def S2_storerhnew_pi : HInst<
   21137 (outs IntRegs:$Rx32),
   21138 (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
   21139 "memh($Rx32++#$Ii) = $Nt8.new",
   21140 tc_e7d02c66, TypeST>, Enc_e26546, AddrModeRel {
   21141 let Inst{2-0} = 0b000;
   21142 let Inst{7-7} = 0b0;
   21143 let Inst{13-11} = 0b001;
   21144 let Inst{31-21} = 0b10101011101;
   21145 let addrMode = PostInc;
   21146 let accessSize = HalfWordAccess;
   21147 let isNVStore = 1;
   21148 let isNewValue = 1;
   21149 let isRestrictNoSlot1Store = 1;
   21150 let mayStore = 1;
   21151 let BaseOpcode = "S2_storerh_pi";
   21152 let isNVStorable = 1;
   21153 let isPredicable = 1;
   21154 let opNewValue = 3;
   21155 let Constraints = "$Rx32 = $Rx32in";
   21156 }
   21157 def S2_storerhnew_pr : HInst<
   21158 (outs IntRegs:$Rx32),
   21159 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21160 "memh($Rx32++$Mu2) = $Nt8.new",
   21161 tc_e7d02c66, TypeST>, Enc_8dbe85 {
   21162 let Inst{7-0} = 0b00000000;
   21163 let Inst{12-11} = 0b01;
   21164 let Inst{31-21} = 0b10101101101;
   21165 let addrMode = PostInc;
   21166 let accessSize = HalfWordAccess;
   21167 let isNVStore = 1;
   21168 let isNewValue = 1;
   21169 let isRestrictNoSlot1Store = 1;
   21170 let mayStore = 1;
   21171 let opNewValue = 3;
   21172 let Constraints = "$Rx32 = $Rx32in";
   21173 }
   21174 def S2_storerhnew_zomap : HInst<
   21175 (outs),
   21176 (ins IntRegs:$Rs32, IntRegs:$Nt8),
   21177 "memh($Rs32) = $Nt8.new",
   21178 tc_f7dd9c9f, TypeMAPPING> {
   21179 let isPseudo = 1;
   21180 let isCodeGenOnly = 1;
   21181 let opNewValue = 1;
   21182 }
   21183 def S2_storerhnewgp : HInst<
   21184 (outs),
   21185 (ins u31_1Imm:$Ii, IntRegs:$Nt8),
   21186 "memh(gp+#$Ii) = $Nt8.new",
   21187 tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
   21188 let Inst{12-11} = 0b01;
   21189 let Inst{24-21} = 0b0101;
   21190 let Inst{31-27} = 0b01001;
   21191 let accessSize = HalfWordAccess;
   21192 let isNVStore = 1;
   21193 let isNewValue = 1;
   21194 let isRestrictNoSlot1Store = 1;
   21195 let mayStore = 1;
   21196 let Uses = [GP];
   21197 let BaseOpcode = "S2_storerhabs";
   21198 let isPredicable = 1;
   21199 let opExtendable = 0;
   21200 let isExtentSigned = 0;
   21201 let opExtentBits = 17;
   21202 let opExtentAlign = 1;
   21203 let opNewValue = 1;
   21204 }
   21205 def S2_storeri_io : HInst<
   21206 (outs),
   21207 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
   21208 "memw($Rs32+#$Ii) = $Rt32",
   21209 tc_05b6c987, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
   21210 let Inst{24-21} = 0b1100;
   21211 let Inst{31-27} = 0b10100;
   21212 let addrMode = BaseImmOffset;
   21213 let accessSize = WordAccess;
   21214 let mayStore = 1;
   21215 let CextOpcode = "S2_storeri";
   21216 let InputType = "imm";
   21217 let BaseOpcode = "S2_storeri_io";
   21218 let isPredicable = 1;
   21219 let isNVStorable = 1;
   21220 let isExtendable = 1;
   21221 let opExtendable = 1;
   21222 let isExtentSigned = 1;
   21223 let opExtentBits = 13;
   21224 let opExtentAlign = 2;
   21225 }
   21226 def S2_storeri_pbr : HInst<
   21227 (outs IntRegs:$Rx32),
   21228 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   21229 "memw($Rx32++$Mu2:brev) = $Rt32",
   21230 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   21231 let Inst{7-0} = 0b00000000;
   21232 let Inst{31-21} = 0b10101111100;
   21233 let accessSize = WordAccess;
   21234 let mayStore = 1;
   21235 let BaseOpcode = "S2_storeri_pbr";
   21236 let isNVStorable = 1;
   21237 let Constraints = "$Rx32 = $Rx32in";
   21238 }
   21239 def S2_storeri_pci : HInst<
   21240 (outs IntRegs:$Rx32),
   21241 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
   21242 "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
   21243 tc_9fdb5406, TypeST>, Enc_79b8c8, AddrModeRel {
   21244 let Inst{2-0} = 0b000;
   21245 let Inst{7-7} = 0b0;
   21246 let Inst{31-21} = 0b10101001100;
   21247 let addrMode = PostInc;
   21248 let accessSize = WordAccess;
   21249 let mayStore = 1;
   21250 let Uses = [CS];
   21251 let BaseOpcode = "S2_storeri_pci";
   21252 let isNVStorable = 1;
   21253 let Constraints = "$Rx32 = $Rx32in";
   21254 }
   21255 def S2_storeri_pcr : HInst<
   21256 (outs IntRegs:$Rx32),
   21257 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   21258 "memw($Rx32++I:circ($Mu2)) = $Rt32",
   21259 tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel {
   21260 let Inst{7-0} = 0b00000010;
   21261 let Inst{31-21} = 0b10101001100;
   21262 let addrMode = PostInc;
   21263 let accessSize = WordAccess;
   21264 let mayStore = 1;
   21265 let Uses = [CS];
   21266 let BaseOpcode = "S2_storeri_pcr";
   21267 let isNVStorable = 1;
   21268 let Constraints = "$Rx32 = $Rx32in";
   21269 }
   21270 def S2_storeri_pi : HInst<
   21271 (outs IntRegs:$Rx32),
   21272 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
   21273 "memw($Rx32++#$Ii) = $Rt32",
   21274 tc_f86c328a, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
   21275 let Inst{2-0} = 0b000;
   21276 let Inst{7-7} = 0b0;
   21277 let Inst{13-13} = 0b0;
   21278 let Inst{31-21} = 0b10101011100;
   21279 let addrMode = PostInc;
   21280 let accessSize = WordAccess;
   21281 let mayStore = 1;
   21282 let CextOpcode = "S2_storeri";
   21283 let BaseOpcode = "S2_storeri_pi";
   21284 let isPredicable = 1;
   21285 let isNVStorable = 1;
   21286 let Constraints = "$Rx32 = $Rx32in";
   21287 }
   21288 def S2_storeri_pr : HInst<
   21289 (outs IntRegs:$Rx32),
   21290 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
   21291 "memw($Rx32++$Mu2) = $Rt32",
   21292 tc_f86c328a, TypeST>, Enc_d5c73f {
   21293 let Inst{7-0} = 0b00000000;
   21294 let Inst{31-21} = 0b10101101100;
   21295 let addrMode = PostInc;
   21296 let accessSize = WordAccess;
   21297 let mayStore = 1;
   21298 let isNVStorable = 1;
   21299 let Constraints = "$Rx32 = $Rx32in";
   21300 }
   21301 def S2_storeri_zomap : HInst<
   21302 (outs),
   21303 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   21304 "memw($Rs32) = $Rt32",
   21305 tc_05b6c987, TypeMAPPING> {
   21306 let isPseudo = 1;
   21307 let isCodeGenOnly = 1;
   21308 }
   21309 def S2_storerigp : HInst<
   21310 (outs),
   21311 (ins u30_2Imm:$Ii, IntRegs:$Rt32),
   21312 "memw(gp+#$Ii) = $Rt32",
   21313 tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel {
   21314 let Inst{24-21} = 0b0100;
   21315 let Inst{31-27} = 0b01001;
   21316 let accessSize = WordAccess;
   21317 let mayStore = 1;
   21318 let Uses = [GP];
   21319 let BaseOpcode = "S2_storeriabs";
   21320 let isPredicable = 1;
   21321 let isNVStorable = 1;
   21322 let opExtendable = 0;
   21323 let isExtentSigned = 0;
   21324 let opExtentBits = 18;
   21325 let opExtentAlign = 2;
   21326 }
   21327 def S2_storerinew_io : HInst<
   21328 (outs),
   21329 (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
   21330 "memw($Rs32+#$Ii) = $Nt8.new",
   21331 tc_f7dd9c9f, TypeST>, Enc_690862, AddrModeRel {
   21332 let Inst{12-11} = 0b10;
   21333 let Inst{24-21} = 0b1101;
   21334 let Inst{31-27} = 0b10100;
   21335 let addrMode = BaseImmOffset;
   21336 let accessSize = WordAccess;
   21337 let isNVStore = 1;
   21338 let isNewValue = 1;
   21339 let isRestrictNoSlot1Store = 1;
   21340 let mayStore = 1;
   21341 let CextOpcode = "S2_storeri";
   21342 let InputType = "imm";
   21343 let BaseOpcode = "S2_storeri_io";
   21344 let isPredicable = 1;
   21345 let isExtendable = 1;
   21346 let opExtendable = 1;
   21347 let isExtentSigned = 1;
   21348 let opExtentBits = 13;
   21349 let opExtentAlign = 2;
   21350 let opNewValue = 2;
   21351 }
   21352 def S2_storerinew_pbr : HInst<
   21353 (outs IntRegs:$Rx32),
   21354 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21355 "memw($Rx32++$Mu2:brev) = $Nt8.new",
   21356 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   21357 let Inst{7-0} = 0b00000000;
   21358 let Inst{12-11} = 0b10;
   21359 let Inst{31-21} = 0b10101111101;
   21360 let accessSize = WordAccess;
   21361 let isNVStore = 1;
   21362 let isNewValue = 1;
   21363 let isRestrictNoSlot1Store = 1;
   21364 let mayStore = 1;
   21365 let BaseOpcode = "S2_storeri_pbr";
   21366 let opNewValue = 3;
   21367 let Constraints = "$Rx32 = $Rx32in";
   21368 }
   21369 def S2_storerinew_pci : HInst<
   21370 (outs IntRegs:$Rx32),
   21371 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
   21372 "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
   21373 tc_9d5941c7, TypeST>, Enc_3f97c8, AddrModeRel {
   21374 let Inst{2-0} = 0b000;
   21375 let Inst{7-7} = 0b0;
   21376 let Inst{12-11} = 0b10;
   21377 let Inst{31-21} = 0b10101001101;
   21378 let addrMode = PostInc;
   21379 let accessSize = WordAccess;
   21380 let isNVStore = 1;
   21381 let isNewValue = 1;
   21382 let isRestrictNoSlot1Store = 1;
   21383 let mayStore = 1;
   21384 let Uses = [CS];
   21385 let BaseOpcode = "S2_storeri_pci";
   21386 let opNewValue = 4;
   21387 let Constraints = "$Rx32 = $Rx32in";
   21388 }
   21389 def S2_storerinew_pcr : HInst<
   21390 (outs IntRegs:$Rx32),
   21391 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21392 "memw($Rx32++I:circ($Mu2)) = $Nt8.new",
   21393 tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel {
   21394 let Inst{7-0} = 0b00000010;
   21395 let Inst{12-11} = 0b10;
   21396 let Inst{31-21} = 0b10101001101;
   21397 let addrMode = PostInc;
   21398 let accessSize = WordAccess;
   21399 let isNVStore = 1;
   21400 let isNewValue = 1;
   21401 let isRestrictNoSlot1Store = 1;
   21402 let mayStore = 1;
   21403 let Uses = [CS];
   21404 let BaseOpcode = "S2_storeri_pcr";
   21405 let opNewValue = 3;
   21406 let Constraints = "$Rx32 = $Rx32in";
   21407 }
   21408 def S2_storerinew_pi : HInst<
   21409 (outs IntRegs:$Rx32),
   21410 (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
   21411 "memw($Rx32++#$Ii) = $Nt8.new",
   21412 tc_e7d02c66, TypeST>, Enc_223005, AddrModeRel {
   21413 let Inst{2-0} = 0b000;
   21414 let Inst{7-7} = 0b0;
   21415 let Inst{13-11} = 0b010;
   21416 let Inst{31-21} = 0b10101011101;
   21417 let addrMode = PostInc;
   21418 let accessSize = WordAccess;
   21419 let isNVStore = 1;
   21420 let isNewValue = 1;
   21421 let isRestrictNoSlot1Store = 1;
   21422 let mayStore = 1;
   21423 let BaseOpcode = "S2_storeri_pi";
   21424 let isPredicable = 1;
   21425 let opNewValue = 3;
   21426 let Constraints = "$Rx32 = $Rx32in";
   21427 }
   21428 def S2_storerinew_pr : HInst<
   21429 (outs IntRegs:$Rx32),
   21430 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
   21431 "memw($Rx32++$Mu2) = $Nt8.new",
   21432 tc_e7d02c66, TypeST>, Enc_8dbe85 {
   21433 let Inst{7-0} = 0b00000000;
   21434 let Inst{12-11} = 0b10;
   21435 let Inst{31-21} = 0b10101101101;
   21436 let addrMode = PostInc;
   21437 let accessSize = WordAccess;
   21438 let isNVStore = 1;
   21439 let isNewValue = 1;
   21440 let isRestrictNoSlot1Store = 1;
   21441 let mayStore = 1;
   21442 let opNewValue = 3;
   21443 let Constraints = "$Rx32 = $Rx32in";
   21444 }
   21445 def S2_storerinew_zomap : HInst<
   21446 (outs),
   21447 (ins IntRegs:$Rs32, IntRegs:$Nt8),
   21448 "memw($Rs32) = $Nt8.new",
   21449 tc_f7dd9c9f, TypeMAPPING> {
   21450 let isPseudo = 1;
   21451 let isCodeGenOnly = 1;
   21452 let opNewValue = 1;
   21453 }
   21454 def S2_storerinewgp : HInst<
   21455 (outs),
   21456 (ins u30_2Imm:$Ii, IntRegs:$Nt8),
   21457 "memw(gp+#$Ii) = $Nt8.new",
   21458 tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
   21459 let Inst{12-11} = 0b10;
   21460 let Inst{24-21} = 0b0101;
   21461 let Inst{31-27} = 0b01001;
   21462 let accessSize = WordAccess;
   21463 let isNVStore = 1;
   21464 let isNewValue = 1;
   21465 let isRestrictNoSlot1Store = 1;
   21466 let mayStore = 1;
   21467 let Uses = [GP];
   21468 let BaseOpcode = "S2_storeriabs";
   21469 let isPredicable = 1;
   21470 let opExtendable = 0;
   21471 let isExtentSigned = 0;
   21472 let opExtentBits = 18;
   21473 let opExtentAlign = 2;
   21474 let opNewValue = 1;
   21475 }
   21476 def S2_storew_locked : HInst<
   21477 (outs PredRegs:$Pd4),
   21478 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   21479 "memw_locked($Rs32,$Pd4) = $Rt32",
   21480 tc_1372bca1, TypeST>, Enc_c2b48e {
   21481 let Inst{7-2} = 0b000000;
   21482 let Inst{13-13} = 0b0;
   21483 let Inst{31-21} = 0b10100000101;
   21484 let accessSize = WordAccess;
   21485 let isPredicateLate = 1;
   21486 let isSoloAX = 1;
   21487 let mayStore = 1;
   21488 }
   21489 def S2_svsathb : HInst<
   21490 (outs IntRegs:$Rd32),
   21491 (ins IntRegs:$Rs32),
   21492 "$Rd32 = vsathb($Rs32)",
   21493 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   21494 let Inst{13-5} = 0b000000000;
   21495 let Inst{31-21} = 0b10001100100;
   21496 let hasNewValue = 1;
   21497 let opNewValue = 0;
   21498 let Defs = [USR_OVF];
   21499 }
   21500 def S2_svsathub : HInst<
   21501 (outs IntRegs:$Rd32),
   21502 (ins IntRegs:$Rs32),
   21503 "$Rd32 = vsathub($Rs32)",
   21504 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   21505 let Inst{13-5} = 0b000000010;
   21506 let Inst{31-21} = 0b10001100100;
   21507 let hasNewValue = 1;
   21508 let opNewValue = 0;
   21509 let Defs = [USR_OVF];
   21510 }
   21511 def S2_tableidxb : HInst<
   21512 (outs IntRegs:$Rx32),
   21513 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
   21514 "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
   21515 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
   21516 let Inst{31-22} = 0b1000011100;
   21517 let hasNewValue = 1;
   21518 let opNewValue = 0;
   21519 let prefersSlot3 = 1;
   21520 let Constraints = "$Rx32 = $Rx32in";
   21521 }
   21522 def S2_tableidxb_goodsyntax : HInst<
   21523 (outs IntRegs:$Rx32),
   21524 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
   21525 "$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
   21526 tc_87735c3b, TypeS_2op> {
   21527 let hasNewValue = 1;
   21528 let opNewValue = 0;
   21529 let isPseudo = 1;
   21530 let isCodeGenOnly = 1;
   21531 let Constraints = "$Rx32 = $Rx32in";
   21532 }
   21533 def S2_tableidxd : HInst<
   21534 (outs IntRegs:$Rx32),
   21535 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
   21536 "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
   21537 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
   21538 let Inst{31-22} = 0b1000011111;
   21539 let hasNewValue = 1;
   21540 let opNewValue = 0;
   21541 let prefersSlot3 = 1;
   21542 let Constraints = "$Rx32 = $Rx32in";
   21543 }
   21544 def S2_tableidxd_goodsyntax : HInst<
   21545 (outs IntRegs:$Rx32),
   21546 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
   21547 "$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
   21548 tc_87735c3b, TypeS_2op> {
   21549 let hasNewValue = 1;
   21550 let opNewValue = 0;
   21551 let isPseudo = 1;
   21552 let Constraints = "$Rx32 = $Rx32in";
   21553 }
   21554 def S2_tableidxh : HInst<
   21555 (outs IntRegs:$Rx32),
   21556 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
   21557 "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
   21558 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
   21559 let Inst{31-22} = 0b1000011101;
   21560 let hasNewValue = 1;
   21561 let opNewValue = 0;
   21562 let prefersSlot3 = 1;
   21563 let Constraints = "$Rx32 = $Rx32in";
   21564 }
   21565 def S2_tableidxh_goodsyntax : HInst<
   21566 (outs IntRegs:$Rx32),
   21567 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
   21568 "$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
   21569 tc_87735c3b, TypeS_2op> {
   21570 let hasNewValue = 1;
   21571 let opNewValue = 0;
   21572 let isPseudo = 1;
   21573 let Constraints = "$Rx32 = $Rx32in";
   21574 }
   21575 def S2_tableidxw : HInst<
   21576 (outs IntRegs:$Rx32),
   21577 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
   21578 "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
   21579 tc_87735c3b, TypeS_2op>, Enc_cd82bc {
   21580 let Inst{31-22} = 0b1000011110;
   21581 let hasNewValue = 1;
   21582 let opNewValue = 0;
   21583 let prefersSlot3 = 1;
   21584 let Constraints = "$Rx32 = $Rx32in";
   21585 }
   21586 def S2_tableidxw_goodsyntax : HInst<
   21587 (outs IntRegs:$Rx32),
   21588 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
   21589 "$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
   21590 tc_87735c3b, TypeS_2op> {
   21591 let hasNewValue = 1;
   21592 let opNewValue = 0;
   21593 let isPseudo = 1;
   21594 let Constraints = "$Rx32 = $Rx32in";
   21595 }
   21596 def S2_togglebit_i : HInst<
   21597 (outs IntRegs:$Rd32),
   21598 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   21599 "$Rd32 = togglebit($Rs32,#$Ii)",
   21600 tc_540fdfbc, TypeS_2op>, Enc_a05677 {
   21601 let Inst{7-5} = 0b010;
   21602 let Inst{13-13} = 0b0;
   21603 let Inst{31-21} = 0b10001100110;
   21604 let hasNewValue = 1;
   21605 let opNewValue = 0;
   21606 }
   21607 def S2_togglebit_r : HInst<
   21608 (outs IntRegs:$Rd32),
   21609 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   21610 "$Rd32 = togglebit($Rs32,$Rt32)",
   21611 tc_540fdfbc, TypeS_3op>, Enc_5ab2be {
   21612 let Inst{7-5} = 0b100;
   21613 let Inst{13-13} = 0b0;
   21614 let Inst{31-21} = 0b11000110100;
   21615 let hasNewValue = 1;
   21616 let opNewValue = 0;
   21617 }
   21618 def S2_tstbit_i : HInst<
   21619 (outs PredRegs:$Pd4),
   21620 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   21621 "$Pd4 = tstbit($Rs32,#$Ii)",
   21622 tc_7a830544, TypeS_2op>, Enc_83ee64 {
   21623 let Inst{7-2} = 0b000000;
   21624 let Inst{13-13} = 0b0;
   21625 let Inst{31-21} = 0b10000101000;
   21626 }
   21627 def S2_tstbit_r : HInst<
   21628 (outs PredRegs:$Pd4),
   21629 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   21630 "$Pd4 = tstbit($Rs32,$Rt32)",
   21631 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   21632 let Inst{7-2} = 0b000000;
   21633 let Inst{13-13} = 0b0;
   21634 let Inst{31-21} = 0b11000111000;
   21635 }
   21636 def S2_valignib : HInst<
   21637 (outs DoubleRegs:$Rdd32),
   21638 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
   21639 "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
   21640 tc_f8eeed7a, TypeS_3op>, Enc_729ff7 {
   21641 let Inst{13-13} = 0b0;
   21642 let Inst{31-21} = 0b11000000000;
   21643 }
   21644 def S2_valignrb : HInst<
   21645 (outs DoubleRegs:$Rdd32),
   21646 (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
   21647 "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
   21648 tc_f8eeed7a, TypeS_3op>, Enc_8c6530 {
   21649 let Inst{7-7} = 0b0;
   21650 let Inst{13-13} = 0b0;
   21651 let Inst{31-21} = 0b11000010000;
   21652 }
   21653 def S2_vcnegh : HInst<
   21654 (outs DoubleRegs:$Rdd32),
   21655 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   21656 "$Rdd32 = vcnegh($Rss32,$Rt32)",
   21657 tc_b44c6e2a, TypeS_3op>, Enc_927852 {
   21658 let Inst{7-5} = 0b010;
   21659 let Inst{13-13} = 0b0;
   21660 let Inst{31-21} = 0b11000011110;
   21661 let prefersSlot3 = 1;
   21662 let Defs = [USR_OVF];
   21663 }
   21664 def S2_vcrotate : HInst<
   21665 (outs DoubleRegs:$Rdd32),
   21666 (ins DoubleRegs:$Rss32, IntRegs:$Rt32),
   21667 "$Rdd32 = vcrotate($Rss32,$Rt32)",
   21668 tc_2b6f77c6, TypeS_3op>, Enc_927852 {
   21669 let Inst{7-5} = 0b000;
   21670 let Inst{13-13} = 0b0;
   21671 let Inst{31-21} = 0b11000011110;
   21672 let prefersSlot3 = 1;
   21673 let Defs = [USR_OVF];
   21674 }
   21675 def S2_vrcnegh : HInst<
   21676 (outs DoubleRegs:$Rxx32),
   21677 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
   21678 "$Rxx32 += vrcnegh($Rss32,$Rt32)",
   21679 tc_e913dc32, TypeS_3op>, Enc_1aa186 {
   21680 let Inst{7-5} = 0b111;
   21681 let Inst{13-13} = 0b1;
   21682 let Inst{31-21} = 0b11001011001;
   21683 let prefersSlot3 = 1;
   21684 let Constraints = "$Rxx32 = $Rxx32in";
   21685 }
   21686 def S2_vrndpackwh : HInst<
   21687 (outs IntRegs:$Rd32),
   21688 (ins DoubleRegs:$Rss32),
   21689 "$Rd32 = vrndwh($Rss32)",
   21690 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   21691 let Inst{13-5} = 0b000000100;
   21692 let Inst{31-21} = 0b10001000100;
   21693 let hasNewValue = 1;
   21694 let opNewValue = 0;
   21695 let prefersSlot3 = 1;
   21696 }
   21697 def S2_vrndpackwhs : HInst<
   21698 (outs IntRegs:$Rd32),
   21699 (ins DoubleRegs:$Rss32),
   21700 "$Rd32 = vrndwh($Rss32):sat",
   21701 tc_c2f7d806, TypeS_2op>, Enc_90cd8b {
   21702 let Inst{13-5} = 0b000000110;
   21703 let Inst{31-21} = 0b10001000100;
   21704 let hasNewValue = 1;
   21705 let opNewValue = 0;
   21706 let prefersSlot3 = 1;
   21707 let Defs = [USR_OVF];
   21708 }
   21709 def S2_vsathb : HInst<
   21710 (outs IntRegs:$Rd32),
   21711 (ins DoubleRegs:$Rss32),
   21712 "$Rd32 = vsathb($Rss32)",
   21713 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21714 let Inst{13-5} = 0b000000110;
   21715 let Inst{31-21} = 0b10001000000;
   21716 let hasNewValue = 1;
   21717 let opNewValue = 0;
   21718 let Defs = [USR_OVF];
   21719 }
   21720 def S2_vsathb_nopack : HInst<
   21721 (outs DoubleRegs:$Rdd32),
   21722 (ins DoubleRegs:$Rss32),
   21723 "$Rdd32 = vsathb($Rss32)",
   21724 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
   21725 let Inst{13-5} = 0b000000111;
   21726 let Inst{31-21} = 0b10000000000;
   21727 let Defs = [USR_OVF];
   21728 }
   21729 def S2_vsathub : HInst<
   21730 (outs IntRegs:$Rd32),
   21731 (ins DoubleRegs:$Rss32),
   21732 "$Rd32 = vsathub($Rss32)",
   21733 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21734 let Inst{13-5} = 0b000000000;
   21735 let Inst{31-21} = 0b10001000000;
   21736 let hasNewValue = 1;
   21737 let opNewValue = 0;
   21738 let Defs = [USR_OVF];
   21739 }
   21740 def S2_vsathub_nopack : HInst<
   21741 (outs DoubleRegs:$Rdd32),
   21742 (ins DoubleRegs:$Rss32),
   21743 "$Rdd32 = vsathub($Rss32)",
   21744 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
   21745 let Inst{13-5} = 0b000000100;
   21746 let Inst{31-21} = 0b10000000000;
   21747 let Defs = [USR_OVF];
   21748 }
   21749 def S2_vsatwh : HInst<
   21750 (outs IntRegs:$Rd32),
   21751 (ins DoubleRegs:$Rss32),
   21752 "$Rd32 = vsatwh($Rss32)",
   21753 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21754 let Inst{13-5} = 0b000000010;
   21755 let Inst{31-21} = 0b10001000000;
   21756 let hasNewValue = 1;
   21757 let opNewValue = 0;
   21758 let Defs = [USR_OVF];
   21759 }
   21760 def S2_vsatwh_nopack : HInst<
   21761 (outs DoubleRegs:$Rdd32),
   21762 (ins DoubleRegs:$Rss32),
   21763 "$Rdd32 = vsatwh($Rss32)",
   21764 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
   21765 let Inst{13-5} = 0b000000110;
   21766 let Inst{31-21} = 0b10000000000;
   21767 let Defs = [USR_OVF];
   21768 }
   21769 def S2_vsatwuh : HInst<
   21770 (outs IntRegs:$Rd32),
   21771 (ins DoubleRegs:$Rss32),
   21772 "$Rd32 = vsatwuh($Rss32)",
   21773 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21774 let Inst{13-5} = 0b000000100;
   21775 let Inst{31-21} = 0b10001000000;
   21776 let hasNewValue = 1;
   21777 let opNewValue = 0;
   21778 let Defs = [USR_OVF];
   21779 }
   21780 def S2_vsatwuh_nopack : HInst<
   21781 (outs DoubleRegs:$Rdd32),
   21782 (ins DoubleRegs:$Rss32),
   21783 "$Rdd32 = vsatwuh($Rss32)",
   21784 tc_cde8b071, TypeS_2op>, Enc_b9c5fb {
   21785 let Inst{13-5} = 0b000000101;
   21786 let Inst{31-21} = 0b10000000000;
   21787 let Defs = [USR_OVF];
   21788 }
   21789 def S2_vsplatrb : HInst<
   21790 (outs IntRegs:$Rd32),
   21791 (ins IntRegs:$Rs32),
   21792 "$Rd32 = vsplatb($Rs32)",
   21793 tc_cde8b071, TypeS_2op>, Enc_5e2823 {
   21794 let Inst{13-5} = 0b000000111;
   21795 let Inst{31-21} = 0b10001100010;
   21796 let hasNewValue = 1;
   21797 let opNewValue = 0;
   21798 let isReMaterializable = 1;
   21799 let isAsCheapAsAMove = 1;
   21800 }
   21801 def S2_vsplatrh : HInst<
   21802 (outs DoubleRegs:$Rdd32),
   21803 (ins IntRegs:$Rs32),
   21804 "$Rdd32 = vsplath($Rs32)",
   21805 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   21806 let Inst{13-5} = 0b000000010;
   21807 let Inst{31-21} = 0b10000100010;
   21808 let isReMaterializable = 1;
   21809 let isAsCheapAsAMove = 1;
   21810 }
   21811 def S2_vspliceib : HInst<
   21812 (outs DoubleRegs:$Rdd32),
   21813 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
   21814 "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
   21815 tc_f8eeed7a, TypeS_3op>, Enc_d50cd3 {
   21816 let Inst{13-13} = 0b0;
   21817 let Inst{31-21} = 0b11000000100;
   21818 }
   21819 def S2_vsplicerb : HInst<
   21820 (outs DoubleRegs:$Rdd32),
   21821 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
   21822 "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
   21823 tc_f8eeed7a, TypeS_3op>, Enc_dbd70c {
   21824 let Inst{7-7} = 0b0;
   21825 let Inst{13-13} = 0b0;
   21826 let Inst{31-21} = 0b11000010100;
   21827 }
   21828 def S2_vsxtbh : HInst<
   21829 (outs DoubleRegs:$Rdd32),
   21830 (ins IntRegs:$Rs32),
   21831 "$Rdd32 = vsxtbh($Rs32)",
   21832 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   21833 let Inst{13-5} = 0b000000000;
   21834 let Inst{31-21} = 0b10000100000;
   21835 let isReMaterializable = 1;
   21836 let isAsCheapAsAMove = 1;
   21837 }
   21838 def S2_vsxthw : HInst<
   21839 (outs DoubleRegs:$Rdd32),
   21840 (ins IntRegs:$Rs32),
   21841 "$Rdd32 = vsxthw($Rs32)",
   21842 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   21843 let Inst{13-5} = 0b000000100;
   21844 let Inst{31-21} = 0b10000100000;
   21845 let isReMaterializable = 1;
   21846 let isAsCheapAsAMove = 1;
   21847 }
   21848 def S2_vtrunehb : HInst<
   21849 (outs IntRegs:$Rd32),
   21850 (ins DoubleRegs:$Rss32),
   21851 "$Rd32 = vtrunehb($Rss32)",
   21852 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21853 let Inst{13-5} = 0b000000010;
   21854 let Inst{31-21} = 0b10001000100;
   21855 let hasNewValue = 1;
   21856 let opNewValue = 0;
   21857 }
   21858 def S2_vtrunewh : HInst<
   21859 (outs DoubleRegs:$Rdd32),
   21860 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   21861 "$Rdd32 = vtrunewh($Rss32,$Rtt32)",
   21862 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
   21863 let Inst{7-5} = 0b010;
   21864 let Inst{13-13} = 0b0;
   21865 let Inst{31-21} = 0b11000001100;
   21866 }
   21867 def S2_vtrunohb : HInst<
   21868 (outs IntRegs:$Rd32),
   21869 (ins DoubleRegs:$Rss32),
   21870 "$Rd32 = vtrunohb($Rss32)",
   21871 tc_cde8b071, TypeS_2op>, Enc_90cd8b {
   21872 let Inst{13-5} = 0b000000000;
   21873 let Inst{31-21} = 0b10001000100;
   21874 let hasNewValue = 1;
   21875 let opNewValue = 0;
   21876 }
   21877 def S2_vtrunowh : HInst<
   21878 (outs DoubleRegs:$Rdd32),
   21879 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   21880 "$Rdd32 = vtrunowh($Rss32,$Rtt32)",
   21881 tc_540fdfbc, TypeS_3op>, Enc_a56825 {
   21882 let Inst{7-5} = 0b100;
   21883 let Inst{13-13} = 0b0;
   21884 let Inst{31-21} = 0b11000001100;
   21885 }
   21886 def S2_vzxtbh : HInst<
   21887 (outs DoubleRegs:$Rdd32),
   21888 (ins IntRegs:$Rs32),
   21889 "$Rdd32 = vzxtbh($Rs32)",
   21890 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   21891 let Inst{13-5} = 0b000000010;
   21892 let Inst{31-21} = 0b10000100000;
   21893 let isReMaterializable = 1;
   21894 let isAsCheapAsAMove = 1;
   21895 }
   21896 def S2_vzxthw : HInst<
   21897 (outs DoubleRegs:$Rdd32),
   21898 (ins IntRegs:$Rs32),
   21899 "$Rdd32 = vzxthw($Rs32)",
   21900 tc_cde8b071, TypeS_2op>, Enc_3a3d62 {
   21901 let Inst{13-5} = 0b000000110;
   21902 let Inst{31-21} = 0b10000100000;
   21903 let isReMaterializable = 1;
   21904 let isAsCheapAsAMove = 1;
   21905 }
   21906 def S4_addaddi : HInst<
   21907 (outs IntRegs:$Rd32),
   21908 (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
   21909 "$Rd32 = add($Rs32,add($Ru32,#$Ii))",
   21910 tc_c74f796f, TypeALU64>, Enc_8b8d61 {
   21911 let Inst{31-23} = 0b110110110;
   21912 let hasNewValue = 1;
   21913 let opNewValue = 0;
   21914 let prefersSlot3 = 1;
   21915 let isExtendable = 1;
   21916 let opExtendable = 3;
   21917 let isExtentSigned = 1;
   21918 let opExtentBits = 6;
   21919 let opExtentAlign = 0;
   21920 }
   21921 def S4_addi_asl_ri : HInst<
   21922 (outs IntRegs:$Rx32),
   21923 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   21924 "$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
   21925 tc_c74f796f, TypeALU64>, Enc_c31910 {
   21926 let Inst{2-0} = 0b100;
   21927 let Inst{4-4} = 0b0;
   21928 let Inst{31-24} = 0b11011110;
   21929 let hasNewValue = 1;
   21930 let opNewValue = 0;
   21931 let prefersSlot3 = 1;
   21932 let isExtendable = 1;
   21933 let opExtendable = 1;
   21934 let isExtentSigned = 0;
   21935 let opExtentBits = 8;
   21936 let opExtentAlign = 0;
   21937 let Constraints = "$Rx32 = $Rx32in";
   21938 }
   21939 def S4_addi_lsr_ri : HInst<
   21940 (outs IntRegs:$Rx32),
   21941 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   21942 "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
   21943 tc_c74f796f, TypeALU64>, Enc_c31910 {
   21944 let Inst{2-0} = 0b100;
   21945 let Inst{4-4} = 0b1;
   21946 let Inst{31-24} = 0b11011110;
   21947 let hasNewValue = 1;
   21948 let opNewValue = 0;
   21949 let prefersSlot3 = 1;
   21950 let isExtendable = 1;
   21951 let opExtendable = 1;
   21952 let isExtentSigned = 0;
   21953 let opExtentBits = 8;
   21954 let opExtentAlign = 0;
   21955 let Constraints = "$Rx32 = $Rx32in";
   21956 }
   21957 def S4_andi_asl_ri : HInst<
   21958 (outs IntRegs:$Rx32),
   21959 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   21960 "$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
   21961 tc_84df2cd3, TypeALU64>, Enc_c31910 {
   21962 let Inst{2-0} = 0b000;
   21963 let Inst{4-4} = 0b0;
   21964 let Inst{31-24} = 0b11011110;
   21965 let hasNewValue = 1;
   21966 let opNewValue = 0;
   21967 let prefersSlot3 = 1;
   21968 let isExtendable = 1;
   21969 let opExtendable = 1;
   21970 let isExtentSigned = 0;
   21971 let opExtentBits = 8;
   21972 let opExtentAlign = 0;
   21973 let Constraints = "$Rx32 = $Rx32in";
   21974 }
   21975 def S4_andi_lsr_ri : HInst<
   21976 (outs IntRegs:$Rx32),
   21977 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   21978 "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
   21979 tc_84df2cd3, TypeALU64>, Enc_c31910 {
   21980 let Inst{2-0} = 0b000;
   21981 let Inst{4-4} = 0b1;
   21982 let Inst{31-24} = 0b11011110;
   21983 let hasNewValue = 1;
   21984 let opNewValue = 0;
   21985 let prefersSlot3 = 1;
   21986 let isExtendable = 1;
   21987 let opExtendable = 1;
   21988 let isExtentSigned = 0;
   21989 let opExtentBits = 8;
   21990 let opExtentAlign = 0;
   21991 let Constraints = "$Rx32 = $Rx32in";
   21992 }
   21993 def S4_clbaddi : HInst<
   21994 (outs IntRegs:$Rd32),
   21995 (ins IntRegs:$Rs32, s6_0Imm:$Ii),
   21996 "$Rd32 = add(clb($Rs32),#$Ii)",
   21997 tc_2b6f77c6, TypeS_2op>, Enc_9fae8a {
   21998 let Inst{7-5} = 0b000;
   21999 let Inst{31-21} = 0b10001100001;
   22000 let hasNewValue = 1;
   22001 let opNewValue = 0;
   22002 let prefersSlot3 = 1;
   22003 }
   22004 def S4_clbpaddi : HInst<
   22005 (outs IntRegs:$Rd32),
   22006 (ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
   22007 "$Rd32 = add(clb($Rss32),#$Ii)",
   22008 tc_2b6f77c6, TypeS_2op>, Enc_a1640c {
   22009 let Inst{7-5} = 0b010;
   22010 let Inst{31-21} = 0b10001000011;
   22011 let hasNewValue = 1;
   22012 let opNewValue = 0;
   22013 let prefersSlot3 = 1;
   22014 }
   22015 def S4_clbpnorm : HInst<
   22016 (outs IntRegs:$Rd32),
   22017 (ins DoubleRegs:$Rss32),
   22018 "$Rd32 = normamt($Rss32)",
   22019 tc_d088982c, TypeS_2op>, Enc_90cd8b {
   22020 let Inst{13-5} = 0b000000000;
   22021 let Inst{31-21} = 0b10001000011;
   22022 let hasNewValue = 1;
   22023 let opNewValue = 0;
   22024 let prefersSlot3 = 1;
   22025 }
   22026 def S4_extract : HInst<
   22027 (outs IntRegs:$Rd32),
   22028 (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
   22029 "$Rd32 = extract($Rs32,#$Ii,#$II)",
   22030 tc_c74f796f, TypeS_2op>, Enc_b388cf {
   22031 let Inst{13-13} = 0b0;
   22032 let Inst{31-23} = 0b100011011;
   22033 let hasNewValue = 1;
   22034 let opNewValue = 0;
   22035 let prefersSlot3 = 1;
   22036 }
   22037 def S4_extract_rp : HInst<
   22038 (outs IntRegs:$Rd32),
   22039 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   22040 "$Rd32 = extract($Rs32,$Rtt32)",
   22041 tc_2b6f77c6, TypeS_3op>, Enc_e07374 {
   22042 let Inst{7-5} = 0b010;
   22043 let Inst{13-13} = 0b0;
   22044 let Inst{31-21} = 0b11001001000;
   22045 let hasNewValue = 1;
   22046 let opNewValue = 0;
   22047 let prefersSlot3 = 1;
   22048 }
   22049 def S4_extractp : HInst<
   22050 (outs DoubleRegs:$Rdd32),
   22051 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
   22052 "$Rdd32 = extract($Rss32,#$Ii,#$II)",
   22053 tc_c74f796f, TypeS_2op>, Enc_b84c4c {
   22054 let Inst{31-24} = 0b10001010;
   22055 let prefersSlot3 = 1;
   22056 }
   22057 def S4_extractp_rp : HInst<
   22058 (outs DoubleRegs:$Rdd32),
   22059 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   22060 "$Rdd32 = extract($Rss32,$Rtt32)",
   22061 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
   22062 let Inst{7-5} = 0b100;
   22063 let Inst{13-13} = 0b0;
   22064 let Inst{31-21} = 0b11000001110;
   22065 let prefersSlot3 = 1;
   22066 }
   22067 def S4_lsli : HInst<
   22068 (outs IntRegs:$Rd32),
   22069 (ins s6_0Imm:$Ii, IntRegs:$Rt32),
   22070 "$Rd32 = lsl(#$Ii,$Rt32)",
   22071 tc_540fdfbc, TypeS_3op>, Enc_fef969 {
   22072 let Inst{7-6} = 0b11;
   22073 let Inst{13-13} = 0b0;
   22074 let Inst{31-21} = 0b11000110100;
   22075 let hasNewValue = 1;
   22076 let opNewValue = 0;
   22077 }
   22078 def S4_ntstbit_i : HInst<
   22079 (outs PredRegs:$Pd4),
   22080 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   22081 "$Pd4 = !tstbit($Rs32,#$Ii)",
   22082 tc_7a830544, TypeS_2op>, Enc_83ee64 {
   22083 let Inst{7-2} = 0b000000;
   22084 let Inst{13-13} = 0b0;
   22085 let Inst{31-21} = 0b10000101001;
   22086 }
   22087 def S4_ntstbit_r : HInst<
   22088 (outs PredRegs:$Pd4),
   22089 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   22090 "$Pd4 = !tstbit($Rs32,$Rt32)",
   22091 tc_1e856f58, TypeS_3op>, Enc_c2b48e {
   22092 let Inst{7-2} = 0b000000;
   22093 let Inst{13-13} = 0b0;
   22094 let Inst{31-21} = 0b11000111001;
   22095 }
   22096 def S4_or_andi : HInst<
   22097 (outs IntRegs:$Rx32),
   22098 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
   22099 "$Rx32 |= and($Rs32,#$Ii)",
   22100 tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
   22101 let Inst{31-22} = 0b1101101000;
   22102 let hasNewValue = 1;
   22103 let opNewValue = 0;
   22104 let prefersSlot3 = 1;
   22105 let InputType = "imm";
   22106 let isExtendable = 1;
   22107 let opExtendable = 3;
   22108 let isExtentSigned = 1;
   22109 let opExtentBits = 10;
   22110 let opExtentAlign = 0;
   22111 let Constraints = "$Rx32 = $Rx32in";
   22112 }
   22113 def S4_or_andix : HInst<
   22114 (outs IntRegs:$Rx32),
   22115 (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
   22116 "$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
   22117 tc_84df2cd3, TypeALU64>, Enc_b4e6cf {
   22118 let Inst{31-22} = 0b1101101001;
   22119 let hasNewValue = 1;
   22120 let opNewValue = 0;
   22121 let prefersSlot3 = 1;
   22122 let isExtendable = 1;
   22123 let opExtendable = 3;
   22124 let isExtentSigned = 1;
   22125 let opExtentBits = 10;
   22126 let opExtentAlign = 0;
   22127 let Constraints = "$Rx32 = $Rx32in";
   22128 }
   22129 def S4_or_ori : HInst<
   22130 (outs IntRegs:$Rx32),
   22131 (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
   22132 "$Rx32 |= or($Rs32,#$Ii)",
   22133 tc_84df2cd3, TypeALU64>, Enc_b0e9d8 {
   22134 let Inst{31-22} = 0b1101101010;
   22135 let hasNewValue = 1;
   22136 let opNewValue = 0;
   22137 let prefersSlot3 = 1;
   22138 let InputType = "imm";
   22139 let isExtendable = 1;
   22140 let opExtendable = 3;
   22141 let isExtentSigned = 1;
   22142 let opExtentBits = 10;
   22143 let opExtentAlign = 0;
   22144 let Constraints = "$Rx32 = $Rx32in";
   22145 }
   22146 def S4_ori_asl_ri : HInst<
   22147 (outs IntRegs:$Rx32),
   22148 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   22149 "$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
   22150 tc_84df2cd3, TypeALU64>, Enc_c31910 {
   22151 let Inst{2-0} = 0b010;
   22152 let Inst{4-4} = 0b0;
   22153 let Inst{31-24} = 0b11011110;
   22154 let hasNewValue = 1;
   22155 let opNewValue = 0;
   22156 let prefersSlot3 = 1;
   22157 let isExtendable = 1;
   22158 let opExtendable = 1;
   22159 let isExtentSigned = 0;
   22160 let opExtentBits = 8;
   22161 let opExtentAlign = 0;
   22162 let Constraints = "$Rx32 = $Rx32in";
   22163 }
   22164 def S4_ori_lsr_ri : HInst<
   22165 (outs IntRegs:$Rx32),
   22166 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   22167 "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
   22168 tc_84df2cd3, TypeALU64>, Enc_c31910 {
   22169 let Inst{2-0} = 0b010;
   22170 let Inst{4-4} = 0b1;
   22171 let Inst{31-24} = 0b11011110;
   22172 let hasNewValue = 1;
   22173 let opNewValue = 0;
   22174 let prefersSlot3 = 1;
   22175 let isExtendable = 1;
   22176 let opExtendable = 1;
   22177 let isExtentSigned = 0;
   22178 let opExtentBits = 8;
   22179 let opExtentAlign = 0;
   22180 let Constraints = "$Rx32 = $Rx32in";
   22181 }
   22182 def S4_parity : HInst<
   22183 (outs IntRegs:$Rd32),
   22184 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   22185 "$Rd32 = parity($Rs32,$Rt32)",
   22186 tc_2b6f77c6, TypeALU64>, Enc_5ab2be {
   22187 let Inst{7-5} = 0b000;
   22188 let Inst{13-13} = 0b0;
   22189 let Inst{31-21} = 0b11010101111;
   22190 let hasNewValue = 1;
   22191 let opNewValue = 0;
   22192 let prefersSlot3 = 1;
   22193 }
   22194 def S4_pstorerbf_abs : HInst<
   22195 (outs),
   22196 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22197 "if (!$Pv4) memb(#$Ii) = $Rt32",
   22198 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   22199 let Inst{2-2} = 0b1;
   22200 let Inst{7-7} = 0b1;
   22201 let Inst{13-13} = 0b0;
   22202 let Inst{31-18} = 0b10101111000000;
   22203 let isPredicated = 1;
   22204 let isPredicatedFalse = 1;
   22205 let addrMode = Absolute;
   22206 let accessSize = ByteAccess;
   22207 let isExtended = 1;
   22208 let mayStore = 1;
   22209 let CextOpcode = "S2_storerb";
   22210 let BaseOpcode = "S2_storerbabs";
   22211 let isNVStorable = 1;
   22212 let DecoderNamespace = "MustExtend";
   22213 let isExtendable = 1;
   22214 let opExtendable = 1;
   22215 let isExtentSigned = 0;
   22216 let opExtentBits = 6;
   22217 let opExtentAlign = 0;
   22218 }
   22219 def S4_pstorerbf_rr : HInst<
   22220 (outs),
   22221 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22222 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
   22223 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   22224 let Inst{31-21} = 0b00110101000;
   22225 let isPredicated = 1;
   22226 let isPredicatedFalse = 1;
   22227 let addrMode = BaseRegOffset;
   22228 let accessSize = ByteAccess;
   22229 let mayStore = 1;
   22230 let CextOpcode = "S2_storerb";
   22231 let InputType = "reg";
   22232 let BaseOpcode = "S4_storerb_rr";
   22233 let isNVStorable = 1;
   22234 }
   22235 def S4_pstorerbfnew_abs : HInst<
   22236 (outs),
   22237 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22238 "if (!$Pv4.new) memb(#$Ii) = $Rt32",
   22239 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   22240 let Inst{2-2} = 0b1;
   22241 let Inst{7-7} = 0b1;
   22242 let Inst{13-13} = 0b1;
   22243 let Inst{31-18} = 0b10101111000000;
   22244 let isPredicated = 1;
   22245 let isPredicatedFalse = 1;
   22246 let addrMode = Absolute;
   22247 let accessSize = ByteAccess;
   22248 let isPredicatedNew = 1;
   22249 let isExtended = 1;
   22250 let mayStore = 1;
   22251 let CextOpcode = "S2_storerb";
   22252 let BaseOpcode = "S2_storerbabs";
   22253 let isNVStorable = 1;
   22254 let DecoderNamespace = "MustExtend";
   22255 let isExtendable = 1;
   22256 let opExtendable = 1;
   22257 let isExtentSigned = 0;
   22258 let opExtentBits = 6;
   22259 let opExtentAlign = 0;
   22260 }
   22261 def S4_pstorerbfnew_io : HInst<
   22262 (outs),
   22263 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   22264 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
   22265 tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
   22266 let Inst{2-2} = 0b0;
   22267 let Inst{31-21} = 0b01000110000;
   22268 let isPredicated = 1;
   22269 let isPredicatedFalse = 1;
   22270 let addrMode = BaseImmOffset;
   22271 let accessSize = ByteAccess;
   22272 let isPredicatedNew = 1;
   22273 let mayStore = 1;
   22274 let CextOpcode = "S2_storerb";
   22275 let InputType = "imm";
   22276 let BaseOpcode = "S2_storerb_io";
   22277 let isNVStorable = 1;
   22278 let isExtendable = 1;
   22279 let opExtendable = 2;
   22280 let isExtentSigned = 0;
   22281 let opExtentBits = 6;
   22282 let opExtentAlign = 0;
   22283 }
   22284 def S4_pstorerbfnew_rr : HInst<
   22285 (outs),
   22286 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22287 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
   22288 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   22289 let Inst{31-21} = 0b00110111000;
   22290 let isPredicated = 1;
   22291 let isPredicatedFalse = 1;
   22292 let addrMode = BaseRegOffset;
   22293 let accessSize = ByteAccess;
   22294 let isPredicatedNew = 1;
   22295 let mayStore = 1;
   22296 let CextOpcode = "S2_storerb";
   22297 let InputType = "reg";
   22298 let BaseOpcode = "S4_storerb_rr";
   22299 let isNVStorable = 1;
   22300 }
   22301 def S4_pstorerbfnew_zomap : HInst<
   22302 (outs),
   22303 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   22304 "if (!$Pv4.new) memb($Rs32) = $Rt32",
   22305 tc_f86c328a, TypeMAPPING> {
   22306 let isPseudo = 1;
   22307 let isCodeGenOnly = 1;
   22308 }
   22309 def S4_pstorerbnewf_abs : HInst<
   22310 (outs),
   22311 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   22312 "if (!$Pv4) memb(#$Ii) = $Nt8.new",
   22313 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   22314 let Inst{2-2} = 0b1;
   22315 let Inst{7-7} = 0b1;
   22316 let Inst{13-11} = 0b000;
   22317 let Inst{31-18} = 0b10101111101000;
   22318 let isPredicated = 1;
   22319 let isPredicatedFalse = 1;
   22320 let addrMode = Absolute;
   22321 let accessSize = ByteAccess;
   22322 let isNVStore = 1;
   22323 let isNewValue = 1;
   22324 let isExtended = 1;
   22325 let isRestrictNoSlot1Store = 1;
   22326 let mayStore = 1;
   22327 let CextOpcode = "S2_storerb";
   22328 let BaseOpcode = "S2_storerbabs";
   22329 let DecoderNamespace = "MustExtend";
   22330 let isExtendable = 1;
   22331 let opExtendable = 1;
   22332 let isExtentSigned = 0;
   22333 let opExtentBits = 6;
   22334 let opExtentAlign = 0;
   22335 let opNewValue = 2;
   22336 }
   22337 def S4_pstorerbnewf_rr : HInst<
   22338 (outs),
   22339 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   22340 "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   22341 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   22342 let Inst{4-3} = 0b00;
   22343 let Inst{31-21} = 0b00110101101;
   22344 let isPredicated = 1;
   22345 let isPredicatedFalse = 1;
   22346 let addrMode = BaseRegOffset;
   22347 let accessSize = ByteAccess;
   22348 let isNVStore = 1;
   22349 let isNewValue = 1;
   22350 let isRestrictNoSlot1Store = 1;
   22351 let mayStore = 1;
   22352 let CextOpcode = "S2_storerb";
   22353 let InputType = "reg";
   22354 let BaseOpcode = "S4_storerb_rr";
   22355 let opNewValue = 4;
   22356 }
   22357 def S4_pstorerbnewfnew_abs : HInst<
   22358 (outs),
   22359 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   22360 "if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
   22361 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   22362 let Inst{2-2} = 0b1;
   22363 let Inst{7-7} = 0b1;
   22364 let Inst{13-11} = 0b100;
   22365 let Inst{31-18} = 0b10101111101000;
   22366 let isPredicated = 1;
   22367 let isPredicatedFalse = 1;
   22368 let addrMode = Absolute;
   22369 let accessSize = ByteAccess;
   22370 let isNVStore = 1;
   22371 let isPredicatedNew = 1;
   22372 let isNewValue = 1;
   22373 let isExtended = 1;
   22374 let isRestrictNoSlot1Store = 1;
   22375 let mayStore = 1;
   22376 let CextOpcode = "S2_storerb";
   22377 let BaseOpcode = "S2_storerbabs";
   22378 let DecoderNamespace = "MustExtend";
   22379 let isExtendable = 1;
   22380 let opExtendable = 1;
   22381 let isExtentSigned = 0;
   22382 let opExtentBits = 6;
   22383 let opExtentAlign = 0;
   22384 let opNewValue = 2;
   22385 }
   22386 def S4_pstorerbnewfnew_io : HInst<
   22387 (outs),
   22388 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
   22389 "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
   22390 tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
   22391 let Inst{2-2} = 0b0;
   22392 let Inst{12-11} = 0b00;
   22393 let Inst{31-21} = 0b01000110101;
   22394 let isPredicated = 1;
   22395 let isPredicatedFalse = 1;
   22396 let addrMode = BaseImmOffset;
   22397 let accessSize = ByteAccess;
   22398 let isNVStore = 1;
   22399 let isPredicatedNew = 1;
   22400 let isNewValue = 1;
   22401 let isRestrictNoSlot1Store = 1;
   22402 let mayStore = 1;
   22403 let CextOpcode = "S2_storerb";
   22404 let InputType = "imm";
   22405 let BaseOpcode = "S2_storerb_io";
   22406 let isExtendable = 1;
   22407 let opExtendable = 2;
   22408 let isExtentSigned = 0;
   22409 let opExtentBits = 6;
   22410 let opExtentAlign = 0;
   22411 let opNewValue = 3;
   22412 }
   22413 def S4_pstorerbnewfnew_rr : HInst<
   22414 (outs),
   22415 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   22416 "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   22417 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   22418 let Inst{4-3} = 0b00;
   22419 let Inst{31-21} = 0b00110111101;
   22420 let isPredicated = 1;
   22421 let isPredicatedFalse = 1;
   22422 let addrMode = BaseRegOffset;
   22423 let accessSize = ByteAccess;
   22424 let isNVStore = 1;
   22425 let isPredicatedNew = 1;
   22426 let isNewValue = 1;
   22427 let isRestrictNoSlot1Store = 1;
   22428 let mayStore = 1;
   22429 let CextOpcode = "S2_storerb";
   22430 let InputType = "reg";
   22431 let BaseOpcode = "S4_storerb_rr";
   22432 let opNewValue = 4;
   22433 }
   22434 def S4_pstorerbnewfnew_zomap : HInst<
   22435 (outs),
   22436 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   22437 "if (!$Pv4.new) memb($Rs32) = $Nt8.new",
   22438 tc_e7d02c66, TypeMAPPING> {
   22439 let isPseudo = 1;
   22440 let isCodeGenOnly = 1;
   22441 let opNewValue = 2;
   22442 }
   22443 def S4_pstorerbnewt_abs : HInst<
   22444 (outs),
   22445 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   22446 "if ($Pv4) memb(#$Ii) = $Nt8.new",
   22447 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   22448 let Inst{2-2} = 0b0;
   22449 let Inst{7-7} = 0b1;
   22450 let Inst{13-11} = 0b000;
   22451 let Inst{31-18} = 0b10101111101000;
   22452 let isPredicated = 1;
   22453 let addrMode = Absolute;
   22454 let accessSize = ByteAccess;
   22455 let isNVStore = 1;
   22456 let isNewValue = 1;
   22457 let isExtended = 1;
   22458 let isRestrictNoSlot1Store = 1;
   22459 let mayStore = 1;
   22460 let CextOpcode = "S2_storerb";
   22461 let BaseOpcode = "S2_storerbabs";
   22462 let DecoderNamespace = "MustExtend";
   22463 let isExtendable = 1;
   22464 let opExtendable = 1;
   22465 let isExtentSigned = 0;
   22466 let opExtentBits = 6;
   22467 let opExtentAlign = 0;
   22468 let opNewValue = 2;
   22469 }
   22470 def S4_pstorerbnewt_rr : HInst<
   22471 (outs),
   22472 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   22473 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   22474 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   22475 let Inst{4-3} = 0b00;
   22476 let Inst{31-21} = 0b00110100101;
   22477 let isPredicated = 1;
   22478 let addrMode = BaseRegOffset;
   22479 let accessSize = ByteAccess;
   22480 let isNVStore = 1;
   22481 let isNewValue = 1;
   22482 let isRestrictNoSlot1Store = 1;
   22483 let mayStore = 1;
   22484 let CextOpcode = "S2_storerb";
   22485 let InputType = "reg";
   22486 let BaseOpcode = "S4_storerb_rr";
   22487 let opNewValue = 4;
   22488 }
   22489 def S4_pstorerbnewtnew_abs : HInst<
   22490 (outs),
   22491 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   22492 "if ($Pv4.new) memb(#$Ii) = $Nt8.new",
   22493 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   22494 let Inst{2-2} = 0b0;
   22495 let Inst{7-7} = 0b1;
   22496 let Inst{13-11} = 0b100;
   22497 let Inst{31-18} = 0b10101111101000;
   22498 let isPredicated = 1;
   22499 let addrMode = Absolute;
   22500 let accessSize = ByteAccess;
   22501 let isNVStore = 1;
   22502 let isPredicatedNew = 1;
   22503 let isNewValue = 1;
   22504 let isExtended = 1;
   22505 let isRestrictNoSlot1Store = 1;
   22506 let mayStore = 1;
   22507 let CextOpcode = "S2_storerb";
   22508 let BaseOpcode = "S2_storerbabs";
   22509 let DecoderNamespace = "MustExtend";
   22510 let isExtendable = 1;
   22511 let opExtendable = 1;
   22512 let isExtentSigned = 0;
   22513 let opExtentBits = 6;
   22514 let opExtentAlign = 0;
   22515 let opNewValue = 2;
   22516 }
   22517 def S4_pstorerbnewtnew_io : HInst<
   22518 (outs),
   22519 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
   22520 "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
   22521 tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel {
   22522 let Inst{2-2} = 0b0;
   22523 let Inst{12-11} = 0b00;
   22524 let Inst{31-21} = 0b01000010101;
   22525 let isPredicated = 1;
   22526 let addrMode = BaseImmOffset;
   22527 let accessSize = ByteAccess;
   22528 let isNVStore = 1;
   22529 let isPredicatedNew = 1;
   22530 let isNewValue = 1;
   22531 let isRestrictNoSlot1Store = 1;
   22532 let mayStore = 1;
   22533 let CextOpcode = "S2_storerb";
   22534 let InputType = "imm";
   22535 let BaseOpcode = "S2_storerb_io";
   22536 let isExtendable = 1;
   22537 let opExtendable = 2;
   22538 let isExtentSigned = 0;
   22539 let opExtentBits = 6;
   22540 let opExtentAlign = 0;
   22541 let opNewValue = 3;
   22542 }
   22543 def S4_pstorerbnewtnew_rr : HInst<
   22544 (outs),
   22545 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   22546 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   22547 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   22548 let Inst{4-3} = 0b00;
   22549 let Inst{31-21} = 0b00110110101;
   22550 let isPredicated = 1;
   22551 let addrMode = BaseRegOffset;
   22552 let accessSize = ByteAccess;
   22553 let isNVStore = 1;
   22554 let isPredicatedNew = 1;
   22555 let isNewValue = 1;
   22556 let isRestrictNoSlot1Store = 1;
   22557 let mayStore = 1;
   22558 let CextOpcode = "S2_storerb";
   22559 let InputType = "reg";
   22560 let BaseOpcode = "S4_storerb_rr";
   22561 let opNewValue = 4;
   22562 }
   22563 def S4_pstorerbnewtnew_zomap : HInst<
   22564 (outs),
   22565 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   22566 "if ($Pv4.new) memb($Rs32) = $Nt8.new",
   22567 tc_e7d02c66, TypeMAPPING> {
   22568 let isPseudo = 1;
   22569 let isCodeGenOnly = 1;
   22570 let opNewValue = 2;
   22571 }
   22572 def S4_pstorerbt_abs : HInst<
   22573 (outs),
   22574 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22575 "if ($Pv4) memb(#$Ii) = $Rt32",
   22576 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   22577 let Inst{2-2} = 0b0;
   22578 let Inst{7-7} = 0b1;
   22579 let Inst{13-13} = 0b0;
   22580 let Inst{31-18} = 0b10101111000000;
   22581 let isPredicated = 1;
   22582 let addrMode = Absolute;
   22583 let accessSize = ByteAccess;
   22584 let isExtended = 1;
   22585 let mayStore = 1;
   22586 let CextOpcode = "S2_storerb";
   22587 let BaseOpcode = "S2_storerbabs";
   22588 let isNVStorable = 1;
   22589 let DecoderNamespace = "MustExtend";
   22590 let isExtendable = 1;
   22591 let opExtendable = 1;
   22592 let isExtentSigned = 0;
   22593 let opExtentBits = 6;
   22594 let opExtentAlign = 0;
   22595 }
   22596 def S4_pstorerbt_rr : HInst<
   22597 (outs),
   22598 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22599 "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
   22600 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   22601 let Inst{31-21} = 0b00110100000;
   22602 let isPredicated = 1;
   22603 let addrMode = BaseRegOffset;
   22604 let accessSize = ByteAccess;
   22605 let mayStore = 1;
   22606 let CextOpcode = "S2_storerb";
   22607 let InputType = "reg";
   22608 let BaseOpcode = "S4_storerb_rr";
   22609 let isNVStorable = 1;
   22610 }
   22611 def S4_pstorerbtnew_abs : HInst<
   22612 (outs),
   22613 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22614 "if ($Pv4.new) memb(#$Ii) = $Rt32",
   22615 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   22616 let Inst{2-2} = 0b0;
   22617 let Inst{7-7} = 0b1;
   22618 let Inst{13-13} = 0b1;
   22619 let Inst{31-18} = 0b10101111000000;
   22620 let isPredicated = 1;
   22621 let addrMode = Absolute;
   22622 let accessSize = ByteAccess;
   22623 let isPredicatedNew = 1;
   22624 let isExtended = 1;
   22625 let mayStore = 1;
   22626 let CextOpcode = "S2_storerb";
   22627 let BaseOpcode = "S2_storerbabs";
   22628 let isNVStorable = 1;
   22629 let DecoderNamespace = "MustExtend";
   22630 let isExtendable = 1;
   22631 let opExtendable = 1;
   22632 let isExtentSigned = 0;
   22633 let opExtentBits = 6;
   22634 let opExtentAlign = 0;
   22635 }
   22636 def S4_pstorerbtnew_io : HInst<
   22637 (outs),
   22638 (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
   22639 "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
   22640 tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel {
   22641 let Inst{2-2} = 0b0;
   22642 let Inst{31-21} = 0b01000010000;
   22643 let isPredicated = 1;
   22644 let addrMode = BaseImmOffset;
   22645 let accessSize = ByteAccess;
   22646 let isPredicatedNew = 1;
   22647 let mayStore = 1;
   22648 let CextOpcode = "S2_storerb";
   22649 let InputType = "imm";
   22650 let BaseOpcode = "S2_storerb_io";
   22651 let isNVStorable = 1;
   22652 let isExtendable = 1;
   22653 let opExtendable = 2;
   22654 let isExtentSigned = 0;
   22655 let opExtentBits = 6;
   22656 let opExtentAlign = 0;
   22657 }
   22658 def S4_pstorerbtnew_rr : HInst<
   22659 (outs),
   22660 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22661 "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
   22662 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   22663 let Inst{31-21} = 0b00110110000;
   22664 let isPredicated = 1;
   22665 let addrMode = BaseRegOffset;
   22666 let accessSize = ByteAccess;
   22667 let isPredicatedNew = 1;
   22668 let mayStore = 1;
   22669 let CextOpcode = "S2_storerb";
   22670 let InputType = "reg";
   22671 let BaseOpcode = "S4_storerb_rr";
   22672 let isNVStorable = 1;
   22673 }
   22674 def S4_pstorerbtnew_zomap : HInst<
   22675 (outs),
   22676 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   22677 "if ($Pv4.new) memb($Rs32) = $Rt32",
   22678 tc_f86c328a, TypeMAPPING> {
   22679 let isPseudo = 1;
   22680 let isCodeGenOnly = 1;
   22681 }
   22682 def S4_pstorerdf_abs : HInst<
   22683 (outs),
   22684 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
   22685 "if (!$Pv4) memd(#$Ii) = $Rtt32",
   22686 tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
   22687 let Inst{2-2} = 0b1;
   22688 let Inst{7-7} = 0b1;
   22689 let Inst{13-13} = 0b0;
   22690 let Inst{31-18} = 0b10101111110000;
   22691 let isPredicated = 1;
   22692 let isPredicatedFalse = 1;
   22693 let addrMode = Absolute;
   22694 let accessSize = DoubleWordAccess;
   22695 let isExtended = 1;
   22696 let mayStore = 1;
   22697 let CextOpcode = "S2_storerd";
   22698 let BaseOpcode = "S2_storerdabs";
   22699 let DecoderNamespace = "MustExtend";
   22700 let isExtendable = 1;
   22701 let opExtendable = 1;
   22702 let isExtentSigned = 0;
   22703 let opExtentBits = 6;
   22704 let opExtentAlign = 0;
   22705 }
   22706 def S4_pstorerdf_rr : HInst<
   22707 (outs),
   22708 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
   22709 "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
   22710 tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
   22711 let Inst{31-21} = 0b00110101110;
   22712 let isPredicated = 1;
   22713 let isPredicatedFalse = 1;
   22714 let addrMode = BaseRegOffset;
   22715 let accessSize = DoubleWordAccess;
   22716 let mayStore = 1;
   22717 let CextOpcode = "S2_storerd";
   22718 let InputType = "reg";
   22719 let BaseOpcode = "S2_storerd_rr";
   22720 }
   22721 def S4_pstorerdfnew_abs : HInst<
   22722 (outs),
   22723 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
   22724 "if (!$Pv4.new) memd(#$Ii) = $Rtt32",
   22725 tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
   22726 let Inst{2-2} = 0b1;
   22727 let Inst{7-7} = 0b1;
   22728 let Inst{13-13} = 0b1;
   22729 let Inst{31-18} = 0b10101111110000;
   22730 let isPredicated = 1;
   22731 let isPredicatedFalse = 1;
   22732 let addrMode = Absolute;
   22733 let accessSize = DoubleWordAccess;
   22734 let isPredicatedNew = 1;
   22735 let isExtended = 1;
   22736 let mayStore = 1;
   22737 let CextOpcode = "S2_storerd";
   22738 let BaseOpcode = "S2_storerdabs";
   22739 let DecoderNamespace = "MustExtend";
   22740 let isExtendable = 1;
   22741 let opExtendable = 1;
   22742 let isExtentSigned = 0;
   22743 let opExtentBits = 6;
   22744 let opExtentAlign = 0;
   22745 }
   22746 def S4_pstorerdfnew_io : HInst<
   22747 (outs),
   22748 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   22749 "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
   22750 tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
   22751 let Inst{2-2} = 0b0;
   22752 let Inst{31-21} = 0b01000110110;
   22753 let isPredicated = 1;
   22754 let isPredicatedFalse = 1;
   22755 let addrMode = BaseImmOffset;
   22756 let accessSize = DoubleWordAccess;
   22757 let isPredicatedNew = 1;
   22758 let mayStore = 1;
   22759 let CextOpcode = "S2_storerd";
   22760 let InputType = "imm";
   22761 let BaseOpcode = "S2_storerd_io";
   22762 let isExtendable = 1;
   22763 let opExtendable = 2;
   22764 let isExtentSigned = 0;
   22765 let opExtentBits = 9;
   22766 let opExtentAlign = 3;
   22767 }
   22768 def S4_pstorerdfnew_rr : HInst<
   22769 (outs),
   22770 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
   22771 "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
   22772 tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
   22773 let Inst{31-21} = 0b00110111110;
   22774 let isPredicated = 1;
   22775 let isPredicatedFalse = 1;
   22776 let addrMode = BaseRegOffset;
   22777 let accessSize = DoubleWordAccess;
   22778 let isPredicatedNew = 1;
   22779 let mayStore = 1;
   22780 let CextOpcode = "S2_storerd";
   22781 let InputType = "reg";
   22782 let BaseOpcode = "S2_storerd_rr";
   22783 }
   22784 def S4_pstorerdfnew_zomap : HInst<
   22785 (outs),
   22786 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
   22787 "if (!$Pv4.new) memd($Rs32) = $Rtt32",
   22788 tc_f86c328a, TypeMAPPING> {
   22789 let isPseudo = 1;
   22790 let isCodeGenOnly = 1;
   22791 }
   22792 def S4_pstorerdt_abs : HInst<
   22793 (outs),
   22794 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
   22795 "if ($Pv4) memd(#$Ii) = $Rtt32",
   22796 tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel {
   22797 let Inst{2-2} = 0b0;
   22798 let Inst{7-7} = 0b1;
   22799 let Inst{13-13} = 0b0;
   22800 let Inst{31-18} = 0b10101111110000;
   22801 let isPredicated = 1;
   22802 let addrMode = Absolute;
   22803 let accessSize = DoubleWordAccess;
   22804 let isExtended = 1;
   22805 let mayStore = 1;
   22806 let CextOpcode = "S2_storerd";
   22807 let BaseOpcode = "S2_storerdabs";
   22808 let DecoderNamespace = "MustExtend";
   22809 let isExtendable = 1;
   22810 let opExtendable = 1;
   22811 let isExtentSigned = 0;
   22812 let opExtentBits = 6;
   22813 let opExtentAlign = 0;
   22814 }
   22815 def S4_pstorerdt_rr : HInst<
   22816 (outs),
   22817 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
   22818 "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
   22819 tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel {
   22820 let Inst{31-21} = 0b00110100110;
   22821 let isPredicated = 1;
   22822 let addrMode = BaseRegOffset;
   22823 let accessSize = DoubleWordAccess;
   22824 let mayStore = 1;
   22825 let CextOpcode = "S2_storerd";
   22826 let InputType = "reg";
   22827 let BaseOpcode = "S2_storerd_rr";
   22828 }
   22829 def S4_pstorerdtnew_abs : HInst<
   22830 (outs),
   22831 (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
   22832 "if ($Pv4.new) memd(#$Ii) = $Rtt32",
   22833 tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel {
   22834 let Inst{2-2} = 0b0;
   22835 let Inst{7-7} = 0b1;
   22836 let Inst{13-13} = 0b1;
   22837 let Inst{31-18} = 0b10101111110000;
   22838 let isPredicated = 1;
   22839 let addrMode = Absolute;
   22840 let accessSize = DoubleWordAccess;
   22841 let isPredicatedNew = 1;
   22842 let isExtended = 1;
   22843 let mayStore = 1;
   22844 let CextOpcode = "S2_storerd";
   22845 let BaseOpcode = "S2_storerdabs";
   22846 let DecoderNamespace = "MustExtend";
   22847 let isExtendable = 1;
   22848 let opExtendable = 1;
   22849 let isExtentSigned = 0;
   22850 let opExtentBits = 6;
   22851 let opExtentAlign = 0;
   22852 }
   22853 def S4_pstorerdtnew_io : HInst<
   22854 (outs),
   22855 (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
   22856 "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
   22857 tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel {
   22858 let Inst{2-2} = 0b0;
   22859 let Inst{31-21} = 0b01000010110;
   22860 let isPredicated = 1;
   22861 let addrMode = BaseImmOffset;
   22862 let accessSize = DoubleWordAccess;
   22863 let isPredicatedNew = 1;
   22864 let mayStore = 1;
   22865 let CextOpcode = "S2_storerd";
   22866 let InputType = "imm";
   22867 let BaseOpcode = "S2_storerd_io";
   22868 let isExtendable = 1;
   22869 let opExtendable = 2;
   22870 let isExtentSigned = 0;
   22871 let opExtentBits = 9;
   22872 let opExtentAlign = 3;
   22873 }
   22874 def S4_pstorerdtnew_rr : HInst<
   22875 (outs),
   22876 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
   22877 "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
   22878 tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel {
   22879 let Inst{31-21} = 0b00110110110;
   22880 let isPredicated = 1;
   22881 let addrMode = BaseRegOffset;
   22882 let accessSize = DoubleWordAccess;
   22883 let isPredicatedNew = 1;
   22884 let mayStore = 1;
   22885 let CextOpcode = "S2_storerd";
   22886 let InputType = "reg";
   22887 let BaseOpcode = "S2_storerd_rr";
   22888 }
   22889 def S4_pstorerdtnew_zomap : HInst<
   22890 (outs),
   22891 (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
   22892 "if ($Pv4.new) memd($Rs32) = $Rtt32",
   22893 tc_f86c328a, TypeMAPPING> {
   22894 let isPseudo = 1;
   22895 let isCodeGenOnly = 1;
   22896 }
   22897 def S4_pstorerff_abs : HInst<
   22898 (outs),
   22899 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22900 "if (!$Pv4) memh(#$Ii) = $Rt32.h",
   22901 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   22902 let Inst{2-2} = 0b1;
   22903 let Inst{7-7} = 0b1;
   22904 let Inst{13-13} = 0b0;
   22905 let Inst{31-18} = 0b10101111011000;
   22906 let isPredicated = 1;
   22907 let isPredicatedFalse = 1;
   22908 let addrMode = Absolute;
   22909 let accessSize = HalfWordAccess;
   22910 let isExtended = 1;
   22911 let mayStore = 1;
   22912 let CextOpcode = "S2_storerf";
   22913 let BaseOpcode = "S2_storerfabs";
   22914 let DecoderNamespace = "MustExtend";
   22915 let isExtendable = 1;
   22916 let opExtendable = 1;
   22917 let isExtentSigned = 0;
   22918 let opExtentBits = 6;
   22919 let opExtentAlign = 0;
   22920 }
   22921 def S4_pstorerff_rr : HInst<
   22922 (outs),
   22923 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22924 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
   22925 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   22926 let Inst{31-21} = 0b00110101011;
   22927 let isPredicated = 1;
   22928 let isPredicatedFalse = 1;
   22929 let addrMode = BaseRegOffset;
   22930 let accessSize = HalfWordAccess;
   22931 let mayStore = 1;
   22932 let CextOpcode = "S2_storerf";
   22933 let InputType = "reg";
   22934 let BaseOpcode = "S4_storerf_rr";
   22935 }
   22936 def S4_pstorerffnew_abs : HInst<
   22937 (outs),
   22938 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   22939 "if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
   22940 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   22941 let Inst{2-2} = 0b1;
   22942 let Inst{7-7} = 0b1;
   22943 let Inst{13-13} = 0b1;
   22944 let Inst{31-18} = 0b10101111011000;
   22945 let isPredicated = 1;
   22946 let isPredicatedFalse = 1;
   22947 let addrMode = Absolute;
   22948 let accessSize = HalfWordAccess;
   22949 let isPredicatedNew = 1;
   22950 let isExtended = 1;
   22951 let mayStore = 1;
   22952 let CextOpcode = "S2_storerf";
   22953 let BaseOpcode = "S2_storerfabs";
   22954 let DecoderNamespace = "MustExtend";
   22955 let isExtendable = 1;
   22956 let opExtendable = 1;
   22957 let isExtentSigned = 0;
   22958 let opExtentBits = 6;
   22959 let opExtentAlign = 0;
   22960 }
   22961 def S4_pstorerffnew_io : HInst<
   22962 (outs),
   22963 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   22964 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
   22965 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   22966 let Inst{2-2} = 0b0;
   22967 let Inst{31-21} = 0b01000110011;
   22968 let isPredicated = 1;
   22969 let isPredicatedFalse = 1;
   22970 let addrMode = BaseImmOffset;
   22971 let accessSize = HalfWordAccess;
   22972 let isPredicatedNew = 1;
   22973 let mayStore = 1;
   22974 let CextOpcode = "S2_storerf";
   22975 let InputType = "imm";
   22976 let BaseOpcode = "S2_storerf_io";
   22977 let isExtendable = 1;
   22978 let opExtendable = 2;
   22979 let isExtentSigned = 0;
   22980 let opExtentBits = 7;
   22981 let opExtentAlign = 1;
   22982 }
   22983 def S4_pstorerffnew_rr : HInst<
   22984 (outs),
   22985 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   22986 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
   22987 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   22988 let Inst{31-21} = 0b00110111011;
   22989 let isPredicated = 1;
   22990 let isPredicatedFalse = 1;
   22991 let addrMode = BaseRegOffset;
   22992 let accessSize = HalfWordAccess;
   22993 let isPredicatedNew = 1;
   22994 let mayStore = 1;
   22995 let CextOpcode = "S2_storerf";
   22996 let InputType = "reg";
   22997 let BaseOpcode = "S4_storerf_rr";
   22998 }
   22999 def S4_pstorerffnew_zomap : HInst<
   23000 (outs),
   23001 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   23002 "if (!$Pv4.new) memh($Rs32) = $Rt32.h",
   23003 tc_f86c328a, TypeMAPPING> {
   23004 let isPseudo = 1;
   23005 let isCodeGenOnly = 1;
   23006 }
   23007 def S4_pstorerft_abs : HInst<
   23008 (outs),
   23009 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23010 "if ($Pv4) memh(#$Ii) = $Rt32.h",
   23011 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   23012 let Inst{2-2} = 0b0;
   23013 let Inst{7-7} = 0b1;
   23014 let Inst{13-13} = 0b0;
   23015 let Inst{31-18} = 0b10101111011000;
   23016 let isPredicated = 1;
   23017 let addrMode = Absolute;
   23018 let accessSize = HalfWordAccess;
   23019 let isExtended = 1;
   23020 let mayStore = 1;
   23021 let CextOpcode = "S2_storerf";
   23022 let BaseOpcode = "S2_storerfabs";
   23023 let DecoderNamespace = "MustExtend";
   23024 let isExtendable = 1;
   23025 let opExtendable = 1;
   23026 let isExtentSigned = 0;
   23027 let opExtentBits = 6;
   23028 let opExtentAlign = 0;
   23029 }
   23030 def S4_pstorerft_rr : HInst<
   23031 (outs),
   23032 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23033 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
   23034 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   23035 let Inst{31-21} = 0b00110100011;
   23036 let isPredicated = 1;
   23037 let addrMode = BaseRegOffset;
   23038 let accessSize = HalfWordAccess;
   23039 let mayStore = 1;
   23040 let CextOpcode = "S2_storerf";
   23041 let InputType = "reg";
   23042 let BaseOpcode = "S4_storerf_rr";
   23043 }
   23044 def S4_pstorerftnew_abs : HInst<
   23045 (outs),
   23046 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23047 "if ($Pv4.new) memh(#$Ii) = $Rt32.h",
   23048 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   23049 let Inst{2-2} = 0b0;
   23050 let Inst{7-7} = 0b1;
   23051 let Inst{13-13} = 0b1;
   23052 let Inst{31-18} = 0b10101111011000;
   23053 let isPredicated = 1;
   23054 let addrMode = Absolute;
   23055 let accessSize = HalfWordAccess;
   23056 let isPredicatedNew = 1;
   23057 let isExtended = 1;
   23058 let mayStore = 1;
   23059 let CextOpcode = "S2_storerf";
   23060 let BaseOpcode = "S2_storerfabs";
   23061 let DecoderNamespace = "MustExtend";
   23062 let isExtendable = 1;
   23063 let opExtendable = 1;
   23064 let isExtentSigned = 0;
   23065 let opExtentBits = 6;
   23066 let opExtentAlign = 0;
   23067 }
   23068 def S4_pstorerftnew_io : HInst<
   23069 (outs),
   23070 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   23071 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
   23072 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   23073 let Inst{2-2} = 0b0;
   23074 let Inst{31-21} = 0b01000010011;
   23075 let isPredicated = 1;
   23076 let addrMode = BaseImmOffset;
   23077 let accessSize = HalfWordAccess;
   23078 let isPredicatedNew = 1;
   23079 let mayStore = 1;
   23080 let CextOpcode = "S2_storerf";
   23081 let InputType = "imm";
   23082 let BaseOpcode = "S2_storerf_io";
   23083 let isExtendable = 1;
   23084 let opExtendable = 2;
   23085 let isExtentSigned = 0;
   23086 let opExtentBits = 7;
   23087 let opExtentAlign = 1;
   23088 }
   23089 def S4_pstorerftnew_rr : HInst<
   23090 (outs),
   23091 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23092 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
   23093 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   23094 let Inst{31-21} = 0b00110110011;
   23095 let isPredicated = 1;
   23096 let addrMode = BaseRegOffset;
   23097 let accessSize = HalfWordAccess;
   23098 let isPredicatedNew = 1;
   23099 let mayStore = 1;
   23100 let CextOpcode = "S2_storerf";
   23101 let InputType = "reg";
   23102 let BaseOpcode = "S4_storerf_rr";
   23103 }
   23104 def S4_pstorerftnew_zomap : HInst<
   23105 (outs),
   23106 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   23107 "if ($Pv4.new) memh($Rs32) = $Rt32.h",
   23108 tc_f86c328a, TypeMAPPING> {
   23109 let isPseudo = 1;
   23110 let isCodeGenOnly = 1;
   23111 }
   23112 def S4_pstorerhf_abs : HInst<
   23113 (outs),
   23114 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23115 "if (!$Pv4) memh(#$Ii) = $Rt32",
   23116 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   23117 let Inst{2-2} = 0b1;
   23118 let Inst{7-7} = 0b1;
   23119 let Inst{13-13} = 0b0;
   23120 let Inst{31-18} = 0b10101111010000;
   23121 let isPredicated = 1;
   23122 let isPredicatedFalse = 1;
   23123 let addrMode = Absolute;
   23124 let accessSize = HalfWordAccess;
   23125 let isExtended = 1;
   23126 let mayStore = 1;
   23127 let CextOpcode = "S2_storerh";
   23128 let BaseOpcode = "S2_storerhabs";
   23129 let isNVStorable = 1;
   23130 let DecoderNamespace = "MustExtend";
   23131 let isExtendable = 1;
   23132 let opExtendable = 1;
   23133 let isExtentSigned = 0;
   23134 let opExtentBits = 6;
   23135 let opExtentAlign = 0;
   23136 }
   23137 def S4_pstorerhf_rr : HInst<
   23138 (outs),
   23139 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23140 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
   23141 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   23142 let Inst{31-21} = 0b00110101010;
   23143 let isPredicated = 1;
   23144 let isPredicatedFalse = 1;
   23145 let addrMode = BaseRegOffset;
   23146 let accessSize = HalfWordAccess;
   23147 let mayStore = 1;
   23148 let CextOpcode = "S2_storerh";
   23149 let InputType = "reg";
   23150 let BaseOpcode = "S2_storerh_rr";
   23151 let isNVStorable = 1;
   23152 }
   23153 def S4_pstorerhfnew_abs : HInst<
   23154 (outs),
   23155 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23156 "if (!$Pv4.new) memh(#$Ii) = $Rt32",
   23157 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   23158 let Inst{2-2} = 0b1;
   23159 let Inst{7-7} = 0b1;
   23160 let Inst{13-13} = 0b1;
   23161 let Inst{31-18} = 0b10101111010000;
   23162 let isPredicated = 1;
   23163 let isPredicatedFalse = 1;
   23164 let addrMode = Absolute;
   23165 let accessSize = HalfWordAccess;
   23166 let isPredicatedNew = 1;
   23167 let isExtended = 1;
   23168 let mayStore = 1;
   23169 let CextOpcode = "S2_storerh";
   23170 let BaseOpcode = "S2_storerhabs";
   23171 let isNVStorable = 1;
   23172 let DecoderNamespace = "MustExtend";
   23173 let isExtendable = 1;
   23174 let opExtendable = 1;
   23175 let isExtentSigned = 0;
   23176 let opExtentBits = 6;
   23177 let opExtentAlign = 0;
   23178 }
   23179 def S4_pstorerhfnew_io : HInst<
   23180 (outs),
   23181 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   23182 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
   23183 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   23184 let Inst{2-2} = 0b0;
   23185 let Inst{31-21} = 0b01000110010;
   23186 let isPredicated = 1;
   23187 let isPredicatedFalse = 1;
   23188 let addrMode = BaseImmOffset;
   23189 let accessSize = HalfWordAccess;
   23190 let isPredicatedNew = 1;
   23191 let mayStore = 1;
   23192 let CextOpcode = "S2_storerh";
   23193 let InputType = "imm";
   23194 let BaseOpcode = "S2_storerh_io";
   23195 let isNVStorable = 1;
   23196 let isExtendable = 1;
   23197 let opExtendable = 2;
   23198 let isExtentSigned = 0;
   23199 let opExtentBits = 7;
   23200 let opExtentAlign = 1;
   23201 }
   23202 def S4_pstorerhfnew_rr : HInst<
   23203 (outs),
   23204 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23205 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
   23206 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   23207 let Inst{31-21} = 0b00110111010;
   23208 let isPredicated = 1;
   23209 let isPredicatedFalse = 1;
   23210 let addrMode = BaseRegOffset;
   23211 let accessSize = HalfWordAccess;
   23212 let isPredicatedNew = 1;
   23213 let mayStore = 1;
   23214 let CextOpcode = "S2_storerh";
   23215 let InputType = "reg";
   23216 let BaseOpcode = "S2_storerh_rr";
   23217 let isNVStorable = 1;
   23218 }
   23219 def S4_pstorerhfnew_zomap : HInst<
   23220 (outs),
   23221 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   23222 "if (!$Pv4.new) memh($Rs32) = $Rt32",
   23223 tc_f86c328a, TypeMAPPING> {
   23224 let isPseudo = 1;
   23225 let isCodeGenOnly = 1;
   23226 }
   23227 def S4_pstorerhnewf_abs : HInst<
   23228 (outs),
   23229 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23230 "if (!$Pv4) memh(#$Ii) = $Nt8.new",
   23231 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   23232 let Inst{2-2} = 0b1;
   23233 let Inst{7-7} = 0b1;
   23234 let Inst{13-11} = 0b001;
   23235 let Inst{31-18} = 0b10101111101000;
   23236 let isPredicated = 1;
   23237 let isPredicatedFalse = 1;
   23238 let addrMode = Absolute;
   23239 let accessSize = HalfWordAccess;
   23240 let isNVStore = 1;
   23241 let isNewValue = 1;
   23242 let isExtended = 1;
   23243 let isRestrictNoSlot1Store = 1;
   23244 let mayStore = 1;
   23245 let CextOpcode = "S2_storerh";
   23246 let BaseOpcode = "S2_storerhabs";
   23247 let DecoderNamespace = "MustExtend";
   23248 let isExtendable = 1;
   23249 let opExtendable = 1;
   23250 let isExtentSigned = 0;
   23251 let opExtentBits = 6;
   23252 let opExtentAlign = 0;
   23253 let opNewValue = 2;
   23254 }
   23255 def S4_pstorerhnewf_rr : HInst<
   23256 (outs),
   23257 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23258 "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23259 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   23260 let Inst{4-3} = 0b01;
   23261 let Inst{31-21} = 0b00110101101;
   23262 let isPredicated = 1;
   23263 let isPredicatedFalse = 1;
   23264 let addrMode = BaseRegOffset;
   23265 let accessSize = HalfWordAccess;
   23266 let isNVStore = 1;
   23267 let isNewValue = 1;
   23268 let isRestrictNoSlot1Store = 1;
   23269 let mayStore = 1;
   23270 let CextOpcode = "S2_storerh";
   23271 let InputType = "reg";
   23272 let BaseOpcode = "S2_storerh_rr";
   23273 let opNewValue = 4;
   23274 }
   23275 def S4_pstorerhnewfnew_abs : HInst<
   23276 (outs),
   23277 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23278 "if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
   23279 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   23280 let Inst{2-2} = 0b1;
   23281 let Inst{7-7} = 0b1;
   23282 let Inst{13-11} = 0b101;
   23283 let Inst{31-18} = 0b10101111101000;
   23284 let isPredicated = 1;
   23285 let isPredicatedFalse = 1;
   23286 let addrMode = Absolute;
   23287 let accessSize = HalfWordAccess;
   23288 let isNVStore = 1;
   23289 let isPredicatedNew = 1;
   23290 let isNewValue = 1;
   23291 let isExtended = 1;
   23292 let isRestrictNoSlot1Store = 1;
   23293 let mayStore = 1;
   23294 let CextOpcode = "S2_storerh";
   23295 let BaseOpcode = "S2_storerhabs";
   23296 let DecoderNamespace = "MustExtend";
   23297 let isExtendable = 1;
   23298 let opExtendable = 1;
   23299 let isExtentSigned = 0;
   23300 let opExtentBits = 6;
   23301 let opExtentAlign = 0;
   23302 let opNewValue = 2;
   23303 }
   23304 def S4_pstorerhnewfnew_io : HInst<
   23305 (outs),
   23306 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
   23307 "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
   23308 tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
   23309 let Inst{2-2} = 0b0;
   23310 let Inst{12-11} = 0b01;
   23311 let Inst{31-21} = 0b01000110101;
   23312 let isPredicated = 1;
   23313 let isPredicatedFalse = 1;
   23314 let addrMode = BaseImmOffset;
   23315 let accessSize = HalfWordAccess;
   23316 let isNVStore = 1;
   23317 let isPredicatedNew = 1;
   23318 let isNewValue = 1;
   23319 let isRestrictNoSlot1Store = 1;
   23320 let mayStore = 1;
   23321 let CextOpcode = "S2_storerh";
   23322 let InputType = "imm";
   23323 let BaseOpcode = "S2_storerh_io";
   23324 let isExtendable = 1;
   23325 let opExtendable = 2;
   23326 let isExtentSigned = 0;
   23327 let opExtentBits = 7;
   23328 let opExtentAlign = 1;
   23329 let opNewValue = 3;
   23330 }
   23331 def S4_pstorerhnewfnew_rr : HInst<
   23332 (outs),
   23333 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23334 "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23335 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   23336 let Inst{4-3} = 0b01;
   23337 let Inst{31-21} = 0b00110111101;
   23338 let isPredicated = 1;
   23339 let isPredicatedFalse = 1;
   23340 let addrMode = BaseRegOffset;
   23341 let accessSize = HalfWordAccess;
   23342 let isNVStore = 1;
   23343 let isPredicatedNew = 1;
   23344 let isNewValue = 1;
   23345 let isRestrictNoSlot1Store = 1;
   23346 let mayStore = 1;
   23347 let CextOpcode = "S2_storerh";
   23348 let InputType = "reg";
   23349 let BaseOpcode = "S2_storerh_rr";
   23350 let opNewValue = 4;
   23351 }
   23352 def S4_pstorerhnewfnew_zomap : HInst<
   23353 (outs),
   23354 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   23355 "if (!$Pv4.new) memh($Rs32) = $Nt8.new",
   23356 tc_e7d02c66, TypeMAPPING> {
   23357 let isPseudo = 1;
   23358 let isCodeGenOnly = 1;
   23359 let opNewValue = 2;
   23360 }
   23361 def S4_pstorerhnewt_abs : HInst<
   23362 (outs),
   23363 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23364 "if ($Pv4) memh(#$Ii) = $Nt8.new",
   23365 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   23366 let Inst{2-2} = 0b0;
   23367 let Inst{7-7} = 0b1;
   23368 let Inst{13-11} = 0b001;
   23369 let Inst{31-18} = 0b10101111101000;
   23370 let isPredicated = 1;
   23371 let addrMode = Absolute;
   23372 let accessSize = HalfWordAccess;
   23373 let isNVStore = 1;
   23374 let isNewValue = 1;
   23375 let isExtended = 1;
   23376 let isRestrictNoSlot1Store = 1;
   23377 let mayStore = 1;
   23378 let CextOpcode = "S2_storerh";
   23379 let BaseOpcode = "S2_storerhabs";
   23380 let DecoderNamespace = "MustExtend";
   23381 let isExtendable = 1;
   23382 let opExtendable = 1;
   23383 let isExtentSigned = 0;
   23384 let opExtentBits = 6;
   23385 let opExtentAlign = 0;
   23386 let opNewValue = 2;
   23387 }
   23388 def S4_pstorerhnewt_rr : HInst<
   23389 (outs),
   23390 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23391 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23392 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   23393 let Inst{4-3} = 0b01;
   23394 let Inst{31-21} = 0b00110100101;
   23395 let isPredicated = 1;
   23396 let addrMode = BaseRegOffset;
   23397 let accessSize = HalfWordAccess;
   23398 let isNVStore = 1;
   23399 let isNewValue = 1;
   23400 let isRestrictNoSlot1Store = 1;
   23401 let mayStore = 1;
   23402 let CextOpcode = "S2_storerh";
   23403 let InputType = "reg";
   23404 let BaseOpcode = "S2_storerh_rr";
   23405 let opNewValue = 4;
   23406 }
   23407 def S4_pstorerhnewtnew_abs : HInst<
   23408 (outs),
   23409 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23410 "if ($Pv4.new) memh(#$Ii) = $Nt8.new",
   23411 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   23412 let Inst{2-2} = 0b0;
   23413 let Inst{7-7} = 0b1;
   23414 let Inst{13-11} = 0b101;
   23415 let Inst{31-18} = 0b10101111101000;
   23416 let isPredicated = 1;
   23417 let addrMode = Absolute;
   23418 let accessSize = HalfWordAccess;
   23419 let isNVStore = 1;
   23420 let isPredicatedNew = 1;
   23421 let isNewValue = 1;
   23422 let isExtended = 1;
   23423 let isRestrictNoSlot1Store = 1;
   23424 let mayStore = 1;
   23425 let CextOpcode = "S2_storerh";
   23426 let BaseOpcode = "S2_storerhabs";
   23427 let DecoderNamespace = "MustExtend";
   23428 let isExtendable = 1;
   23429 let opExtendable = 1;
   23430 let isExtentSigned = 0;
   23431 let opExtentBits = 6;
   23432 let opExtentAlign = 0;
   23433 let opNewValue = 2;
   23434 }
   23435 def S4_pstorerhnewtnew_io : HInst<
   23436 (outs),
   23437 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
   23438 "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
   23439 tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel {
   23440 let Inst{2-2} = 0b0;
   23441 let Inst{12-11} = 0b01;
   23442 let Inst{31-21} = 0b01000010101;
   23443 let isPredicated = 1;
   23444 let addrMode = BaseImmOffset;
   23445 let accessSize = HalfWordAccess;
   23446 let isNVStore = 1;
   23447 let isPredicatedNew = 1;
   23448 let isNewValue = 1;
   23449 let isRestrictNoSlot1Store = 1;
   23450 let mayStore = 1;
   23451 let CextOpcode = "S2_storerh";
   23452 let InputType = "imm";
   23453 let BaseOpcode = "S2_storerh_io";
   23454 let isExtendable = 1;
   23455 let opExtendable = 2;
   23456 let isExtentSigned = 0;
   23457 let opExtentBits = 7;
   23458 let opExtentAlign = 1;
   23459 let opNewValue = 3;
   23460 }
   23461 def S4_pstorerhnewtnew_rr : HInst<
   23462 (outs),
   23463 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23464 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23465 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   23466 let Inst{4-3} = 0b01;
   23467 let Inst{31-21} = 0b00110110101;
   23468 let isPredicated = 1;
   23469 let addrMode = BaseRegOffset;
   23470 let accessSize = HalfWordAccess;
   23471 let isNVStore = 1;
   23472 let isPredicatedNew = 1;
   23473 let isNewValue = 1;
   23474 let isRestrictNoSlot1Store = 1;
   23475 let mayStore = 1;
   23476 let CextOpcode = "S2_storerh";
   23477 let InputType = "reg";
   23478 let BaseOpcode = "S2_storerh_rr";
   23479 let opNewValue = 4;
   23480 }
   23481 def S4_pstorerhnewtnew_zomap : HInst<
   23482 (outs),
   23483 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   23484 "if ($Pv4.new) memh($Rs32) = $Nt8.new",
   23485 tc_e7d02c66, TypeMAPPING> {
   23486 let isPseudo = 1;
   23487 let isCodeGenOnly = 1;
   23488 let opNewValue = 2;
   23489 }
   23490 def S4_pstorerht_abs : HInst<
   23491 (outs),
   23492 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23493 "if ($Pv4) memh(#$Ii) = $Rt32",
   23494 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   23495 let Inst{2-2} = 0b0;
   23496 let Inst{7-7} = 0b1;
   23497 let Inst{13-13} = 0b0;
   23498 let Inst{31-18} = 0b10101111010000;
   23499 let isPredicated = 1;
   23500 let addrMode = Absolute;
   23501 let accessSize = HalfWordAccess;
   23502 let isExtended = 1;
   23503 let mayStore = 1;
   23504 let CextOpcode = "S2_storerh";
   23505 let BaseOpcode = "S2_storerhabs";
   23506 let isNVStorable = 1;
   23507 let DecoderNamespace = "MustExtend";
   23508 let isExtendable = 1;
   23509 let opExtendable = 1;
   23510 let isExtentSigned = 0;
   23511 let opExtentBits = 6;
   23512 let opExtentAlign = 0;
   23513 }
   23514 def S4_pstorerht_rr : HInst<
   23515 (outs),
   23516 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23517 "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
   23518 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   23519 let Inst{31-21} = 0b00110100010;
   23520 let isPredicated = 1;
   23521 let addrMode = BaseRegOffset;
   23522 let accessSize = HalfWordAccess;
   23523 let mayStore = 1;
   23524 let CextOpcode = "S2_storerh";
   23525 let InputType = "reg";
   23526 let BaseOpcode = "S2_storerh_rr";
   23527 let isNVStorable = 1;
   23528 }
   23529 def S4_pstorerhtnew_abs : HInst<
   23530 (outs),
   23531 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23532 "if ($Pv4.new) memh(#$Ii) = $Rt32",
   23533 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   23534 let Inst{2-2} = 0b0;
   23535 let Inst{7-7} = 0b1;
   23536 let Inst{13-13} = 0b1;
   23537 let Inst{31-18} = 0b10101111010000;
   23538 let isPredicated = 1;
   23539 let addrMode = Absolute;
   23540 let accessSize = HalfWordAccess;
   23541 let isPredicatedNew = 1;
   23542 let isExtended = 1;
   23543 let mayStore = 1;
   23544 let CextOpcode = "S2_storerh";
   23545 let BaseOpcode = "S2_storerhabs";
   23546 let isNVStorable = 1;
   23547 let DecoderNamespace = "MustExtend";
   23548 let isExtendable = 1;
   23549 let opExtendable = 1;
   23550 let isExtentSigned = 0;
   23551 let opExtentBits = 6;
   23552 let opExtentAlign = 0;
   23553 }
   23554 def S4_pstorerhtnew_io : HInst<
   23555 (outs),
   23556 (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
   23557 "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
   23558 tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
   23559 let Inst{2-2} = 0b0;
   23560 let Inst{31-21} = 0b01000010010;
   23561 let isPredicated = 1;
   23562 let addrMode = BaseImmOffset;
   23563 let accessSize = HalfWordAccess;
   23564 let isPredicatedNew = 1;
   23565 let mayStore = 1;
   23566 let CextOpcode = "S2_storerh";
   23567 let InputType = "imm";
   23568 let BaseOpcode = "S2_storerh_io";
   23569 let isNVStorable = 1;
   23570 let isExtendable = 1;
   23571 let opExtendable = 2;
   23572 let isExtentSigned = 0;
   23573 let opExtentBits = 7;
   23574 let opExtentAlign = 1;
   23575 }
   23576 def S4_pstorerhtnew_rr : HInst<
   23577 (outs),
   23578 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23579 "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
   23580 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   23581 let Inst{31-21} = 0b00110110010;
   23582 let isPredicated = 1;
   23583 let addrMode = BaseRegOffset;
   23584 let accessSize = HalfWordAccess;
   23585 let isPredicatedNew = 1;
   23586 let mayStore = 1;
   23587 let CextOpcode = "S2_storerh";
   23588 let InputType = "reg";
   23589 let BaseOpcode = "S2_storerh_rr";
   23590 let isNVStorable = 1;
   23591 }
   23592 def S4_pstorerhtnew_zomap : HInst<
   23593 (outs),
   23594 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   23595 "if ($Pv4.new) memh($Rs32) = $Rt32",
   23596 tc_f86c328a, TypeMAPPING> {
   23597 let isPseudo = 1;
   23598 let isCodeGenOnly = 1;
   23599 }
   23600 def S4_pstorerif_abs : HInst<
   23601 (outs),
   23602 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23603 "if (!$Pv4) memw(#$Ii) = $Rt32",
   23604 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   23605 let Inst{2-2} = 0b1;
   23606 let Inst{7-7} = 0b1;
   23607 let Inst{13-13} = 0b0;
   23608 let Inst{31-18} = 0b10101111100000;
   23609 let isPredicated = 1;
   23610 let isPredicatedFalse = 1;
   23611 let addrMode = Absolute;
   23612 let accessSize = WordAccess;
   23613 let isExtended = 1;
   23614 let mayStore = 1;
   23615 let CextOpcode = "S2_storeri";
   23616 let BaseOpcode = "S2_storeriabs";
   23617 let isNVStorable = 1;
   23618 let DecoderNamespace = "MustExtend";
   23619 let isExtendable = 1;
   23620 let opExtendable = 1;
   23621 let isExtentSigned = 0;
   23622 let opExtentBits = 6;
   23623 let opExtentAlign = 0;
   23624 }
   23625 def S4_pstorerif_rr : HInst<
   23626 (outs),
   23627 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23628 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
   23629 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   23630 let Inst{31-21} = 0b00110101100;
   23631 let isPredicated = 1;
   23632 let isPredicatedFalse = 1;
   23633 let addrMode = BaseRegOffset;
   23634 let accessSize = WordAccess;
   23635 let mayStore = 1;
   23636 let CextOpcode = "S2_storeri";
   23637 let InputType = "reg";
   23638 let BaseOpcode = "S2_storeri_rr";
   23639 let isNVStorable = 1;
   23640 }
   23641 def S4_pstorerifnew_abs : HInst<
   23642 (outs),
   23643 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23644 "if (!$Pv4.new) memw(#$Ii) = $Rt32",
   23645 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   23646 let Inst{2-2} = 0b1;
   23647 let Inst{7-7} = 0b1;
   23648 let Inst{13-13} = 0b1;
   23649 let Inst{31-18} = 0b10101111100000;
   23650 let isPredicated = 1;
   23651 let isPredicatedFalse = 1;
   23652 let addrMode = Absolute;
   23653 let accessSize = WordAccess;
   23654 let isPredicatedNew = 1;
   23655 let isExtended = 1;
   23656 let mayStore = 1;
   23657 let CextOpcode = "S2_storeri";
   23658 let BaseOpcode = "S2_storeriabs";
   23659 let isNVStorable = 1;
   23660 let DecoderNamespace = "MustExtend";
   23661 let isExtendable = 1;
   23662 let opExtendable = 1;
   23663 let isExtentSigned = 0;
   23664 let opExtentBits = 6;
   23665 let opExtentAlign = 0;
   23666 }
   23667 def S4_pstorerifnew_io : HInst<
   23668 (outs),
   23669 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   23670 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
   23671 tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
   23672 let Inst{2-2} = 0b0;
   23673 let Inst{31-21} = 0b01000110100;
   23674 let isPredicated = 1;
   23675 let isPredicatedFalse = 1;
   23676 let addrMode = BaseImmOffset;
   23677 let accessSize = WordAccess;
   23678 let isPredicatedNew = 1;
   23679 let mayStore = 1;
   23680 let CextOpcode = "S2_storeri";
   23681 let InputType = "imm";
   23682 let BaseOpcode = "S2_storeri_io";
   23683 let isNVStorable = 1;
   23684 let isExtendable = 1;
   23685 let opExtendable = 2;
   23686 let isExtentSigned = 0;
   23687 let opExtentBits = 8;
   23688 let opExtentAlign = 2;
   23689 }
   23690 def S4_pstorerifnew_rr : HInst<
   23691 (outs),
   23692 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   23693 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
   23694 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   23695 let Inst{31-21} = 0b00110111100;
   23696 let isPredicated = 1;
   23697 let isPredicatedFalse = 1;
   23698 let addrMode = BaseRegOffset;
   23699 let accessSize = WordAccess;
   23700 let isPredicatedNew = 1;
   23701 let mayStore = 1;
   23702 let CextOpcode = "S2_storeri";
   23703 let InputType = "reg";
   23704 let BaseOpcode = "S2_storeri_rr";
   23705 let isNVStorable = 1;
   23706 }
   23707 def S4_pstorerifnew_zomap : HInst<
   23708 (outs),
   23709 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   23710 "if (!$Pv4.new) memw($Rs32) = $Rt32",
   23711 tc_f86c328a, TypeMAPPING> {
   23712 let isPseudo = 1;
   23713 let isCodeGenOnly = 1;
   23714 }
   23715 def S4_pstorerinewf_abs : HInst<
   23716 (outs),
   23717 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23718 "if (!$Pv4) memw(#$Ii) = $Nt8.new",
   23719 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   23720 let Inst{2-2} = 0b1;
   23721 let Inst{7-7} = 0b1;
   23722 let Inst{13-11} = 0b010;
   23723 let Inst{31-18} = 0b10101111101000;
   23724 let isPredicated = 1;
   23725 let isPredicatedFalse = 1;
   23726 let addrMode = Absolute;
   23727 let accessSize = WordAccess;
   23728 let isNVStore = 1;
   23729 let isNewValue = 1;
   23730 let isExtended = 1;
   23731 let isRestrictNoSlot1Store = 1;
   23732 let mayStore = 1;
   23733 let CextOpcode = "S2_storeri";
   23734 let BaseOpcode = "S2_storeriabs";
   23735 let DecoderNamespace = "MustExtend";
   23736 let isExtendable = 1;
   23737 let opExtendable = 1;
   23738 let isExtentSigned = 0;
   23739 let opExtentBits = 6;
   23740 let opExtentAlign = 0;
   23741 let opNewValue = 2;
   23742 }
   23743 def S4_pstorerinewf_rr : HInst<
   23744 (outs),
   23745 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23746 "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23747 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   23748 let Inst{4-3} = 0b10;
   23749 let Inst{31-21} = 0b00110101101;
   23750 let isPredicated = 1;
   23751 let isPredicatedFalse = 1;
   23752 let addrMode = BaseRegOffset;
   23753 let accessSize = WordAccess;
   23754 let isNVStore = 1;
   23755 let isNewValue = 1;
   23756 let isRestrictNoSlot1Store = 1;
   23757 let mayStore = 1;
   23758 let CextOpcode = "S2_storeri";
   23759 let InputType = "reg";
   23760 let BaseOpcode = "S2_storeri_rr";
   23761 let opNewValue = 4;
   23762 }
   23763 def S4_pstorerinewfnew_abs : HInst<
   23764 (outs),
   23765 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23766 "if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
   23767 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   23768 let Inst{2-2} = 0b1;
   23769 let Inst{7-7} = 0b1;
   23770 let Inst{13-11} = 0b110;
   23771 let Inst{31-18} = 0b10101111101000;
   23772 let isPredicated = 1;
   23773 let isPredicatedFalse = 1;
   23774 let addrMode = Absolute;
   23775 let accessSize = WordAccess;
   23776 let isNVStore = 1;
   23777 let isPredicatedNew = 1;
   23778 let isNewValue = 1;
   23779 let isExtended = 1;
   23780 let isRestrictNoSlot1Store = 1;
   23781 let mayStore = 1;
   23782 let CextOpcode = "S2_storeri";
   23783 let BaseOpcode = "S2_storeriabs";
   23784 let DecoderNamespace = "MustExtend";
   23785 let isExtendable = 1;
   23786 let opExtendable = 1;
   23787 let isExtentSigned = 0;
   23788 let opExtentBits = 6;
   23789 let opExtentAlign = 0;
   23790 let opNewValue = 2;
   23791 }
   23792 def S4_pstorerinewfnew_io : HInst<
   23793 (outs),
   23794 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
   23795 "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
   23796 tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
   23797 let Inst{2-2} = 0b0;
   23798 let Inst{12-11} = 0b10;
   23799 let Inst{31-21} = 0b01000110101;
   23800 let isPredicated = 1;
   23801 let isPredicatedFalse = 1;
   23802 let addrMode = BaseImmOffset;
   23803 let accessSize = WordAccess;
   23804 let isNVStore = 1;
   23805 let isPredicatedNew = 1;
   23806 let isNewValue = 1;
   23807 let isRestrictNoSlot1Store = 1;
   23808 let mayStore = 1;
   23809 let CextOpcode = "S2_storeri";
   23810 let InputType = "imm";
   23811 let BaseOpcode = "S2_storeri_io";
   23812 let isExtendable = 1;
   23813 let opExtendable = 2;
   23814 let isExtentSigned = 0;
   23815 let opExtentBits = 8;
   23816 let opExtentAlign = 2;
   23817 let opNewValue = 3;
   23818 }
   23819 def S4_pstorerinewfnew_rr : HInst<
   23820 (outs),
   23821 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23822 "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23823 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   23824 let Inst{4-3} = 0b10;
   23825 let Inst{31-21} = 0b00110111101;
   23826 let isPredicated = 1;
   23827 let isPredicatedFalse = 1;
   23828 let addrMode = BaseRegOffset;
   23829 let accessSize = WordAccess;
   23830 let isNVStore = 1;
   23831 let isPredicatedNew = 1;
   23832 let isNewValue = 1;
   23833 let isRestrictNoSlot1Store = 1;
   23834 let mayStore = 1;
   23835 let CextOpcode = "S2_storeri";
   23836 let InputType = "reg";
   23837 let BaseOpcode = "S2_storeri_rr";
   23838 let opNewValue = 4;
   23839 }
   23840 def S4_pstorerinewfnew_zomap : HInst<
   23841 (outs),
   23842 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   23843 "if (!$Pv4.new) memw($Rs32) = $Nt8.new",
   23844 tc_e7d02c66, TypeMAPPING> {
   23845 let isPseudo = 1;
   23846 let isCodeGenOnly = 1;
   23847 let opNewValue = 2;
   23848 }
   23849 def S4_pstorerinewt_abs : HInst<
   23850 (outs),
   23851 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23852 "if ($Pv4) memw(#$Ii) = $Nt8.new",
   23853 tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel {
   23854 let Inst{2-2} = 0b0;
   23855 let Inst{7-7} = 0b1;
   23856 let Inst{13-11} = 0b010;
   23857 let Inst{31-18} = 0b10101111101000;
   23858 let isPredicated = 1;
   23859 let addrMode = Absolute;
   23860 let accessSize = WordAccess;
   23861 let isNVStore = 1;
   23862 let isNewValue = 1;
   23863 let isExtended = 1;
   23864 let isRestrictNoSlot1Store = 1;
   23865 let mayStore = 1;
   23866 let CextOpcode = "S2_storeri";
   23867 let BaseOpcode = "S2_storeriabs";
   23868 let DecoderNamespace = "MustExtend";
   23869 let isExtendable = 1;
   23870 let opExtendable = 1;
   23871 let isExtentSigned = 0;
   23872 let opExtentBits = 6;
   23873 let opExtentAlign = 0;
   23874 let opNewValue = 2;
   23875 }
   23876 def S4_pstorerinewt_rr : HInst<
   23877 (outs),
   23878 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23879 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23880 tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel {
   23881 let Inst{4-3} = 0b10;
   23882 let Inst{31-21} = 0b00110100101;
   23883 let isPredicated = 1;
   23884 let addrMode = BaseRegOffset;
   23885 let accessSize = WordAccess;
   23886 let isNVStore = 1;
   23887 let isNewValue = 1;
   23888 let isRestrictNoSlot1Store = 1;
   23889 let mayStore = 1;
   23890 let CextOpcode = "S2_storeri";
   23891 let InputType = "reg";
   23892 let BaseOpcode = "S2_storeri_rr";
   23893 let opNewValue = 4;
   23894 }
   23895 def S4_pstorerinewtnew_abs : HInst<
   23896 (outs),
   23897 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
   23898 "if ($Pv4.new) memw(#$Ii) = $Nt8.new",
   23899 tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel {
   23900 let Inst{2-2} = 0b0;
   23901 let Inst{7-7} = 0b1;
   23902 let Inst{13-11} = 0b110;
   23903 let Inst{31-18} = 0b10101111101000;
   23904 let isPredicated = 1;
   23905 let addrMode = Absolute;
   23906 let accessSize = WordAccess;
   23907 let isNVStore = 1;
   23908 let isPredicatedNew = 1;
   23909 let isNewValue = 1;
   23910 let isExtended = 1;
   23911 let isRestrictNoSlot1Store = 1;
   23912 let mayStore = 1;
   23913 let CextOpcode = "S2_storeri";
   23914 let BaseOpcode = "S2_storeriabs";
   23915 let DecoderNamespace = "MustExtend";
   23916 let isExtendable = 1;
   23917 let opExtendable = 1;
   23918 let isExtentSigned = 0;
   23919 let opExtentBits = 6;
   23920 let opExtentAlign = 0;
   23921 let opNewValue = 2;
   23922 }
   23923 def S4_pstorerinewtnew_io : HInst<
   23924 (outs),
   23925 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
   23926 "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
   23927 tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
   23928 let Inst{2-2} = 0b0;
   23929 let Inst{12-11} = 0b10;
   23930 let Inst{31-21} = 0b01000010101;
   23931 let isPredicated = 1;
   23932 let addrMode = BaseImmOffset;
   23933 let accessSize = WordAccess;
   23934 let isNVStore = 1;
   23935 let isPredicatedNew = 1;
   23936 let isNewValue = 1;
   23937 let isRestrictNoSlot1Store = 1;
   23938 let mayStore = 1;
   23939 let CextOpcode = "S2_storeri";
   23940 let InputType = "imm";
   23941 let BaseOpcode = "S2_storeri_io";
   23942 let isExtendable = 1;
   23943 let opExtendable = 2;
   23944 let isExtentSigned = 0;
   23945 let opExtentBits = 8;
   23946 let opExtentAlign = 2;
   23947 let opNewValue = 3;
   23948 }
   23949 def S4_pstorerinewtnew_rr : HInst<
   23950 (outs),
   23951 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   23952 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   23953 tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel {
   23954 let Inst{4-3} = 0b10;
   23955 let Inst{31-21} = 0b00110110101;
   23956 let isPredicated = 1;
   23957 let addrMode = BaseRegOffset;
   23958 let accessSize = WordAccess;
   23959 let isNVStore = 1;
   23960 let isPredicatedNew = 1;
   23961 let isNewValue = 1;
   23962 let isRestrictNoSlot1Store = 1;
   23963 let mayStore = 1;
   23964 let CextOpcode = "S2_storeri";
   23965 let InputType = "reg";
   23966 let BaseOpcode = "S2_storeri_rr";
   23967 let opNewValue = 4;
   23968 }
   23969 def S4_pstorerinewtnew_zomap : HInst<
   23970 (outs),
   23971 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
   23972 "if ($Pv4.new) memw($Rs32) = $Nt8.new",
   23973 tc_e7d02c66, TypeMAPPING> {
   23974 let isPseudo = 1;
   23975 let isCodeGenOnly = 1;
   23976 let opNewValue = 2;
   23977 }
   23978 def S4_pstorerit_abs : HInst<
   23979 (outs),
   23980 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   23981 "if ($Pv4) memw(#$Ii) = $Rt32",
   23982 tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel {
   23983 let Inst{2-2} = 0b0;
   23984 let Inst{7-7} = 0b1;
   23985 let Inst{13-13} = 0b0;
   23986 let Inst{31-18} = 0b10101111100000;
   23987 let isPredicated = 1;
   23988 let addrMode = Absolute;
   23989 let accessSize = WordAccess;
   23990 let isExtended = 1;
   23991 let mayStore = 1;
   23992 let CextOpcode = "S2_storeri";
   23993 let BaseOpcode = "S2_storeriabs";
   23994 let isNVStorable = 1;
   23995 let DecoderNamespace = "MustExtend";
   23996 let isExtendable = 1;
   23997 let opExtendable = 1;
   23998 let isExtentSigned = 0;
   23999 let opExtentBits = 6;
   24000 let opExtentAlign = 0;
   24001 }
   24002 def S4_pstorerit_rr : HInst<
   24003 (outs),
   24004 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24005 "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
   24006 tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel {
   24007 let Inst{31-21} = 0b00110100100;
   24008 let isPredicated = 1;
   24009 let addrMode = BaseRegOffset;
   24010 let accessSize = WordAccess;
   24011 let mayStore = 1;
   24012 let CextOpcode = "S2_storeri";
   24013 let InputType = "reg";
   24014 let BaseOpcode = "S2_storeri_rr";
   24015 let isNVStorable = 1;
   24016 }
   24017 def S4_pstoreritnew_abs : HInst<
   24018 (outs),
   24019 (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
   24020 "if ($Pv4.new) memw(#$Ii) = $Rt32",
   24021 tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel {
   24022 let Inst{2-2} = 0b0;
   24023 let Inst{7-7} = 0b1;
   24024 let Inst{13-13} = 0b1;
   24025 let Inst{31-18} = 0b10101111100000;
   24026 let isPredicated = 1;
   24027 let addrMode = Absolute;
   24028 let accessSize = WordAccess;
   24029 let isPredicatedNew = 1;
   24030 let isExtended = 1;
   24031 let mayStore = 1;
   24032 let CextOpcode = "S2_storeri";
   24033 let BaseOpcode = "S2_storeriabs";
   24034 let isNVStorable = 1;
   24035 let DecoderNamespace = "MustExtend";
   24036 let isExtendable = 1;
   24037 let opExtendable = 1;
   24038 let isExtentSigned = 0;
   24039 let opExtentBits = 6;
   24040 let opExtentAlign = 0;
   24041 }
   24042 def S4_pstoreritnew_io : HInst<
   24043 (outs),
   24044 (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
   24045 "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
   24046 tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel {
   24047 let Inst{2-2} = 0b0;
   24048 let Inst{31-21} = 0b01000010100;
   24049 let isPredicated = 1;
   24050 let addrMode = BaseImmOffset;
   24051 let accessSize = WordAccess;
   24052 let isPredicatedNew = 1;
   24053 let mayStore = 1;
   24054 let CextOpcode = "S2_storeri";
   24055 let InputType = "imm";
   24056 let BaseOpcode = "S2_storeri_io";
   24057 let isNVStorable = 1;
   24058 let isExtendable = 1;
   24059 let opExtendable = 2;
   24060 let isExtentSigned = 0;
   24061 let opExtentBits = 8;
   24062 let opExtentAlign = 2;
   24063 }
   24064 def S4_pstoreritnew_rr : HInst<
   24065 (outs),
   24066 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24067 "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
   24068 tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel {
   24069 let Inst{31-21} = 0b00110110100;
   24070 let isPredicated = 1;
   24071 let addrMode = BaseRegOffset;
   24072 let accessSize = WordAccess;
   24073 let isPredicatedNew = 1;
   24074 let mayStore = 1;
   24075 let CextOpcode = "S2_storeri";
   24076 let InputType = "reg";
   24077 let BaseOpcode = "S2_storeri_rr";
   24078 let isNVStorable = 1;
   24079 }
   24080 def S4_pstoreritnew_zomap : HInst<
   24081 (outs),
   24082 (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
   24083 "if ($Pv4.new) memw($Rs32) = $Rt32",
   24084 tc_f86c328a, TypeMAPPING> {
   24085 let isPseudo = 1;
   24086 let isCodeGenOnly = 1;
   24087 }
   24088 def S4_stored_locked : HInst<
   24089 (outs PredRegs:$Pd4),
   24090 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   24091 "memd_locked($Rs32,$Pd4) = $Rtt32",
   24092 tc_1372bca1, TypeST>, Enc_d7dc10 {
   24093 let Inst{7-2} = 0b000000;
   24094 let Inst{13-13} = 0b0;
   24095 let Inst{31-21} = 0b10100000111;
   24096 let accessSize = DoubleWordAccess;
   24097 let isPredicateLate = 1;
   24098 let isSoloAX = 1;
   24099 let mayStore = 1;
   24100 }
   24101 def S4_storeirb_io : HInst<
   24102 (outs),
   24103 (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
   24104 "memb($Rs32+#$Ii) = #$II",
   24105 tc_05b6c987, TypeST>, Enc_8203bb, PredNewRel {
   24106 let Inst{31-21} = 0b00111100000;
   24107 let addrMode = BaseImmOffset;
   24108 let accessSize = ByteAccess;
   24109 let mayStore = 1;
   24110 let CextOpcode = "S2_storerb";
   24111 let InputType = "imm";
   24112 let BaseOpcode = "S4_storeirb_io";
   24113 let isPredicable = 1;
   24114 let isExtendable = 1;
   24115 let opExtendable = 2;
   24116 let isExtentSigned = 1;
   24117 let opExtentBits = 8;
   24118 let opExtentAlign = 0;
   24119 }
   24120 def S4_storeirb_zomap : HInst<
   24121 (outs),
   24122 (ins IntRegs:$Rs32, s8_0Imm:$II),
   24123 "memb($Rs32) = #$II",
   24124 tc_05b6c987, TypeMAPPING> {
   24125 let isPseudo = 1;
   24126 let isCodeGenOnly = 1;
   24127 }
   24128 def S4_storeirbf_io : HInst<
   24129 (outs),
   24130 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
   24131 "if (!$Pv4) memb($Rs32+#$Ii) = #$II",
   24132 tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
   24133 let Inst{31-21} = 0b00111000100;
   24134 let isPredicated = 1;
   24135 let isPredicatedFalse = 1;
   24136 let addrMode = BaseImmOffset;
   24137 let accessSize = ByteAccess;
   24138 let mayStore = 1;
   24139 let CextOpcode = "S2_storerb";
   24140 let InputType = "imm";
   24141 let BaseOpcode = "S4_storeirb_io";
   24142 let isExtendable = 1;
   24143 let opExtendable = 3;
   24144 let isExtentSigned = 1;
   24145 let opExtentBits = 6;
   24146 let opExtentAlign = 0;
   24147 }
   24148 def S4_storeirbf_zomap : HInst<
   24149 (outs),
   24150 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24151 "if (!$Pv4) memb($Rs32) = #$II",
   24152 tc_8b15472a, TypeMAPPING> {
   24153 let isPseudo = 1;
   24154 let isCodeGenOnly = 1;
   24155 }
   24156 def S4_storeirbfnew_io : HInst<
   24157 (outs),
   24158 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
   24159 "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
   24160 tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
   24161 let Inst{31-21} = 0b00111001100;
   24162 let isPredicated = 1;
   24163 let isPredicatedFalse = 1;
   24164 let addrMode = BaseImmOffset;
   24165 let accessSize = ByteAccess;
   24166 let isPredicatedNew = 1;
   24167 let mayStore = 1;
   24168 let CextOpcode = "S2_storerb";
   24169 let InputType = "imm";
   24170 let BaseOpcode = "S4_storeirb_io";
   24171 let isExtendable = 1;
   24172 let opExtendable = 3;
   24173 let isExtentSigned = 1;
   24174 let opExtentBits = 6;
   24175 let opExtentAlign = 0;
   24176 }
   24177 def S4_storeirbfnew_zomap : HInst<
   24178 (outs),
   24179 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24180 "if (!$Pv4.new) memb($Rs32) = #$II",
   24181 tc_f86c328a, TypeMAPPING> {
   24182 let isPseudo = 1;
   24183 let isCodeGenOnly = 1;
   24184 }
   24185 def S4_storeirbt_io : HInst<
   24186 (outs),
   24187 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
   24188 "if ($Pv4) memb($Rs32+#$Ii) = #$II",
   24189 tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel {
   24190 let Inst{31-21} = 0b00111000000;
   24191 let isPredicated = 1;
   24192 let addrMode = BaseImmOffset;
   24193 let accessSize = ByteAccess;
   24194 let mayStore = 1;
   24195 let CextOpcode = "S2_storerb";
   24196 let InputType = "imm";
   24197 let BaseOpcode = "S4_storeirb_io";
   24198 let isExtendable = 1;
   24199 let opExtendable = 3;
   24200 let isExtentSigned = 1;
   24201 let opExtentBits = 6;
   24202 let opExtentAlign = 0;
   24203 }
   24204 def S4_storeirbt_zomap : HInst<
   24205 (outs),
   24206 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24207 "if ($Pv4) memb($Rs32) = #$II",
   24208 tc_8b15472a, TypeMAPPING> {
   24209 let isPseudo = 1;
   24210 let isCodeGenOnly = 1;
   24211 }
   24212 def S4_storeirbtnew_io : HInst<
   24213 (outs),
   24214 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
   24215 "if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
   24216 tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel {
   24217 let Inst{31-21} = 0b00111001000;
   24218 let isPredicated = 1;
   24219 let addrMode = BaseImmOffset;
   24220 let accessSize = ByteAccess;
   24221 let isPredicatedNew = 1;
   24222 let mayStore = 1;
   24223 let CextOpcode = "S2_storerb";
   24224 let InputType = "imm";
   24225 let BaseOpcode = "S4_storeirb_io";
   24226 let isExtendable = 1;
   24227 let opExtendable = 3;
   24228 let isExtentSigned = 1;
   24229 let opExtentBits = 6;
   24230 let opExtentAlign = 0;
   24231 }
   24232 def S4_storeirbtnew_zomap : HInst<
   24233 (outs),
   24234 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24235 "if ($Pv4.new) memb($Rs32) = #$II",
   24236 tc_f86c328a, TypeMAPPING> {
   24237 let isPseudo = 1;
   24238 let isCodeGenOnly = 1;
   24239 }
   24240 def S4_storeirh_io : HInst<
   24241 (outs),
   24242 (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
   24243 "memh($Rs32+#$Ii) = #$II",
   24244 tc_05b6c987, TypeST>, Enc_a803e0, PredNewRel {
   24245 let Inst{31-21} = 0b00111100001;
   24246 let addrMode = BaseImmOffset;
   24247 let accessSize = HalfWordAccess;
   24248 let mayStore = 1;
   24249 let CextOpcode = "S2_storerh";
   24250 let InputType = "imm";
   24251 let BaseOpcode = "S4_storeirh_io";
   24252 let isPredicable = 1;
   24253 let isExtendable = 1;
   24254 let opExtendable = 2;
   24255 let isExtentSigned = 1;
   24256 let opExtentBits = 8;
   24257 let opExtentAlign = 0;
   24258 }
   24259 def S4_storeirh_zomap : HInst<
   24260 (outs),
   24261 (ins IntRegs:$Rs32, s8_0Imm:$II),
   24262 "memh($Rs32) = #$II",
   24263 tc_05b6c987, TypeMAPPING> {
   24264 let isPseudo = 1;
   24265 let isCodeGenOnly = 1;
   24266 }
   24267 def S4_storeirhf_io : HInst<
   24268 (outs),
   24269 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
   24270 "if (!$Pv4) memh($Rs32+#$Ii) = #$II",
   24271 tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
   24272 let Inst{31-21} = 0b00111000101;
   24273 let isPredicated = 1;
   24274 let isPredicatedFalse = 1;
   24275 let addrMode = BaseImmOffset;
   24276 let accessSize = HalfWordAccess;
   24277 let mayStore = 1;
   24278 let CextOpcode = "S2_storerh";
   24279 let InputType = "imm";
   24280 let BaseOpcode = "S4_storeirh_io";
   24281 let isExtendable = 1;
   24282 let opExtendable = 3;
   24283 let isExtentSigned = 1;
   24284 let opExtentBits = 6;
   24285 let opExtentAlign = 0;
   24286 }
   24287 def S4_storeirhf_zomap : HInst<
   24288 (outs),
   24289 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24290 "if (!$Pv4) memh($Rs32) = #$II",
   24291 tc_8b15472a, TypeMAPPING> {
   24292 let isPseudo = 1;
   24293 let isCodeGenOnly = 1;
   24294 }
   24295 def S4_storeirhfnew_io : HInst<
   24296 (outs),
   24297 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
   24298 "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
   24299 tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
   24300 let Inst{31-21} = 0b00111001101;
   24301 let isPredicated = 1;
   24302 let isPredicatedFalse = 1;
   24303 let addrMode = BaseImmOffset;
   24304 let accessSize = HalfWordAccess;
   24305 let isPredicatedNew = 1;
   24306 let mayStore = 1;
   24307 let CextOpcode = "S2_storerh";
   24308 let InputType = "imm";
   24309 let BaseOpcode = "S4_storeirh_io";
   24310 let isExtendable = 1;
   24311 let opExtendable = 3;
   24312 let isExtentSigned = 1;
   24313 let opExtentBits = 6;
   24314 let opExtentAlign = 0;
   24315 }
   24316 def S4_storeirhfnew_zomap : HInst<
   24317 (outs),
   24318 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24319 "if (!$Pv4.new) memh($Rs32) = #$II",
   24320 tc_f86c328a, TypeMAPPING> {
   24321 let isPseudo = 1;
   24322 let isCodeGenOnly = 1;
   24323 }
   24324 def S4_storeirht_io : HInst<
   24325 (outs),
   24326 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
   24327 "if ($Pv4) memh($Rs32+#$Ii) = #$II",
   24328 tc_8b15472a, TypeST>, Enc_f20719, PredNewRel {
   24329 let Inst{31-21} = 0b00111000001;
   24330 let isPredicated = 1;
   24331 let addrMode = BaseImmOffset;
   24332 let accessSize = HalfWordAccess;
   24333 let mayStore = 1;
   24334 let CextOpcode = "S2_storerh";
   24335 let InputType = "imm";
   24336 let BaseOpcode = "S4_storeirh_io";
   24337 let isExtendable = 1;
   24338 let opExtendable = 3;
   24339 let isExtentSigned = 1;
   24340 let opExtentBits = 6;
   24341 let opExtentAlign = 0;
   24342 }
   24343 def S4_storeirht_zomap : HInst<
   24344 (outs),
   24345 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24346 "if ($Pv4) memh($Rs32) = #$II",
   24347 tc_8b15472a, TypeMAPPING> {
   24348 let isPseudo = 1;
   24349 let isCodeGenOnly = 1;
   24350 }
   24351 def S4_storeirhtnew_io : HInst<
   24352 (outs),
   24353 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
   24354 "if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
   24355 tc_f86c328a, TypeST>, Enc_f20719, PredNewRel {
   24356 let Inst{31-21} = 0b00111001001;
   24357 let isPredicated = 1;
   24358 let addrMode = BaseImmOffset;
   24359 let accessSize = HalfWordAccess;
   24360 let isPredicatedNew = 1;
   24361 let mayStore = 1;
   24362 let CextOpcode = "S2_storerh";
   24363 let InputType = "imm";
   24364 let BaseOpcode = "S4_storeirh_io";
   24365 let isExtendable = 1;
   24366 let opExtendable = 3;
   24367 let isExtentSigned = 1;
   24368 let opExtentBits = 6;
   24369 let opExtentAlign = 0;
   24370 }
   24371 def S4_storeirhtnew_zomap : HInst<
   24372 (outs),
   24373 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24374 "if ($Pv4.new) memh($Rs32) = #$II",
   24375 tc_f86c328a, TypeMAPPING> {
   24376 let isPseudo = 1;
   24377 let isCodeGenOnly = 1;
   24378 }
   24379 def S4_storeiri_io : HInst<
   24380 (outs),
   24381 (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
   24382 "memw($Rs32+#$Ii) = #$II",
   24383 tc_05b6c987, TypeST>, Enc_f37377, PredNewRel {
   24384 let Inst{31-21} = 0b00111100010;
   24385 let addrMode = BaseImmOffset;
   24386 let accessSize = WordAccess;
   24387 let mayStore = 1;
   24388 let CextOpcode = "S2_storeri";
   24389 let InputType = "imm";
   24390 let BaseOpcode = "S4_storeiri_io";
   24391 let isPredicable = 1;
   24392 let isExtendable = 1;
   24393 let opExtendable = 2;
   24394 let isExtentSigned = 1;
   24395 let opExtentBits = 8;
   24396 let opExtentAlign = 0;
   24397 }
   24398 def S4_storeiri_zomap : HInst<
   24399 (outs),
   24400 (ins IntRegs:$Rs32, s8_0Imm:$II),
   24401 "memw($Rs32) = #$II",
   24402 tc_05b6c987, TypeMAPPING> {
   24403 let isPseudo = 1;
   24404 let isCodeGenOnly = 1;
   24405 }
   24406 def S4_storeirif_io : HInst<
   24407 (outs),
   24408 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
   24409 "if (!$Pv4) memw($Rs32+#$Ii) = #$II",
   24410 tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
   24411 let Inst{31-21} = 0b00111000110;
   24412 let isPredicated = 1;
   24413 let isPredicatedFalse = 1;
   24414 let addrMode = BaseImmOffset;
   24415 let accessSize = WordAccess;
   24416 let mayStore = 1;
   24417 let CextOpcode = "S2_storeri";
   24418 let InputType = "imm";
   24419 let BaseOpcode = "S4_storeiri_io";
   24420 let isExtendable = 1;
   24421 let opExtendable = 3;
   24422 let isExtentSigned = 1;
   24423 let opExtentBits = 6;
   24424 let opExtentAlign = 0;
   24425 }
   24426 def S4_storeirif_zomap : HInst<
   24427 (outs),
   24428 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24429 "if (!$Pv4) memw($Rs32) = #$II",
   24430 tc_8b15472a, TypeMAPPING> {
   24431 let isPseudo = 1;
   24432 let isCodeGenOnly = 1;
   24433 }
   24434 def S4_storeirifnew_io : HInst<
   24435 (outs),
   24436 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
   24437 "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
   24438 tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
   24439 let Inst{31-21} = 0b00111001110;
   24440 let isPredicated = 1;
   24441 let isPredicatedFalse = 1;
   24442 let addrMode = BaseImmOffset;
   24443 let accessSize = WordAccess;
   24444 let isPredicatedNew = 1;
   24445 let mayStore = 1;
   24446 let CextOpcode = "S2_storeri";
   24447 let InputType = "imm";
   24448 let BaseOpcode = "S4_storeiri_io";
   24449 let isExtendable = 1;
   24450 let opExtendable = 3;
   24451 let isExtentSigned = 1;
   24452 let opExtentBits = 6;
   24453 let opExtentAlign = 0;
   24454 }
   24455 def S4_storeirifnew_zomap : HInst<
   24456 (outs),
   24457 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24458 "if (!$Pv4.new) memw($Rs32) = #$II",
   24459 tc_f86c328a, TypeMAPPING> {
   24460 let isPseudo = 1;
   24461 let isCodeGenOnly = 1;
   24462 }
   24463 def S4_storeirit_io : HInst<
   24464 (outs),
   24465 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
   24466 "if ($Pv4) memw($Rs32+#$Ii) = #$II",
   24467 tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel {
   24468 let Inst{31-21} = 0b00111000010;
   24469 let isPredicated = 1;
   24470 let addrMode = BaseImmOffset;
   24471 let accessSize = WordAccess;
   24472 let mayStore = 1;
   24473 let CextOpcode = "S2_storeri";
   24474 let InputType = "imm";
   24475 let BaseOpcode = "S4_storeiri_io";
   24476 let isExtendable = 1;
   24477 let opExtendable = 3;
   24478 let isExtentSigned = 1;
   24479 let opExtentBits = 6;
   24480 let opExtentAlign = 0;
   24481 }
   24482 def S4_storeirit_zomap : HInst<
   24483 (outs),
   24484 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24485 "if ($Pv4) memw($Rs32) = #$II",
   24486 tc_8b15472a, TypeMAPPING> {
   24487 let isPseudo = 1;
   24488 let isCodeGenOnly = 1;
   24489 }
   24490 def S4_storeiritnew_io : HInst<
   24491 (outs),
   24492 (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
   24493 "if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
   24494 tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel {
   24495 let Inst{31-21} = 0b00111001010;
   24496 let isPredicated = 1;
   24497 let addrMode = BaseImmOffset;
   24498 let accessSize = WordAccess;
   24499 let isPredicatedNew = 1;
   24500 let mayStore = 1;
   24501 let CextOpcode = "S2_storeri";
   24502 let InputType = "imm";
   24503 let BaseOpcode = "S4_storeiri_io";
   24504 let isExtendable = 1;
   24505 let opExtendable = 3;
   24506 let isExtentSigned = 1;
   24507 let opExtentBits = 6;
   24508 let opExtentAlign = 0;
   24509 }
   24510 def S4_storeiritnew_zomap : HInst<
   24511 (outs),
   24512 (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
   24513 "if ($Pv4.new) memw($Rs32) = #$II",
   24514 tc_f86c328a, TypeMAPPING> {
   24515 let isPseudo = 1;
   24516 let isCodeGenOnly = 1;
   24517 }
   24518 def S4_storerb_ap : HInst<
   24519 (outs IntRegs:$Re32),
   24520 (ins u32_0Imm:$II, IntRegs:$Rt32),
   24521 "memb($Re32=#$II) = $Rt32",
   24522 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
   24523 let Inst{7-6} = 0b10;
   24524 let Inst{13-13} = 0b0;
   24525 let Inst{31-21} = 0b10101011000;
   24526 let addrMode = AbsoluteSet;
   24527 let accessSize = ByteAccess;
   24528 let isExtended = 1;
   24529 let mayStore = 1;
   24530 let BaseOpcode = "S2_storerb_ap";
   24531 let isNVStorable = 1;
   24532 let DecoderNamespace = "MustExtend";
   24533 let isExtendable = 1;
   24534 let opExtendable = 1;
   24535 let isExtentSigned = 0;
   24536 let opExtentBits = 6;
   24537 let opExtentAlign = 0;
   24538 }
   24539 def S4_storerb_rr : HInst<
   24540 (outs),
   24541 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24542 "memb($Rs32+$Ru32<<#$Ii) = $Rt32",
   24543 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
   24544 let Inst{6-5} = 0b00;
   24545 let Inst{31-21} = 0b00111011000;
   24546 let addrMode = BaseRegOffset;
   24547 let accessSize = ByteAccess;
   24548 let mayStore = 1;
   24549 let CextOpcode = "S2_storerb";
   24550 let InputType = "reg";
   24551 let BaseOpcode = "S4_storerb_rr";
   24552 let isNVStorable = 1;
   24553 let isPredicable = 1;
   24554 }
   24555 def S4_storerb_ur : HInst<
   24556 (outs),
   24557 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
   24558 "memb($Ru32<<#$Ii+#$II) = $Rt32",
   24559 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
   24560 let Inst{7-7} = 0b1;
   24561 let Inst{31-21} = 0b10101101000;
   24562 let addrMode = BaseLongOffset;
   24563 let accessSize = ByteAccess;
   24564 let isExtended = 1;
   24565 let mayStore = 1;
   24566 let CextOpcode = "S2_storerb";
   24567 let InputType = "imm";
   24568 let BaseOpcode = "S4_storerb_ur";
   24569 let isNVStorable = 1;
   24570 let DecoderNamespace = "MustExtend";
   24571 let isExtendable = 1;
   24572 let opExtendable = 2;
   24573 let isExtentSigned = 0;
   24574 let opExtentBits = 6;
   24575 let opExtentAlign = 0;
   24576 }
   24577 def S4_storerbnew_ap : HInst<
   24578 (outs IntRegs:$Re32),
   24579 (ins u32_0Imm:$II, IntRegs:$Nt8),
   24580 "memb($Re32=#$II) = $Nt8.new",
   24581 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
   24582 let Inst{7-6} = 0b10;
   24583 let Inst{13-11} = 0b000;
   24584 let Inst{31-21} = 0b10101011101;
   24585 let addrMode = AbsoluteSet;
   24586 let accessSize = ByteAccess;
   24587 let isNVStore = 1;
   24588 let isNewValue = 1;
   24589 let isExtended = 1;
   24590 let isRestrictNoSlot1Store = 1;
   24591 let mayStore = 1;
   24592 let BaseOpcode = "S2_storerb_ap";
   24593 let DecoderNamespace = "MustExtend";
   24594 let isExtendable = 1;
   24595 let opExtendable = 1;
   24596 let isExtentSigned = 0;
   24597 let opExtentBits = 6;
   24598 let opExtentAlign = 0;
   24599 let opNewValue = 2;
   24600 }
   24601 def S4_storerbnew_rr : HInst<
   24602 (outs),
   24603 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   24604 "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   24605 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
   24606 let Inst{6-3} = 0b0000;
   24607 let Inst{31-21} = 0b00111011101;
   24608 let addrMode = BaseRegOffset;
   24609 let accessSize = ByteAccess;
   24610 let isNVStore = 1;
   24611 let isNewValue = 1;
   24612 let isRestrictNoSlot1Store = 1;
   24613 let mayStore = 1;
   24614 let CextOpcode = "S2_storerb";
   24615 let InputType = "reg";
   24616 let BaseOpcode = "S4_storerb_rr";
   24617 let isPredicable = 1;
   24618 let opNewValue = 3;
   24619 }
   24620 def S4_storerbnew_ur : HInst<
   24621 (outs),
   24622 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
   24623 "memb($Ru32<<#$Ii+#$II) = $Nt8.new",
   24624 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
   24625 let Inst{7-7} = 0b1;
   24626 let Inst{12-11} = 0b00;
   24627 let Inst{31-21} = 0b10101101101;
   24628 let addrMode = BaseLongOffset;
   24629 let accessSize = ByteAccess;
   24630 let isNVStore = 1;
   24631 let isNewValue = 1;
   24632 let isExtended = 1;
   24633 let isRestrictNoSlot1Store = 1;
   24634 let mayStore = 1;
   24635 let CextOpcode = "S2_storerb";
   24636 let BaseOpcode = "S4_storerb_ur";
   24637 let DecoderNamespace = "MustExtend";
   24638 let isExtendable = 1;
   24639 let opExtendable = 2;
   24640 let isExtentSigned = 0;
   24641 let opExtentBits = 6;
   24642 let opExtentAlign = 0;
   24643 let opNewValue = 3;
   24644 }
   24645 def S4_storerd_ap : HInst<
   24646 (outs IntRegs:$Re32),
   24647 (ins u32_0Imm:$II, DoubleRegs:$Rtt32),
   24648 "memd($Re32=#$II) = $Rtt32",
   24649 tc_66888ded, TypeST>, Enc_c7a204 {
   24650 let Inst{7-6} = 0b10;
   24651 let Inst{13-13} = 0b0;
   24652 let Inst{31-21} = 0b10101011110;
   24653 let addrMode = AbsoluteSet;
   24654 let accessSize = DoubleWordAccess;
   24655 let isExtended = 1;
   24656 let mayStore = 1;
   24657 let BaseOpcode = "S4_storerd_ap";
   24658 let DecoderNamespace = "MustExtend";
   24659 let isExtendable = 1;
   24660 let opExtendable = 1;
   24661 let isExtentSigned = 0;
   24662 let opExtentBits = 6;
   24663 let opExtentAlign = 0;
   24664 }
   24665 def S4_storerd_rr : HInst<
   24666 (outs),
   24667 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
   24668 "memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
   24669 tc_d9709180, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
   24670 let Inst{6-5} = 0b00;
   24671 let Inst{31-21} = 0b00111011110;
   24672 let addrMode = BaseRegOffset;
   24673 let accessSize = DoubleWordAccess;
   24674 let mayStore = 1;
   24675 let CextOpcode = "S2_storerd";
   24676 let InputType = "reg";
   24677 let BaseOpcode = "S2_storerd_rr";
   24678 let isPredicable = 1;
   24679 }
   24680 def S4_storerd_ur : HInst<
   24681 (outs),
   24682 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
   24683 "memd($Ru32<<#$Ii+#$II) = $Rtt32",
   24684 tc_0dc560de, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
   24685 let Inst{7-7} = 0b1;
   24686 let Inst{31-21} = 0b10101101110;
   24687 let addrMode = BaseLongOffset;
   24688 let accessSize = DoubleWordAccess;
   24689 let isExtended = 1;
   24690 let mayStore = 1;
   24691 let CextOpcode = "S2_storerd";
   24692 let InputType = "imm";
   24693 let BaseOpcode = "S2_storerd_ur";
   24694 let DecoderNamespace = "MustExtend";
   24695 let isExtendable = 1;
   24696 let opExtendable = 2;
   24697 let isExtentSigned = 0;
   24698 let opExtentBits = 6;
   24699 let opExtentAlign = 0;
   24700 }
   24701 def S4_storerf_ap : HInst<
   24702 (outs IntRegs:$Re32),
   24703 (ins u32_0Imm:$II, IntRegs:$Rt32),
   24704 "memh($Re32=#$II) = $Rt32.h",
   24705 tc_66888ded, TypeST>, Enc_8bcba4 {
   24706 let Inst{7-6} = 0b10;
   24707 let Inst{13-13} = 0b0;
   24708 let Inst{31-21} = 0b10101011011;
   24709 let addrMode = AbsoluteSet;
   24710 let accessSize = HalfWordAccess;
   24711 let isExtended = 1;
   24712 let mayStore = 1;
   24713 let BaseOpcode = "S4_storerf_ap";
   24714 let DecoderNamespace = "MustExtend";
   24715 let isExtendable = 1;
   24716 let opExtendable = 1;
   24717 let isExtentSigned = 0;
   24718 let opExtentBits = 6;
   24719 let opExtentAlign = 0;
   24720 }
   24721 def S4_storerf_rr : HInst<
   24722 (outs),
   24723 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24724 "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
   24725 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
   24726 let Inst{6-5} = 0b00;
   24727 let Inst{31-21} = 0b00111011011;
   24728 let addrMode = BaseRegOffset;
   24729 let accessSize = HalfWordAccess;
   24730 let mayStore = 1;
   24731 let CextOpcode = "S2_storerf";
   24732 let InputType = "reg";
   24733 let BaseOpcode = "S4_storerf_rr";
   24734 let isPredicable = 1;
   24735 }
   24736 def S4_storerf_ur : HInst<
   24737 (outs),
   24738 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
   24739 "memh($Ru32<<#$Ii+#$II) = $Rt32.h",
   24740 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
   24741 let Inst{7-7} = 0b1;
   24742 let Inst{31-21} = 0b10101101011;
   24743 let addrMode = BaseLongOffset;
   24744 let accessSize = HalfWordAccess;
   24745 let isExtended = 1;
   24746 let mayStore = 1;
   24747 let CextOpcode = "S2_storerf";
   24748 let InputType = "imm";
   24749 let BaseOpcode = "S4_storerf_rr";
   24750 let DecoderNamespace = "MustExtend";
   24751 let isExtendable = 1;
   24752 let opExtendable = 2;
   24753 let isExtentSigned = 0;
   24754 let opExtentBits = 6;
   24755 let opExtentAlign = 0;
   24756 }
   24757 def S4_storerh_ap : HInst<
   24758 (outs IntRegs:$Re32),
   24759 (ins u32_0Imm:$II, IntRegs:$Rt32),
   24760 "memh($Re32=#$II) = $Rt32",
   24761 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
   24762 let Inst{7-6} = 0b10;
   24763 let Inst{13-13} = 0b0;
   24764 let Inst{31-21} = 0b10101011010;
   24765 let addrMode = AbsoluteSet;
   24766 let accessSize = HalfWordAccess;
   24767 let isExtended = 1;
   24768 let mayStore = 1;
   24769 let BaseOpcode = "S2_storerh_ap";
   24770 let isNVStorable = 1;
   24771 let DecoderNamespace = "MustExtend";
   24772 let isExtendable = 1;
   24773 let opExtendable = 1;
   24774 let isExtentSigned = 0;
   24775 let opExtentBits = 6;
   24776 let opExtentAlign = 0;
   24777 }
   24778 def S4_storerh_rr : HInst<
   24779 (outs),
   24780 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24781 "memh($Rs32+$Ru32<<#$Ii) = $Rt32",
   24782 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
   24783 let Inst{6-5} = 0b00;
   24784 let Inst{31-21} = 0b00111011010;
   24785 let addrMode = BaseRegOffset;
   24786 let accessSize = HalfWordAccess;
   24787 let mayStore = 1;
   24788 let CextOpcode = "S2_storerh";
   24789 let InputType = "reg";
   24790 let BaseOpcode = "S2_storerh_rr";
   24791 let isNVStorable = 1;
   24792 let isPredicable = 1;
   24793 }
   24794 def S4_storerh_ur : HInst<
   24795 (outs),
   24796 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
   24797 "memh($Ru32<<#$Ii+#$II) = $Rt32",
   24798 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
   24799 let Inst{7-7} = 0b1;
   24800 let Inst{31-21} = 0b10101101010;
   24801 let addrMode = BaseLongOffset;
   24802 let accessSize = HalfWordAccess;
   24803 let isExtended = 1;
   24804 let mayStore = 1;
   24805 let CextOpcode = "S2_storerh";
   24806 let InputType = "imm";
   24807 let BaseOpcode = "S2_storerh_ur";
   24808 let isNVStorable = 1;
   24809 let DecoderNamespace = "MustExtend";
   24810 let isExtendable = 1;
   24811 let opExtendable = 2;
   24812 let isExtentSigned = 0;
   24813 let opExtentBits = 6;
   24814 let opExtentAlign = 0;
   24815 }
   24816 def S4_storerhnew_ap : HInst<
   24817 (outs IntRegs:$Re32),
   24818 (ins u32_0Imm:$II, IntRegs:$Nt8),
   24819 "memh($Re32=#$II) = $Nt8.new",
   24820 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
   24821 let Inst{7-6} = 0b10;
   24822 let Inst{13-11} = 0b001;
   24823 let Inst{31-21} = 0b10101011101;
   24824 let addrMode = AbsoluteSet;
   24825 let accessSize = HalfWordAccess;
   24826 let isNVStore = 1;
   24827 let isNewValue = 1;
   24828 let isExtended = 1;
   24829 let isRestrictNoSlot1Store = 1;
   24830 let mayStore = 1;
   24831 let BaseOpcode = "S2_storerh_ap";
   24832 let DecoderNamespace = "MustExtend";
   24833 let isExtendable = 1;
   24834 let opExtendable = 1;
   24835 let isExtentSigned = 0;
   24836 let opExtentBits = 6;
   24837 let opExtentAlign = 0;
   24838 let opNewValue = 2;
   24839 }
   24840 def S4_storerhnew_rr : HInst<
   24841 (outs),
   24842 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   24843 "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   24844 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
   24845 let Inst{6-3} = 0b0001;
   24846 let Inst{31-21} = 0b00111011101;
   24847 let addrMode = BaseRegOffset;
   24848 let accessSize = HalfWordAccess;
   24849 let isNVStore = 1;
   24850 let isNewValue = 1;
   24851 let isRestrictNoSlot1Store = 1;
   24852 let mayStore = 1;
   24853 let CextOpcode = "S2_storerh";
   24854 let InputType = "reg";
   24855 let BaseOpcode = "S2_storerh_rr";
   24856 let isPredicable = 1;
   24857 let opNewValue = 3;
   24858 }
   24859 def S4_storerhnew_ur : HInst<
   24860 (outs),
   24861 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
   24862 "memh($Ru32<<#$Ii+#$II) = $Nt8.new",
   24863 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
   24864 let Inst{7-7} = 0b1;
   24865 let Inst{12-11} = 0b01;
   24866 let Inst{31-21} = 0b10101101101;
   24867 let addrMode = BaseLongOffset;
   24868 let accessSize = HalfWordAccess;
   24869 let isNVStore = 1;
   24870 let isNewValue = 1;
   24871 let isExtended = 1;
   24872 let isRestrictNoSlot1Store = 1;
   24873 let mayStore = 1;
   24874 let CextOpcode = "S2_storerh";
   24875 let BaseOpcode = "S2_storerh_ur";
   24876 let DecoderNamespace = "MustExtend";
   24877 let isExtendable = 1;
   24878 let opExtendable = 2;
   24879 let isExtentSigned = 0;
   24880 let opExtentBits = 6;
   24881 let opExtentAlign = 0;
   24882 let opNewValue = 3;
   24883 }
   24884 def S4_storeri_ap : HInst<
   24885 (outs IntRegs:$Re32),
   24886 (ins u32_0Imm:$II, IntRegs:$Rt32),
   24887 "memw($Re32=#$II) = $Rt32",
   24888 tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel {
   24889 let Inst{7-6} = 0b10;
   24890 let Inst{13-13} = 0b0;
   24891 let Inst{31-21} = 0b10101011100;
   24892 let addrMode = AbsoluteSet;
   24893 let accessSize = WordAccess;
   24894 let isExtended = 1;
   24895 let mayStore = 1;
   24896 let BaseOpcode = "S2_storeri_ap";
   24897 let isNVStorable = 1;
   24898 let DecoderNamespace = "MustExtend";
   24899 let isExtendable = 1;
   24900 let opExtendable = 1;
   24901 let isExtentSigned = 0;
   24902 let opExtentBits = 6;
   24903 let opExtentAlign = 0;
   24904 }
   24905 def S4_storeri_rr : HInst<
   24906 (outs),
   24907 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
   24908 "memw($Rs32+$Ru32<<#$Ii) = $Rt32",
   24909 tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
   24910 let Inst{6-5} = 0b00;
   24911 let Inst{31-21} = 0b00111011100;
   24912 let addrMode = BaseRegOffset;
   24913 let accessSize = WordAccess;
   24914 let mayStore = 1;
   24915 let CextOpcode = "S2_storeri";
   24916 let InputType = "reg";
   24917 let BaseOpcode = "S2_storeri_rr";
   24918 let isNVStorable = 1;
   24919 let isPredicable = 1;
   24920 }
   24921 def S4_storeri_ur : HInst<
   24922 (outs),
   24923 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
   24924 "memw($Ru32<<#$Ii+#$II) = $Rt32",
   24925 tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
   24926 let Inst{7-7} = 0b1;
   24927 let Inst{31-21} = 0b10101101100;
   24928 let addrMode = BaseLongOffset;
   24929 let accessSize = WordAccess;
   24930 let isExtended = 1;
   24931 let mayStore = 1;
   24932 let CextOpcode = "S2_storeri";
   24933 let InputType = "imm";
   24934 let BaseOpcode = "S2_storeri_ur";
   24935 let isNVStorable = 1;
   24936 let DecoderNamespace = "MustExtend";
   24937 let isExtendable = 1;
   24938 let opExtendable = 2;
   24939 let isExtentSigned = 0;
   24940 let opExtentBits = 6;
   24941 let opExtentAlign = 0;
   24942 }
   24943 def S4_storerinew_ap : HInst<
   24944 (outs IntRegs:$Re32),
   24945 (ins u32_0Imm:$II, IntRegs:$Nt8),
   24946 "memw($Re32=#$II) = $Nt8.new",
   24947 tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel {
   24948 let Inst{7-6} = 0b10;
   24949 let Inst{13-11} = 0b010;
   24950 let Inst{31-21} = 0b10101011101;
   24951 let addrMode = AbsoluteSet;
   24952 let accessSize = WordAccess;
   24953 let isNVStore = 1;
   24954 let isNewValue = 1;
   24955 let isExtended = 1;
   24956 let isRestrictNoSlot1Store = 1;
   24957 let mayStore = 1;
   24958 let BaseOpcode = "S2_storeri_ap";
   24959 let DecoderNamespace = "MustExtend";
   24960 let isExtendable = 1;
   24961 let opExtendable = 1;
   24962 let isExtentSigned = 0;
   24963 let opExtentBits = 6;
   24964 let opExtentAlign = 0;
   24965 let opNewValue = 2;
   24966 }
   24967 def S4_storerinew_rr : HInst<
   24968 (outs),
   24969 (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
   24970 "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
   24971 tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel {
   24972 let Inst{6-3} = 0b0010;
   24973 let Inst{31-21} = 0b00111011101;
   24974 let addrMode = BaseRegOffset;
   24975 let accessSize = WordAccess;
   24976 let isNVStore = 1;
   24977 let isNewValue = 1;
   24978 let isRestrictNoSlot1Store = 1;
   24979 let mayStore = 1;
   24980 let CextOpcode = "S2_storeri";
   24981 let InputType = "reg";
   24982 let BaseOpcode = "S2_storeri_rr";
   24983 let isPredicable = 1;
   24984 let opNewValue = 3;
   24985 }
   24986 def S4_storerinew_ur : HInst<
   24987 (outs),
   24988 (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
   24989 "memw($Ru32<<#$Ii+#$II) = $Nt8.new",
   24990 tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel {
   24991 let Inst{7-7} = 0b1;
   24992 let Inst{12-11} = 0b10;
   24993 let Inst{31-21} = 0b10101101101;
   24994 let addrMode = BaseLongOffset;
   24995 let accessSize = WordAccess;
   24996 let isNVStore = 1;
   24997 let isNewValue = 1;
   24998 let isExtended = 1;
   24999 let isRestrictNoSlot1Store = 1;
   25000 let mayStore = 1;
   25001 let CextOpcode = "S2_storeri";
   25002 let BaseOpcode = "S2_storeri_ur";
   25003 let DecoderNamespace = "MustExtend";
   25004 let isExtendable = 1;
   25005 let opExtendable = 2;
   25006 let isExtentSigned = 0;
   25007 let opExtentBits = 6;
   25008 let opExtentAlign = 0;
   25009 let opNewValue = 3;
   25010 }
   25011 def S4_subaddi : HInst<
   25012 (outs IntRegs:$Rd32),
   25013 (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
   25014 "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
   25015 tc_c74f796f, TypeALU64>, Enc_8b8d61 {
   25016 let Inst{31-23} = 0b110110111;
   25017 let hasNewValue = 1;
   25018 let opNewValue = 0;
   25019 let prefersSlot3 = 1;
   25020 let isExtendable = 1;
   25021 let opExtendable = 2;
   25022 let isExtentSigned = 1;
   25023 let opExtentBits = 6;
   25024 let opExtentAlign = 0;
   25025 }
   25026 def S4_subi_asl_ri : HInst<
   25027 (outs IntRegs:$Rx32),
   25028 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   25029 "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
   25030 tc_c74f796f, TypeALU64>, Enc_c31910 {
   25031 let Inst{2-0} = 0b110;
   25032 let Inst{4-4} = 0b0;
   25033 let Inst{31-24} = 0b11011110;
   25034 let hasNewValue = 1;
   25035 let opNewValue = 0;
   25036 let prefersSlot3 = 1;
   25037 let isExtendable = 1;
   25038 let opExtendable = 1;
   25039 let isExtentSigned = 0;
   25040 let opExtentBits = 8;
   25041 let opExtentAlign = 0;
   25042 let Constraints = "$Rx32 = $Rx32in";
   25043 }
   25044 def S4_subi_lsr_ri : HInst<
   25045 (outs IntRegs:$Rx32),
   25046 (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
   25047 "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
   25048 tc_c74f796f, TypeALU64>, Enc_c31910 {
   25049 let Inst{2-0} = 0b110;
   25050 let Inst{4-4} = 0b1;
   25051 let Inst{31-24} = 0b11011110;
   25052 let hasNewValue = 1;
   25053 let opNewValue = 0;
   25054 let prefersSlot3 = 1;
   25055 let isExtendable = 1;
   25056 let opExtendable = 1;
   25057 let isExtentSigned = 0;
   25058 let opExtentBits = 8;
   25059 let opExtentAlign = 0;
   25060 let Constraints = "$Rx32 = $Rx32in";
   25061 }
   25062 def S4_vrcrotate : HInst<
   25063 (outs DoubleRegs:$Rdd32),
   25064 (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
   25065 "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
   25066 tc_b9c0b731, TypeS_3op>, Enc_645d54 {
   25067 let Inst{7-6} = 0b11;
   25068 let Inst{31-21} = 0b11000011110;
   25069 let prefersSlot3 = 1;
   25070 }
   25071 def S4_vrcrotate_acc : HInst<
   25072 (outs DoubleRegs:$Rxx32),
   25073 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
   25074 "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
   25075 tc_60571023, TypeS_3op>, Enc_b72622 {
   25076 let Inst{7-6} = 0b00;
   25077 let Inst{31-21} = 0b11001011101;
   25078 let prefersSlot3 = 1;
   25079 let Constraints = "$Rxx32 = $Rxx32in";
   25080 }
   25081 def S4_vxaddsubh : HInst<
   25082 (outs DoubleRegs:$Rdd32),
   25083 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25084 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
   25085 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
   25086 let Inst{7-5} = 0b100;
   25087 let Inst{13-13} = 0b0;
   25088 let Inst{31-21} = 0b11000001010;
   25089 let prefersSlot3 = 1;
   25090 let Defs = [USR_OVF];
   25091 }
   25092 def S4_vxaddsubhr : HInst<
   25093 (outs DoubleRegs:$Rdd32),
   25094 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25095 "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
   25096 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
   25097 let Inst{7-5} = 0b000;
   25098 let Inst{13-13} = 0b0;
   25099 let Inst{31-21} = 0b11000001110;
   25100 let prefersSlot3 = 1;
   25101 let Defs = [USR_OVF];
   25102 }
   25103 def S4_vxaddsubw : HInst<
   25104 (outs DoubleRegs:$Rdd32),
   25105 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25106 "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
   25107 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
   25108 let Inst{7-5} = 0b000;
   25109 let Inst{13-13} = 0b0;
   25110 let Inst{31-21} = 0b11000001010;
   25111 let prefersSlot3 = 1;
   25112 let Defs = [USR_OVF];
   25113 }
   25114 def S4_vxsubaddh : HInst<
   25115 (outs DoubleRegs:$Rdd32),
   25116 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25117 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
   25118 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
   25119 let Inst{7-5} = 0b110;
   25120 let Inst{13-13} = 0b0;
   25121 let Inst{31-21} = 0b11000001010;
   25122 let prefersSlot3 = 1;
   25123 let Defs = [USR_OVF];
   25124 }
   25125 def S4_vxsubaddhr : HInst<
   25126 (outs DoubleRegs:$Rdd32),
   25127 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25128 "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
   25129 tc_2b6f77c6, TypeS_3op>, Enc_a56825 {
   25130 let Inst{7-5} = 0b010;
   25131 let Inst{13-13} = 0b0;
   25132 let Inst{31-21} = 0b11000001110;
   25133 let prefersSlot3 = 1;
   25134 let Defs = [USR_OVF];
   25135 }
   25136 def S4_vxsubaddw : HInst<
   25137 (outs DoubleRegs:$Rdd32),
   25138 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25139 "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
   25140 tc_b44c6e2a, TypeS_3op>, Enc_a56825 {
   25141 let Inst{7-5} = 0b010;
   25142 let Inst{13-13} = 0b0;
   25143 let Inst{31-21} = 0b11000001010;
   25144 let prefersSlot3 = 1;
   25145 let Defs = [USR_OVF];
   25146 }
   25147 def S5_asrhub_rnd_sat : HInst<
   25148 (outs IntRegs:$Rd32),
   25149 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   25150 "$Rd32 = vasrhub($Rss32,#$Ii):raw",
   25151 tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> {
   25152 let Inst{7-5} = 0b100;
   25153 let Inst{13-12} = 0b00;
   25154 let Inst{31-21} = 0b10001000011;
   25155 let hasNewValue = 1;
   25156 let opNewValue = 0;
   25157 let prefersSlot3 = 1;
   25158 let Defs = [USR_OVF];
   25159 }
   25160 def S5_asrhub_rnd_sat_goodsyntax : HInst<
   25161 (outs IntRegs:$Rd32),
   25162 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   25163 "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
   25164 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> {
   25165 let hasNewValue = 1;
   25166 let opNewValue = 0;
   25167 let isPseudo = 1;
   25168 }
   25169 def S5_asrhub_sat : HInst<
   25170 (outs IntRegs:$Rd32),
   25171 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   25172 "$Rd32 = vasrhub($Rss32,#$Ii):sat",
   25173 tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> {
   25174 let Inst{7-5} = 0b101;
   25175 let Inst{13-12} = 0b00;
   25176 let Inst{31-21} = 0b10001000011;
   25177 let hasNewValue = 1;
   25178 let opNewValue = 0;
   25179 let prefersSlot3 = 1;
   25180 let Defs = [USR_OVF];
   25181 }
   25182 def S5_popcountp : HInst<
   25183 (outs IntRegs:$Rd32),
   25184 (ins DoubleRegs:$Rss32),
   25185 "$Rd32 = popcount($Rss32)",
   25186 tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> {
   25187 let Inst{13-5} = 0b000000011;
   25188 let Inst{31-21} = 0b10001000011;
   25189 let hasNewValue = 1;
   25190 let opNewValue = 0;
   25191 let prefersSlot3 = 1;
   25192 }
   25193 def S5_vasrhrnd : HInst<
   25194 (outs DoubleRegs:$Rdd32),
   25195 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   25196 "$Rdd32 = vasrh($Rss32,#$Ii):raw",
   25197 tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5]> {
   25198 let Inst{7-5} = 0b000;
   25199 let Inst{13-12} = 0b00;
   25200 let Inst{31-21} = 0b10000000001;
   25201 let prefersSlot3 = 1;
   25202 }
   25203 def S5_vasrhrnd_goodsyntax : HInst<
   25204 (outs DoubleRegs:$Rdd32),
   25205 (ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
   25206 "$Rdd32 = vasrh($Rss32,#$Ii):rnd",
   25207 tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> {
   25208 let isPseudo = 1;
   25209 }
   25210 def S6_allocframe_to_raw : HInst<
   25211 (outs),
   25212 (ins u11_3Imm:$Ii),
   25213 "allocframe(#$Ii)",
   25214 tc_e216a5db, TypeMAPPING>, Requires<[HasV65]> {
   25215 let isPseudo = 1;
   25216 let isCodeGenOnly = 1;
   25217 }
   25218 def S6_rol_i_p : HInst<
   25219 (outs DoubleRegs:$Rdd32),
   25220 (ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25221 "$Rdd32 = rol($Rss32,#$Ii)",
   25222 tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
   25223 let Inst{7-5} = 0b011;
   25224 let Inst{31-21} = 0b10000000000;
   25225 }
   25226 def S6_rol_i_p_acc : HInst<
   25227 (outs DoubleRegs:$Rxx32),
   25228 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25229 "$Rxx32 += rol($Rss32,#$Ii)",
   25230 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
   25231 let Inst{7-5} = 0b111;
   25232 let Inst{31-21} = 0b10000010000;
   25233 let prefersSlot3 = 1;
   25234 let Constraints = "$Rxx32 = $Rxx32in";
   25235 }
   25236 def S6_rol_i_p_and : HInst<
   25237 (outs DoubleRegs:$Rxx32),
   25238 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25239 "$Rxx32 &= rol($Rss32,#$Ii)",
   25240 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
   25241 let Inst{7-5} = 0b011;
   25242 let Inst{31-21} = 0b10000010010;
   25243 let prefersSlot3 = 1;
   25244 let Constraints = "$Rxx32 = $Rxx32in";
   25245 }
   25246 def S6_rol_i_p_nac : HInst<
   25247 (outs DoubleRegs:$Rxx32),
   25248 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25249 "$Rxx32 -= rol($Rss32,#$Ii)",
   25250 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
   25251 let Inst{7-5} = 0b011;
   25252 let Inst{31-21} = 0b10000010000;
   25253 let prefersSlot3 = 1;
   25254 let Constraints = "$Rxx32 = $Rxx32in";
   25255 }
   25256 def S6_rol_i_p_or : HInst<
   25257 (outs DoubleRegs:$Rxx32),
   25258 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25259 "$Rxx32 |= rol($Rss32,#$Ii)",
   25260 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
   25261 let Inst{7-5} = 0b111;
   25262 let Inst{31-21} = 0b10000010010;
   25263 let prefersSlot3 = 1;
   25264 let Constraints = "$Rxx32 = $Rxx32in";
   25265 }
   25266 def S6_rol_i_p_xacc : HInst<
   25267 (outs DoubleRegs:$Rxx32),
   25268 (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
   25269 "$Rxx32 ^= rol($Rss32,#$Ii)",
   25270 tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
   25271 let Inst{7-5} = 0b011;
   25272 let Inst{31-21} = 0b10000010100;
   25273 let prefersSlot3 = 1;
   25274 let Constraints = "$Rxx32 = $Rxx32in";
   25275 }
   25276 def S6_rol_i_r : HInst<
   25277 (outs IntRegs:$Rd32),
   25278 (ins IntRegs:$Rs32, u5_0Imm:$Ii),
   25279 "$Rd32 = rol($Rs32,#$Ii)",
   25280 tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
   25281 let Inst{7-5} = 0b011;
   25282 let Inst{13-13} = 0b0;
   25283 let Inst{31-21} = 0b10001100000;
   25284 let hasNewValue = 1;
   25285 let opNewValue = 0;
   25286 }
   25287 def S6_rol_i_r_acc : HInst<
   25288 (outs IntRegs:$Rx32),
   25289 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   25290 "$Rx32 += rol($Rs32,#$Ii)",
   25291 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
   25292 let Inst{7-5} = 0b111;
   25293 let Inst{13-13} = 0b0;
   25294 let Inst{31-21} = 0b10001110000;
   25295 let hasNewValue = 1;
   25296 let opNewValue = 0;
   25297 let prefersSlot3 = 1;
   25298 let Constraints = "$Rx32 = $Rx32in";
   25299 }
   25300 def S6_rol_i_r_and : HInst<
   25301 (outs IntRegs:$Rx32),
   25302 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   25303 "$Rx32 &= rol($Rs32,#$Ii)",
   25304 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
   25305 let Inst{7-5} = 0b011;
   25306 let Inst{13-13} = 0b0;
   25307 let Inst{31-21} = 0b10001110010;
   25308 let hasNewValue = 1;
   25309 let opNewValue = 0;
   25310 let prefersSlot3 = 1;
   25311 let Constraints = "$Rx32 = $Rx32in";
   25312 }
   25313 def S6_rol_i_r_nac : HInst<
   25314 (outs IntRegs:$Rx32),
   25315 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   25316 "$Rx32 -= rol($Rs32,#$Ii)",
   25317 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
   25318 let Inst{7-5} = 0b011;
   25319 let Inst{13-13} = 0b0;
   25320 let Inst{31-21} = 0b10001110000;
   25321 let hasNewValue = 1;
   25322 let opNewValue = 0;
   25323 let prefersSlot3 = 1;
   25324 let Constraints = "$Rx32 = $Rx32in";
   25325 }
   25326 def S6_rol_i_r_or : HInst<
   25327 (outs IntRegs:$Rx32),
   25328 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   25329 "$Rx32 |= rol($Rs32,#$Ii)",
   25330 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
   25331 let Inst{7-5} = 0b111;
   25332 let Inst{13-13} = 0b0;
   25333 let Inst{31-21} = 0b10001110010;
   25334 let hasNewValue = 1;
   25335 let opNewValue = 0;
   25336 let prefersSlot3 = 1;
   25337 let Constraints = "$Rx32 = $Rx32in";
   25338 }
   25339 def S6_rol_i_r_xacc : HInst<
   25340 (outs IntRegs:$Rx32),
   25341 (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
   25342 "$Rx32 ^= rol($Rs32,#$Ii)",
   25343 tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
   25344 let Inst{7-5} = 0b011;
   25345 let Inst{13-13} = 0b0;
   25346 let Inst{31-21} = 0b10001110100;
   25347 let hasNewValue = 1;
   25348 let opNewValue = 0;
   25349 let prefersSlot3 = 1;
   25350 let Constraints = "$Rx32 = $Rx32in";
   25351 }
   25352 def S6_vsplatrbp : HInst<
   25353 (outs DoubleRegs:$Rdd32),
   25354 (ins IntRegs:$Rs32),
   25355 "$Rdd32 = vsplatb($Rs32)",
   25356 tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
   25357 let Inst{13-5} = 0b000000100;
   25358 let Inst{31-21} = 0b10000100010;
   25359 }
   25360 def S6_vtrunehb_ppp : HInst<
   25361 (outs DoubleRegs:$Rdd32),
   25362 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25363 "$Rdd32 = vtrunehb($Rss32,$Rtt32)",
   25364 tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
   25365 let Inst{7-5} = 0b011;
   25366 let Inst{13-13} = 0b0;
   25367 let Inst{31-21} = 0b11000001100;
   25368 }
   25369 def S6_vtrunohb_ppp : HInst<
   25370 (outs DoubleRegs:$Rdd32),
   25371 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
   25372 "$Rdd32 = vtrunohb($Rss32,$Rtt32)",
   25373 tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
   25374 let Inst{7-5} = 0b101;
   25375 let Inst{13-13} = 0b0;
   25376 let Inst{31-21} = 0b11000001100;
   25377 }
   25378 def SA1_addi : HInst<
   25379 (outs GeneralSubRegs:$Rx16),
   25380 (ins IntRegs:$Rx16in, s32_0Imm:$Ii),
   25381 "$Rx16 = add($Rx16in,#$Ii)",
   25382 tc_609d2efe, TypeSUBINSN>, Enc_93af4c {
   25383 let Inst{12-11} = 0b00;
   25384 let hasNewValue = 1;
   25385 let opNewValue = 0;
   25386 let AsmVariantName = "NonParsable";
   25387 let DecoderNamespace = "SUBINSN_A";
   25388 let isExtendable = 1;
   25389 let opExtendable = 2;
   25390 let isExtentSigned = 1;
   25391 let opExtentBits = 7;
   25392 let opExtentAlign = 0;
   25393 let Constraints = "$Rx16 = $Rx16in";
   25394 }
   25395 def SA1_addrx : HInst<
   25396 (outs GeneralSubRegs:$Rx16),
   25397 (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16),
   25398 "$Rx16 = add($Rx16in,$Rs16)",
   25399 tc_609d2efe, TypeSUBINSN>, Enc_0527db {
   25400 let Inst{12-8} = 0b11000;
   25401 let hasNewValue = 1;
   25402 let opNewValue = 0;
   25403 let AsmVariantName = "NonParsable";
   25404 let DecoderNamespace = "SUBINSN_A";
   25405 let Constraints = "$Rx16 = $Rx16in";
   25406 }
   25407 def SA1_addsp : HInst<
   25408 (outs GeneralSubRegs:$Rd16),
   25409 (ins u6_2Imm:$Ii),
   25410 "$Rd16 = add(r29,#$Ii)",
   25411 tc_a904d137, TypeSUBINSN>, Enc_2df31d {
   25412 let Inst{12-10} = 0b011;
   25413 let hasNewValue = 1;
   25414 let opNewValue = 0;
   25415 let AsmVariantName = "NonParsable";
   25416 let Uses = [R29];
   25417 let DecoderNamespace = "SUBINSN_A";
   25418 }
   25419 def SA1_and1 : HInst<
   25420 (outs GeneralSubRegs:$Rd16),
   25421 (ins GeneralSubRegs:$Rs16),
   25422 "$Rd16 = and($Rs16,#1)",
   25423 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25424 let Inst{12-8} = 0b10010;
   25425 let hasNewValue = 1;
   25426 let opNewValue = 0;
   25427 let AsmVariantName = "NonParsable";
   25428 let DecoderNamespace = "SUBINSN_A";
   25429 }
   25430 def SA1_clrf : HInst<
   25431 (outs GeneralSubRegs:$Rd16),
   25432 (ins),
   25433 "if (!p0) $Rd16 = #0",
   25434 tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
   25435 let Inst{12-4} = 0b110100111;
   25436 let isPredicated = 1;
   25437 let isPredicatedFalse = 1;
   25438 let hasNewValue = 1;
   25439 let opNewValue = 0;
   25440 let AsmVariantName = "NonParsable";
   25441 let Uses = [P0];
   25442 let DecoderNamespace = "SUBINSN_A";
   25443 }
   25444 def SA1_clrfnew : HInst<
   25445 (outs GeneralSubRegs:$Rd16),
   25446 (ins),
   25447 "if (!p0.new) $Rd16 = #0",
   25448 tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
   25449 let Inst{12-4} = 0b110100101;
   25450 let isPredicated = 1;
   25451 let isPredicatedFalse = 1;
   25452 let hasNewValue = 1;
   25453 let opNewValue = 0;
   25454 let AsmVariantName = "NonParsable";
   25455 let isPredicatedNew = 1;
   25456 let Uses = [P0];
   25457 let DecoderNamespace = "SUBINSN_A";
   25458 }
   25459 def SA1_clrt : HInst<
   25460 (outs GeneralSubRegs:$Rd16),
   25461 (ins),
   25462 "if (p0) $Rd16 = #0",
   25463 tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 {
   25464 let Inst{12-4} = 0b110100110;
   25465 let isPredicated = 1;
   25466 let hasNewValue = 1;
   25467 let opNewValue = 0;
   25468 let AsmVariantName = "NonParsable";
   25469 let Uses = [P0];
   25470 let DecoderNamespace = "SUBINSN_A";
   25471 }
   25472 def SA1_clrtnew : HInst<
   25473 (outs GeneralSubRegs:$Rd16),
   25474 (ins),
   25475 "if (p0.new) $Rd16 = #0",
   25476 tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 {
   25477 let Inst{12-4} = 0b110100100;
   25478 let isPredicated = 1;
   25479 let hasNewValue = 1;
   25480 let opNewValue = 0;
   25481 let AsmVariantName = "NonParsable";
   25482 let isPredicatedNew = 1;
   25483 let Uses = [P0];
   25484 let DecoderNamespace = "SUBINSN_A";
   25485 }
   25486 def SA1_cmpeqi : HInst<
   25487 (outs),
   25488 (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
   25489 "p0 = cmp.eq($Rs16,#$Ii)",
   25490 tc_90f3e30c, TypeSUBINSN>, Enc_63eaeb {
   25491 let Inst{3-2} = 0b00;
   25492 let Inst{12-8} = 0b11001;
   25493 let AsmVariantName = "NonParsable";
   25494 let Defs = [P0];
   25495 let DecoderNamespace = "SUBINSN_A";
   25496 }
   25497 def SA1_combine0i : HInst<
   25498 (outs GeneralDoubleLow8Regs:$Rdd8),
   25499 (ins u2_0Imm:$Ii),
   25500 "$Rdd8 = combine(#0,#$Ii)",
   25501 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
   25502 let Inst{4-3} = 0b00;
   25503 let Inst{12-7} = 0b111000;
   25504 let hasNewValue = 1;
   25505 let opNewValue = 0;
   25506 let AsmVariantName = "NonParsable";
   25507 let DecoderNamespace = "SUBINSN_A";
   25508 }
   25509 def SA1_combine1i : HInst<
   25510 (outs GeneralDoubleLow8Regs:$Rdd8),
   25511 (ins u2_0Imm:$Ii),
   25512 "$Rdd8 = combine(#1,#$Ii)",
   25513 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
   25514 let Inst{4-3} = 0b01;
   25515 let Inst{12-7} = 0b111000;
   25516 let hasNewValue = 1;
   25517 let opNewValue = 0;
   25518 let AsmVariantName = "NonParsable";
   25519 let DecoderNamespace = "SUBINSN_A";
   25520 }
   25521 def SA1_combine2i : HInst<
   25522 (outs GeneralDoubleLow8Regs:$Rdd8),
   25523 (ins u2_0Imm:$Ii),
   25524 "$Rdd8 = combine(#2,#$Ii)",
   25525 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
   25526 let Inst{4-3} = 0b10;
   25527 let Inst{12-7} = 0b111000;
   25528 let hasNewValue = 1;
   25529 let opNewValue = 0;
   25530 let AsmVariantName = "NonParsable";
   25531 let DecoderNamespace = "SUBINSN_A";
   25532 }
   25533 def SA1_combine3i : HInst<
   25534 (outs GeneralDoubleLow8Regs:$Rdd8),
   25535 (ins u2_0Imm:$Ii),
   25536 "$Rdd8 = combine(#3,#$Ii)",
   25537 tc_a904d137, TypeSUBINSN>, Enc_ed48be {
   25538 let Inst{4-3} = 0b11;
   25539 let Inst{12-7} = 0b111000;
   25540 let hasNewValue = 1;
   25541 let opNewValue = 0;
   25542 let AsmVariantName = "NonParsable";
   25543 let DecoderNamespace = "SUBINSN_A";
   25544 }
   25545 def SA1_combinerz : HInst<
   25546 (outs GeneralDoubleLow8Regs:$Rdd8),
   25547 (ins GeneralSubRegs:$Rs16),
   25548 "$Rdd8 = combine($Rs16,#0)",
   25549 tc_a904d137, TypeSUBINSN>, Enc_399e12 {
   25550 let Inst{3-3} = 0b1;
   25551 let Inst{12-8} = 0b11101;
   25552 let hasNewValue = 1;
   25553 let opNewValue = 0;
   25554 let AsmVariantName = "NonParsable";
   25555 let DecoderNamespace = "SUBINSN_A";
   25556 }
   25557 def SA1_combinezr : HInst<
   25558 (outs GeneralDoubleLow8Regs:$Rdd8),
   25559 (ins GeneralSubRegs:$Rs16),
   25560 "$Rdd8 = combine(#0,$Rs16)",
   25561 tc_a904d137, TypeSUBINSN>, Enc_399e12 {
   25562 let Inst{3-3} = 0b0;
   25563 let Inst{12-8} = 0b11101;
   25564 let hasNewValue = 1;
   25565 let opNewValue = 0;
   25566 let AsmVariantName = "NonParsable";
   25567 let DecoderNamespace = "SUBINSN_A";
   25568 }
   25569 def SA1_dec : HInst<
   25570 (outs GeneralSubRegs:$Rd16),
   25571 (ins GeneralSubRegs:$Rs16, n1Const:$n1),
   25572 "$Rd16 = add($Rs16,#$n1)",
   25573 tc_609d2efe, TypeSUBINSN>, Enc_ee5ed0 {
   25574 let Inst{12-8} = 0b10011;
   25575 let hasNewValue = 1;
   25576 let opNewValue = 0;
   25577 let AsmVariantName = "NonParsable";
   25578 let DecoderNamespace = "SUBINSN_A";
   25579 }
   25580 def SA1_inc : HInst<
   25581 (outs GeneralSubRegs:$Rd16),
   25582 (ins GeneralSubRegs:$Rs16),
   25583 "$Rd16 = add($Rs16,#1)",
   25584 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25585 let Inst{12-8} = 0b10001;
   25586 let hasNewValue = 1;
   25587 let opNewValue = 0;
   25588 let AsmVariantName = "NonParsable";
   25589 let DecoderNamespace = "SUBINSN_A";
   25590 }
   25591 def SA1_seti : HInst<
   25592 (outs GeneralSubRegs:$Rd16),
   25593 (ins u32_0Imm:$Ii),
   25594 "$Rd16 = #$Ii",
   25595 tc_a904d137, TypeSUBINSN>, Enc_e39bb2 {
   25596 let Inst{12-10} = 0b010;
   25597 let hasNewValue = 1;
   25598 let opNewValue = 0;
   25599 let AsmVariantName = "NonParsable";
   25600 let DecoderNamespace = "SUBINSN_A";
   25601 let isExtendable = 1;
   25602 let opExtendable = 1;
   25603 let isExtentSigned = 0;
   25604 let opExtentBits = 6;
   25605 let opExtentAlign = 0;
   25606 }
   25607 def SA1_setin1 : HInst<
   25608 (outs GeneralSubRegs:$Rd16),
   25609 (ins n1Const:$n1),
   25610 "$Rd16 = #$n1",
   25611 tc_a904d137, TypeSUBINSN>, Enc_7a0ea6 {
   25612 let Inst{12-4} = 0b110100000;
   25613 let hasNewValue = 1;
   25614 let opNewValue = 0;
   25615 let AsmVariantName = "NonParsable";
   25616 let DecoderNamespace = "SUBINSN_A";
   25617 }
   25618 def SA1_sxtb : HInst<
   25619 (outs GeneralSubRegs:$Rd16),
   25620 (ins GeneralSubRegs:$Rs16),
   25621 "$Rd16 = sxtb($Rs16)",
   25622 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25623 let Inst{12-8} = 0b10101;
   25624 let hasNewValue = 1;
   25625 let opNewValue = 0;
   25626 let AsmVariantName = "NonParsable";
   25627 let DecoderNamespace = "SUBINSN_A";
   25628 }
   25629 def SA1_sxth : HInst<
   25630 (outs GeneralSubRegs:$Rd16),
   25631 (ins GeneralSubRegs:$Rs16),
   25632 "$Rd16 = sxth($Rs16)",
   25633 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25634 let Inst{12-8} = 0b10100;
   25635 let hasNewValue = 1;
   25636 let opNewValue = 0;
   25637 let AsmVariantName = "NonParsable";
   25638 let DecoderNamespace = "SUBINSN_A";
   25639 }
   25640 def SA1_tfr : HInst<
   25641 (outs GeneralSubRegs:$Rd16),
   25642 (ins GeneralSubRegs:$Rs16),
   25643 "$Rd16 = $Rs16",
   25644 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25645 let Inst{12-8} = 0b10000;
   25646 let hasNewValue = 1;
   25647 let opNewValue = 0;
   25648 let AsmVariantName = "NonParsable";
   25649 let DecoderNamespace = "SUBINSN_A";
   25650 }
   25651 def SA1_zxtb : HInst<
   25652 (outs GeneralSubRegs:$Rd16),
   25653 (ins GeneralSubRegs:$Rs16),
   25654 "$Rd16 = and($Rs16,#255)",
   25655 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25656 let Inst{12-8} = 0b10111;
   25657 let hasNewValue = 1;
   25658 let opNewValue = 0;
   25659 let AsmVariantName = "NonParsable";
   25660 let DecoderNamespace = "SUBINSN_A";
   25661 }
   25662 def SA1_zxth : HInst<
   25663 (outs GeneralSubRegs:$Rd16),
   25664 (ins GeneralSubRegs:$Rs16),
   25665 "$Rd16 = zxth($Rs16)",
   25666 tc_a904d137, TypeSUBINSN>, Enc_97d666 {
   25667 let Inst{12-8} = 0b10110;
   25668 let hasNewValue = 1;
   25669 let opNewValue = 0;
   25670 let AsmVariantName = "NonParsable";
   25671 let DecoderNamespace = "SUBINSN_A";
   25672 }
   25673 def SL1_loadri_io : HInst<
   25674 (outs GeneralSubRegs:$Rd16),
   25675 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
   25676 "$Rd16 = memw($Rs16+#$Ii)",
   25677 tc_7f881c76, TypeSUBINSN>, Enc_53dca9 {
   25678 let Inst{12-12} = 0b0;
   25679 let hasNewValue = 1;
   25680 let opNewValue = 0;
   25681 let addrMode = BaseImmOffset;
   25682 let accessSize = WordAccess;
   25683 let AsmVariantName = "NonParsable";
   25684 let mayLoad = 1;
   25685 let DecoderNamespace = "SUBINSN_L1";
   25686 }
   25687 def SL1_loadrub_io : HInst<
   25688 (outs GeneralSubRegs:$Rd16),
   25689 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
   25690 "$Rd16 = memub($Rs16+#$Ii)",
   25691 tc_7f881c76, TypeSUBINSN>, Enc_c175d0 {
   25692 let Inst{12-12} = 0b1;
   25693 let hasNewValue = 1;
   25694 let opNewValue = 0;
   25695 let addrMode = BaseImmOffset;
   25696 let accessSize = ByteAccess;
   25697 let AsmVariantName = "NonParsable";
   25698 let mayLoad = 1;
   25699 let DecoderNamespace = "SUBINSN_L1";
   25700 }
   25701 def SL2_deallocframe : HInst<
   25702 (outs),
   25703 (ins),
   25704 "deallocframe",
   25705 tc_36c68ad1, TypeSUBINSN>, Enc_e3b0c4 {
   25706 let Inst{12-0} = 0b1111100000000;
   25707 let accessSize = DoubleWordAccess;
   25708 let AsmVariantName = "NonParsable";
   25709 let mayLoad = 1;
   25710 let Uses = [FRAMEKEY, R30];
   25711 let Defs = [R30, R29, R31];
   25712 let DecoderNamespace = "SUBINSN_L2";
   25713 }
   25714 def SL2_jumpr31 : HInst<
   25715 (outs),
   25716 (ins),
   25717 "jumpr r31",
   25718 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
   25719 let Inst{12-0} = 0b1111111000000;
   25720 let isTerminator = 1;
   25721 let isIndirectBranch = 1;
   25722 let AsmVariantName = "NonParsable";
   25723 let cofMax1 = 1;
   25724 let isReturn = 1;
   25725 let Uses = [R31];
   25726 let Defs = [PC];
   25727 let DecoderNamespace = "SUBINSN_L2";
   25728 }
   25729 def SL2_jumpr31_f : HInst<
   25730 (outs),
   25731 (ins),
   25732 "if (!p0) jumpr r31",
   25733 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
   25734 let Inst{12-0} = 0b1111111000101;
   25735 let isPredicated = 1;
   25736 let isPredicatedFalse = 1;
   25737 let isTerminator = 1;
   25738 let isIndirectBranch = 1;
   25739 let AsmVariantName = "NonParsable";
   25740 let cofMax1 = 1;
   25741 let isReturn = 1;
   25742 let Uses = [P0, R31];
   25743 let Defs = [PC];
   25744 let isTaken = Inst{4};
   25745 let DecoderNamespace = "SUBINSN_L2";
   25746 }
   25747 def SL2_jumpr31_fnew : HInst<
   25748 (outs),
   25749 (ins),
   25750 "if (!p0.new) jumpr:nt r31",
   25751 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
   25752 let Inst{12-0} = 0b1111111000111;
   25753 let isPredicated = 1;
   25754 let isPredicatedFalse = 1;
   25755 let isTerminator = 1;
   25756 let isIndirectBranch = 1;
   25757 let AsmVariantName = "NonParsable";
   25758 let isPredicatedNew = 1;
   25759 let cofMax1 = 1;
   25760 let isReturn = 1;
   25761 let Uses = [P0, R31];
   25762 let Defs = [PC];
   25763 let isTaken = Inst{4};
   25764 let DecoderNamespace = "SUBINSN_L2";
   25765 }
   25766 def SL2_jumpr31_t : HInst<
   25767 (outs),
   25768 (ins),
   25769 "if (p0) jumpr r31",
   25770 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
   25771 let Inst{12-0} = 0b1111111000100;
   25772 let isPredicated = 1;
   25773 let isTerminator = 1;
   25774 let isIndirectBranch = 1;
   25775 let AsmVariantName = "NonParsable";
   25776 let cofMax1 = 1;
   25777 let isReturn = 1;
   25778 let Uses = [P0, R31];
   25779 let Defs = [PC];
   25780 let isTaken = Inst{4};
   25781 let DecoderNamespace = "SUBINSN_L2";
   25782 }
   25783 def SL2_jumpr31_tnew : HInst<
   25784 (outs),
   25785 (ins),
   25786 "if (p0.new) jumpr:nt r31",
   25787 tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 {
   25788 let Inst{12-0} = 0b1111111000110;
   25789 let isPredicated = 1;
   25790 let isTerminator = 1;
   25791 let isIndirectBranch = 1;
   25792 let AsmVariantName = "NonParsable";
   25793 let isPredicatedNew = 1;
   25794 let cofMax1 = 1;
   25795 let isReturn = 1;
   25796 let Uses = [P0, R31];
   25797 let Defs = [PC];
   25798 let isTaken = Inst{4};
   25799 let DecoderNamespace = "SUBINSN_L2";
   25800 }
   25801 def SL2_loadrb_io : HInst<
   25802 (outs GeneralSubRegs:$Rd16),
   25803 (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
   25804 "$Rd16 = memb($Rs16+#$Ii)",
   25805 tc_7f881c76, TypeSUBINSN>, Enc_2fbf3c {
   25806 let Inst{12-11} = 0b10;
   25807 let hasNewValue = 1;
   25808 let opNewValue = 0;
   25809 let addrMode = BaseImmOffset;
   25810 let accessSize = ByteAccess;
   25811 let AsmVariantName = "NonParsable";
   25812 let mayLoad = 1;
   25813 let DecoderNamespace = "SUBINSN_L2";
   25814 }
   25815 def SL2_loadrd_sp : HInst<
   25816 (outs GeneralDoubleLow8Regs:$Rdd8),
   25817 (ins u5_3Imm:$Ii),
   25818 "$Rdd8 = memd(r29+#$Ii)",
   25819 tc_9c98e8af, TypeSUBINSN>, Enc_86a14b {
   25820 let Inst{12-8} = 0b11110;
   25821 let hasNewValue = 1;
   25822 let opNewValue = 0;
   25823 let addrMode = BaseImmOffset;
   25824 let accessSize = DoubleWordAccess;
   25825 let AsmVariantName = "NonParsable";
   25826 let mayLoad = 1;
   25827 let Uses = [R29];
   25828 let DecoderNamespace = "SUBINSN_L2";
   25829 }
   25830 def SL2_loadrh_io : HInst<
   25831 (outs GeneralSubRegs:$Rd16),
   25832 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
   25833 "$Rd16 = memh($Rs16+#$Ii)",
   25834 tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
   25835 let Inst{12-11} = 0b00;
   25836 let hasNewValue = 1;
   25837 let opNewValue = 0;
   25838 let addrMode = BaseImmOffset;
   25839 let accessSize = HalfWordAccess;
   25840 let AsmVariantName = "NonParsable";
   25841 let mayLoad = 1;
   25842 let DecoderNamespace = "SUBINSN_L2";
   25843 }
   25844 def SL2_loadri_sp : HInst<
   25845 (outs GeneralSubRegs:$Rd16),
   25846 (ins u5_2Imm:$Ii),
   25847 "$Rd16 = memw(r29+#$Ii)",
   25848 tc_9c98e8af, TypeSUBINSN>, Enc_51635c {
   25849 let Inst{12-9} = 0b1110;
   25850 let hasNewValue = 1;
   25851 let opNewValue = 0;
   25852 let addrMode = BaseImmOffset;
   25853 let accessSize = WordAccess;
   25854 let AsmVariantName = "NonParsable";
   25855 let mayLoad = 1;
   25856 let Uses = [R29];
   25857 let DecoderNamespace = "SUBINSN_L2";
   25858 }
   25859 def SL2_loadruh_io : HInst<
   25860 (outs GeneralSubRegs:$Rd16),
   25861 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
   25862 "$Rd16 = memuh($Rs16+#$Ii)",
   25863 tc_7f881c76, TypeSUBINSN>, Enc_2bae10 {
   25864 let Inst{12-11} = 0b01;
   25865 let hasNewValue = 1;
   25866 let opNewValue = 0;
   25867 let addrMode = BaseImmOffset;
   25868 let accessSize = HalfWordAccess;
   25869 let AsmVariantName = "NonParsable";
   25870 let mayLoad = 1;
   25871 let DecoderNamespace = "SUBINSN_L2";
   25872 }
   25873 def SL2_return : HInst<
   25874 (outs),
   25875 (ins),
   25876 "dealloc_return",
   25877 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
   25878 let Inst{12-0} = 0b1111101000000;
   25879 let isTerminator = 1;
   25880 let isIndirectBranch = 1;
   25881 let accessSize = DoubleWordAccess;
   25882 let AsmVariantName = "NonParsable";
   25883 let mayLoad = 1;
   25884 let cofMax1 = 1;
   25885 let isRestrictNoSlot1Store = 1;
   25886 let isReturn = 1;
   25887 let Uses = [FRAMEKEY, R30];
   25888 let Defs = [PC, R30, R29, R31];
   25889 let DecoderNamespace = "SUBINSN_L2";
   25890 }
   25891 def SL2_return_f : HInst<
   25892 (outs),
   25893 (ins),
   25894 "if (!p0) dealloc_return",
   25895 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
   25896 let Inst{12-0} = 0b1111101000101;
   25897 let isPredicated = 1;
   25898 let isPredicatedFalse = 1;
   25899 let isTerminator = 1;
   25900 let isIndirectBranch = 1;
   25901 let accessSize = DoubleWordAccess;
   25902 let AsmVariantName = "NonParsable";
   25903 let mayLoad = 1;
   25904 let cofMax1 = 1;
   25905 let isRestrictNoSlot1Store = 1;
   25906 let isReturn = 1;
   25907 let Uses = [FRAMEKEY, P0, R30];
   25908 let Defs = [PC, R30, R29, R31];
   25909 let isTaken = Inst{4};
   25910 let DecoderNamespace = "SUBINSN_L2";
   25911 }
   25912 def SL2_return_fnew : HInst<
   25913 (outs),
   25914 (ins),
   25915 "if (!p0.new) dealloc_return:nt",
   25916 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
   25917 let Inst{12-0} = 0b1111101000111;
   25918 let isPredicated = 1;
   25919 let isPredicatedFalse = 1;
   25920 let isTerminator = 1;
   25921 let isIndirectBranch = 1;
   25922 let accessSize = DoubleWordAccess;
   25923 let AsmVariantName = "NonParsable";
   25924 let isPredicatedNew = 1;
   25925 let mayLoad = 1;
   25926 let cofMax1 = 1;
   25927 let isRestrictNoSlot1Store = 1;
   25928 let isReturn = 1;
   25929 let Uses = [FRAMEKEY, P0, R30];
   25930 let Defs = [PC, R30, R29, R31];
   25931 let isTaken = Inst{4};
   25932 let DecoderNamespace = "SUBINSN_L2";
   25933 }
   25934 def SL2_return_t : HInst<
   25935 (outs),
   25936 (ins),
   25937 "if (p0) dealloc_return",
   25938 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
   25939 let Inst{12-0} = 0b1111101000100;
   25940 let isPredicated = 1;
   25941 let isTerminator = 1;
   25942 let isIndirectBranch = 1;
   25943 let accessSize = DoubleWordAccess;
   25944 let AsmVariantName = "NonParsable";
   25945 let mayLoad = 1;
   25946 let cofMax1 = 1;
   25947 let isRestrictNoSlot1Store = 1;
   25948 let isReturn = 1;
   25949 let Uses = [FRAMEKEY, P0, R30];
   25950 let Defs = [PC, R30, R29, R31];
   25951 let isTaken = Inst{4};
   25952 let DecoderNamespace = "SUBINSN_L2";
   25953 }
   25954 def SL2_return_tnew : HInst<
   25955 (outs),
   25956 (ins),
   25957 "if (p0.new) dealloc_return:nt",
   25958 tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 {
   25959 let Inst{12-0} = 0b1111101000110;
   25960 let isPredicated = 1;
   25961 let isTerminator = 1;
   25962 let isIndirectBranch = 1;
   25963 let accessSize = DoubleWordAccess;
   25964 let AsmVariantName = "NonParsable";
   25965 let isPredicatedNew = 1;
   25966 let mayLoad = 1;
   25967 let cofMax1 = 1;
   25968 let isRestrictNoSlot1Store = 1;
   25969 let isReturn = 1;
   25970 let Uses = [FRAMEKEY, P0, R30];
   25971 let Defs = [PC, R30, R29, R31];
   25972 let isTaken = Inst{4};
   25973 let DecoderNamespace = "SUBINSN_L2";
   25974 }
   25975 def SS1_storeb_io : HInst<
   25976 (outs),
   25977 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
   25978 "memb($Rs16+#$Ii) = $Rt16",
   25979 tc_05b6c987, TypeSUBINSN>, Enc_b38ffc {
   25980 let Inst{12-12} = 0b1;
   25981 let addrMode = BaseImmOffset;
   25982 let accessSize = ByteAccess;
   25983 let AsmVariantName = "NonParsable";
   25984 let mayStore = 1;
   25985 let DecoderNamespace = "SUBINSN_S1";
   25986 }
   25987 def SS1_storew_io : HInst<
   25988 (outs),
   25989 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
   25990 "memw($Rs16+#$Ii) = $Rt16",
   25991 tc_05b6c987, TypeSUBINSN>, Enc_f55a0c {
   25992 let Inst{12-12} = 0b0;
   25993 let addrMode = BaseImmOffset;
   25994 let accessSize = WordAccess;
   25995 let AsmVariantName = "NonParsable";
   25996 let mayStore = 1;
   25997 let DecoderNamespace = "SUBINSN_S1";
   25998 }
   25999 def SS2_allocframe : HInst<
   26000 (outs),
   26001 (ins u5_3Imm:$Ii),
   26002 "allocframe(#$Ii)",
   26003 tc_0fc1ae07, TypeSUBINSN>, Enc_6f70ca {
   26004 let Inst{3-0} = 0b0000;
   26005 let Inst{12-9} = 0b1110;
   26006 let addrMode = BaseImmOffset;
   26007 let accessSize = DoubleWordAccess;
   26008 let AsmVariantName = "NonParsable";
   26009 let mayStore = 1;
   26010 let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31];
   26011 let Defs = [R30, R29];
   26012 let DecoderNamespace = "SUBINSN_S2";
   26013 }
   26014 def SS2_storebi0 : HInst<
   26015 (outs),
   26016 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
   26017 "memb($Rs16+#$Ii) = #0",
   26018 tc_57288781, TypeSUBINSN>, Enc_84d359 {
   26019 let Inst{12-8} = 0b10010;
   26020 let addrMode = BaseImmOffset;
   26021 let accessSize = ByteAccess;
   26022 let AsmVariantName = "NonParsable";
   26023 let mayStore = 1;
   26024 let DecoderNamespace = "SUBINSN_S2";
   26025 }
   26026 def SS2_storebi1 : HInst<
   26027 (outs),
   26028 (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
   26029 "memb($Rs16+#$Ii) = #1",
   26030 tc_57288781, TypeSUBINSN>, Enc_84d359 {
   26031 let Inst{12-8} = 0b10011;
   26032 let addrMode = BaseImmOffset;
   26033 let accessSize = ByteAccess;
   26034 let AsmVariantName = "NonParsable";
   26035 let mayStore = 1;
   26036 let DecoderNamespace = "SUBINSN_S2";
   26037 }
   26038 def SS2_stored_sp : HInst<
   26039 (outs),
   26040 (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
   26041 "memd(r29+#$Ii) = $Rtt8",
   26042 tc_a788683e, TypeSUBINSN>, Enc_b8309d {
   26043 let Inst{12-9} = 0b0101;
   26044 let addrMode = BaseImmOffset;
   26045 let accessSize = DoubleWordAccess;
   26046 let AsmVariantName = "NonParsable";
   26047 let mayStore = 1;
   26048 let Uses = [R29];
   26049 let DecoderNamespace = "SUBINSN_S2";
   26050 }
   26051 def SS2_storeh_io : HInst<
   26052 (outs),
   26053 (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
   26054 "memh($Rs16+#$Ii) = $Rt16",
   26055 tc_05b6c987, TypeSUBINSN>, Enc_625deb {
   26056 let Inst{12-11} = 0b00;
   26057 let addrMode = BaseImmOffset;
   26058 let accessSize = HalfWordAccess;
   26059 let AsmVariantName = "NonParsable";
   26060 let mayStore = 1;
   26061 let DecoderNamespace = "SUBINSN_S2";
   26062 }
   26063 def SS2_storew_sp : HInst<
   26064 (outs),
   26065 (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
   26066 "memw(r29+#$Ii) = $Rt16",
   26067 tc_a788683e, TypeSUBINSN>, Enc_87c142 {
   26068 let Inst{12-9} = 0b0100;
   26069 let addrMode = BaseImmOffset;
   26070 let accessSize = WordAccess;
   26071 let AsmVariantName = "NonParsable";
   26072 let mayStore = 1;
   26073 let Uses = [R29];
   26074 let DecoderNamespace = "SUBINSN_S2";
   26075 }
   26076 def SS2_storewi0 : HInst<
   26077 (outs),
   26078 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
   26079 "memw($Rs16+#$Ii) = #0",
   26080 tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
   26081 let Inst{12-8} = 0b10000;
   26082 let addrMode = BaseImmOffset;
   26083 let accessSize = WordAccess;
   26084 let AsmVariantName = "NonParsable";
   26085 let mayStore = 1;
   26086 let DecoderNamespace = "SUBINSN_S2";
   26087 }
   26088 def SS2_storewi1 : HInst<
   26089 (outs),
   26090 (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
   26091 "memw($Rs16+#$Ii) = #1",
   26092 tc_57288781, TypeSUBINSN>, Enc_a6ce9c {
   26093 let Inst{12-8} = 0b10001;
   26094 let addrMode = BaseImmOffset;
   26095 let accessSize = WordAccess;
   26096 let AsmVariantName = "NonParsable";
   26097 let mayStore = 1;
   26098 let DecoderNamespace = "SUBINSN_S2";
   26099 }
   26100 def V6_MAP_equb : HInst<
   26101 (outs HvxQR:$Qd4),
   26102 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   26103 "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
   26104 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26105 let hasNewValue = 1;
   26106 let opNewValue = 0;
   26107 let isPseudo = 1;
   26108 let isCodeGenOnly = 1;
   26109 let DecoderNamespace = "EXT_mmvec";
   26110 }
   26111 def V6_MAP_equb_and : HInst<
   26112 (outs HvxQR:$Qx4),
   26113 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26114 "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
   26115 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26116 let isPseudo = 1;
   26117 let isCodeGenOnly = 1;
   26118 let DecoderNamespace = "EXT_mmvec";
   26119 let Constraints = "$Qx4 = $Qx4in";
   26120 }
   26121 def V6_MAP_equb_ior : HInst<
   26122 (outs HvxQR:$Qx4),
   26123 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26124 "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
   26125 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26126 let isAccumulator = 1;
   26127 let isPseudo = 1;
   26128 let isCodeGenOnly = 1;
   26129 let DecoderNamespace = "EXT_mmvec";
   26130 let Constraints = "$Qx4 = $Qx4in";
   26131 }
   26132 def V6_MAP_equb_xor : HInst<
   26133 (outs HvxQR:$Qx4),
   26134 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26135 "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
   26136 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26137 let isPseudo = 1;
   26138 let isCodeGenOnly = 1;
   26139 let DecoderNamespace = "EXT_mmvec";
   26140 let Constraints = "$Qx4 = $Qx4in";
   26141 }
   26142 def V6_MAP_equh : HInst<
   26143 (outs HvxQR:$Qd4),
   26144 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   26145 "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
   26146 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26147 let hasNewValue = 1;
   26148 let opNewValue = 0;
   26149 let isPseudo = 1;
   26150 let isCodeGenOnly = 1;
   26151 let DecoderNamespace = "EXT_mmvec";
   26152 }
   26153 def V6_MAP_equh_and : HInst<
   26154 (outs HvxQR:$Qx4),
   26155 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26156 "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
   26157 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26158 let isPseudo = 1;
   26159 let isCodeGenOnly = 1;
   26160 let DecoderNamespace = "EXT_mmvec";
   26161 let Constraints = "$Qx4 = $Qx4in";
   26162 }
   26163 def V6_MAP_equh_ior : HInst<
   26164 (outs HvxQR:$Qx4),
   26165 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26166 "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
   26167 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26168 let isAccumulator = 1;
   26169 let isPseudo = 1;
   26170 let isCodeGenOnly = 1;
   26171 let DecoderNamespace = "EXT_mmvec";
   26172 let Constraints = "$Qx4 = $Qx4in";
   26173 }
   26174 def V6_MAP_equh_xor : HInst<
   26175 (outs HvxQR:$Qx4),
   26176 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26177 "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
   26178 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26179 let isPseudo = 1;
   26180 let isCodeGenOnly = 1;
   26181 let DecoderNamespace = "EXT_mmvec";
   26182 let Constraints = "$Qx4 = $Qx4in";
   26183 }
   26184 def V6_MAP_equw : HInst<
   26185 (outs HvxQR:$Qd4),
   26186 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   26187 "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
   26188 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26189 let hasNewValue = 1;
   26190 let opNewValue = 0;
   26191 let isPseudo = 1;
   26192 let isCodeGenOnly = 1;
   26193 let DecoderNamespace = "EXT_mmvec";
   26194 }
   26195 def V6_MAP_equw_and : HInst<
   26196 (outs HvxQR:$Qx4),
   26197 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26198 "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
   26199 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26200 let isPseudo = 1;
   26201 let isCodeGenOnly = 1;
   26202 let DecoderNamespace = "EXT_mmvec";
   26203 let Constraints = "$Qx4 = $Qx4in";
   26204 }
   26205 def V6_MAP_equw_ior : HInst<
   26206 (outs HvxQR:$Qx4),
   26207 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26208 "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
   26209 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26210 let isAccumulator = 1;
   26211 let isPseudo = 1;
   26212 let isCodeGenOnly = 1;
   26213 let DecoderNamespace = "EXT_mmvec";
   26214 let Constraints = "$Qx4 = $Qx4in";
   26215 }
   26216 def V6_MAP_equw_xor : HInst<
   26217 (outs HvxQR:$Qx4),
   26218 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   26219 "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
   26220 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26221 let isPseudo = 1;
   26222 let isCodeGenOnly = 1;
   26223 let DecoderNamespace = "EXT_mmvec";
   26224 let Constraints = "$Qx4 = $Qx4in";
   26225 }
   26226 def V6_extractw : HInst<
   26227 (outs IntRegs:$Rd32),
   26228 (ins HvxVR:$Vu32, IntRegs:$Rs32),
   26229 "$Rd32 = vextract($Vu32,$Rs32)",
   26230 tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
   26231 let Inst{7-5} = 0b001;
   26232 let Inst{13-13} = 0b0;
   26233 let Inst{31-21} = 0b10010010000;
   26234 let hasNewValue = 1;
   26235 let opNewValue = 0;
   26236 let isSolo = 1;
   26237 let mayLoad = 1;
   26238 let DecoderNamespace = "EXT_mmvec";
   26239 }
   26240 def V6_extractw_alt : HInst<
   26241 (outs IntRegs:$Rd32),
   26242 (ins HvxVR:$Vu32, IntRegs:$Rs32),
   26243 "$Rd32.w = vextract($Vu32,$Rs32)",
   26244 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   26245 let hasNewValue = 1;
   26246 let opNewValue = 0;
   26247 let isPseudo = 1;
   26248 let isCodeGenOnly = 1;
   26249 let DecoderNamespace = "EXT_mmvec";
   26250 }
   26251 def V6_hi : HInst<
   26252 (outs HvxVR:$Vd32),
   26253 (ins HvxWR:$Vss32),
   26254 "$Vd32 = hi($Vss32)",
   26255 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
   26256 let hasNewValue = 1;
   26257 let opNewValue = 0;
   26258 let isPseudo = 1;
   26259 let DecoderNamespace = "EXT_mmvec";
   26260 }
   26261 def V6_ld0 : HInst<
   26262 (outs HvxVR:$Vd32),
   26263 (ins IntRegs:$Rt32),
   26264 "$Vd32 = vmem($Rt32)",
   26265 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
   26266 let hasNewValue = 1;
   26267 let opNewValue = 0;
   26268 let isPseudo = 1;
   26269 let isCodeGenOnly = 1;
   26270 let DecoderNamespace = "EXT_mmvec";
   26271 }
   26272 def V6_ldcnp0 : HInst<
   26273 (outs HvxVR:$Vd32),
   26274 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26275 "if (!$Pv4) $Vd32.cur = vmem($Rt32)",
   26276 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26277 let hasNewValue = 1;
   26278 let opNewValue = 0;
   26279 let isPseudo = 1;
   26280 let isCodeGenOnly = 1;
   26281 let DecoderNamespace = "EXT_mmvec";
   26282 }
   26283 def V6_ldcnpnt0 : HInst<
   26284 (outs HvxVR:$Vd32),
   26285 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26286 "if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
   26287 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26288 let hasNewValue = 1;
   26289 let opNewValue = 0;
   26290 let isPseudo = 1;
   26291 let isCodeGenOnly = 1;
   26292 let DecoderNamespace = "EXT_mmvec";
   26293 }
   26294 def V6_ldcp0 : HInst<
   26295 (outs HvxVR:$Vd32),
   26296 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26297 "if ($Pv4) $Vd32.cur = vmem($Rt32)",
   26298 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26299 let hasNewValue = 1;
   26300 let opNewValue = 0;
   26301 let isPseudo = 1;
   26302 let isCodeGenOnly = 1;
   26303 let DecoderNamespace = "EXT_mmvec";
   26304 }
   26305 def V6_ldcpnt0 : HInst<
   26306 (outs HvxVR:$Vd32),
   26307 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26308 "if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
   26309 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26310 let hasNewValue = 1;
   26311 let opNewValue = 0;
   26312 let isPseudo = 1;
   26313 let isCodeGenOnly = 1;
   26314 let DecoderNamespace = "EXT_mmvec";
   26315 }
   26316 def V6_ldnp0 : HInst<
   26317 (outs HvxVR:$Vd32),
   26318 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26319 "if (!$Pv4) $Vd32 = vmem($Rt32)",
   26320 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26321 let hasNewValue = 1;
   26322 let opNewValue = 0;
   26323 let isPseudo = 1;
   26324 let isCodeGenOnly = 1;
   26325 let DecoderNamespace = "EXT_mmvec";
   26326 }
   26327 def V6_ldnpnt0 : HInst<
   26328 (outs HvxVR:$Vd32),
   26329 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26330 "if (!$Pv4) $Vd32 = vmem($Rt32):nt",
   26331 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26332 let hasNewValue = 1;
   26333 let opNewValue = 0;
   26334 let isPseudo = 1;
   26335 let isCodeGenOnly = 1;
   26336 let DecoderNamespace = "EXT_mmvec";
   26337 }
   26338 def V6_ldnt0 : HInst<
   26339 (outs HvxVR:$Vd32),
   26340 (ins IntRegs:$Rt32),
   26341 "$Vd32 = vmem($Rt32):nt",
   26342 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
   26343 let hasNewValue = 1;
   26344 let opNewValue = 0;
   26345 let isPseudo = 1;
   26346 let isCodeGenOnly = 1;
   26347 let DecoderNamespace = "EXT_mmvec";
   26348 }
   26349 def V6_ldntnt0 : HInst<
   26350 (outs HvxVR:$Vd32),
   26351 (ins IntRegs:$Rt32),
   26352 "$Vd32 = vmem($Rt32):nt",
   26353 PSEUDO, TypeMAPPING>, Requires<[HasV62]> {
   26354 let hasNewValue = 1;
   26355 let opNewValue = 0;
   26356 let isPseudo = 1;
   26357 let isCodeGenOnly = 1;
   26358 let DecoderNamespace = "EXT_mmvec";
   26359 }
   26360 def V6_ldp0 : HInst<
   26361 (outs HvxVR:$Vd32),
   26362 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26363 "if ($Pv4) $Vd32 = vmem($Rt32)",
   26364 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26365 let hasNewValue = 1;
   26366 let opNewValue = 0;
   26367 let isPseudo = 1;
   26368 let isCodeGenOnly = 1;
   26369 let DecoderNamespace = "EXT_mmvec";
   26370 }
   26371 def V6_ldpnt0 : HInst<
   26372 (outs HvxVR:$Vd32),
   26373 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26374 "if ($Pv4) $Vd32 = vmem($Rt32):nt",
   26375 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26376 let hasNewValue = 1;
   26377 let opNewValue = 0;
   26378 let isPseudo = 1;
   26379 let isCodeGenOnly = 1;
   26380 let DecoderNamespace = "EXT_mmvec";
   26381 }
   26382 def V6_ldtnp0 : HInst<
   26383 (outs HvxVR:$Vd32),
   26384 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26385 "if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
   26386 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26387 let hasNewValue = 1;
   26388 let opNewValue = 0;
   26389 let isPseudo = 1;
   26390 let isCodeGenOnly = 1;
   26391 let DecoderNamespace = "EXT_mmvec";
   26392 }
   26393 def V6_ldtnpnt0 : HInst<
   26394 (outs HvxVR:$Vd32),
   26395 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26396 "if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
   26397 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26398 let hasNewValue = 1;
   26399 let opNewValue = 0;
   26400 let isPseudo = 1;
   26401 let isCodeGenOnly = 1;
   26402 let DecoderNamespace = "EXT_mmvec";
   26403 }
   26404 def V6_ldtp0 : HInst<
   26405 (outs HvxVR:$Vd32),
   26406 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26407 "if ($Pv4) $Vd32.tmp = vmem($Rt32)",
   26408 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26409 let hasNewValue = 1;
   26410 let opNewValue = 0;
   26411 let isPseudo = 1;
   26412 let isCodeGenOnly = 1;
   26413 let DecoderNamespace = "EXT_mmvec";
   26414 }
   26415 def V6_ldtpnt0 : HInst<
   26416 (outs HvxVR:$Vd32),
   26417 (ins PredRegs:$Pv4, IntRegs:$Rt32),
   26418 "if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
   26419 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   26420 let hasNewValue = 1;
   26421 let opNewValue = 0;
   26422 let isPseudo = 1;
   26423 let isCodeGenOnly = 1;
   26424 let DecoderNamespace = "EXT_mmvec";
   26425 }
   26426 def V6_ldu0 : HInst<
   26427 (outs HvxVR:$Vd32),
   26428 (ins IntRegs:$Rt32),
   26429 "$Vd32 = vmemu($Rt32)",
   26430 PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
   26431 let hasNewValue = 1;
   26432 let opNewValue = 0;
   26433 let isPseudo = 1;
   26434 let isCodeGenOnly = 1;
   26435 let DecoderNamespace = "EXT_mmvec";
   26436 }
   26437 def V6_lo : HInst<
   26438 (outs HvxVR:$Vd32),
   26439 (ins HvxWR:$Vss32),
   26440 "$Vd32 = lo($Vss32)",
   26441 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
   26442 let hasNewValue = 1;
   26443 let opNewValue = 0;
   26444 let isPseudo = 1;
   26445 let DecoderNamespace = "EXT_mmvec";
   26446 }
   26447 def V6_lvsplatb : HInst<
   26448 (outs HvxVR:$Vd32),
   26449 (ins IntRegs:$Rt32),
   26450 "$Vd32.b = vsplat($Rt32)",
   26451 tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
   26452 let Inst{13-5} = 0b000000010;
   26453 let Inst{31-21} = 0b00011001110;
   26454 let hasNewValue = 1;
   26455 let opNewValue = 0;
   26456 let DecoderNamespace = "EXT_mmvec";
   26457 }
   26458 def V6_lvsplath : HInst<
   26459 (outs HvxVR:$Vd32),
   26460 (ins IntRegs:$Rt32),
   26461 "$Vd32.h = vsplat($Rt32)",
   26462 tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
   26463 let Inst{13-5} = 0b000000001;
   26464 let Inst{31-21} = 0b00011001110;
   26465 let hasNewValue = 1;
   26466 let opNewValue = 0;
   26467 let DecoderNamespace = "EXT_mmvec";
   26468 }
   26469 def V6_lvsplatw : HInst<
   26470 (outs HvxVR:$Vd32),
   26471 (ins IntRegs:$Rt32),
   26472 "$Vd32 = vsplat($Rt32)",
   26473 tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
   26474 let Inst{13-5} = 0b000000001;
   26475 let Inst{31-21} = 0b00011001101;
   26476 let hasNewValue = 1;
   26477 let opNewValue = 0;
   26478 let DecoderNamespace = "EXT_mmvec";
   26479 }
   26480 def V6_pred_and : HInst<
   26481 (outs HvxQR:$Qd4),
   26482 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26483 "$Qd4 = and($Qs4,$Qt4)",
   26484 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
   26485 let Inst{7-2} = 0b000000;
   26486 let Inst{13-10} = 0b0000;
   26487 let Inst{21-16} = 0b000011;
   26488 let Inst{31-24} = 0b00011110;
   26489 let hasNewValue = 1;
   26490 let opNewValue = 0;
   26491 let DecoderNamespace = "EXT_mmvec";
   26492 }
   26493 def V6_pred_and_n : HInst<
   26494 (outs HvxQR:$Qd4),
   26495 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26496 "$Qd4 = and($Qs4,!$Qt4)",
   26497 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
   26498 let Inst{7-2} = 0b000101;
   26499 let Inst{13-10} = 0b0000;
   26500 let Inst{21-16} = 0b000011;
   26501 let Inst{31-24} = 0b00011110;
   26502 let hasNewValue = 1;
   26503 let opNewValue = 0;
   26504 let DecoderNamespace = "EXT_mmvec";
   26505 }
   26506 def V6_pred_not : HInst<
   26507 (outs HvxQR:$Qd4),
   26508 (ins HvxQR:$Qs4),
   26509 "$Qd4 = not($Qs4)",
   26510 tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
   26511 let Inst{7-2} = 0b000010;
   26512 let Inst{13-10} = 0b0000;
   26513 let Inst{31-16} = 0b0001111000000011;
   26514 let hasNewValue = 1;
   26515 let opNewValue = 0;
   26516 let DecoderNamespace = "EXT_mmvec";
   26517 }
   26518 def V6_pred_or : HInst<
   26519 (outs HvxQR:$Qd4),
   26520 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26521 "$Qd4 = or($Qs4,$Qt4)",
   26522 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
   26523 let Inst{7-2} = 0b000001;
   26524 let Inst{13-10} = 0b0000;
   26525 let Inst{21-16} = 0b000011;
   26526 let Inst{31-24} = 0b00011110;
   26527 let hasNewValue = 1;
   26528 let opNewValue = 0;
   26529 let DecoderNamespace = "EXT_mmvec";
   26530 }
   26531 def V6_pred_or_n : HInst<
   26532 (outs HvxQR:$Qd4),
   26533 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26534 "$Qd4 = or($Qs4,!$Qt4)",
   26535 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
   26536 let Inst{7-2} = 0b000100;
   26537 let Inst{13-10} = 0b0000;
   26538 let Inst{21-16} = 0b000011;
   26539 let Inst{31-24} = 0b00011110;
   26540 let hasNewValue = 1;
   26541 let opNewValue = 0;
   26542 let DecoderNamespace = "EXT_mmvec";
   26543 }
   26544 def V6_pred_scalar2 : HInst<
   26545 (outs HvxQR:$Qd4),
   26546 (ins IntRegs:$Rt32),
   26547 "$Qd4 = vsetq($Rt32)",
   26548 tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
   26549 let Inst{13-2} = 0b000000010001;
   26550 let Inst{31-21} = 0b00011001101;
   26551 let hasNewValue = 1;
   26552 let opNewValue = 0;
   26553 let DecoderNamespace = "EXT_mmvec";
   26554 }
   26555 def V6_pred_scalar2v2 : HInst<
   26556 (outs HvxQR:$Qd4),
   26557 (ins IntRegs:$Rt32),
   26558 "$Qd4 = vsetq2($Rt32)",
   26559 tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
   26560 let Inst{13-2} = 0b000000010011;
   26561 let Inst{31-21} = 0b00011001101;
   26562 let hasNewValue = 1;
   26563 let opNewValue = 0;
   26564 let DecoderNamespace = "EXT_mmvec";
   26565 }
   26566 def V6_pred_xor : HInst<
   26567 (outs HvxQR:$Qd4),
   26568 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26569 "$Qd4 = xor($Qs4,$Qt4)",
   26570 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
   26571 let Inst{7-2} = 0b000011;
   26572 let Inst{13-10} = 0b0000;
   26573 let Inst{21-16} = 0b000011;
   26574 let Inst{31-24} = 0b00011110;
   26575 let hasNewValue = 1;
   26576 let opNewValue = 0;
   26577 let DecoderNamespace = "EXT_mmvec";
   26578 }
   26579 def V6_shuffeqh : HInst<
   26580 (outs HvxQR:$Qd4),
   26581 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26582 "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
   26583 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
   26584 let Inst{7-2} = 0b000110;
   26585 let Inst{13-10} = 0b0000;
   26586 let Inst{21-16} = 0b000011;
   26587 let Inst{31-24} = 0b00011110;
   26588 let hasNewValue = 1;
   26589 let opNewValue = 0;
   26590 let DecoderNamespace = "EXT_mmvec";
   26591 }
   26592 def V6_shuffeqw : HInst<
   26593 (outs HvxQR:$Qd4),
   26594 (ins HvxQR:$Qs4, HvxQR:$Qt4),
   26595 "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
   26596 tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
   26597 let Inst{7-2} = 0b000111;
   26598 let Inst{13-10} = 0b0000;
   26599 let Inst{21-16} = 0b000011;
   26600 let Inst{31-24} = 0b00011110;
   26601 let hasNewValue = 1;
   26602 let opNewValue = 0;
   26603 let DecoderNamespace = "EXT_mmvec";
   26604 }
   26605 def V6_st0 : HInst<
   26606 (outs),
   26607 (ins IntRegs:$Rt32, HvxVR:$Vs32),
   26608 "vmem($Rt32) = $Vs32",
   26609 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26610 let isPseudo = 1;
   26611 let isCodeGenOnly = 1;
   26612 let DecoderNamespace = "EXT_mmvec";
   26613 }
   26614 def V6_stn0 : HInst<
   26615 (outs),
   26616 (ins IntRegs:$Rt32, HvxVR:$Os8),
   26617 "vmem($Rt32) = $Os8.new",
   26618 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26619 let isPseudo = 1;
   26620 let isCodeGenOnly = 1;
   26621 let DecoderNamespace = "EXT_mmvec";
   26622 let opNewValue = 1;
   26623 }
   26624 def V6_stnnt0 : HInst<
   26625 (outs),
   26626 (ins IntRegs:$Rt32, HvxVR:$Os8),
   26627 "vmem($Rt32):nt = $Os8.new",
   26628 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26629 let isPseudo = 1;
   26630 let isCodeGenOnly = 1;
   26631 let DecoderNamespace = "EXT_mmvec";
   26632 let opNewValue = 1;
   26633 }
   26634 def V6_stnp0 : HInst<
   26635 (outs),
   26636 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26637 "if (!$Pv4) vmem($Rt32) = $Vs32",
   26638 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26639 let isPseudo = 1;
   26640 let isCodeGenOnly = 1;
   26641 let DecoderNamespace = "EXT_mmvec";
   26642 }
   26643 def V6_stnpnt0 : HInst<
   26644 (outs),
   26645 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26646 "if (!$Pv4) vmem($Rt32):nt = $Vs32",
   26647 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26648 let isPseudo = 1;
   26649 let isCodeGenOnly = 1;
   26650 let DecoderNamespace = "EXT_mmvec";
   26651 }
   26652 def V6_stnq0 : HInst<
   26653 (outs),
   26654 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26655 "if (!$Qv4) vmem($Rt32) = $Vs32",
   26656 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26657 let isPseudo = 1;
   26658 let isCodeGenOnly = 1;
   26659 let DecoderNamespace = "EXT_mmvec";
   26660 }
   26661 def V6_stnqnt0 : HInst<
   26662 (outs),
   26663 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26664 "if (!$Qv4) vmem($Rt32):nt = $Vs32",
   26665 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26666 let isPseudo = 1;
   26667 let isCodeGenOnly = 1;
   26668 let DecoderNamespace = "EXT_mmvec";
   26669 }
   26670 def V6_stnt0 : HInst<
   26671 (outs),
   26672 (ins IntRegs:$Rt32, HvxVR:$Vs32),
   26673 "vmem($Rt32):nt = $Vs32",
   26674 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26675 let isPseudo = 1;
   26676 let isCodeGenOnly = 1;
   26677 let DecoderNamespace = "EXT_mmvec";
   26678 }
   26679 def V6_stp0 : HInst<
   26680 (outs),
   26681 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26682 "if ($Pv4) vmem($Rt32) = $Vs32",
   26683 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26684 let isPseudo = 1;
   26685 let isCodeGenOnly = 1;
   26686 let DecoderNamespace = "EXT_mmvec";
   26687 }
   26688 def V6_stpnt0 : HInst<
   26689 (outs),
   26690 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26691 "if ($Pv4) vmem($Rt32):nt = $Vs32",
   26692 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26693 let isPseudo = 1;
   26694 let isCodeGenOnly = 1;
   26695 let DecoderNamespace = "EXT_mmvec";
   26696 }
   26697 def V6_stq0 : HInst<
   26698 (outs),
   26699 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26700 "if ($Qv4) vmem($Rt32) = $Vs32",
   26701 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26702 let isPseudo = 1;
   26703 let isCodeGenOnly = 1;
   26704 let DecoderNamespace = "EXT_mmvec";
   26705 }
   26706 def V6_stqnt0 : HInst<
   26707 (outs),
   26708 (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26709 "if ($Qv4) vmem($Rt32):nt = $Vs32",
   26710 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26711 let isPseudo = 1;
   26712 let isCodeGenOnly = 1;
   26713 let DecoderNamespace = "EXT_mmvec";
   26714 }
   26715 def V6_stu0 : HInst<
   26716 (outs),
   26717 (ins IntRegs:$Rt32, HvxVR:$Vs32),
   26718 "vmemu($Rt32) = $Vs32",
   26719 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26720 let isPseudo = 1;
   26721 let isCodeGenOnly = 1;
   26722 let DecoderNamespace = "EXT_mmvec";
   26723 }
   26724 def V6_stunp0 : HInst<
   26725 (outs),
   26726 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26727 "if (!$Pv4) vmemu($Rt32) = $Vs32",
   26728 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26729 let isPseudo = 1;
   26730 let isCodeGenOnly = 1;
   26731 let DecoderNamespace = "EXT_mmvec";
   26732 }
   26733 def V6_stup0 : HInst<
   26734 (outs),
   26735 (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
   26736 "if ($Pv4) vmemu($Rt32) = $Vs32",
   26737 PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
   26738 let isPseudo = 1;
   26739 let isCodeGenOnly = 1;
   26740 let DecoderNamespace = "EXT_mmvec";
   26741 }
   26742 def V6_vL32Ub_ai : HInst<
   26743 (outs HvxVR:$Vd32),
   26744 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   26745 "$Vd32 = vmemu($Rt32+#$Ii)",
   26746 tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
   26747 let Inst{7-5} = 0b111;
   26748 let Inst{12-11} = 0b00;
   26749 let Inst{31-21} = 0b00101000000;
   26750 let hasNewValue = 1;
   26751 let opNewValue = 0;
   26752 let addrMode = BaseImmOffset;
   26753 let accessSize = HVXVectorAccess;
   26754 let isCVLoad = 1;
   26755 let mayLoad = 1;
   26756 let isRestrictNoSlot1Store = 1;
   26757 let DecoderNamespace = "EXT_mmvec";
   26758 }
   26759 def V6_vL32Ub_pi : HInst<
   26760 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26761 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   26762 "$Vd32 = vmemu($Rx32++#$Ii)",
   26763 tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
   26764 let Inst{7-5} = 0b111;
   26765 let Inst{13-11} = 0b000;
   26766 let Inst{31-21} = 0b00101001000;
   26767 let hasNewValue = 1;
   26768 let opNewValue = 0;
   26769 let addrMode = PostInc;
   26770 let accessSize = HVXVectorAccess;
   26771 let isCVLoad = 1;
   26772 let mayLoad = 1;
   26773 let isRestrictNoSlot1Store = 1;
   26774 let BaseOpcode = "V6_vL32b_pi";
   26775 let DecoderNamespace = "EXT_mmvec";
   26776 let Constraints = "$Rx32 = $Rx32in";
   26777 }
   26778 def V6_vL32Ub_ppu : HInst<
   26779 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26780 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   26781 "$Vd32 = vmemu($Rx32++$Mu2)",
   26782 tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
   26783 let Inst{12-5} = 0b00000111;
   26784 let Inst{31-21} = 0b00101011000;
   26785 let hasNewValue = 1;
   26786 let opNewValue = 0;
   26787 let addrMode = PostInc;
   26788 let accessSize = HVXVectorAccess;
   26789 let isCVLoad = 1;
   26790 let mayLoad = 1;
   26791 let isRestrictNoSlot1Store = 1;
   26792 let DecoderNamespace = "EXT_mmvec";
   26793 let Constraints = "$Rx32 = $Rx32in";
   26794 }
   26795 def V6_vL32b_ai : HInst<
   26796 (outs HvxVR:$Vd32),
   26797 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   26798 "$Vd32 = vmem($Rt32+#$Ii)",
   26799 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   26800 let Inst{7-5} = 0b000;
   26801 let Inst{12-11} = 0b00;
   26802 let Inst{31-21} = 0b00101000000;
   26803 let hasNewValue = 1;
   26804 let opNewValue = 0;
   26805 let addrMode = BaseImmOffset;
   26806 let accessSize = HVXVectorAccess;
   26807 let isCVLoad = 1;
   26808 let mayLoad = 1;
   26809 let isRestrictNoSlot1Store = 1;
   26810 let BaseOpcode = "V6_vL32b_ai";
   26811 let isCVLoadable = 1;
   26812 let isPredicable = 1;
   26813 let DecoderNamespace = "EXT_mmvec";
   26814 }
   26815 def V6_vL32b_cur_ai : HInst<
   26816 (outs HvxVR:$Vd32),
   26817 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   26818 "$Vd32.cur = vmem($Rt32+#$Ii)",
   26819 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   26820 let Inst{7-5} = 0b001;
   26821 let Inst{12-11} = 0b00;
   26822 let Inst{31-21} = 0b00101000000;
   26823 let hasNewValue = 1;
   26824 let opNewValue = 0;
   26825 let addrMode = BaseImmOffset;
   26826 let accessSize = HVXVectorAccess;
   26827 let isCVLoad = 1;
   26828 let CVINew = 1;
   26829 let mayLoad = 1;
   26830 let isRestrictNoSlot1Store = 1;
   26831 let BaseOpcode = "V6_vL32b_cur_ai";
   26832 let isPredicable = 1;
   26833 let DecoderNamespace = "EXT_mmvec";
   26834 }
   26835 def V6_vL32b_cur_npred_ai : HInst<
   26836 (outs HvxVR:$Vd32),
   26837 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   26838 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
   26839 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   26840 let Inst{7-5} = 0b101;
   26841 let Inst{31-21} = 0b00101000100;
   26842 let isPredicated = 1;
   26843 let isPredicatedFalse = 1;
   26844 let hasNewValue = 1;
   26845 let opNewValue = 0;
   26846 let addrMode = BaseImmOffset;
   26847 let accessSize = HVXVectorAccess;
   26848 let isCVLoad = 1;
   26849 let CVINew = 1;
   26850 let mayLoad = 1;
   26851 let isRestrictNoSlot1Store = 1;
   26852 let BaseOpcode = "V6_vL32b_cur_ai";
   26853 let DecoderNamespace = "EXT_mmvec";
   26854 }
   26855 def V6_vL32b_cur_npred_pi : HInst<
   26856 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26857 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   26858 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
   26859 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   26860 let Inst{7-5} = 0b101;
   26861 let Inst{13-13} = 0b0;
   26862 let Inst{31-21} = 0b00101001100;
   26863 let isPredicated = 1;
   26864 let isPredicatedFalse = 1;
   26865 let hasNewValue = 1;
   26866 let opNewValue = 0;
   26867 let addrMode = PostInc;
   26868 let accessSize = HVXVectorAccess;
   26869 let isCVLoad = 1;
   26870 let CVINew = 1;
   26871 let mayLoad = 1;
   26872 let isRestrictNoSlot1Store = 1;
   26873 let BaseOpcode = "V6_vL32b_cur_pi";
   26874 let DecoderNamespace = "EXT_mmvec";
   26875 let Constraints = "$Rx32 = $Rx32in";
   26876 }
   26877 def V6_vL32b_cur_npred_ppu : HInst<
   26878 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26879 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   26880 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
   26881 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   26882 let Inst{10-5} = 0b000101;
   26883 let Inst{31-21} = 0b00101011100;
   26884 let isPredicated = 1;
   26885 let isPredicatedFalse = 1;
   26886 let hasNewValue = 1;
   26887 let opNewValue = 0;
   26888 let addrMode = PostInc;
   26889 let accessSize = HVXVectorAccess;
   26890 let isCVLoad = 1;
   26891 let CVINew = 1;
   26892 let mayLoad = 1;
   26893 let isRestrictNoSlot1Store = 1;
   26894 let BaseOpcode = "V6_vL32b_cur_ppu";
   26895 let DecoderNamespace = "EXT_mmvec";
   26896 let Constraints = "$Rx32 = $Rx32in";
   26897 }
   26898 def V6_vL32b_cur_pi : HInst<
   26899 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26900 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   26901 "$Vd32.cur = vmem($Rx32++#$Ii)",
   26902 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   26903 let Inst{7-5} = 0b001;
   26904 let Inst{13-11} = 0b000;
   26905 let Inst{31-21} = 0b00101001000;
   26906 let hasNewValue = 1;
   26907 let opNewValue = 0;
   26908 let addrMode = PostInc;
   26909 let accessSize = HVXVectorAccess;
   26910 let isCVLoad = 1;
   26911 let CVINew = 1;
   26912 let mayLoad = 1;
   26913 let isRestrictNoSlot1Store = 1;
   26914 let BaseOpcode = "V6_vL32b_cur_pi";
   26915 let isPredicable = 1;
   26916 let DecoderNamespace = "EXT_mmvec";
   26917 let Constraints = "$Rx32 = $Rx32in";
   26918 }
   26919 def V6_vL32b_cur_ppu : HInst<
   26920 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26921 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   26922 "$Vd32.cur = vmem($Rx32++$Mu2)",
   26923 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   26924 let Inst{12-5} = 0b00000001;
   26925 let Inst{31-21} = 0b00101011000;
   26926 let hasNewValue = 1;
   26927 let opNewValue = 0;
   26928 let addrMode = PostInc;
   26929 let accessSize = HVXVectorAccess;
   26930 let isCVLoad = 1;
   26931 let CVINew = 1;
   26932 let mayLoad = 1;
   26933 let isRestrictNoSlot1Store = 1;
   26934 let BaseOpcode = "V6_vL32b_cur_ppu";
   26935 let isPredicable = 1;
   26936 let DecoderNamespace = "EXT_mmvec";
   26937 let Constraints = "$Rx32 = $Rx32in";
   26938 }
   26939 def V6_vL32b_cur_pred_ai : HInst<
   26940 (outs HvxVR:$Vd32),
   26941 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   26942 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
   26943 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   26944 let Inst{7-5} = 0b100;
   26945 let Inst{31-21} = 0b00101000100;
   26946 let isPredicated = 1;
   26947 let hasNewValue = 1;
   26948 let opNewValue = 0;
   26949 let addrMode = BaseImmOffset;
   26950 let accessSize = HVXVectorAccess;
   26951 let isCVLoad = 1;
   26952 let CVINew = 1;
   26953 let mayLoad = 1;
   26954 let isRestrictNoSlot1Store = 1;
   26955 let BaseOpcode = "V6_vL32b_cur_ai";
   26956 let DecoderNamespace = "EXT_mmvec";
   26957 }
   26958 def V6_vL32b_cur_pred_pi : HInst<
   26959 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26960 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   26961 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
   26962 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   26963 let Inst{7-5} = 0b100;
   26964 let Inst{13-13} = 0b0;
   26965 let Inst{31-21} = 0b00101001100;
   26966 let isPredicated = 1;
   26967 let hasNewValue = 1;
   26968 let opNewValue = 0;
   26969 let addrMode = PostInc;
   26970 let accessSize = HVXVectorAccess;
   26971 let isCVLoad = 1;
   26972 let CVINew = 1;
   26973 let mayLoad = 1;
   26974 let isRestrictNoSlot1Store = 1;
   26975 let BaseOpcode = "V6_vL32b_cur_pi";
   26976 let DecoderNamespace = "EXT_mmvec";
   26977 let Constraints = "$Rx32 = $Rx32in";
   26978 }
   26979 def V6_vL32b_cur_pred_ppu : HInst<
   26980 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   26981 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   26982 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
   26983 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   26984 let Inst{10-5} = 0b000100;
   26985 let Inst{31-21} = 0b00101011100;
   26986 let isPredicated = 1;
   26987 let hasNewValue = 1;
   26988 let opNewValue = 0;
   26989 let addrMode = PostInc;
   26990 let accessSize = HVXVectorAccess;
   26991 let isCVLoad = 1;
   26992 let CVINew = 1;
   26993 let mayLoad = 1;
   26994 let isRestrictNoSlot1Store = 1;
   26995 let BaseOpcode = "V6_vL32b_cur_ppu";
   26996 let DecoderNamespace = "EXT_mmvec";
   26997 let Constraints = "$Rx32 = $Rx32in";
   26998 }
   26999 def V6_vL32b_npred_ai : HInst<
   27000 (outs HvxVR:$Vd32),
   27001 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27002 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
   27003 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27004 let Inst{7-5} = 0b011;
   27005 let Inst{31-21} = 0b00101000100;
   27006 let isPredicated = 1;
   27007 let isPredicatedFalse = 1;
   27008 let hasNewValue = 1;
   27009 let opNewValue = 0;
   27010 let addrMode = BaseImmOffset;
   27011 let accessSize = HVXVectorAccess;
   27012 let isCVLoad = 1;
   27013 let mayLoad = 1;
   27014 let isRestrictNoSlot1Store = 1;
   27015 let BaseOpcode = "V6_vL32b_ai";
   27016 let DecoderNamespace = "EXT_mmvec";
   27017 }
   27018 def V6_vL32b_npred_pi : HInst<
   27019 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27020 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27021 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
   27022 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27023 let Inst{7-5} = 0b011;
   27024 let Inst{13-13} = 0b0;
   27025 let Inst{31-21} = 0b00101001100;
   27026 let isPredicated = 1;
   27027 let isPredicatedFalse = 1;
   27028 let hasNewValue = 1;
   27029 let opNewValue = 0;
   27030 let addrMode = PostInc;
   27031 let accessSize = HVXVectorAccess;
   27032 let isCVLoad = 1;
   27033 let mayLoad = 1;
   27034 let isRestrictNoSlot1Store = 1;
   27035 let BaseOpcode = "V6_vL32b_pi";
   27036 let DecoderNamespace = "EXT_mmvec";
   27037 let Constraints = "$Rx32 = $Rx32in";
   27038 }
   27039 def V6_vL32b_npred_ppu : HInst<
   27040 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27041 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27042 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
   27043 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27044 let Inst{10-5} = 0b000011;
   27045 let Inst{31-21} = 0b00101011100;
   27046 let isPredicated = 1;
   27047 let isPredicatedFalse = 1;
   27048 let hasNewValue = 1;
   27049 let opNewValue = 0;
   27050 let addrMode = PostInc;
   27051 let accessSize = HVXVectorAccess;
   27052 let isCVLoad = 1;
   27053 let mayLoad = 1;
   27054 let isRestrictNoSlot1Store = 1;
   27055 let BaseOpcode = "V6_vL32b_ppu";
   27056 let DecoderNamespace = "EXT_mmvec";
   27057 let Constraints = "$Rx32 = $Rx32in";
   27058 }
   27059 def V6_vL32b_nt_ai : HInst<
   27060 (outs HvxVR:$Vd32),
   27061 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   27062 "$Vd32 = vmem($Rt32+#$Ii):nt",
   27063 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   27064 let Inst{7-5} = 0b000;
   27065 let Inst{12-11} = 0b00;
   27066 let Inst{31-21} = 0b00101000010;
   27067 let hasNewValue = 1;
   27068 let opNewValue = 0;
   27069 let addrMode = BaseImmOffset;
   27070 let accessSize = HVXVectorAccess;
   27071 let isCVLoad = 1;
   27072 let mayLoad = 1;
   27073 let isNonTemporal = 1;
   27074 let isRestrictNoSlot1Store = 1;
   27075 let BaseOpcode = "V6_vL32b_nt_ai";
   27076 let isCVLoadable = 1;
   27077 let isPredicable = 1;
   27078 let DecoderNamespace = "EXT_mmvec";
   27079 }
   27080 def V6_vL32b_nt_cur_ai : HInst<
   27081 (outs HvxVR:$Vd32),
   27082 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   27083 "$Vd32.cur = vmem($Rt32+#$Ii):nt",
   27084 tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   27085 let Inst{7-5} = 0b001;
   27086 let Inst{12-11} = 0b00;
   27087 let Inst{31-21} = 0b00101000010;
   27088 let hasNewValue = 1;
   27089 let opNewValue = 0;
   27090 let addrMode = BaseImmOffset;
   27091 let accessSize = HVXVectorAccess;
   27092 let isCVLoad = 1;
   27093 let CVINew = 1;
   27094 let mayLoad = 1;
   27095 let isNonTemporal = 1;
   27096 let isRestrictNoSlot1Store = 1;
   27097 let BaseOpcode = "V6_vL32b_nt_cur_ai";
   27098 let isPredicable = 1;
   27099 let DecoderNamespace = "EXT_mmvec";
   27100 }
   27101 def V6_vL32b_nt_cur_npred_ai : HInst<
   27102 (outs HvxVR:$Vd32),
   27103 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27104 "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
   27105 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27106 let Inst{7-5} = 0b101;
   27107 let Inst{31-21} = 0b00101000110;
   27108 let isPredicated = 1;
   27109 let isPredicatedFalse = 1;
   27110 let hasNewValue = 1;
   27111 let opNewValue = 0;
   27112 let addrMode = BaseImmOffset;
   27113 let accessSize = HVXVectorAccess;
   27114 let isCVLoad = 1;
   27115 let CVINew = 1;
   27116 let mayLoad = 1;
   27117 let isNonTemporal = 1;
   27118 let isRestrictNoSlot1Store = 1;
   27119 let BaseOpcode = "V6_vL32b_nt_cur_ai";
   27120 let DecoderNamespace = "EXT_mmvec";
   27121 }
   27122 def V6_vL32b_nt_cur_npred_pi : HInst<
   27123 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27124 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27125 "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
   27126 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27127 let Inst{7-5} = 0b101;
   27128 let Inst{13-13} = 0b0;
   27129 let Inst{31-21} = 0b00101001110;
   27130 let isPredicated = 1;
   27131 let isPredicatedFalse = 1;
   27132 let hasNewValue = 1;
   27133 let opNewValue = 0;
   27134 let addrMode = PostInc;
   27135 let accessSize = HVXVectorAccess;
   27136 let isCVLoad = 1;
   27137 let CVINew = 1;
   27138 let mayLoad = 1;
   27139 let isNonTemporal = 1;
   27140 let isRestrictNoSlot1Store = 1;
   27141 let BaseOpcode = "V6_vL32b_nt_cur_pi";
   27142 let DecoderNamespace = "EXT_mmvec";
   27143 let Constraints = "$Rx32 = $Rx32in";
   27144 }
   27145 def V6_vL32b_nt_cur_npred_ppu : HInst<
   27146 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27147 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27148 "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
   27149 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27150 let Inst{10-5} = 0b000101;
   27151 let Inst{31-21} = 0b00101011110;
   27152 let isPredicated = 1;
   27153 let isPredicatedFalse = 1;
   27154 let hasNewValue = 1;
   27155 let opNewValue = 0;
   27156 let addrMode = PostInc;
   27157 let accessSize = HVXVectorAccess;
   27158 let isCVLoad = 1;
   27159 let CVINew = 1;
   27160 let mayLoad = 1;
   27161 let isNonTemporal = 1;
   27162 let isRestrictNoSlot1Store = 1;
   27163 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
   27164 let DecoderNamespace = "EXT_mmvec";
   27165 let Constraints = "$Rx32 = $Rx32in";
   27166 }
   27167 def V6_vL32b_nt_cur_pi : HInst<
   27168 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27169 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   27170 "$Vd32.cur = vmem($Rx32++#$Ii):nt",
   27171 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   27172 let Inst{7-5} = 0b001;
   27173 let Inst{13-11} = 0b000;
   27174 let Inst{31-21} = 0b00101001010;
   27175 let hasNewValue = 1;
   27176 let opNewValue = 0;
   27177 let addrMode = PostInc;
   27178 let accessSize = HVXVectorAccess;
   27179 let isCVLoad = 1;
   27180 let CVINew = 1;
   27181 let mayLoad = 1;
   27182 let isNonTemporal = 1;
   27183 let isRestrictNoSlot1Store = 1;
   27184 let BaseOpcode = "V6_vL32b_nt_cur_pi";
   27185 let isPredicable = 1;
   27186 let DecoderNamespace = "EXT_mmvec";
   27187 let Constraints = "$Rx32 = $Rx32in";
   27188 }
   27189 def V6_vL32b_nt_cur_ppu : HInst<
   27190 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27191 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   27192 "$Vd32.cur = vmem($Rx32++$Mu2):nt",
   27193 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   27194 let Inst{12-5} = 0b00000001;
   27195 let Inst{31-21} = 0b00101011010;
   27196 let hasNewValue = 1;
   27197 let opNewValue = 0;
   27198 let addrMode = PostInc;
   27199 let accessSize = HVXVectorAccess;
   27200 let isCVLoad = 1;
   27201 let CVINew = 1;
   27202 let mayLoad = 1;
   27203 let isNonTemporal = 1;
   27204 let isRestrictNoSlot1Store = 1;
   27205 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
   27206 let isPredicable = 1;
   27207 let DecoderNamespace = "EXT_mmvec";
   27208 let Constraints = "$Rx32 = $Rx32in";
   27209 }
   27210 def V6_vL32b_nt_cur_pred_ai : HInst<
   27211 (outs HvxVR:$Vd32),
   27212 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27213 "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
   27214 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27215 let Inst{7-5} = 0b100;
   27216 let Inst{31-21} = 0b00101000110;
   27217 let isPredicated = 1;
   27218 let hasNewValue = 1;
   27219 let opNewValue = 0;
   27220 let addrMode = BaseImmOffset;
   27221 let accessSize = HVXVectorAccess;
   27222 let isCVLoad = 1;
   27223 let CVINew = 1;
   27224 let mayLoad = 1;
   27225 let isNonTemporal = 1;
   27226 let isRestrictNoSlot1Store = 1;
   27227 let BaseOpcode = "V6_vL32b_nt_cur_ai";
   27228 let DecoderNamespace = "EXT_mmvec";
   27229 }
   27230 def V6_vL32b_nt_cur_pred_pi : HInst<
   27231 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27232 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27233 "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
   27234 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27235 let Inst{7-5} = 0b100;
   27236 let Inst{13-13} = 0b0;
   27237 let Inst{31-21} = 0b00101001110;
   27238 let isPredicated = 1;
   27239 let hasNewValue = 1;
   27240 let opNewValue = 0;
   27241 let addrMode = PostInc;
   27242 let accessSize = HVXVectorAccess;
   27243 let isCVLoad = 1;
   27244 let CVINew = 1;
   27245 let mayLoad = 1;
   27246 let isNonTemporal = 1;
   27247 let isRestrictNoSlot1Store = 1;
   27248 let BaseOpcode = "V6_vL32b_nt_cur_pi";
   27249 let DecoderNamespace = "EXT_mmvec";
   27250 let Constraints = "$Rx32 = $Rx32in";
   27251 }
   27252 def V6_vL32b_nt_cur_pred_ppu : HInst<
   27253 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27254 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27255 "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
   27256 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27257 let Inst{10-5} = 0b000100;
   27258 let Inst{31-21} = 0b00101011110;
   27259 let isPredicated = 1;
   27260 let hasNewValue = 1;
   27261 let opNewValue = 0;
   27262 let addrMode = PostInc;
   27263 let accessSize = HVXVectorAccess;
   27264 let isCVLoad = 1;
   27265 let CVINew = 1;
   27266 let mayLoad = 1;
   27267 let isNonTemporal = 1;
   27268 let isRestrictNoSlot1Store = 1;
   27269 let BaseOpcode = "V6_vL32b_nt_cur_ppu";
   27270 let DecoderNamespace = "EXT_mmvec";
   27271 let Constraints = "$Rx32 = $Rx32in";
   27272 }
   27273 def V6_vL32b_nt_npred_ai : HInst<
   27274 (outs HvxVR:$Vd32),
   27275 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27276 "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
   27277 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27278 let Inst{7-5} = 0b011;
   27279 let Inst{31-21} = 0b00101000110;
   27280 let isPredicated = 1;
   27281 let isPredicatedFalse = 1;
   27282 let hasNewValue = 1;
   27283 let opNewValue = 0;
   27284 let addrMode = BaseImmOffset;
   27285 let accessSize = HVXVectorAccess;
   27286 let isCVLoad = 1;
   27287 let mayLoad = 1;
   27288 let isNonTemporal = 1;
   27289 let isRestrictNoSlot1Store = 1;
   27290 let BaseOpcode = "V6_vL32b_nt_ai";
   27291 let DecoderNamespace = "EXT_mmvec";
   27292 }
   27293 def V6_vL32b_nt_npred_pi : HInst<
   27294 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27295 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27296 "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
   27297 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27298 let Inst{7-5} = 0b011;
   27299 let Inst{13-13} = 0b0;
   27300 let Inst{31-21} = 0b00101001110;
   27301 let isPredicated = 1;
   27302 let isPredicatedFalse = 1;
   27303 let hasNewValue = 1;
   27304 let opNewValue = 0;
   27305 let addrMode = PostInc;
   27306 let accessSize = HVXVectorAccess;
   27307 let isCVLoad = 1;
   27308 let mayLoad = 1;
   27309 let isNonTemporal = 1;
   27310 let isRestrictNoSlot1Store = 1;
   27311 let BaseOpcode = "V6_vL32b_nt_pi";
   27312 let DecoderNamespace = "EXT_mmvec";
   27313 let Constraints = "$Rx32 = $Rx32in";
   27314 }
   27315 def V6_vL32b_nt_npred_ppu : HInst<
   27316 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27317 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27318 "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
   27319 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27320 let Inst{10-5} = 0b000011;
   27321 let Inst{31-21} = 0b00101011110;
   27322 let isPredicated = 1;
   27323 let isPredicatedFalse = 1;
   27324 let hasNewValue = 1;
   27325 let opNewValue = 0;
   27326 let addrMode = PostInc;
   27327 let accessSize = HVXVectorAccess;
   27328 let isCVLoad = 1;
   27329 let mayLoad = 1;
   27330 let isNonTemporal = 1;
   27331 let isRestrictNoSlot1Store = 1;
   27332 let BaseOpcode = "V6_vL32b_nt_ppu";
   27333 let DecoderNamespace = "EXT_mmvec";
   27334 let Constraints = "$Rx32 = $Rx32in";
   27335 }
   27336 def V6_vL32b_nt_pi : HInst<
   27337 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27338 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   27339 "$Vd32 = vmem($Rx32++#$Ii):nt",
   27340 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   27341 let Inst{7-5} = 0b000;
   27342 let Inst{13-11} = 0b000;
   27343 let Inst{31-21} = 0b00101001010;
   27344 let hasNewValue = 1;
   27345 let opNewValue = 0;
   27346 let addrMode = PostInc;
   27347 let accessSize = HVXVectorAccess;
   27348 let isCVLoad = 1;
   27349 let mayLoad = 1;
   27350 let isNonTemporal = 1;
   27351 let isRestrictNoSlot1Store = 1;
   27352 let BaseOpcode = "V6_vL32b_nt_pi";
   27353 let isCVLoadable = 1;
   27354 let isPredicable = 1;
   27355 let DecoderNamespace = "EXT_mmvec";
   27356 let Constraints = "$Rx32 = $Rx32in";
   27357 }
   27358 def V6_vL32b_nt_ppu : HInst<
   27359 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27360 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   27361 "$Vd32 = vmem($Rx32++$Mu2):nt",
   27362 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   27363 let Inst{12-5} = 0b00000000;
   27364 let Inst{31-21} = 0b00101011010;
   27365 let hasNewValue = 1;
   27366 let opNewValue = 0;
   27367 let addrMode = PostInc;
   27368 let accessSize = HVXVectorAccess;
   27369 let isCVLoad = 1;
   27370 let mayLoad = 1;
   27371 let isNonTemporal = 1;
   27372 let isRestrictNoSlot1Store = 1;
   27373 let BaseOpcode = "V6_vL32b_nt_ppu";
   27374 let isCVLoadable = 1;
   27375 let isPredicable = 1;
   27376 let DecoderNamespace = "EXT_mmvec";
   27377 let Constraints = "$Rx32 = $Rx32in";
   27378 }
   27379 def V6_vL32b_nt_pred_ai : HInst<
   27380 (outs HvxVR:$Vd32),
   27381 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27382 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
   27383 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27384 let Inst{7-5} = 0b010;
   27385 let Inst{31-21} = 0b00101000110;
   27386 let isPredicated = 1;
   27387 let hasNewValue = 1;
   27388 let opNewValue = 0;
   27389 let addrMode = BaseImmOffset;
   27390 let accessSize = HVXVectorAccess;
   27391 let isCVLoad = 1;
   27392 let mayLoad = 1;
   27393 let isNonTemporal = 1;
   27394 let isRestrictNoSlot1Store = 1;
   27395 let BaseOpcode = "V6_vL32b_nt_ai";
   27396 let DecoderNamespace = "EXT_mmvec";
   27397 }
   27398 def V6_vL32b_nt_pred_pi : HInst<
   27399 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27400 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27401 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
   27402 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27403 let Inst{7-5} = 0b010;
   27404 let Inst{13-13} = 0b0;
   27405 let Inst{31-21} = 0b00101001110;
   27406 let isPredicated = 1;
   27407 let hasNewValue = 1;
   27408 let opNewValue = 0;
   27409 let addrMode = PostInc;
   27410 let accessSize = HVXVectorAccess;
   27411 let isCVLoad = 1;
   27412 let mayLoad = 1;
   27413 let isNonTemporal = 1;
   27414 let isRestrictNoSlot1Store = 1;
   27415 let BaseOpcode = "V6_vL32b_nt_pi";
   27416 let DecoderNamespace = "EXT_mmvec";
   27417 let Constraints = "$Rx32 = $Rx32in";
   27418 }
   27419 def V6_vL32b_nt_pred_ppu : HInst<
   27420 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27421 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27422 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
   27423 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27424 let Inst{10-5} = 0b000010;
   27425 let Inst{31-21} = 0b00101011110;
   27426 let isPredicated = 1;
   27427 let hasNewValue = 1;
   27428 let opNewValue = 0;
   27429 let addrMode = PostInc;
   27430 let accessSize = HVXVectorAccess;
   27431 let isCVLoad = 1;
   27432 let mayLoad = 1;
   27433 let isNonTemporal = 1;
   27434 let isRestrictNoSlot1Store = 1;
   27435 let BaseOpcode = "V6_vL32b_nt_ppu";
   27436 let DecoderNamespace = "EXT_mmvec";
   27437 let Constraints = "$Rx32 = $Rx32in";
   27438 }
   27439 def V6_vL32b_nt_tmp_ai : HInst<
   27440 (outs HvxVR:$Vd32),
   27441 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   27442 "$Vd32.tmp = vmem($Rt32+#$Ii):nt",
   27443 tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   27444 let Inst{7-5} = 0b010;
   27445 let Inst{12-11} = 0b00;
   27446 let Inst{31-21} = 0b00101000010;
   27447 let hasNewValue = 1;
   27448 let opNewValue = 0;
   27449 let addrMode = BaseImmOffset;
   27450 let accessSize = HVXVectorAccess;
   27451 let isCVLoad = 1;
   27452 let mayLoad = 1;
   27453 let isNonTemporal = 1;
   27454 let isRestrictNoSlot1Store = 1;
   27455 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
   27456 let isPredicable = 1;
   27457 let DecoderNamespace = "EXT_mmvec";
   27458 }
   27459 def V6_vL32b_nt_tmp_npred_ai : HInst<
   27460 (outs HvxVR:$Vd32),
   27461 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27462 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
   27463 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27464 let Inst{7-5} = 0b111;
   27465 let Inst{31-21} = 0b00101000110;
   27466 let isPredicated = 1;
   27467 let isPredicatedFalse = 1;
   27468 let hasNewValue = 1;
   27469 let opNewValue = 0;
   27470 let addrMode = BaseImmOffset;
   27471 let accessSize = HVXVectorAccess;
   27472 let isCVLoad = 1;
   27473 let mayLoad = 1;
   27474 let isNonTemporal = 1;
   27475 let isRestrictNoSlot1Store = 1;
   27476 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
   27477 let DecoderNamespace = "EXT_mmvec";
   27478 }
   27479 def V6_vL32b_nt_tmp_npred_pi : HInst<
   27480 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27481 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27482 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
   27483 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27484 let Inst{7-5} = 0b111;
   27485 let Inst{13-13} = 0b0;
   27486 let Inst{31-21} = 0b00101001110;
   27487 let isPredicated = 1;
   27488 let isPredicatedFalse = 1;
   27489 let hasNewValue = 1;
   27490 let opNewValue = 0;
   27491 let addrMode = PostInc;
   27492 let accessSize = HVXVectorAccess;
   27493 let isCVLoad = 1;
   27494 let mayLoad = 1;
   27495 let isNonTemporal = 1;
   27496 let isRestrictNoSlot1Store = 1;
   27497 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
   27498 let DecoderNamespace = "EXT_mmvec";
   27499 let Constraints = "$Rx32 = $Rx32in";
   27500 }
   27501 def V6_vL32b_nt_tmp_npred_ppu : HInst<
   27502 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27503 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27504 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
   27505 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27506 let Inst{10-5} = 0b000111;
   27507 let Inst{31-21} = 0b00101011110;
   27508 let isPredicated = 1;
   27509 let isPredicatedFalse = 1;
   27510 let hasNewValue = 1;
   27511 let opNewValue = 0;
   27512 let addrMode = PostInc;
   27513 let accessSize = HVXVectorAccess;
   27514 let isCVLoad = 1;
   27515 let mayLoad = 1;
   27516 let isNonTemporal = 1;
   27517 let isRestrictNoSlot1Store = 1;
   27518 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
   27519 let DecoderNamespace = "EXT_mmvec";
   27520 let Constraints = "$Rx32 = $Rx32in";
   27521 }
   27522 def V6_vL32b_nt_tmp_pi : HInst<
   27523 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27524 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   27525 "$Vd32.tmp = vmem($Rx32++#$Ii):nt",
   27526 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   27527 let Inst{7-5} = 0b010;
   27528 let Inst{13-11} = 0b000;
   27529 let Inst{31-21} = 0b00101001010;
   27530 let hasNewValue = 1;
   27531 let opNewValue = 0;
   27532 let addrMode = PostInc;
   27533 let accessSize = HVXVectorAccess;
   27534 let isCVLoad = 1;
   27535 let mayLoad = 1;
   27536 let isNonTemporal = 1;
   27537 let isRestrictNoSlot1Store = 1;
   27538 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
   27539 let isPredicable = 1;
   27540 let DecoderNamespace = "EXT_mmvec";
   27541 let Constraints = "$Rx32 = $Rx32in";
   27542 }
   27543 def V6_vL32b_nt_tmp_ppu : HInst<
   27544 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27545 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   27546 "$Vd32.tmp = vmem($Rx32++$Mu2):nt",
   27547 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   27548 let Inst{12-5} = 0b00000010;
   27549 let Inst{31-21} = 0b00101011010;
   27550 let hasNewValue = 1;
   27551 let opNewValue = 0;
   27552 let addrMode = PostInc;
   27553 let accessSize = HVXVectorAccess;
   27554 let isCVLoad = 1;
   27555 let mayLoad = 1;
   27556 let isNonTemporal = 1;
   27557 let isRestrictNoSlot1Store = 1;
   27558 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
   27559 let isPredicable = 1;
   27560 let DecoderNamespace = "EXT_mmvec";
   27561 let Constraints = "$Rx32 = $Rx32in";
   27562 }
   27563 def V6_vL32b_nt_tmp_pred_ai : HInst<
   27564 (outs HvxVR:$Vd32),
   27565 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27566 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
   27567 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27568 let Inst{7-5} = 0b110;
   27569 let Inst{31-21} = 0b00101000110;
   27570 let isPredicated = 1;
   27571 let hasNewValue = 1;
   27572 let opNewValue = 0;
   27573 let addrMode = BaseImmOffset;
   27574 let accessSize = HVXVectorAccess;
   27575 let isCVLoad = 1;
   27576 let mayLoad = 1;
   27577 let isNonTemporal = 1;
   27578 let isRestrictNoSlot1Store = 1;
   27579 let BaseOpcode = "V6_vL32b_nt_tmp_ai";
   27580 let DecoderNamespace = "EXT_mmvec";
   27581 }
   27582 def V6_vL32b_nt_tmp_pred_pi : HInst<
   27583 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27584 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27585 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
   27586 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27587 let Inst{7-5} = 0b110;
   27588 let Inst{13-13} = 0b0;
   27589 let Inst{31-21} = 0b00101001110;
   27590 let isPredicated = 1;
   27591 let hasNewValue = 1;
   27592 let opNewValue = 0;
   27593 let addrMode = PostInc;
   27594 let accessSize = HVXVectorAccess;
   27595 let isCVLoad = 1;
   27596 let mayLoad = 1;
   27597 let isNonTemporal = 1;
   27598 let isRestrictNoSlot1Store = 1;
   27599 let BaseOpcode = "V6_vL32b_nt_tmp_pi";
   27600 let DecoderNamespace = "EXT_mmvec";
   27601 let Constraints = "$Rx32 = $Rx32in";
   27602 }
   27603 def V6_vL32b_nt_tmp_pred_ppu : HInst<
   27604 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27605 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27606 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
   27607 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27608 let Inst{10-5} = 0b000110;
   27609 let Inst{31-21} = 0b00101011110;
   27610 let isPredicated = 1;
   27611 let hasNewValue = 1;
   27612 let opNewValue = 0;
   27613 let addrMode = PostInc;
   27614 let accessSize = HVXVectorAccess;
   27615 let isCVLoad = 1;
   27616 let mayLoad = 1;
   27617 let isNonTemporal = 1;
   27618 let isRestrictNoSlot1Store = 1;
   27619 let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
   27620 let DecoderNamespace = "EXT_mmvec";
   27621 let Constraints = "$Rx32 = $Rx32in";
   27622 }
   27623 def V6_vL32b_pi : HInst<
   27624 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27625 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   27626 "$Vd32 = vmem($Rx32++#$Ii)",
   27627 tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   27628 let Inst{7-5} = 0b000;
   27629 let Inst{13-11} = 0b000;
   27630 let Inst{31-21} = 0b00101001000;
   27631 let hasNewValue = 1;
   27632 let opNewValue = 0;
   27633 let addrMode = PostInc;
   27634 let accessSize = HVXVectorAccess;
   27635 let isCVLoad = 1;
   27636 let mayLoad = 1;
   27637 let isRestrictNoSlot1Store = 1;
   27638 let BaseOpcode = "V6_vL32b_pi";
   27639 let isCVLoadable = 1;
   27640 let isPredicable = 1;
   27641 let DecoderNamespace = "EXT_mmvec";
   27642 let Constraints = "$Rx32 = $Rx32in";
   27643 }
   27644 def V6_vL32b_ppu : HInst<
   27645 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27646 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   27647 "$Vd32 = vmem($Rx32++$Mu2)",
   27648 tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   27649 let Inst{12-5} = 0b00000000;
   27650 let Inst{31-21} = 0b00101011000;
   27651 let hasNewValue = 1;
   27652 let opNewValue = 0;
   27653 let addrMode = PostInc;
   27654 let accessSize = HVXVectorAccess;
   27655 let isCVLoad = 1;
   27656 let mayLoad = 1;
   27657 let isRestrictNoSlot1Store = 1;
   27658 let BaseOpcode = "V6_vL32b_ppu";
   27659 let isCVLoadable = 1;
   27660 let isPredicable = 1;
   27661 let DecoderNamespace = "EXT_mmvec";
   27662 let Constraints = "$Rx32 = $Rx32in";
   27663 }
   27664 def V6_vL32b_pred_ai : HInst<
   27665 (outs HvxVR:$Vd32),
   27666 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27667 "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
   27668 tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27669 let Inst{7-5} = 0b010;
   27670 let Inst{31-21} = 0b00101000100;
   27671 let isPredicated = 1;
   27672 let hasNewValue = 1;
   27673 let opNewValue = 0;
   27674 let addrMode = BaseImmOffset;
   27675 let accessSize = HVXVectorAccess;
   27676 let isCVLoad = 1;
   27677 let mayLoad = 1;
   27678 let isRestrictNoSlot1Store = 1;
   27679 let BaseOpcode = "V6_vL32b_ai";
   27680 let DecoderNamespace = "EXT_mmvec";
   27681 }
   27682 def V6_vL32b_pred_pi : HInst<
   27683 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27684 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27685 "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
   27686 tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27687 let Inst{7-5} = 0b010;
   27688 let Inst{13-13} = 0b0;
   27689 let Inst{31-21} = 0b00101001100;
   27690 let isPredicated = 1;
   27691 let hasNewValue = 1;
   27692 let opNewValue = 0;
   27693 let addrMode = PostInc;
   27694 let accessSize = HVXVectorAccess;
   27695 let isCVLoad = 1;
   27696 let mayLoad = 1;
   27697 let isRestrictNoSlot1Store = 1;
   27698 let BaseOpcode = "V6_vL32b_pi";
   27699 let DecoderNamespace = "EXT_mmvec";
   27700 let Constraints = "$Rx32 = $Rx32in";
   27701 }
   27702 def V6_vL32b_pred_ppu : HInst<
   27703 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27704 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27705 "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
   27706 tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27707 let Inst{10-5} = 0b000010;
   27708 let Inst{31-21} = 0b00101011100;
   27709 let isPredicated = 1;
   27710 let hasNewValue = 1;
   27711 let opNewValue = 0;
   27712 let addrMode = PostInc;
   27713 let accessSize = HVXVectorAccess;
   27714 let isCVLoad = 1;
   27715 let mayLoad = 1;
   27716 let isRestrictNoSlot1Store = 1;
   27717 let BaseOpcode = "V6_vL32b_ppu";
   27718 let DecoderNamespace = "EXT_mmvec";
   27719 let Constraints = "$Rx32 = $Rx32in";
   27720 }
   27721 def V6_vL32b_tmp_ai : HInst<
   27722 (outs HvxVR:$Vd32),
   27723 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   27724 "$Vd32.tmp = vmem($Rt32+#$Ii)",
   27725 tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
   27726 let Inst{7-5} = 0b010;
   27727 let Inst{12-11} = 0b00;
   27728 let Inst{31-21} = 0b00101000000;
   27729 let hasNewValue = 1;
   27730 let opNewValue = 0;
   27731 let addrMode = BaseImmOffset;
   27732 let accessSize = HVXVectorAccess;
   27733 let isCVLoad = 1;
   27734 let mayLoad = 1;
   27735 let isRestrictNoSlot1Store = 1;
   27736 let BaseOpcode = "V6_vL32b_tmp_ai";
   27737 let isPredicable = 1;
   27738 let DecoderNamespace = "EXT_mmvec";
   27739 }
   27740 def V6_vL32b_tmp_npred_ai : HInst<
   27741 (outs HvxVR:$Vd32),
   27742 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27743 "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
   27744 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27745 let Inst{7-5} = 0b111;
   27746 let Inst{31-21} = 0b00101000100;
   27747 let isPredicated = 1;
   27748 let isPredicatedFalse = 1;
   27749 let hasNewValue = 1;
   27750 let opNewValue = 0;
   27751 let addrMode = BaseImmOffset;
   27752 let accessSize = HVXVectorAccess;
   27753 let isCVLoad = 1;
   27754 let mayLoad = 1;
   27755 let isRestrictNoSlot1Store = 1;
   27756 let BaseOpcode = "V6_vL32b_tmp_ai";
   27757 let DecoderNamespace = "EXT_mmvec";
   27758 }
   27759 def V6_vL32b_tmp_npred_pi : HInst<
   27760 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27761 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27762 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
   27763 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27764 let Inst{7-5} = 0b111;
   27765 let Inst{13-13} = 0b0;
   27766 let Inst{31-21} = 0b00101001100;
   27767 let isPredicated = 1;
   27768 let isPredicatedFalse = 1;
   27769 let hasNewValue = 1;
   27770 let opNewValue = 0;
   27771 let addrMode = PostInc;
   27772 let accessSize = HVXVectorAccess;
   27773 let isCVLoad = 1;
   27774 let mayLoad = 1;
   27775 let isRestrictNoSlot1Store = 1;
   27776 let BaseOpcode = "V6_vL32b_tmp_pi";
   27777 let DecoderNamespace = "EXT_mmvec";
   27778 let Constraints = "$Rx32 = $Rx32in";
   27779 }
   27780 def V6_vL32b_tmp_npred_ppu : HInst<
   27781 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27782 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27783 "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
   27784 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27785 let Inst{10-5} = 0b000111;
   27786 let Inst{31-21} = 0b00101011100;
   27787 let isPredicated = 1;
   27788 let isPredicatedFalse = 1;
   27789 let hasNewValue = 1;
   27790 let opNewValue = 0;
   27791 let addrMode = PostInc;
   27792 let accessSize = HVXVectorAccess;
   27793 let isCVLoad = 1;
   27794 let mayLoad = 1;
   27795 let isRestrictNoSlot1Store = 1;
   27796 let BaseOpcode = "V6_vL32b_tmp_ppu";
   27797 let DecoderNamespace = "EXT_mmvec";
   27798 let Constraints = "$Rx32 = $Rx32in";
   27799 }
   27800 def V6_vL32b_tmp_pi : HInst<
   27801 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27802 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   27803 "$Vd32.tmp = vmem($Rx32++#$Ii)",
   27804 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
   27805 let Inst{7-5} = 0b010;
   27806 let Inst{13-11} = 0b000;
   27807 let Inst{31-21} = 0b00101001000;
   27808 let hasNewValue = 1;
   27809 let opNewValue = 0;
   27810 let addrMode = PostInc;
   27811 let accessSize = HVXVectorAccess;
   27812 let isCVLoad = 1;
   27813 let mayLoad = 1;
   27814 let isRestrictNoSlot1Store = 1;
   27815 let BaseOpcode = "V6_vL32b_tmp_pi";
   27816 let isPredicable = 1;
   27817 let DecoderNamespace = "EXT_mmvec";
   27818 let Constraints = "$Rx32 = $Rx32in";
   27819 }
   27820 def V6_vL32b_tmp_ppu : HInst<
   27821 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27822 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   27823 "$Vd32.tmp = vmem($Rx32++$Mu2)",
   27824 tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
   27825 let Inst{12-5} = 0b00000010;
   27826 let Inst{31-21} = 0b00101011000;
   27827 let hasNewValue = 1;
   27828 let opNewValue = 0;
   27829 let addrMode = PostInc;
   27830 let accessSize = HVXVectorAccess;
   27831 let isCVLoad = 1;
   27832 let mayLoad = 1;
   27833 let isRestrictNoSlot1Store = 1;
   27834 let BaseOpcode = "V6_vL32b_tmp_ppu";
   27835 let isPredicable = 1;
   27836 let DecoderNamespace = "EXT_mmvec";
   27837 let Constraints = "$Rx32 = $Rx32in";
   27838 }
   27839 def V6_vL32b_tmp_pred_ai : HInst<
   27840 (outs HvxVR:$Vd32),
   27841 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
   27842 "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
   27843 tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
   27844 let Inst{7-5} = 0b110;
   27845 let Inst{31-21} = 0b00101000100;
   27846 let isPredicated = 1;
   27847 let hasNewValue = 1;
   27848 let opNewValue = 0;
   27849 let addrMode = BaseImmOffset;
   27850 let accessSize = HVXVectorAccess;
   27851 let isCVLoad = 1;
   27852 let mayLoad = 1;
   27853 let isRestrictNoSlot1Store = 1;
   27854 let BaseOpcode = "V6_vL32b_tmp_ai";
   27855 let DecoderNamespace = "EXT_mmvec";
   27856 }
   27857 def V6_vL32b_tmp_pred_pi : HInst<
   27858 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27859 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
   27860 "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
   27861 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
   27862 let Inst{7-5} = 0b110;
   27863 let Inst{13-13} = 0b0;
   27864 let Inst{31-21} = 0b00101001100;
   27865 let isPredicated = 1;
   27866 let hasNewValue = 1;
   27867 let opNewValue = 0;
   27868 let addrMode = PostInc;
   27869 let accessSize = HVXVectorAccess;
   27870 let isCVLoad = 1;
   27871 let mayLoad = 1;
   27872 let isRestrictNoSlot1Store = 1;
   27873 let BaseOpcode = "V6_vL32b_tmp_pi";
   27874 let DecoderNamespace = "EXT_mmvec";
   27875 let Constraints = "$Rx32 = $Rx32in";
   27876 }
   27877 def V6_vL32b_tmp_pred_ppu : HInst<
   27878 (outs HvxVR:$Vd32, IntRegs:$Rx32),
   27879 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
   27880 "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
   27881 tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
   27882 let Inst{10-5} = 0b000110;
   27883 let Inst{31-21} = 0b00101011100;
   27884 let isPredicated = 1;
   27885 let hasNewValue = 1;
   27886 let opNewValue = 0;
   27887 let addrMode = PostInc;
   27888 let accessSize = HVXVectorAccess;
   27889 let isCVLoad = 1;
   27890 let mayLoad = 1;
   27891 let isRestrictNoSlot1Store = 1;
   27892 let BaseOpcode = "V6_vL32b_tmp_ppu";
   27893 let DecoderNamespace = "EXT_mmvec";
   27894 let Constraints = "$Rx32 = $Rx32in";
   27895 }
   27896 def V6_vS32Ub_ai : HInst<
   27897 (outs),
   27898 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   27899 "vmemu($Rt32+#$Ii) = $Vs32",
   27900 tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
   27901 let Inst{7-5} = 0b111;
   27902 let Inst{12-11} = 0b00;
   27903 let Inst{31-21} = 0b00101000001;
   27904 let addrMode = BaseImmOffset;
   27905 let accessSize = HVXVectorAccess;
   27906 let mayStore = 1;
   27907 let BaseOpcode = "V6_vS32Ub_ai";
   27908 let isPredicable = 1;
   27909 let DecoderNamespace = "EXT_mmvec";
   27910 }
   27911 def V6_vS32Ub_npred_ai : HInst<
   27912 (outs),
   27913 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   27914 "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
   27915 tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   27916 let Inst{7-5} = 0b111;
   27917 let Inst{31-21} = 0b00101000101;
   27918 let isPredicated = 1;
   27919 let isPredicatedFalse = 1;
   27920 let addrMode = BaseImmOffset;
   27921 let accessSize = HVXVectorAccess;
   27922 let mayStore = 1;
   27923 let BaseOpcode = "V6_vS32Ub_ai";
   27924 let DecoderNamespace = "EXT_mmvec";
   27925 }
   27926 def V6_vS32Ub_npred_pi : HInst<
   27927 (outs IntRegs:$Rx32),
   27928 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   27929 "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
   27930 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   27931 let Inst{7-5} = 0b111;
   27932 let Inst{13-13} = 0b0;
   27933 let Inst{31-21} = 0b00101001101;
   27934 let isPredicated = 1;
   27935 let isPredicatedFalse = 1;
   27936 let addrMode = PostInc;
   27937 let accessSize = HVXVectorAccess;
   27938 let mayStore = 1;
   27939 let BaseOpcode = "V6_vS32Ub_pi";
   27940 let DecoderNamespace = "EXT_mmvec";
   27941 let Constraints = "$Rx32 = $Rx32in";
   27942 }
   27943 def V6_vS32Ub_npred_ppu : HInst<
   27944 (outs IntRegs:$Rx32),
   27945 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   27946 "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
   27947 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   27948 let Inst{10-5} = 0b000111;
   27949 let Inst{31-21} = 0b00101011101;
   27950 let isPredicated = 1;
   27951 let isPredicatedFalse = 1;
   27952 let addrMode = PostInc;
   27953 let accessSize = HVXVectorAccess;
   27954 let mayStore = 1;
   27955 let BaseOpcode = "V6_vS32Ub_ppu";
   27956 let DecoderNamespace = "EXT_mmvec";
   27957 let Constraints = "$Rx32 = $Rx32in";
   27958 }
   27959 def V6_vS32Ub_pi : HInst<
   27960 (outs IntRegs:$Rx32),
   27961 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   27962 "vmemu($Rx32++#$Ii) = $Vs32",
   27963 tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
   27964 let Inst{7-5} = 0b111;
   27965 let Inst{13-11} = 0b000;
   27966 let Inst{31-21} = 0b00101001001;
   27967 let addrMode = PostInc;
   27968 let accessSize = HVXVectorAccess;
   27969 let mayStore = 1;
   27970 let BaseOpcode = "V6_vS32Ub_pi";
   27971 let isPredicable = 1;
   27972 let DecoderNamespace = "EXT_mmvec";
   27973 let Constraints = "$Rx32 = $Rx32in";
   27974 }
   27975 def V6_vS32Ub_ppu : HInst<
   27976 (outs IntRegs:$Rx32),
   27977 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   27978 "vmemu($Rx32++$Mu2) = $Vs32",
   27979 tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
   27980 let Inst{12-5} = 0b00000111;
   27981 let Inst{31-21} = 0b00101011001;
   27982 let addrMode = PostInc;
   27983 let accessSize = HVXVectorAccess;
   27984 let mayStore = 1;
   27985 let BaseOpcode = "V6_vS32Ub_ppu";
   27986 let isPredicable = 1;
   27987 let DecoderNamespace = "EXT_mmvec";
   27988 let Constraints = "$Rx32 = $Rx32in";
   27989 }
   27990 def V6_vS32Ub_pred_ai : HInst<
   27991 (outs),
   27992 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   27993 "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
   27994 tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   27995 let Inst{7-5} = 0b110;
   27996 let Inst{31-21} = 0b00101000101;
   27997 let isPredicated = 1;
   27998 let addrMode = BaseImmOffset;
   27999 let accessSize = HVXVectorAccess;
   28000 let mayStore = 1;
   28001 let BaseOpcode = "V6_vS32Ub_ai";
   28002 let DecoderNamespace = "EXT_mmvec";
   28003 }
   28004 def V6_vS32Ub_pred_pi : HInst<
   28005 (outs IntRegs:$Rx32),
   28006 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28007 "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
   28008 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   28009 let Inst{7-5} = 0b110;
   28010 let Inst{13-13} = 0b0;
   28011 let Inst{31-21} = 0b00101001101;
   28012 let isPredicated = 1;
   28013 let addrMode = PostInc;
   28014 let accessSize = HVXVectorAccess;
   28015 let mayStore = 1;
   28016 let BaseOpcode = "V6_vS32Ub_pi";
   28017 let DecoderNamespace = "EXT_mmvec";
   28018 let Constraints = "$Rx32 = $Rx32in";
   28019 }
   28020 def V6_vS32Ub_pred_ppu : HInst<
   28021 (outs IntRegs:$Rx32),
   28022 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28023 "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
   28024 tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   28025 let Inst{10-5} = 0b000110;
   28026 let Inst{31-21} = 0b00101011101;
   28027 let isPredicated = 1;
   28028 let addrMode = PostInc;
   28029 let accessSize = HVXVectorAccess;
   28030 let mayStore = 1;
   28031 let BaseOpcode = "V6_vS32Ub_ppu";
   28032 let DecoderNamespace = "EXT_mmvec";
   28033 let Constraints = "$Rx32 = $Rx32in";
   28034 }
   28035 def V6_vS32b_ai : HInst<
   28036 (outs),
   28037 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28038 "vmem($Rt32+#$Ii) = $Vs32",
   28039 tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
   28040 let Inst{7-5} = 0b000;
   28041 let Inst{12-11} = 0b00;
   28042 let Inst{31-21} = 0b00101000001;
   28043 let addrMode = BaseImmOffset;
   28044 let accessSize = HVXVectorAccess;
   28045 let mayStore = 1;
   28046 let BaseOpcode = "V6_vS32b_ai";
   28047 let isNVStorable = 1;
   28048 let isPredicable = 1;
   28049 let DecoderNamespace = "EXT_mmvec";
   28050 }
   28051 def V6_vS32b_new_ai : HInst<
   28052 (outs),
   28053 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28054 "vmem($Rt32+#$Ii) = $Os8.new",
   28055 tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
   28056 let Inst{7-3} = 0b00100;
   28057 let Inst{12-11} = 0b00;
   28058 let Inst{31-21} = 0b00101000001;
   28059 let addrMode = BaseImmOffset;
   28060 let accessSize = HVXVectorAccess;
   28061 let isNVStore = 1;
   28062 let CVINew = 1;
   28063 let isNewValue = 1;
   28064 let mayStore = 1;
   28065 let BaseOpcode = "V6_vS32b_ai";
   28066 let isPredicable = 1;
   28067 let DecoderNamespace = "EXT_mmvec";
   28068 let opNewValue = 2;
   28069 }
   28070 def V6_vS32b_new_npred_ai : HInst<
   28071 (outs),
   28072 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28073 "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
   28074 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
   28075 let Inst{7-3} = 0b01101;
   28076 let Inst{31-21} = 0b00101000101;
   28077 let isPredicated = 1;
   28078 let isPredicatedFalse = 1;
   28079 let addrMode = BaseImmOffset;
   28080 let accessSize = HVXVectorAccess;
   28081 let isNVStore = 1;
   28082 let CVINew = 1;
   28083 let isNewValue = 1;
   28084 let mayStore = 1;
   28085 let BaseOpcode = "V6_vS32b_ai";
   28086 let DecoderNamespace = "EXT_mmvec";
   28087 let opNewValue = 3;
   28088 }
   28089 def V6_vS32b_new_npred_pi : HInst<
   28090 (outs IntRegs:$Rx32),
   28091 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28092 "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
   28093 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
   28094 let Inst{7-3} = 0b01101;
   28095 let Inst{13-13} = 0b0;
   28096 let Inst{31-21} = 0b00101001101;
   28097 let isPredicated = 1;
   28098 let isPredicatedFalse = 1;
   28099 let addrMode = PostInc;
   28100 let accessSize = HVXVectorAccess;
   28101 let isNVStore = 1;
   28102 let CVINew = 1;
   28103 let isNewValue = 1;
   28104 let mayStore = 1;
   28105 let BaseOpcode = "V6_vS32b_pi";
   28106 let DecoderNamespace = "EXT_mmvec";
   28107 let opNewValue = 4;
   28108 let Constraints = "$Rx32 = $Rx32in";
   28109 }
   28110 def V6_vS32b_new_npred_ppu : HInst<
   28111 (outs IntRegs:$Rx32),
   28112 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28113 "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
   28114 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
   28115 let Inst{10-3} = 0b00001101;
   28116 let Inst{31-21} = 0b00101011101;
   28117 let isPredicated = 1;
   28118 let isPredicatedFalse = 1;
   28119 let addrMode = PostInc;
   28120 let accessSize = HVXVectorAccess;
   28121 let isNVStore = 1;
   28122 let CVINew = 1;
   28123 let isNewValue = 1;
   28124 let mayStore = 1;
   28125 let BaseOpcode = "V6_vS32b_ppu";
   28126 let DecoderNamespace = "EXT_mmvec";
   28127 let opNewValue = 4;
   28128 let Constraints = "$Rx32 = $Rx32in";
   28129 }
   28130 def V6_vS32b_new_pi : HInst<
   28131 (outs IntRegs:$Rx32),
   28132 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28133 "vmem($Rx32++#$Ii) = $Os8.new",
   28134 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
   28135 let Inst{7-3} = 0b00100;
   28136 let Inst{13-11} = 0b000;
   28137 let Inst{31-21} = 0b00101001001;
   28138 let addrMode = PostInc;
   28139 let accessSize = HVXVectorAccess;
   28140 let isNVStore = 1;
   28141 let CVINew = 1;
   28142 let isNewValue = 1;
   28143 let mayStore = 1;
   28144 let BaseOpcode = "V6_vS32b_pi";
   28145 let isPredicable = 1;
   28146 let DecoderNamespace = "EXT_mmvec";
   28147 let opNewValue = 3;
   28148 let Constraints = "$Rx32 = $Rx32in";
   28149 }
   28150 def V6_vS32b_new_ppu : HInst<
   28151 (outs IntRegs:$Rx32),
   28152 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28153 "vmem($Rx32++$Mu2) = $Os8.new",
   28154 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
   28155 let Inst{12-3} = 0b0000000100;
   28156 let Inst{31-21} = 0b00101011001;
   28157 let addrMode = PostInc;
   28158 let accessSize = HVXVectorAccess;
   28159 let isNVStore = 1;
   28160 let CVINew = 1;
   28161 let isNewValue = 1;
   28162 let mayStore = 1;
   28163 let BaseOpcode = "V6_vS32b_ppu";
   28164 let isPredicable = 1;
   28165 let DecoderNamespace = "EXT_mmvec";
   28166 let opNewValue = 3;
   28167 let Constraints = "$Rx32 = $Rx32in";
   28168 }
   28169 def V6_vS32b_new_pred_ai : HInst<
   28170 (outs),
   28171 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28172 "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
   28173 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
   28174 let Inst{7-3} = 0b01000;
   28175 let Inst{31-21} = 0b00101000101;
   28176 let isPredicated = 1;
   28177 let addrMode = BaseImmOffset;
   28178 let accessSize = HVXVectorAccess;
   28179 let isNVStore = 1;
   28180 let CVINew = 1;
   28181 let isNewValue = 1;
   28182 let mayStore = 1;
   28183 let BaseOpcode = "V6_vS32b_ai";
   28184 let DecoderNamespace = "EXT_mmvec";
   28185 let opNewValue = 3;
   28186 }
   28187 def V6_vS32b_new_pred_pi : HInst<
   28188 (outs IntRegs:$Rx32),
   28189 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28190 "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
   28191 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
   28192 let Inst{7-3} = 0b01000;
   28193 let Inst{13-13} = 0b0;
   28194 let Inst{31-21} = 0b00101001101;
   28195 let isPredicated = 1;
   28196 let addrMode = PostInc;
   28197 let accessSize = HVXVectorAccess;
   28198 let isNVStore = 1;
   28199 let CVINew = 1;
   28200 let isNewValue = 1;
   28201 let mayStore = 1;
   28202 let BaseOpcode = "V6_vS32b_pi";
   28203 let DecoderNamespace = "EXT_mmvec";
   28204 let opNewValue = 4;
   28205 let Constraints = "$Rx32 = $Rx32in";
   28206 }
   28207 def V6_vS32b_new_pred_ppu : HInst<
   28208 (outs IntRegs:$Rx32),
   28209 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28210 "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
   28211 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
   28212 let Inst{10-3} = 0b00001000;
   28213 let Inst{31-21} = 0b00101011101;
   28214 let isPredicated = 1;
   28215 let addrMode = PostInc;
   28216 let accessSize = HVXVectorAccess;
   28217 let isNVStore = 1;
   28218 let CVINew = 1;
   28219 let isNewValue = 1;
   28220 let mayStore = 1;
   28221 let BaseOpcode = "V6_vS32b_ppu";
   28222 let DecoderNamespace = "EXT_mmvec";
   28223 let opNewValue = 4;
   28224 let Constraints = "$Rx32 = $Rx32in";
   28225 }
   28226 def V6_vS32b_npred_ai : HInst<
   28227 (outs),
   28228 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28229 "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
   28230 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   28231 let Inst{7-5} = 0b001;
   28232 let Inst{31-21} = 0b00101000101;
   28233 let isPredicated = 1;
   28234 let isPredicatedFalse = 1;
   28235 let addrMode = BaseImmOffset;
   28236 let accessSize = HVXVectorAccess;
   28237 let mayStore = 1;
   28238 let BaseOpcode = "V6_vS32b_ai";
   28239 let isNVStorable = 1;
   28240 let DecoderNamespace = "EXT_mmvec";
   28241 }
   28242 def V6_vS32b_npred_pi : HInst<
   28243 (outs IntRegs:$Rx32),
   28244 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28245 "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
   28246 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   28247 let Inst{7-5} = 0b001;
   28248 let Inst{13-13} = 0b0;
   28249 let Inst{31-21} = 0b00101001101;
   28250 let isPredicated = 1;
   28251 let isPredicatedFalse = 1;
   28252 let addrMode = PostInc;
   28253 let accessSize = HVXVectorAccess;
   28254 let mayStore = 1;
   28255 let BaseOpcode = "V6_vS32b_pi";
   28256 let isNVStorable = 1;
   28257 let DecoderNamespace = "EXT_mmvec";
   28258 let Constraints = "$Rx32 = $Rx32in";
   28259 }
   28260 def V6_vS32b_npred_ppu : HInst<
   28261 (outs IntRegs:$Rx32),
   28262 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28263 "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
   28264 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   28265 let Inst{10-5} = 0b000001;
   28266 let Inst{31-21} = 0b00101011101;
   28267 let isPredicated = 1;
   28268 let isPredicatedFalse = 1;
   28269 let addrMode = PostInc;
   28270 let accessSize = HVXVectorAccess;
   28271 let mayStore = 1;
   28272 let BaseOpcode = "V6_vS32b_ppu";
   28273 let isNVStorable = 1;
   28274 let DecoderNamespace = "EXT_mmvec";
   28275 let Constraints = "$Rx32 = $Rx32in";
   28276 }
   28277 def V6_vS32b_nqpred_ai : HInst<
   28278 (outs),
   28279 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28280 "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
   28281 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
   28282 let Inst{7-5} = 0b001;
   28283 let Inst{31-21} = 0b00101000100;
   28284 let addrMode = BaseImmOffset;
   28285 let accessSize = HVXVectorAccess;
   28286 let mayStore = 1;
   28287 let DecoderNamespace = "EXT_mmvec";
   28288 }
   28289 def V6_vS32b_nqpred_pi : HInst<
   28290 (outs IntRegs:$Rx32),
   28291 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28292 "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
   28293 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
   28294 let Inst{7-5} = 0b001;
   28295 let Inst{13-13} = 0b0;
   28296 let Inst{31-21} = 0b00101001100;
   28297 let addrMode = PostInc;
   28298 let accessSize = HVXVectorAccess;
   28299 let mayStore = 1;
   28300 let DecoderNamespace = "EXT_mmvec";
   28301 let Constraints = "$Rx32 = $Rx32in";
   28302 }
   28303 def V6_vS32b_nqpred_ppu : HInst<
   28304 (outs IntRegs:$Rx32),
   28305 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28306 "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
   28307 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
   28308 let Inst{10-5} = 0b000001;
   28309 let Inst{31-21} = 0b00101011100;
   28310 let addrMode = PostInc;
   28311 let accessSize = HVXVectorAccess;
   28312 let mayStore = 1;
   28313 let DecoderNamespace = "EXT_mmvec";
   28314 let Constraints = "$Rx32 = $Rx32in";
   28315 }
   28316 def V6_vS32b_nt_ai : HInst<
   28317 (outs),
   28318 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28319 "vmem($Rt32+#$Ii):nt = $Vs32",
   28320 tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
   28321 let Inst{7-5} = 0b000;
   28322 let Inst{12-11} = 0b00;
   28323 let Inst{31-21} = 0b00101000011;
   28324 let addrMode = BaseImmOffset;
   28325 let accessSize = HVXVectorAccess;
   28326 let isNonTemporal = 1;
   28327 let mayStore = 1;
   28328 let BaseOpcode = "V6_vS32b_ai";
   28329 let isNVStorable = 1;
   28330 let isPredicable = 1;
   28331 let DecoderNamespace = "EXT_mmvec";
   28332 }
   28333 def V6_vS32b_nt_new_ai : HInst<
   28334 (outs),
   28335 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28336 "vmem($Rt32+#$Ii):nt = $Os8.new",
   28337 tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
   28338 let Inst{7-3} = 0b00100;
   28339 let Inst{12-11} = 0b00;
   28340 let Inst{31-21} = 0b00101000011;
   28341 let addrMode = BaseImmOffset;
   28342 let accessSize = HVXVectorAccess;
   28343 let isNVStore = 1;
   28344 let CVINew = 1;
   28345 let isNewValue = 1;
   28346 let isNonTemporal = 1;
   28347 let mayStore = 1;
   28348 let BaseOpcode = "V6_vS32b_ai";
   28349 let isPredicable = 1;
   28350 let DecoderNamespace = "EXT_mmvec";
   28351 let opNewValue = 2;
   28352 }
   28353 def V6_vS32b_nt_new_npred_ai : HInst<
   28354 (outs),
   28355 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28356 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
   28357 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
   28358 let Inst{7-3} = 0b01111;
   28359 let Inst{31-21} = 0b00101000111;
   28360 let isPredicated = 1;
   28361 let isPredicatedFalse = 1;
   28362 let addrMode = BaseImmOffset;
   28363 let accessSize = HVXVectorAccess;
   28364 let isNVStore = 1;
   28365 let CVINew = 1;
   28366 let isNewValue = 1;
   28367 let isNonTemporal = 1;
   28368 let mayStore = 1;
   28369 let BaseOpcode = "V6_vS32b_ai";
   28370 let DecoderNamespace = "EXT_mmvec";
   28371 let opNewValue = 3;
   28372 }
   28373 def V6_vS32b_nt_new_npred_pi : HInst<
   28374 (outs IntRegs:$Rx32),
   28375 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28376 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
   28377 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
   28378 let Inst{7-3} = 0b01111;
   28379 let Inst{13-13} = 0b0;
   28380 let Inst{31-21} = 0b00101001111;
   28381 let isPredicated = 1;
   28382 let isPredicatedFalse = 1;
   28383 let addrMode = PostInc;
   28384 let accessSize = HVXVectorAccess;
   28385 let isNVStore = 1;
   28386 let CVINew = 1;
   28387 let isNewValue = 1;
   28388 let isNonTemporal = 1;
   28389 let mayStore = 1;
   28390 let BaseOpcode = "V6_vS32b_pi";
   28391 let DecoderNamespace = "EXT_mmvec";
   28392 let opNewValue = 4;
   28393 let Constraints = "$Rx32 = $Rx32in";
   28394 }
   28395 def V6_vS32b_nt_new_npred_ppu : HInst<
   28396 (outs IntRegs:$Rx32),
   28397 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28398 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
   28399 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
   28400 let Inst{10-3} = 0b00001111;
   28401 let Inst{31-21} = 0b00101011111;
   28402 let isPredicated = 1;
   28403 let isPredicatedFalse = 1;
   28404 let addrMode = PostInc;
   28405 let accessSize = HVXVectorAccess;
   28406 let isNVStore = 1;
   28407 let CVINew = 1;
   28408 let isNewValue = 1;
   28409 let isNonTemporal = 1;
   28410 let mayStore = 1;
   28411 let BaseOpcode = "V6_vS32b_ppu";
   28412 let DecoderNamespace = "EXT_mmvec";
   28413 let opNewValue = 4;
   28414 let Constraints = "$Rx32 = $Rx32in";
   28415 }
   28416 def V6_vS32b_nt_new_pi : HInst<
   28417 (outs IntRegs:$Rx32),
   28418 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28419 "vmem($Rx32++#$Ii):nt = $Os8.new",
   28420 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
   28421 let Inst{7-3} = 0b00100;
   28422 let Inst{13-11} = 0b000;
   28423 let Inst{31-21} = 0b00101001011;
   28424 let addrMode = PostInc;
   28425 let accessSize = HVXVectorAccess;
   28426 let isNVStore = 1;
   28427 let CVINew = 1;
   28428 let isNewValue = 1;
   28429 let isNonTemporal = 1;
   28430 let mayStore = 1;
   28431 let BaseOpcode = "V6_vS32b_pi";
   28432 let isPredicable = 1;
   28433 let DecoderNamespace = "EXT_mmvec";
   28434 let opNewValue = 3;
   28435 let Constraints = "$Rx32 = $Rx32in";
   28436 }
   28437 def V6_vS32b_nt_new_ppu : HInst<
   28438 (outs IntRegs:$Rx32),
   28439 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28440 "vmem($Rx32++$Mu2):nt = $Os8.new",
   28441 tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
   28442 let Inst{12-3} = 0b0000000100;
   28443 let Inst{31-21} = 0b00101011011;
   28444 let addrMode = PostInc;
   28445 let accessSize = HVXVectorAccess;
   28446 let isNVStore = 1;
   28447 let CVINew = 1;
   28448 let isNewValue = 1;
   28449 let isNonTemporal = 1;
   28450 let mayStore = 1;
   28451 let BaseOpcode = "V6_vS32b_ppu";
   28452 let isPredicable = 1;
   28453 let DecoderNamespace = "EXT_mmvec";
   28454 let opNewValue = 3;
   28455 let Constraints = "$Rx32 = $Rx32in";
   28456 }
   28457 def V6_vS32b_nt_new_pred_ai : HInst<
   28458 (outs),
   28459 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
   28460 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
   28461 tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
   28462 let Inst{7-3} = 0b01010;
   28463 let Inst{31-21} = 0b00101000111;
   28464 let isPredicated = 1;
   28465 let addrMode = BaseImmOffset;
   28466 let accessSize = HVXVectorAccess;
   28467 let isNVStore = 1;
   28468 let CVINew = 1;
   28469 let isNewValue = 1;
   28470 let isNonTemporal = 1;
   28471 let mayStore = 1;
   28472 let BaseOpcode = "V6_vS32b_ai";
   28473 let DecoderNamespace = "EXT_mmvec";
   28474 let opNewValue = 3;
   28475 }
   28476 def V6_vS32b_nt_new_pred_pi : HInst<
   28477 (outs IntRegs:$Rx32),
   28478 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
   28479 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
   28480 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
   28481 let Inst{7-3} = 0b01010;
   28482 let Inst{13-13} = 0b0;
   28483 let Inst{31-21} = 0b00101001111;
   28484 let isPredicated = 1;
   28485 let addrMode = PostInc;
   28486 let accessSize = HVXVectorAccess;
   28487 let isNVStore = 1;
   28488 let CVINew = 1;
   28489 let isNewValue = 1;
   28490 let isNonTemporal = 1;
   28491 let mayStore = 1;
   28492 let BaseOpcode = "V6_vS32b_pi";
   28493 let DecoderNamespace = "EXT_mmvec";
   28494 let opNewValue = 4;
   28495 let Constraints = "$Rx32 = $Rx32in";
   28496 }
   28497 def V6_vS32b_nt_new_pred_ppu : HInst<
   28498 (outs IntRegs:$Rx32),
   28499 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
   28500 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
   28501 tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
   28502 let Inst{10-3} = 0b00001010;
   28503 let Inst{31-21} = 0b00101011111;
   28504 let isPredicated = 1;
   28505 let addrMode = PostInc;
   28506 let accessSize = HVXVectorAccess;
   28507 let isNVStore = 1;
   28508 let CVINew = 1;
   28509 let isNewValue = 1;
   28510 let isNonTemporal = 1;
   28511 let mayStore = 1;
   28512 let BaseOpcode = "V6_vS32b_ppu";
   28513 let DecoderNamespace = "EXT_mmvec";
   28514 let opNewValue = 4;
   28515 let Constraints = "$Rx32 = $Rx32in";
   28516 }
   28517 def V6_vS32b_nt_npred_ai : HInst<
   28518 (outs),
   28519 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28520 "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
   28521 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   28522 let Inst{7-5} = 0b001;
   28523 let Inst{31-21} = 0b00101000111;
   28524 let isPredicated = 1;
   28525 let isPredicatedFalse = 1;
   28526 let addrMode = BaseImmOffset;
   28527 let accessSize = HVXVectorAccess;
   28528 let isNonTemporal = 1;
   28529 let mayStore = 1;
   28530 let BaseOpcode = "V6_vS32b_ai";
   28531 let isNVStorable = 1;
   28532 let DecoderNamespace = "EXT_mmvec";
   28533 }
   28534 def V6_vS32b_nt_npred_pi : HInst<
   28535 (outs IntRegs:$Rx32),
   28536 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28537 "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
   28538 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   28539 let Inst{7-5} = 0b001;
   28540 let Inst{13-13} = 0b0;
   28541 let Inst{31-21} = 0b00101001111;
   28542 let isPredicated = 1;
   28543 let isPredicatedFalse = 1;
   28544 let addrMode = PostInc;
   28545 let accessSize = HVXVectorAccess;
   28546 let isNonTemporal = 1;
   28547 let mayStore = 1;
   28548 let BaseOpcode = "V6_vS32b_pi";
   28549 let isNVStorable = 1;
   28550 let DecoderNamespace = "EXT_mmvec";
   28551 let Constraints = "$Rx32 = $Rx32in";
   28552 }
   28553 def V6_vS32b_nt_npred_ppu : HInst<
   28554 (outs IntRegs:$Rx32),
   28555 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28556 "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
   28557 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   28558 let Inst{10-5} = 0b000001;
   28559 let Inst{31-21} = 0b00101011111;
   28560 let isPredicated = 1;
   28561 let isPredicatedFalse = 1;
   28562 let addrMode = PostInc;
   28563 let accessSize = HVXVectorAccess;
   28564 let isNonTemporal = 1;
   28565 let mayStore = 1;
   28566 let BaseOpcode = "V6_vS32b_ppu";
   28567 let isNVStorable = 1;
   28568 let DecoderNamespace = "EXT_mmvec";
   28569 let Constraints = "$Rx32 = $Rx32in";
   28570 }
   28571 def V6_vS32b_nt_nqpred_ai : HInst<
   28572 (outs),
   28573 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28574 "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
   28575 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
   28576 let Inst{7-5} = 0b001;
   28577 let Inst{31-21} = 0b00101000110;
   28578 let addrMode = BaseImmOffset;
   28579 let accessSize = HVXVectorAccess;
   28580 let isNonTemporal = 1;
   28581 let mayStore = 1;
   28582 let DecoderNamespace = "EXT_mmvec";
   28583 }
   28584 def V6_vS32b_nt_nqpred_pi : HInst<
   28585 (outs IntRegs:$Rx32),
   28586 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28587 "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
   28588 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
   28589 let Inst{7-5} = 0b001;
   28590 let Inst{13-13} = 0b0;
   28591 let Inst{31-21} = 0b00101001110;
   28592 let addrMode = PostInc;
   28593 let accessSize = HVXVectorAccess;
   28594 let isNonTemporal = 1;
   28595 let mayStore = 1;
   28596 let DecoderNamespace = "EXT_mmvec";
   28597 let Constraints = "$Rx32 = $Rx32in";
   28598 }
   28599 def V6_vS32b_nt_nqpred_ppu : HInst<
   28600 (outs IntRegs:$Rx32),
   28601 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28602 "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
   28603 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
   28604 let Inst{10-5} = 0b000001;
   28605 let Inst{31-21} = 0b00101011110;
   28606 let addrMode = PostInc;
   28607 let accessSize = HVXVectorAccess;
   28608 let isNonTemporal = 1;
   28609 let mayStore = 1;
   28610 let DecoderNamespace = "EXT_mmvec";
   28611 let Constraints = "$Rx32 = $Rx32in";
   28612 }
   28613 def V6_vS32b_nt_pi : HInst<
   28614 (outs IntRegs:$Rx32),
   28615 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28616 "vmem($Rx32++#$Ii):nt = $Vs32",
   28617 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
   28618 let Inst{7-5} = 0b000;
   28619 let Inst{13-11} = 0b000;
   28620 let Inst{31-21} = 0b00101001011;
   28621 let addrMode = PostInc;
   28622 let accessSize = HVXVectorAccess;
   28623 let isNonTemporal = 1;
   28624 let mayStore = 1;
   28625 let BaseOpcode = "V6_vS32b_pi";
   28626 let isNVStorable = 1;
   28627 let isPredicable = 1;
   28628 let DecoderNamespace = "EXT_mmvec";
   28629 let Constraints = "$Rx32 = $Rx32in";
   28630 }
   28631 def V6_vS32b_nt_ppu : HInst<
   28632 (outs IntRegs:$Rx32),
   28633 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28634 "vmem($Rx32++$Mu2):nt = $Vs32",
   28635 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
   28636 let Inst{12-5} = 0b00000000;
   28637 let Inst{31-21} = 0b00101011011;
   28638 let addrMode = PostInc;
   28639 let accessSize = HVXVectorAccess;
   28640 let isNonTemporal = 1;
   28641 let mayStore = 1;
   28642 let BaseOpcode = "V6_vS32b_ppu";
   28643 let isNVStorable = 1;
   28644 let isPredicable = 1;
   28645 let DecoderNamespace = "EXT_mmvec";
   28646 let Constraints = "$Rx32 = $Rx32in";
   28647 }
   28648 def V6_vS32b_nt_pred_ai : HInst<
   28649 (outs),
   28650 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28651 "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
   28652 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   28653 let Inst{7-5} = 0b000;
   28654 let Inst{31-21} = 0b00101000111;
   28655 let isPredicated = 1;
   28656 let addrMode = BaseImmOffset;
   28657 let accessSize = HVXVectorAccess;
   28658 let isNonTemporal = 1;
   28659 let mayStore = 1;
   28660 let BaseOpcode = "V6_vS32b_ai";
   28661 let isNVStorable = 1;
   28662 let DecoderNamespace = "EXT_mmvec";
   28663 }
   28664 def V6_vS32b_nt_pred_pi : HInst<
   28665 (outs IntRegs:$Rx32),
   28666 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28667 "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
   28668 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   28669 let Inst{7-5} = 0b000;
   28670 let Inst{13-13} = 0b0;
   28671 let Inst{31-21} = 0b00101001111;
   28672 let isPredicated = 1;
   28673 let addrMode = PostInc;
   28674 let accessSize = HVXVectorAccess;
   28675 let isNonTemporal = 1;
   28676 let mayStore = 1;
   28677 let BaseOpcode = "V6_vS32b_pi";
   28678 let isNVStorable = 1;
   28679 let DecoderNamespace = "EXT_mmvec";
   28680 let Constraints = "$Rx32 = $Rx32in";
   28681 }
   28682 def V6_vS32b_nt_pred_ppu : HInst<
   28683 (outs IntRegs:$Rx32),
   28684 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28685 "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
   28686 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   28687 let Inst{10-5} = 0b000000;
   28688 let Inst{31-21} = 0b00101011111;
   28689 let isPredicated = 1;
   28690 let addrMode = PostInc;
   28691 let accessSize = HVXVectorAccess;
   28692 let isNonTemporal = 1;
   28693 let mayStore = 1;
   28694 let BaseOpcode = "V6_vS32b_ppu";
   28695 let isNVStorable = 1;
   28696 let DecoderNamespace = "EXT_mmvec";
   28697 let Constraints = "$Rx32 = $Rx32in";
   28698 }
   28699 def V6_vS32b_nt_qpred_ai : HInst<
   28700 (outs),
   28701 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28702 "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
   28703 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
   28704 let Inst{7-5} = 0b000;
   28705 let Inst{31-21} = 0b00101000110;
   28706 let addrMode = BaseImmOffset;
   28707 let accessSize = HVXVectorAccess;
   28708 let isNonTemporal = 1;
   28709 let mayStore = 1;
   28710 let DecoderNamespace = "EXT_mmvec";
   28711 }
   28712 def V6_vS32b_nt_qpred_pi : HInst<
   28713 (outs IntRegs:$Rx32),
   28714 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28715 "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
   28716 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
   28717 let Inst{7-5} = 0b000;
   28718 let Inst{13-13} = 0b0;
   28719 let Inst{31-21} = 0b00101001110;
   28720 let addrMode = PostInc;
   28721 let accessSize = HVXVectorAccess;
   28722 let isNonTemporal = 1;
   28723 let mayStore = 1;
   28724 let DecoderNamespace = "EXT_mmvec";
   28725 let Constraints = "$Rx32 = $Rx32in";
   28726 }
   28727 def V6_vS32b_nt_qpred_ppu : HInst<
   28728 (outs IntRegs:$Rx32),
   28729 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28730 "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
   28731 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
   28732 let Inst{10-5} = 0b000000;
   28733 let Inst{31-21} = 0b00101011110;
   28734 let addrMode = PostInc;
   28735 let accessSize = HVXVectorAccess;
   28736 let isNonTemporal = 1;
   28737 let mayStore = 1;
   28738 let DecoderNamespace = "EXT_mmvec";
   28739 let Constraints = "$Rx32 = $Rx32in";
   28740 }
   28741 def V6_vS32b_pi : HInst<
   28742 (outs IntRegs:$Rx32),
   28743 (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28744 "vmem($Rx32++#$Ii) = $Vs32",
   28745 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
   28746 let Inst{7-5} = 0b000;
   28747 let Inst{13-11} = 0b000;
   28748 let Inst{31-21} = 0b00101001001;
   28749 let addrMode = PostInc;
   28750 let accessSize = HVXVectorAccess;
   28751 let mayStore = 1;
   28752 let BaseOpcode = "V6_vS32b_pi";
   28753 let isNVStorable = 1;
   28754 let isPredicable = 1;
   28755 let DecoderNamespace = "EXT_mmvec";
   28756 let Constraints = "$Rx32 = $Rx32in";
   28757 }
   28758 def V6_vS32b_ppu : HInst<
   28759 (outs IntRegs:$Rx32),
   28760 (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28761 "vmem($Rx32++$Mu2) = $Vs32",
   28762 tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
   28763 let Inst{12-5} = 0b00000000;
   28764 let Inst{31-21} = 0b00101011001;
   28765 let addrMode = PostInc;
   28766 let accessSize = HVXVectorAccess;
   28767 let mayStore = 1;
   28768 let isNVStorable = 1;
   28769 let isPredicable = 1;
   28770 let DecoderNamespace = "EXT_mmvec";
   28771 let Constraints = "$Rx32 = $Rx32in";
   28772 }
   28773 def V6_vS32b_pred_ai : HInst<
   28774 (outs),
   28775 (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28776 "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
   28777 tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
   28778 let Inst{7-5} = 0b000;
   28779 let Inst{31-21} = 0b00101000101;
   28780 let isPredicated = 1;
   28781 let addrMode = BaseImmOffset;
   28782 let accessSize = HVXVectorAccess;
   28783 let mayStore = 1;
   28784 let BaseOpcode = "V6_vS32b_ai";
   28785 let isNVStorable = 1;
   28786 let DecoderNamespace = "EXT_mmvec";
   28787 }
   28788 def V6_vS32b_pred_pi : HInst<
   28789 (outs IntRegs:$Rx32),
   28790 (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28791 "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
   28792 tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
   28793 let Inst{7-5} = 0b000;
   28794 let Inst{13-13} = 0b0;
   28795 let Inst{31-21} = 0b00101001101;
   28796 let isPredicated = 1;
   28797 let addrMode = PostInc;
   28798 let accessSize = HVXVectorAccess;
   28799 let mayStore = 1;
   28800 let BaseOpcode = "V6_vS32b_pi";
   28801 let isNVStorable = 1;
   28802 let DecoderNamespace = "EXT_mmvec";
   28803 let Constraints = "$Rx32 = $Rx32in";
   28804 }
   28805 def V6_vS32b_pred_ppu : HInst<
   28806 (outs IntRegs:$Rx32),
   28807 (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28808 "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
   28809 tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
   28810 let Inst{10-5} = 0b000000;
   28811 let Inst{31-21} = 0b00101011101;
   28812 let isPredicated = 1;
   28813 let addrMode = PostInc;
   28814 let accessSize = HVXVectorAccess;
   28815 let mayStore = 1;
   28816 let BaseOpcode = "V6_vS32b_ppu";
   28817 let isNVStorable = 1;
   28818 let DecoderNamespace = "EXT_mmvec";
   28819 let Constraints = "$Rx32 = $Rx32in";
   28820 }
   28821 def V6_vS32b_qpred_ai : HInst<
   28822 (outs),
   28823 (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
   28824 "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
   28825 tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
   28826 let Inst{7-5} = 0b000;
   28827 let Inst{31-21} = 0b00101000100;
   28828 let addrMode = BaseImmOffset;
   28829 let accessSize = HVXVectorAccess;
   28830 let mayStore = 1;
   28831 let DecoderNamespace = "EXT_mmvec";
   28832 }
   28833 def V6_vS32b_qpred_pi : HInst<
   28834 (outs IntRegs:$Rx32),
   28835 (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
   28836 "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
   28837 tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
   28838 let Inst{7-5} = 0b000;
   28839 let Inst{13-13} = 0b0;
   28840 let Inst{31-21} = 0b00101001100;
   28841 let addrMode = PostInc;
   28842 let accessSize = HVXVectorAccess;
   28843 let mayStore = 1;
   28844 let DecoderNamespace = "EXT_mmvec";
   28845 let Constraints = "$Rx32 = $Rx32in";
   28846 }
   28847 def V6_vS32b_qpred_ppu : HInst<
   28848 (outs IntRegs:$Rx32),
   28849 (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
   28850 "if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
   28851 tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
   28852 let Inst{10-5} = 0b000000;
   28853 let Inst{31-21} = 0b00101011100;
   28854 let addrMode = PostInc;
   28855 let accessSize = HVXVectorAccess;
   28856 let mayStore = 1;
   28857 let DecoderNamespace = "EXT_mmvec";
   28858 let Constraints = "$Rx32 = $Rx32in";
   28859 }
   28860 def V6_vS32b_srls_ai : HInst<
   28861 (outs),
   28862 (ins IntRegs:$Rt32, s4_0Imm:$Ii),
   28863 "vmem($Rt32+#$Ii):scatter_release",
   28864 tc_29841470, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
   28865 let Inst{7-0} = 0b00101000;
   28866 let Inst{12-11} = 0b00;
   28867 let Inst{31-21} = 0b00101000001;
   28868 let addrMode = BaseImmOffset;
   28869 let accessSize = HVXVectorAccess;
   28870 let CVINew = 1;
   28871 let mayStore = 1;
   28872 let DecoderNamespace = "EXT_mmvec";
   28873 }
   28874 def V6_vS32b_srls_pi : HInst<
   28875 (outs IntRegs:$Rx32),
   28876 (ins IntRegs:$Rx32in, s3_0Imm:$Ii),
   28877 "vmem($Rx32++#$Ii):scatter_release",
   28878 tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
   28879 let Inst{7-0} = 0b00101000;
   28880 let Inst{13-11} = 0b000;
   28881 let Inst{31-21} = 0b00101001001;
   28882 let addrMode = PostInc;
   28883 let accessSize = HVXVectorAccess;
   28884 let CVINew = 1;
   28885 let mayStore = 1;
   28886 let DecoderNamespace = "EXT_mmvec";
   28887 let Constraints = "$Rx32 = $Rx32in";
   28888 }
   28889 def V6_vS32b_srls_ppu : HInst<
   28890 (outs IntRegs:$Rx32),
   28891 (ins IntRegs:$Rx32in, ModRegs:$Mu2),
   28892 "vmem($Rx32++$Mu2):scatter_release",
   28893 tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
   28894 let Inst{12-0} = 0b0000000101000;
   28895 let Inst{31-21} = 0b00101011001;
   28896 let addrMode = PostInc;
   28897 let accessSize = HVXVectorAccess;
   28898 let CVINew = 1;
   28899 let mayStore = 1;
   28900 let DecoderNamespace = "EXT_mmvec";
   28901 let Constraints = "$Rx32 = $Rx32in";
   28902 }
   28903 def V6_vabsb : HInst<
   28904 (outs HvxVR:$Vd32),
   28905 (ins HvxVR:$Vu32),
   28906 "$Vd32.b = vabs($Vu32.b)",
   28907 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
   28908 let Inst{7-5} = 0b100;
   28909 let Inst{13-13} = 0b0;
   28910 let Inst{31-16} = 0b0001111000000001;
   28911 let hasNewValue = 1;
   28912 let opNewValue = 0;
   28913 let DecoderNamespace = "EXT_mmvec";
   28914 }
   28915 def V6_vabsb_alt : HInst<
   28916 (outs HvxVR:$Vd32),
   28917 (ins HvxVR:$Vu32),
   28918 "$Vd32 = vabsb($Vu32)",
   28919 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   28920 let hasNewValue = 1;
   28921 let opNewValue = 0;
   28922 let isPseudo = 1;
   28923 let isCodeGenOnly = 1;
   28924 let DecoderNamespace = "EXT_mmvec";
   28925 }
   28926 def V6_vabsb_sat : HInst<
   28927 (outs HvxVR:$Vd32),
   28928 (ins HvxVR:$Vu32),
   28929 "$Vd32.b = vabs($Vu32.b):sat",
   28930 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
   28931 let Inst{7-5} = 0b101;
   28932 let Inst{13-13} = 0b0;
   28933 let Inst{31-16} = 0b0001111000000001;
   28934 let hasNewValue = 1;
   28935 let opNewValue = 0;
   28936 let DecoderNamespace = "EXT_mmvec";
   28937 }
   28938 def V6_vabsb_sat_alt : HInst<
   28939 (outs HvxVR:$Vd32),
   28940 (ins HvxVR:$Vu32),
   28941 "$Vd32 = vabsb($Vu32):sat",
   28942 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   28943 let hasNewValue = 1;
   28944 let opNewValue = 0;
   28945 let isPseudo = 1;
   28946 let isCodeGenOnly = 1;
   28947 let DecoderNamespace = "EXT_mmvec";
   28948 }
   28949 def V6_vabsdiffh : HInst<
   28950 (outs HvxVR:$Vd32),
   28951 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   28952 "$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
   28953 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   28954 let Inst{7-5} = 0b001;
   28955 let Inst{13-13} = 0b0;
   28956 let Inst{31-21} = 0b00011100110;
   28957 let hasNewValue = 1;
   28958 let opNewValue = 0;
   28959 let DecoderNamespace = "EXT_mmvec";
   28960 }
   28961 def V6_vabsdiffh_alt : HInst<
   28962 (outs HvxVR:$Vd32),
   28963 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   28964 "$Vd32 = vabsdiffh($Vu32,$Vv32)",
   28965 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   28966 let hasNewValue = 1;
   28967 let opNewValue = 0;
   28968 let isPseudo = 1;
   28969 let isCodeGenOnly = 1;
   28970 let DecoderNamespace = "EXT_mmvec";
   28971 }
   28972 def V6_vabsdiffub : HInst<
   28973 (outs HvxVR:$Vd32),
   28974 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   28975 "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
   28976 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   28977 let Inst{7-5} = 0b000;
   28978 let Inst{13-13} = 0b0;
   28979 let Inst{31-21} = 0b00011100110;
   28980 let hasNewValue = 1;
   28981 let opNewValue = 0;
   28982 let DecoderNamespace = "EXT_mmvec";
   28983 }
   28984 def V6_vabsdiffub_alt : HInst<
   28985 (outs HvxVR:$Vd32),
   28986 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   28987 "$Vd32 = vabsdiffub($Vu32,$Vv32)",
   28988 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   28989 let hasNewValue = 1;
   28990 let opNewValue = 0;
   28991 let isPseudo = 1;
   28992 let isCodeGenOnly = 1;
   28993 let DecoderNamespace = "EXT_mmvec";
   28994 }
   28995 def V6_vabsdiffuh : HInst<
   28996 (outs HvxVR:$Vd32),
   28997 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   28998 "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
   28999 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   29000 let Inst{7-5} = 0b010;
   29001 let Inst{13-13} = 0b0;
   29002 let Inst{31-21} = 0b00011100110;
   29003 let hasNewValue = 1;
   29004 let opNewValue = 0;
   29005 let DecoderNamespace = "EXT_mmvec";
   29006 }
   29007 def V6_vabsdiffuh_alt : HInst<
   29008 (outs HvxVR:$Vd32),
   29009 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29010 "$Vd32 = vabsdiffuh($Vu32,$Vv32)",
   29011 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29012 let hasNewValue = 1;
   29013 let opNewValue = 0;
   29014 let isPseudo = 1;
   29015 let isCodeGenOnly = 1;
   29016 let DecoderNamespace = "EXT_mmvec";
   29017 }
   29018 def V6_vabsdiffw : HInst<
   29019 (outs HvxVR:$Vd32),
   29020 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29021 "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
   29022 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   29023 let Inst{7-5} = 0b011;
   29024 let Inst{13-13} = 0b0;
   29025 let Inst{31-21} = 0b00011100110;
   29026 let hasNewValue = 1;
   29027 let opNewValue = 0;
   29028 let DecoderNamespace = "EXT_mmvec";
   29029 }
   29030 def V6_vabsdiffw_alt : HInst<
   29031 (outs HvxVR:$Vd32),
   29032 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29033 "$Vd32 = vabsdiffw($Vu32,$Vv32)",
   29034 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29035 let hasNewValue = 1;
   29036 let opNewValue = 0;
   29037 let isPseudo = 1;
   29038 let isCodeGenOnly = 1;
   29039 let DecoderNamespace = "EXT_mmvec";
   29040 }
   29041 def V6_vabsh : HInst<
   29042 (outs HvxVR:$Vd32),
   29043 (ins HvxVR:$Vu32),
   29044 "$Vd32.h = vabs($Vu32.h)",
   29045 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   29046 let Inst{7-5} = 0b000;
   29047 let Inst{13-13} = 0b0;
   29048 let Inst{31-16} = 0b0001111000000000;
   29049 let hasNewValue = 1;
   29050 let opNewValue = 0;
   29051 let DecoderNamespace = "EXT_mmvec";
   29052 }
   29053 def V6_vabsh_alt : HInst<
   29054 (outs HvxVR:$Vd32),
   29055 (ins HvxVR:$Vu32),
   29056 "$Vd32 = vabsh($Vu32)",
   29057 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29058 let hasNewValue = 1;
   29059 let opNewValue = 0;
   29060 let isPseudo = 1;
   29061 let isCodeGenOnly = 1;
   29062 let DecoderNamespace = "EXT_mmvec";
   29063 }
   29064 def V6_vabsh_sat : HInst<
   29065 (outs HvxVR:$Vd32),
   29066 (ins HvxVR:$Vu32),
   29067 "$Vd32.h = vabs($Vu32.h):sat",
   29068 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   29069 let Inst{7-5} = 0b001;
   29070 let Inst{13-13} = 0b0;
   29071 let Inst{31-16} = 0b0001111000000000;
   29072 let hasNewValue = 1;
   29073 let opNewValue = 0;
   29074 let DecoderNamespace = "EXT_mmvec";
   29075 }
   29076 def V6_vabsh_sat_alt : HInst<
   29077 (outs HvxVR:$Vd32),
   29078 (ins HvxVR:$Vu32),
   29079 "$Vd32 = vabsh($Vu32):sat",
   29080 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29081 let hasNewValue = 1;
   29082 let opNewValue = 0;
   29083 let isPseudo = 1;
   29084 let isCodeGenOnly = 1;
   29085 let DecoderNamespace = "EXT_mmvec";
   29086 }
   29087 def V6_vabsub_alt : HInst<
   29088 (outs HvxVR:$Vd32),
   29089 (ins HvxVR:$Vu32),
   29090 "$Vd32.ub = vabs($Vu32.b)",
   29091 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
   29092 let hasNewValue = 1;
   29093 let opNewValue = 0;
   29094 let isPseudo = 1;
   29095 let isCodeGenOnly = 1;
   29096 let DecoderNamespace = "EXT_mmvec";
   29097 }
   29098 def V6_vabsuh_alt : HInst<
   29099 (outs HvxVR:$Vd32),
   29100 (ins HvxVR:$Vu32),
   29101 "$Vd32.uh = vabs($Vu32.h)",
   29102 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
   29103 let hasNewValue = 1;
   29104 let opNewValue = 0;
   29105 let isPseudo = 1;
   29106 let isCodeGenOnly = 1;
   29107 let DecoderNamespace = "EXT_mmvec";
   29108 }
   29109 def V6_vabsuw_alt : HInst<
   29110 (outs HvxVR:$Vd32),
   29111 (ins HvxVR:$Vu32),
   29112 "$Vd32.uw = vabs($Vu32.w)",
   29113 tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> {
   29114 let hasNewValue = 1;
   29115 let opNewValue = 0;
   29116 let isPseudo = 1;
   29117 let isCodeGenOnly = 1;
   29118 let DecoderNamespace = "EXT_mmvec";
   29119 }
   29120 def V6_vabsw : HInst<
   29121 (outs HvxVR:$Vd32),
   29122 (ins HvxVR:$Vu32),
   29123 "$Vd32.w = vabs($Vu32.w)",
   29124 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   29125 let Inst{7-5} = 0b010;
   29126 let Inst{13-13} = 0b0;
   29127 let Inst{31-16} = 0b0001111000000000;
   29128 let hasNewValue = 1;
   29129 let opNewValue = 0;
   29130 let DecoderNamespace = "EXT_mmvec";
   29131 }
   29132 def V6_vabsw_alt : HInst<
   29133 (outs HvxVR:$Vd32),
   29134 (ins HvxVR:$Vu32),
   29135 "$Vd32 = vabsw($Vu32)",
   29136 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29137 let hasNewValue = 1;
   29138 let opNewValue = 0;
   29139 let isPseudo = 1;
   29140 let isCodeGenOnly = 1;
   29141 let DecoderNamespace = "EXT_mmvec";
   29142 }
   29143 def V6_vabsw_sat : HInst<
   29144 (outs HvxVR:$Vd32),
   29145 (ins HvxVR:$Vu32),
   29146 "$Vd32.w = vabs($Vu32.w):sat",
   29147 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   29148 let Inst{7-5} = 0b011;
   29149 let Inst{13-13} = 0b0;
   29150 let Inst{31-16} = 0b0001111000000000;
   29151 let hasNewValue = 1;
   29152 let opNewValue = 0;
   29153 let DecoderNamespace = "EXT_mmvec";
   29154 }
   29155 def V6_vabsw_sat_alt : HInst<
   29156 (outs HvxVR:$Vd32),
   29157 (ins HvxVR:$Vu32),
   29158 "$Vd32 = vabsw($Vu32):sat",
   29159 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29160 let hasNewValue = 1;
   29161 let opNewValue = 0;
   29162 let isPseudo = 1;
   29163 let isCodeGenOnly = 1;
   29164 let DecoderNamespace = "EXT_mmvec";
   29165 }
   29166 def V6_vaddb : HInst<
   29167 (outs HvxVR:$Vd32),
   29168 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29169 "$Vd32.b = vadd($Vu32.b,$Vv32.b)",
   29170 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29171 let Inst{7-5} = 0b110;
   29172 let Inst{13-13} = 0b0;
   29173 let Inst{31-21} = 0b00011111101;
   29174 let hasNewValue = 1;
   29175 let opNewValue = 0;
   29176 let DecoderNamespace = "EXT_mmvec";
   29177 }
   29178 def V6_vaddb_alt : HInst<
   29179 (outs HvxVR:$Vd32),
   29180 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29181 "$Vd32 = vaddb($Vu32,$Vv32)",
   29182 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29183 let hasNewValue = 1;
   29184 let opNewValue = 0;
   29185 let isPseudo = 1;
   29186 let isCodeGenOnly = 1;
   29187 let DecoderNamespace = "EXT_mmvec";
   29188 }
   29189 def V6_vaddb_dv : HInst<
   29190 (outs HvxWR:$Vdd32),
   29191 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29192 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
   29193 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29194 let Inst{7-5} = 0b100;
   29195 let Inst{13-13} = 0b0;
   29196 let Inst{31-21} = 0b00011100011;
   29197 let hasNewValue = 1;
   29198 let opNewValue = 0;
   29199 let DecoderNamespace = "EXT_mmvec";
   29200 }
   29201 def V6_vaddb_dv_alt : HInst<
   29202 (outs HvxWR:$Vdd32),
   29203 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29204 "$Vdd32 = vaddb($Vuu32,$Vvv32)",
   29205 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29206 let hasNewValue = 1;
   29207 let opNewValue = 0;
   29208 let isPseudo = 1;
   29209 let isCodeGenOnly = 1;
   29210 let DecoderNamespace = "EXT_mmvec";
   29211 }
   29212 def V6_vaddbnq : HInst<
   29213 (outs HvxVR:$Vx32),
   29214 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29215 "if (!$Qv4) $Vx32.b += $Vu32.b",
   29216 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29217 let Inst{7-5} = 0b011;
   29218 let Inst{13-13} = 0b1;
   29219 let Inst{21-16} = 0b000001;
   29220 let Inst{31-24} = 0b00011110;
   29221 let hasNewValue = 1;
   29222 let opNewValue = 0;
   29223 let isAccumulator = 1;
   29224 let DecoderNamespace = "EXT_mmvec";
   29225 let Constraints = "$Vx32 = $Vx32in";
   29226 }
   29227 def V6_vaddbnq_alt : HInst<
   29228 (outs HvxVR:$Vx32),
   29229 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29230 "if (!$Qv4.b) $Vx32.b += $Vu32.b",
   29231 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29232 let hasNewValue = 1;
   29233 let opNewValue = 0;
   29234 let isAccumulator = 1;
   29235 let isPseudo = 1;
   29236 let isCodeGenOnly = 1;
   29237 let DecoderNamespace = "EXT_mmvec";
   29238 let Constraints = "$Vx32 = $Vx32in";
   29239 }
   29240 def V6_vaddbq : HInst<
   29241 (outs HvxVR:$Vx32),
   29242 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29243 "if ($Qv4) $Vx32.b += $Vu32.b",
   29244 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29245 let Inst{7-5} = 0b000;
   29246 let Inst{13-13} = 0b1;
   29247 let Inst{21-16} = 0b000001;
   29248 let Inst{31-24} = 0b00011110;
   29249 let hasNewValue = 1;
   29250 let opNewValue = 0;
   29251 let isAccumulator = 1;
   29252 let DecoderNamespace = "EXT_mmvec";
   29253 let Constraints = "$Vx32 = $Vx32in";
   29254 }
   29255 def V6_vaddbq_alt : HInst<
   29256 (outs HvxVR:$Vx32),
   29257 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29258 "if ($Qv4.b) $Vx32.b += $Vu32.b",
   29259 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29260 let hasNewValue = 1;
   29261 let opNewValue = 0;
   29262 let isAccumulator = 1;
   29263 let isPseudo = 1;
   29264 let isCodeGenOnly = 1;
   29265 let DecoderNamespace = "EXT_mmvec";
   29266 let Constraints = "$Vx32 = $Vx32in";
   29267 }
   29268 def V6_vaddbsat : HInst<
   29269 (outs HvxVR:$Vd32),
   29270 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29271 "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
   29272 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   29273 let Inst{7-5} = 0b000;
   29274 let Inst{13-13} = 0b0;
   29275 let Inst{31-21} = 0b00011111000;
   29276 let hasNewValue = 1;
   29277 let opNewValue = 0;
   29278 let DecoderNamespace = "EXT_mmvec";
   29279 }
   29280 def V6_vaddbsat_alt : HInst<
   29281 (outs HvxVR:$Vd32),
   29282 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29283 "$Vd32 = vaddb($Vu32,$Vv32):sat",
   29284 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29285 let hasNewValue = 1;
   29286 let opNewValue = 0;
   29287 let isPseudo = 1;
   29288 let isCodeGenOnly = 1;
   29289 let DecoderNamespace = "EXT_mmvec";
   29290 }
   29291 def V6_vaddbsat_dv : HInst<
   29292 (outs HvxWR:$Vdd32),
   29293 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29294 "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
   29295 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
   29296 let Inst{7-5} = 0b000;
   29297 let Inst{13-13} = 0b0;
   29298 let Inst{31-21} = 0b00011110101;
   29299 let hasNewValue = 1;
   29300 let opNewValue = 0;
   29301 let DecoderNamespace = "EXT_mmvec";
   29302 }
   29303 def V6_vaddbsat_dv_alt : HInst<
   29304 (outs HvxWR:$Vdd32),
   29305 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29306 "$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
   29307 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29308 let hasNewValue = 1;
   29309 let opNewValue = 0;
   29310 let isPseudo = 1;
   29311 let isCodeGenOnly = 1;
   29312 let DecoderNamespace = "EXT_mmvec";
   29313 }
   29314 def V6_vaddcarry : HInst<
   29315 (outs HvxVR:$Vd32, HvxQR:$Qx4),
   29316 (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
   29317 "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
   29318 tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
   29319 let Inst{7-7} = 0b0;
   29320 let Inst{13-13} = 0b1;
   29321 let Inst{31-21} = 0b00011100101;
   29322 let hasNewValue = 1;
   29323 let opNewValue = 0;
   29324 let DecoderNamespace = "EXT_mmvec";
   29325 let Constraints = "$Qx4 = $Qx4in";
   29326 }
   29327 def V6_vaddclbh : HInst<
   29328 (outs HvxVR:$Vd32),
   29329 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29330 "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
   29331 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
   29332 let Inst{7-5} = 0b000;
   29333 let Inst{13-13} = 0b1;
   29334 let Inst{31-21} = 0b00011111000;
   29335 let hasNewValue = 1;
   29336 let opNewValue = 0;
   29337 let DecoderNamespace = "EXT_mmvec";
   29338 }
   29339 def V6_vaddclbw : HInst<
   29340 (outs HvxVR:$Vd32),
   29341 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29342 "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
   29343 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
   29344 let Inst{7-5} = 0b001;
   29345 let Inst{13-13} = 0b1;
   29346 let Inst{31-21} = 0b00011111000;
   29347 let hasNewValue = 1;
   29348 let opNewValue = 0;
   29349 let DecoderNamespace = "EXT_mmvec";
   29350 }
   29351 def V6_vaddh : HInst<
   29352 (outs HvxVR:$Vd32),
   29353 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29354 "$Vd32.h = vadd($Vu32.h,$Vv32.h)",
   29355 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29356 let Inst{7-5} = 0b111;
   29357 let Inst{13-13} = 0b0;
   29358 let Inst{31-21} = 0b00011111101;
   29359 let hasNewValue = 1;
   29360 let opNewValue = 0;
   29361 let DecoderNamespace = "EXT_mmvec";
   29362 }
   29363 def V6_vaddh_alt : HInst<
   29364 (outs HvxVR:$Vd32),
   29365 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29366 "$Vd32 = vaddh($Vu32,$Vv32)",
   29367 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29368 let hasNewValue = 1;
   29369 let opNewValue = 0;
   29370 let isPseudo = 1;
   29371 let isCodeGenOnly = 1;
   29372 let DecoderNamespace = "EXT_mmvec";
   29373 }
   29374 def V6_vaddh_dv : HInst<
   29375 (outs HvxWR:$Vdd32),
   29376 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29377 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
   29378 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29379 let Inst{7-5} = 0b101;
   29380 let Inst{13-13} = 0b0;
   29381 let Inst{31-21} = 0b00011100011;
   29382 let hasNewValue = 1;
   29383 let opNewValue = 0;
   29384 let DecoderNamespace = "EXT_mmvec";
   29385 }
   29386 def V6_vaddh_dv_alt : HInst<
   29387 (outs HvxWR:$Vdd32),
   29388 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29389 "$Vdd32 = vaddh($Vuu32,$Vvv32)",
   29390 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29391 let hasNewValue = 1;
   29392 let opNewValue = 0;
   29393 let isPseudo = 1;
   29394 let isCodeGenOnly = 1;
   29395 let DecoderNamespace = "EXT_mmvec";
   29396 }
   29397 def V6_vaddhnq : HInst<
   29398 (outs HvxVR:$Vx32),
   29399 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29400 "if (!$Qv4) $Vx32.h += $Vu32.h",
   29401 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29402 let Inst{7-5} = 0b100;
   29403 let Inst{13-13} = 0b1;
   29404 let Inst{21-16} = 0b000001;
   29405 let Inst{31-24} = 0b00011110;
   29406 let hasNewValue = 1;
   29407 let opNewValue = 0;
   29408 let isAccumulator = 1;
   29409 let DecoderNamespace = "EXT_mmvec";
   29410 let Constraints = "$Vx32 = $Vx32in";
   29411 }
   29412 def V6_vaddhnq_alt : HInst<
   29413 (outs HvxVR:$Vx32),
   29414 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29415 "if (!$Qv4.h) $Vx32.h += $Vu32.h",
   29416 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29417 let hasNewValue = 1;
   29418 let opNewValue = 0;
   29419 let isAccumulator = 1;
   29420 let isPseudo = 1;
   29421 let isCodeGenOnly = 1;
   29422 let DecoderNamespace = "EXT_mmvec";
   29423 let Constraints = "$Vx32 = $Vx32in";
   29424 }
   29425 def V6_vaddhq : HInst<
   29426 (outs HvxVR:$Vx32),
   29427 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29428 "if ($Qv4) $Vx32.h += $Vu32.h",
   29429 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29430 let Inst{7-5} = 0b001;
   29431 let Inst{13-13} = 0b1;
   29432 let Inst{21-16} = 0b000001;
   29433 let Inst{31-24} = 0b00011110;
   29434 let hasNewValue = 1;
   29435 let opNewValue = 0;
   29436 let isAccumulator = 1;
   29437 let DecoderNamespace = "EXT_mmvec";
   29438 let Constraints = "$Vx32 = $Vx32in";
   29439 }
   29440 def V6_vaddhq_alt : HInst<
   29441 (outs HvxVR:$Vx32),
   29442 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29443 "if ($Qv4.h) $Vx32.h += $Vu32.h",
   29444 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29445 let hasNewValue = 1;
   29446 let opNewValue = 0;
   29447 let isAccumulator = 1;
   29448 let isPseudo = 1;
   29449 let isCodeGenOnly = 1;
   29450 let DecoderNamespace = "EXT_mmvec";
   29451 let Constraints = "$Vx32 = $Vx32in";
   29452 }
   29453 def V6_vaddhsat : HInst<
   29454 (outs HvxVR:$Vd32),
   29455 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29456 "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
   29457 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29458 let Inst{7-5} = 0b011;
   29459 let Inst{13-13} = 0b0;
   29460 let Inst{31-21} = 0b00011100010;
   29461 let hasNewValue = 1;
   29462 let opNewValue = 0;
   29463 let DecoderNamespace = "EXT_mmvec";
   29464 }
   29465 def V6_vaddhsat_alt : HInst<
   29466 (outs HvxVR:$Vd32),
   29467 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29468 "$Vd32 = vaddh($Vu32,$Vv32):sat",
   29469 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29470 let hasNewValue = 1;
   29471 let opNewValue = 0;
   29472 let isPseudo = 1;
   29473 let isCodeGenOnly = 1;
   29474 let DecoderNamespace = "EXT_mmvec";
   29475 }
   29476 def V6_vaddhsat_dv : HInst<
   29477 (outs HvxWR:$Vdd32),
   29478 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29479 "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
   29480 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29481 let Inst{7-5} = 0b001;
   29482 let Inst{13-13} = 0b0;
   29483 let Inst{31-21} = 0b00011100100;
   29484 let hasNewValue = 1;
   29485 let opNewValue = 0;
   29486 let DecoderNamespace = "EXT_mmvec";
   29487 }
   29488 def V6_vaddhsat_dv_alt : HInst<
   29489 (outs HvxWR:$Vdd32),
   29490 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29491 "$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
   29492 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29493 let hasNewValue = 1;
   29494 let opNewValue = 0;
   29495 let isPseudo = 1;
   29496 let isCodeGenOnly = 1;
   29497 let DecoderNamespace = "EXT_mmvec";
   29498 }
   29499 def V6_vaddhw : HInst<
   29500 (outs HvxWR:$Vdd32),
   29501 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29502 "$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
   29503 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   29504 let Inst{7-5} = 0b100;
   29505 let Inst{13-13} = 0b0;
   29506 let Inst{31-21} = 0b00011100101;
   29507 let hasNewValue = 1;
   29508 let opNewValue = 0;
   29509 let DecoderNamespace = "EXT_mmvec";
   29510 }
   29511 def V6_vaddhw_acc : HInst<
   29512 (outs HvxWR:$Vxx32),
   29513 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29514 "$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
   29515 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
   29516 let Inst{7-5} = 0b010;
   29517 let Inst{13-13} = 0b1;
   29518 let Inst{31-21} = 0b00011100001;
   29519 let hasNewValue = 1;
   29520 let opNewValue = 0;
   29521 let isAccumulator = 1;
   29522 let DecoderNamespace = "EXT_mmvec";
   29523 let Constraints = "$Vxx32 = $Vxx32in";
   29524 }
   29525 def V6_vaddhw_acc_alt : HInst<
   29526 (outs HvxWR:$Vxx32),
   29527 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29528 "$Vxx32 += vaddh($Vu32,$Vv32)",
   29529 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29530 let hasNewValue = 1;
   29531 let opNewValue = 0;
   29532 let isAccumulator = 1;
   29533 let isPseudo = 1;
   29534 let isCodeGenOnly = 1;
   29535 let DecoderNamespace = "EXT_mmvec";
   29536 let Constraints = "$Vxx32 = $Vxx32in";
   29537 }
   29538 def V6_vaddhw_alt : HInst<
   29539 (outs HvxWR:$Vdd32),
   29540 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29541 "$Vdd32 = vaddh($Vu32,$Vv32)",
   29542 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29543 let hasNewValue = 1;
   29544 let opNewValue = 0;
   29545 let isPseudo = 1;
   29546 let isCodeGenOnly = 1;
   29547 let DecoderNamespace = "EXT_mmvec";
   29548 }
   29549 def V6_vaddubh : HInst<
   29550 (outs HvxWR:$Vdd32),
   29551 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29552 "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
   29553 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   29554 let Inst{7-5} = 0b010;
   29555 let Inst{13-13} = 0b0;
   29556 let Inst{31-21} = 0b00011100101;
   29557 let hasNewValue = 1;
   29558 let opNewValue = 0;
   29559 let DecoderNamespace = "EXT_mmvec";
   29560 }
   29561 def V6_vaddubh_acc : HInst<
   29562 (outs HvxWR:$Vxx32),
   29563 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29564 "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
   29565 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
   29566 let Inst{7-5} = 0b101;
   29567 let Inst{13-13} = 0b1;
   29568 let Inst{31-21} = 0b00011100010;
   29569 let hasNewValue = 1;
   29570 let opNewValue = 0;
   29571 let isAccumulator = 1;
   29572 let DecoderNamespace = "EXT_mmvec";
   29573 let Constraints = "$Vxx32 = $Vxx32in";
   29574 }
   29575 def V6_vaddubh_acc_alt : HInst<
   29576 (outs HvxWR:$Vxx32),
   29577 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29578 "$Vxx32 += vaddub($Vu32,$Vv32)",
   29579 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29580 let hasNewValue = 1;
   29581 let opNewValue = 0;
   29582 let isAccumulator = 1;
   29583 let isPseudo = 1;
   29584 let isCodeGenOnly = 1;
   29585 let DecoderNamespace = "EXT_mmvec";
   29586 let Constraints = "$Vxx32 = $Vxx32in";
   29587 }
   29588 def V6_vaddubh_alt : HInst<
   29589 (outs HvxWR:$Vdd32),
   29590 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29591 "$Vdd32 = vaddub($Vu32,$Vv32)",
   29592 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29593 let hasNewValue = 1;
   29594 let opNewValue = 0;
   29595 let isPseudo = 1;
   29596 let isCodeGenOnly = 1;
   29597 let DecoderNamespace = "EXT_mmvec";
   29598 }
   29599 def V6_vaddubsat : HInst<
   29600 (outs HvxVR:$Vd32),
   29601 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29602 "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
   29603 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29604 let Inst{7-5} = 0b001;
   29605 let Inst{13-13} = 0b0;
   29606 let Inst{31-21} = 0b00011100010;
   29607 let hasNewValue = 1;
   29608 let opNewValue = 0;
   29609 let DecoderNamespace = "EXT_mmvec";
   29610 }
   29611 def V6_vaddubsat_alt : HInst<
   29612 (outs HvxVR:$Vd32),
   29613 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29614 "$Vd32 = vaddub($Vu32,$Vv32):sat",
   29615 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29616 let hasNewValue = 1;
   29617 let opNewValue = 0;
   29618 let isPseudo = 1;
   29619 let isCodeGenOnly = 1;
   29620 let DecoderNamespace = "EXT_mmvec";
   29621 }
   29622 def V6_vaddubsat_dv : HInst<
   29623 (outs HvxWR:$Vdd32),
   29624 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29625 "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
   29626 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29627 let Inst{7-5} = 0b111;
   29628 let Inst{13-13} = 0b0;
   29629 let Inst{31-21} = 0b00011100011;
   29630 let hasNewValue = 1;
   29631 let opNewValue = 0;
   29632 let DecoderNamespace = "EXT_mmvec";
   29633 }
   29634 def V6_vaddubsat_dv_alt : HInst<
   29635 (outs HvxWR:$Vdd32),
   29636 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29637 "$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
   29638 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29639 let hasNewValue = 1;
   29640 let opNewValue = 0;
   29641 let isPseudo = 1;
   29642 let isCodeGenOnly = 1;
   29643 let DecoderNamespace = "EXT_mmvec";
   29644 }
   29645 def V6_vaddububb_sat : HInst<
   29646 (outs HvxVR:$Vd32),
   29647 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29648 "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
   29649 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   29650 let Inst{7-5} = 0b100;
   29651 let Inst{13-13} = 0b0;
   29652 let Inst{31-21} = 0b00011110101;
   29653 let hasNewValue = 1;
   29654 let opNewValue = 0;
   29655 let DecoderNamespace = "EXT_mmvec";
   29656 }
   29657 def V6_vadduhsat : HInst<
   29658 (outs HvxVR:$Vd32),
   29659 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29660 "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
   29661 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29662 let Inst{7-5} = 0b010;
   29663 let Inst{13-13} = 0b0;
   29664 let Inst{31-21} = 0b00011100010;
   29665 let hasNewValue = 1;
   29666 let opNewValue = 0;
   29667 let DecoderNamespace = "EXT_mmvec";
   29668 }
   29669 def V6_vadduhsat_alt : HInst<
   29670 (outs HvxVR:$Vd32),
   29671 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29672 "$Vd32 = vadduh($Vu32,$Vv32):sat",
   29673 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29674 let hasNewValue = 1;
   29675 let opNewValue = 0;
   29676 let isPseudo = 1;
   29677 let isCodeGenOnly = 1;
   29678 let DecoderNamespace = "EXT_mmvec";
   29679 }
   29680 def V6_vadduhsat_dv : HInst<
   29681 (outs HvxWR:$Vdd32),
   29682 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29683 "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
   29684 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29685 let Inst{7-5} = 0b000;
   29686 let Inst{13-13} = 0b0;
   29687 let Inst{31-21} = 0b00011100100;
   29688 let hasNewValue = 1;
   29689 let opNewValue = 0;
   29690 let DecoderNamespace = "EXT_mmvec";
   29691 }
   29692 def V6_vadduhsat_dv_alt : HInst<
   29693 (outs HvxWR:$Vdd32),
   29694 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29695 "$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
   29696 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29697 let hasNewValue = 1;
   29698 let opNewValue = 0;
   29699 let isPseudo = 1;
   29700 let isCodeGenOnly = 1;
   29701 let DecoderNamespace = "EXT_mmvec";
   29702 }
   29703 def V6_vadduhw : HInst<
   29704 (outs HvxWR:$Vdd32),
   29705 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29706 "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
   29707 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   29708 let Inst{7-5} = 0b011;
   29709 let Inst{13-13} = 0b0;
   29710 let Inst{31-21} = 0b00011100101;
   29711 let hasNewValue = 1;
   29712 let opNewValue = 0;
   29713 let DecoderNamespace = "EXT_mmvec";
   29714 }
   29715 def V6_vadduhw_acc : HInst<
   29716 (outs HvxWR:$Vxx32),
   29717 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29718 "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
   29719 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
   29720 let Inst{7-5} = 0b100;
   29721 let Inst{13-13} = 0b1;
   29722 let Inst{31-21} = 0b00011100010;
   29723 let hasNewValue = 1;
   29724 let opNewValue = 0;
   29725 let isAccumulator = 1;
   29726 let DecoderNamespace = "EXT_mmvec";
   29727 let Constraints = "$Vxx32 = $Vxx32in";
   29728 }
   29729 def V6_vadduhw_acc_alt : HInst<
   29730 (outs HvxWR:$Vxx32),
   29731 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   29732 "$Vxx32 += vadduh($Vu32,$Vv32)",
   29733 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29734 let hasNewValue = 1;
   29735 let opNewValue = 0;
   29736 let isAccumulator = 1;
   29737 let isPseudo = 1;
   29738 let isCodeGenOnly = 1;
   29739 let DecoderNamespace = "EXT_mmvec";
   29740 let Constraints = "$Vxx32 = $Vxx32in";
   29741 }
   29742 def V6_vadduhw_alt : HInst<
   29743 (outs HvxWR:$Vdd32),
   29744 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29745 "$Vdd32 = vadduh($Vu32,$Vv32)",
   29746 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29747 let hasNewValue = 1;
   29748 let opNewValue = 0;
   29749 let isPseudo = 1;
   29750 let isCodeGenOnly = 1;
   29751 let DecoderNamespace = "EXT_mmvec";
   29752 }
   29753 def V6_vadduwsat : HInst<
   29754 (outs HvxVR:$Vd32),
   29755 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29756 "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
   29757 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   29758 let Inst{7-5} = 0b001;
   29759 let Inst{13-13} = 0b0;
   29760 let Inst{31-21} = 0b00011111011;
   29761 let hasNewValue = 1;
   29762 let opNewValue = 0;
   29763 let DecoderNamespace = "EXT_mmvec";
   29764 }
   29765 def V6_vadduwsat_alt : HInst<
   29766 (outs HvxVR:$Vd32),
   29767 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29768 "$Vd32 = vadduw($Vu32,$Vv32):sat",
   29769 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29770 let hasNewValue = 1;
   29771 let opNewValue = 0;
   29772 let isPseudo = 1;
   29773 let isCodeGenOnly = 1;
   29774 let DecoderNamespace = "EXT_mmvec";
   29775 }
   29776 def V6_vadduwsat_dv : HInst<
   29777 (outs HvxWR:$Vdd32),
   29778 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29779 "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
   29780 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
   29781 let Inst{7-5} = 0b010;
   29782 let Inst{13-13} = 0b0;
   29783 let Inst{31-21} = 0b00011110101;
   29784 let hasNewValue = 1;
   29785 let opNewValue = 0;
   29786 let DecoderNamespace = "EXT_mmvec";
   29787 }
   29788 def V6_vadduwsat_dv_alt : HInst<
   29789 (outs HvxWR:$Vdd32),
   29790 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29791 "$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
   29792 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   29793 let hasNewValue = 1;
   29794 let opNewValue = 0;
   29795 let isPseudo = 1;
   29796 let isCodeGenOnly = 1;
   29797 let DecoderNamespace = "EXT_mmvec";
   29798 }
   29799 def V6_vaddw : HInst<
   29800 (outs HvxVR:$Vd32),
   29801 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29802 "$Vd32.w = vadd($Vu32.w,$Vv32.w)",
   29803 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29804 let Inst{7-5} = 0b000;
   29805 let Inst{13-13} = 0b0;
   29806 let Inst{31-21} = 0b00011100010;
   29807 let hasNewValue = 1;
   29808 let opNewValue = 0;
   29809 let DecoderNamespace = "EXT_mmvec";
   29810 }
   29811 def V6_vaddw_alt : HInst<
   29812 (outs HvxVR:$Vd32),
   29813 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29814 "$Vd32 = vaddw($Vu32,$Vv32)",
   29815 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29816 let hasNewValue = 1;
   29817 let opNewValue = 0;
   29818 let isPseudo = 1;
   29819 let isCodeGenOnly = 1;
   29820 let DecoderNamespace = "EXT_mmvec";
   29821 }
   29822 def V6_vaddw_dv : HInst<
   29823 (outs HvxWR:$Vdd32),
   29824 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29825 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
   29826 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29827 let Inst{7-5} = 0b110;
   29828 let Inst{13-13} = 0b0;
   29829 let Inst{31-21} = 0b00011100011;
   29830 let hasNewValue = 1;
   29831 let opNewValue = 0;
   29832 let DecoderNamespace = "EXT_mmvec";
   29833 }
   29834 def V6_vaddw_dv_alt : HInst<
   29835 (outs HvxWR:$Vdd32),
   29836 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29837 "$Vdd32 = vaddw($Vuu32,$Vvv32)",
   29838 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29839 let hasNewValue = 1;
   29840 let opNewValue = 0;
   29841 let isPseudo = 1;
   29842 let isCodeGenOnly = 1;
   29843 let DecoderNamespace = "EXT_mmvec";
   29844 }
   29845 def V6_vaddwnq : HInst<
   29846 (outs HvxVR:$Vx32),
   29847 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29848 "if (!$Qv4) $Vx32.w += $Vu32.w",
   29849 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29850 let Inst{7-5} = 0b101;
   29851 let Inst{13-13} = 0b1;
   29852 let Inst{21-16} = 0b000001;
   29853 let Inst{31-24} = 0b00011110;
   29854 let hasNewValue = 1;
   29855 let opNewValue = 0;
   29856 let isAccumulator = 1;
   29857 let DecoderNamespace = "EXT_mmvec";
   29858 let Constraints = "$Vx32 = $Vx32in";
   29859 }
   29860 def V6_vaddwnq_alt : HInst<
   29861 (outs HvxVR:$Vx32),
   29862 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29863 "if (!$Qv4.w) $Vx32.w += $Vu32.w",
   29864 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29865 let hasNewValue = 1;
   29866 let opNewValue = 0;
   29867 let isAccumulator = 1;
   29868 let isPseudo = 1;
   29869 let isCodeGenOnly = 1;
   29870 let DecoderNamespace = "EXT_mmvec";
   29871 let Constraints = "$Vx32 = $Vx32in";
   29872 }
   29873 def V6_vaddwq : HInst<
   29874 (outs HvxVR:$Vx32),
   29875 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29876 "if ($Qv4) $Vx32.w += $Vu32.w",
   29877 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   29878 let Inst{7-5} = 0b010;
   29879 let Inst{13-13} = 0b1;
   29880 let Inst{21-16} = 0b000001;
   29881 let Inst{31-24} = 0b00011110;
   29882 let hasNewValue = 1;
   29883 let opNewValue = 0;
   29884 let isAccumulator = 1;
   29885 let DecoderNamespace = "EXT_mmvec";
   29886 let Constraints = "$Vx32 = $Vx32in";
   29887 }
   29888 def V6_vaddwq_alt : HInst<
   29889 (outs HvxVR:$Vx32),
   29890 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   29891 "if ($Qv4.w) $Vx32.w += $Vu32.w",
   29892 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29893 let hasNewValue = 1;
   29894 let opNewValue = 0;
   29895 let isAccumulator = 1;
   29896 let isPseudo = 1;
   29897 let isCodeGenOnly = 1;
   29898 let DecoderNamespace = "EXT_mmvec";
   29899 let Constraints = "$Vx32 = $Vx32in";
   29900 }
   29901 def V6_vaddwsat : HInst<
   29902 (outs HvxVR:$Vd32),
   29903 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29904 "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
   29905 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29906 let Inst{7-5} = 0b100;
   29907 let Inst{13-13} = 0b0;
   29908 let Inst{31-21} = 0b00011100010;
   29909 let hasNewValue = 1;
   29910 let opNewValue = 0;
   29911 let DecoderNamespace = "EXT_mmvec";
   29912 }
   29913 def V6_vaddwsat_alt : HInst<
   29914 (outs HvxVR:$Vd32),
   29915 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29916 "$Vd32 = vaddw($Vu32,$Vv32):sat",
   29917 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29918 let hasNewValue = 1;
   29919 let opNewValue = 0;
   29920 let isPseudo = 1;
   29921 let isCodeGenOnly = 1;
   29922 let DecoderNamespace = "EXT_mmvec";
   29923 }
   29924 def V6_vaddwsat_dv : HInst<
   29925 (outs HvxWR:$Vdd32),
   29926 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29927 "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
   29928 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   29929 let Inst{7-5} = 0b010;
   29930 let Inst{13-13} = 0b0;
   29931 let Inst{31-21} = 0b00011100100;
   29932 let hasNewValue = 1;
   29933 let opNewValue = 0;
   29934 let DecoderNamespace = "EXT_mmvec";
   29935 }
   29936 def V6_vaddwsat_dv_alt : HInst<
   29937 (outs HvxWR:$Vdd32),
   29938 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   29939 "$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
   29940 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   29941 let hasNewValue = 1;
   29942 let opNewValue = 0;
   29943 let isPseudo = 1;
   29944 let isCodeGenOnly = 1;
   29945 let DecoderNamespace = "EXT_mmvec";
   29946 }
   29947 def V6_valignb : HInst<
   29948 (outs HvxVR:$Vd32),
   29949 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   29950 "$Vd32 = valign($Vu32,$Vv32,$Rt8)",
   29951 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
   29952 let Inst{7-5} = 0b000;
   29953 let Inst{13-13} = 0b0;
   29954 let Inst{31-24} = 0b00011011;
   29955 let hasNewValue = 1;
   29956 let opNewValue = 0;
   29957 let DecoderNamespace = "EXT_mmvec";
   29958 }
   29959 def V6_valignbi : HInst<
   29960 (outs HvxVR:$Vd32),
   29961 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   29962 "$Vd32 = valign($Vu32,$Vv32,#$Ii)",
   29963 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
   29964 let Inst{13-13} = 0b1;
   29965 let Inst{31-21} = 0b00011110001;
   29966 let hasNewValue = 1;
   29967 let opNewValue = 0;
   29968 let DecoderNamespace = "EXT_mmvec";
   29969 }
   29970 def V6_vand : HInst<
   29971 (outs HvxVR:$Vd32),
   29972 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   29973 "$Vd32 = vand($Vu32,$Vv32)",
   29974 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   29975 let Inst{7-5} = 0b101;
   29976 let Inst{13-13} = 0b0;
   29977 let Inst{31-21} = 0b00011100001;
   29978 let hasNewValue = 1;
   29979 let opNewValue = 0;
   29980 let DecoderNamespace = "EXT_mmvec";
   29981 }
   29982 def V6_vandnqrt : HInst<
   29983 (outs HvxVR:$Vd32),
   29984 (ins HvxQR:$Qu4, IntRegs:$Rt32),
   29985 "$Vd32 = vand(!$Qu4,$Rt32)",
   29986 tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> {
   29987 let Inst{7-5} = 0b101;
   29988 let Inst{13-10} = 0b0001;
   29989 let Inst{31-21} = 0b00011001101;
   29990 let hasNewValue = 1;
   29991 let opNewValue = 0;
   29992 let DecoderNamespace = "EXT_mmvec";
   29993 }
   29994 def V6_vandnqrt_acc : HInst<
   29995 (outs HvxVR:$Vx32),
   29996 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
   29997 "$Vx32 |= vand(!$Qu4,$Rt32)",
   29998 tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> {
   29999 let Inst{7-5} = 0b011;
   30000 let Inst{13-10} = 0b1001;
   30001 let Inst{31-21} = 0b00011001011;
   30002 let hasNewValue = 1;
   30003 let opNewValue = 0;
   30004 let isAccumulator = 1;
   30005 let DecoderNamespace = "EXT_mmvec";
   30006 let Constraints = "$Vx32 = $Vx32in";
   30007 }
   30008 def V6_vandnqrt_acc_alt : HInst<
   30009 (outs HvxVR:$Vx32),
   30010 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
   30011 "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
   30012 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   30013 let hasNewValue = 1;
   30014 let opNewValue = 0;
   30015 let isAccumulator = 1;
   30016 let isPseudo = 1;
   30017 let isCodeGenOnly = 1;
   30018 let DecoderNamespace = "EXT_mmvec";
   30019 let Constraints = "$Vx32 = $Vx32in";
   30020 }
   30021 def V6_vandnqrt_alt : HInst<
   30022 (outs HvxVR:$Vd32),
   30023 (ins HvxQR:$Qu4, IntRegs:$Rt32),
   30024 "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
   30025 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   30026 let hasNewValue = 1;
   30027 let opNewValue = 0;
   30028 let isPseudo = 1;
   30029 let isCodeGenOnly = 1;
   30030 let DecoderNamespace = "EXT_mmvec";
   30031 }
   30032 def V6_vandqrt : HInst<
   30033 (outs HvxVR:$Vd32),
   30034 (ins HvxQR:$Qu4, IntRegs:$Rt32),
   30035 "$Vd32 = vand($Qu4,$Rt32)",
   30036 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
   30037 let Inst{7-5} = 0b101;
   30038 let Inst{13-10} = 0b0000;
   30039 let Inst{31-21} = 0b00011001101;
   30040 let hasNewValue = 1;
   30041 let opNewValue = 0;
   30042 let DecoderNamespace = "EXT_mmvec";
   30043 }
   30044 def V6_vandqrt_acc : HInst<
   30045 (outs HvxVR:$Vx32),
   30046 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
   30047 "$Vx32 |= vand($Qu4,$Rt32)",
   30048 tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
   30049 let Inst{7-5} = 0b011;
   30050 let Inst{13-10} = 0b1000;
   30051 let Inst{31-21} = 0b00011001011;
   30052 let hasNewValue = 1;
   30053 let opNewValue = 0;
   30054 let isAccumulator = 1;
   30055 let DecoderNamespace = "EXT_mmvec";
   30056 let Constraints = "$Vx32 = $Vx32in";
   30057 }
   30058 def V6_vandqrt_acc_alt : HInst<
   30059 (outs HvxVR:$Vx32),
   30060 (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
   30061 "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
   30062 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30063 let hasNewValue = 1;
   30064 let opNewValue = 0;
   30065 let isAccumulator = 1;
   30066 let isPseudo = 1;
   30067 let isCodeGenOnly = 1;
   30068 let DecoderNamespace = "EXT_mmvec";
   30069 let Constraints = "$Vx32 = $Vx32in";
   30070 }
   30071 def V6_vandqrt_alt : HInst<
   30072 (outs HvxVR:$Vd32),
   30073 (ins HvxQR:$Qu4, IntRegs:$Rt32),
   30074 "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
   30075 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30076 let hasNewValue = 1;
   30077 let opNewValue = 0;
   30078 let isPseudo = 1;
   30079 let isCodeGenOnly = 1;
   30080 let DecoderNamespace = "EXT_mmvec";
   30081 }
   30082 def V6_vandvnqv : HInst<
   30083 (outs HvxVR:$Vd32),
   30084 (ins HvxQR:$Qv4, HvxVR:$Vu32),
   30085 "$Vd32 = vand(!$Qv4,$Vu32)",
   30086 tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
   30087 let Inst{7-5} = 0b001;
   30088 let Inst{13-13} = 0b1;
   30089 let Inst{21-16} = 0b000011;
   30090 let Inst{31-24} = 0b00011110;
   30091 let hasNewValue = 1;
   30092 let opNewValue = 0;
   30093 let DecoderNamespace = "EXT_mmvec";
   30094 }
   30095 def V6_vandvqv : HInst<
   30096 (outs HvxVR:$Vd32),
   30097 (ins HvxQR:$Qv4, HvxVR:$Vu32),
   30098 "$Vd32 = vand($Qv4,$Vu32)",
   30099 tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
   30100 let Inst{7-5} = 0b000;
   30101 let Inst{13-13} = 0b1;
   30102 let Inst{21-16} = 0b000011;
   30103 let Inst{31-24} = 0b00011110;
   30104 let hasNewValue = 1;
   30105 let opNewValue = 0;
   30106 let DecoderNamespace = "EXT_mmvec";
   30107 }
   30108 def V6_vandvrt : HInst<
   30109 (outs HvxQR:$Qd4),
   30110 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30111 "$Qd4 = vand($Vu32,$Rt32)",
   30112 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
   30113 let Inst{7-2} = 0b010010;
   30114 let Inst{13-13} = 0b0;
   30115 let Inst{31-21} = 0b00011001101;
   30116 let hasNewValue = 1;
   30117 let opNewValue = 0;
   30118 let DecoderNamespace = "EXT_mmvec";
   30119 }
   30120 def V6_vandvrt_acc : HInst<
   30121 (outs HvxQR:$Qx4),
   30122 (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
   30123 "$Qx4 |= vand($Vu32,$Rt32)",
   30124 tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
   30125 let Inst{7-2} = 0b100000;
   30126 let Inst{13-13} = 0b1;
   30127 let Inst{31-21} = 0b00011001011;
   30128 let isAccumulator = 1;
   30129 let DecoderNamespace = "EXT_mmvec";
   30130 let Constraints = "$Qx4 = $Qx4in";
   30131 }
   30132 def V6_vandvrt_acc_alt : HInst<
   30133 (outs HvxQR:$Qx4),
   30134 (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
   30135 "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
   30136 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30137 let isAccumulator = 1;
   30138 let isPseudo = 1;
   30139 let isCodeGenOnly = 1;
   30140 let DecoderNamespace = "EXT_mmvec";
   30141 let Constraints = "$Qx4 = $Qx4in";
   30142 }
   30143 def V6_vandvrt_alt : HInst<
   30144 (outs HvxQR:$Qd4),
   30145 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30146 "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
   30147 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30148 let hasNewValue = 1;
   30149 let opNewValue = 0;
   30150 let isPseudo = 1;
   30151 let isCodeGenOnly = 1;
   30152 let DecoderNamespace = "EXT_mmvec";
   30153 }
   30154 def V6_vaslh : HInst<
   30155 (outs HvxVR:$Vd32),
   30156 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30157 "$Vd32.h = vasl($Vu32.h,$Rt32)",
   30158 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   30159 let Inst{7-5} = 0b000;
   30160 let Inst{13-13} = 0b0;
   30161 let Inst{31-21} = 0b00011001100;
   30162 let hasNewValue = 1;
   30163 let opNewValue = 0;
   30164 let DecoderNamespace = "EXT_mmvec";
   30165 }
   30166 def V6_vaslh_acc : HInst<
   30167 (outs HvxVR:$Vx32),
   30168 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30169 "$Vx32.h += vasl($Vu32.h,$Rt32)",
   30170 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
   30171 let Inst{7-5} = 0b101;
   30172 let Inst{13-13} = 0b1;
   30173 let Inst{31-21} = 0b00011001101;
   30174 let hasNewValue = 1;
   30175 let opNewValue = 0;
   30176 let isAccumulator = 1;
   30177 let DecoderNamespace = "EXT_mmvec";
   30178 let Constraints = "$Vx32 = $Vx32in";
   30179 }
   30180 def V6_vaslh_acc_alt : HInst<
   30181 (outs HvxVR:$Vx32),
   30182 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30183 "$Vx32 += vaslh($Vu32,$Rt32)",
   30184 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30185 let hasNewValue = 1;
   30186 let opNewValue = 0;
   30187 let isAccumulator = 1;
   30188 let isPseudo = 1;
   30189 let isCodeGenOnly = 1;
   30190 let DecoderNamespace = "EXT_mmvec";
   30191 let Constraints = "$Vx32 = $Vx32in";
   30192 }
   30193 def V6_vaslh_alt : HInst<
   30194 (outs HvxVR:$Vd32),
   30195 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30196 "$Vd32 = vaslh($Vu32,$Rt32)",
   30197 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30198 let hasNewValue = 1;
   30199 let opNewValue = 0;
   30200 let isPseudo = 1;
   30201 let isCodeGenOnly = 1;
   30202 let DecoderNamespace = "EXT_mmvec";
   30203 }
   30204 def V6_vaslhv : HInst<
   30205 (outs HvxVR:$Vd32),
   30206 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30207 "$Vd32.h = vasl($Vu32.h,$Vv32.h)",
   30208 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   30209 let Inst{7-5} = 0b101;
   30210 let Inst{13-13} = 0b0;
   30211 let Inst{31-21} = 0b00011111101;
   30212 let hasNewValue = 1;
   30213 let opNewValue = 0;
   30214 let DecoderNamespace = "EXT_mmvec";
   30215 }
   30216 def V6_vaslhv_alt : HInst<
   30217 (outs HvxVR:$Vd32),
   30218 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30219 "$Vd32 = vaslh($Vu32,$Vv32)",
   30220 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30221 let hasNewValue = 1;
   30222 let opNewValue = 0;
   30223 let isPseudo = 1;
   30224 let isCodeGenOnly = 1;
   30225 let DecoderNamespace = "EXT_mmvec";
   30226 }
   30227 def V6_vaslw : HInst<
   30228 (outs HvxVR:$Vd32),
   30229 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30230 "$Vd32.w = vasl($Vu32.w,$Rt32)",
   30231 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   30232 let Inst{7-5} = 0b111;
   30233 let Inst{13-13} = 0b0;
   30234 let Inst{31-21} = 0b00011001011;
   30235 let hasNewValue = 1;
   30236 let opNewValue = 0;
   30237 let DecoderNamespace = "EXT_mmvec";
   30238 }
   30239 def V6_vaslw_acc : HInst<
   30240 (outs HvxVR:$Vx32),
   30241 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30242 "$Vx32.w += vasl($Vu32.w,$Rt32)",
   30243 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
   30244 let Inst{7-5} = 0b010;
   30245 let Inst{13-13} = 0b1;
   30246 let Inst{31-21} = 0b00011001011;
   30247 let hasNewValue = 1;
   30248 let opNewValue = 0;
   30249 let isAccumulator = 1;
   30250 let DecoderNamespace = "EXT_mmvec";
   30251 let Constraints = "$Vx32 = $Vx32in";
   30252 }
   30253 def V6_vaslw_acc_alt : HInst<
   30254 (outs HvxVR:$Vx32),
   30255 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30256 "$Vx32 += vaslw($Vu32,$Rt32)",
   30257 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30258 let hasNewValue = 1;
   30259 let opNewValue = 0;
   30260 let isAccumulator = 1;
   30261 let isPseudo = 1;
   30262 let isCodeGenOnly = 1;
   30263 let DecoderNamespace = "EXT_mmvec";
   30264 let Constraints = "$Vx32 = $Vx32in";
   30265 }
   30266 def V6_vaslw_alt : HInst<
   30267 (outs HvxVR:$Vd32),
   30268 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30269 "$Vd32 = vaslw($Vu32,$Rt32)",
   30270 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30271 let hasNewValue = 1;
   30272 let opNewValue = 0;
   30273 let isPseudo = 1;
   30274 let isCodeGenOnly = 1;
   30275 let DecoderNamespace = "EXT_mmvec";
   30276 }
   30277 def V6_vaslwv : HInst<
   30278 (outs HvxVR:$Vd32),
   30279 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30280 "$Vd32.w = vasl($Vu32.w,$Vv32.w)",
   30281 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   30282 let Inst{7-5} = 0b100;
   30283 let Inst{13-13} = 0b0;
   30284 let Inst{31-21} = 0b00011111101;
   30285 let hasNewValue = 1;
   30286 let opNewValue = 0;
   30287 let DecoderNamespace = "EXT_mmvec";
   30288 }
   30289 def V6_vaslwv_alt : HInst<
   30290 (outs HvxVR:$Vd32),
   30291 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30292 "$Vd32 = vaslw($Vu32,$Vv32)",
   30293 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30294 let hasNewValue = 1;
   30295 let opNewValue = 0;
   30296 let isPseudo = 1;
   30297 let isCodeGenOnly = 1;
   30298 let DecoderNamespace = "EXT_mmvec";
   30299 }
   30300 def V6_vasrh : HInst<
   30301 (outs HvxVR:$Vd32),
   30302 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30303 "$Vd32.h = vasr($Vu32.h,$Rt32)",
   30304 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   30305 let Inst{7-5} = 0b110;
   30306 let Inst{13-13} = 0b0;
   30307 let Inst{31-21} = 0b00011001011;
   30308 let hasNewValue = 1;
   30309 let opNewValue = 0;
   30310 let DecoderNamespace = "EXT_mmvec";
   30311 }
   30312 def V6_vasrh_acc : HInst<
   30313 (outs HvxVR:$Vx32),
   30314 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30315 "$Vx32.h += vasr($Vu32.h,$Rt32)",
   30316 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
   30317 let Inst{7-5} = 0b111;
   30318 let Inst{13-13} = 0b1;
   30319 let Inst{31-21} = 0b00011001100;
   30320 let hasNewValue = 1;
   30321 let opNewValue = 0;
   30322 let isAccumulator = 1;
   30323 let DecoderNamespace = "EXT_mmvec";
   30324 let Constraints = "$Vx32 = $Vx32in";
   30325 }
   30326 def V6_vasrh_acc_alt : HInst<
   30327 (outs HvxVR:$Vx32),
   30328 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30329 "$Vx32 += vasrh($Vu32,$Rt32)",
   30330 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30331 let hasNewValue = 1;
   30332 let opNewValue = 0;
   30333 let isAccumulator = 1;
   30334 let isPseudo = 1;
   30335 let isCodeGenOnly = 1;
   30336 let DecoderNamespace = "EXT_mmvec";
   30337 let Constraints = "$Vx32 = $Vx32in";
   30338 }
   30339 def V6_vasrh_alt : HInst<
   30340 (outs HvxVR:$Vd32),
   30341 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30342 "$Vd32 = vasrh($Vu32,$Rt32)",
   30343 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30344 let hasNewValue = 1;
   30345 let opNewValue = 0;
   30346 let isPseudo = 1;
   30347 let isCodeGenOnly = 1;
   30348 let DecoderNamespace = "EXT_mmvec";
   30349 }
   30350 def V6_vasrhbrndsat : HInst<
   30351 (outs HvxVR:$Vd32),
   30352 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30353 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
   30354 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30355 let Inst{7-5} = 0b000;
   30356 let Inst{13-13} = 0b1;
   30357 let Inst{31-24} = 0b00011011;
   30358 let hasNewValue = 1;
   30359 let opNewValue = 0;
   30360 let DecoderNamespace = "EXT_mmvec";
   30361 }
   30362 def V6_vasrhbrndsat_alt : HInst<
   30363 (outs HvxVR:$Vd32),
   30364 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30365 "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat",
   30366 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30367 let hasNewValue = 1;
   30368 let opNewValue = 0;
   30369 let isPseudo = 1;
   30370 let isCodeGenOnly = 1;
   30371 }
   30372 def V6_vasrhbsat : HInst<
   30373 (outs HvxVR:$Vd32),
   30374 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30375 "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
   30376 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
   30377 let Inst{7-5} = 0b000;
   30378 let Inst{13-13} = 0b0;
   30379 let Inst{31-24} = 0b00011000;
   30380 let hasNewValue = 1;
   30381 let opNewValue = 0;
   30382 let DecoderNamespace = "EXT_mmvec";
   30383 }
   30384 def V6_vasrhubrndsat : HInst<
   30385 (outs HvxVR:$Vd32),
   30386 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30387 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
   30388 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30389 let Inst{7-5} = 0b111;
   30390 let Inst{13-13} = 0b0;
   30391 let Inst{31-24} = 0b00011011;
   30392 let hasNewValue = 1;
   30393 let opNewValue = 0;
   30394 let DecoderNamespace = "EXT_mmvec";
   30395 }
   30396 def V6_vasrhubrndsat_alt : HInst<
   30397 (outs HvxVR:$Vd32),
   30398 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30399 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat",
   30400 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30401 let hasNewValue = 1;
   30402 let opNewValue = 0;
   30403 let isPseudo = 1;
   30404 let isCodeGenOnly = 1;
   30405 }
   30406 def V6_vasrhubsat : HInst<
   30407 (outs HvxVR:$Vd32),
   30408 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30409 "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
   30410 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30411 let Inst{7-5} = 0b110;
   30412 let Inst{13-13} = 0b0;
   30413 let Inst{31-24} = 0b00011011;
   30414 let hasNewValue = 1;
   30415 let opNewValue = 0;
   30416 let DecoderNamespace = "EXT_mmvec";
   30417 }
   30418 def V6_vasrhubsat_alt : HInst<
   30419 (outs HvxVR:$Vd32),
   30420 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30421 "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat",
   30422 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30423 let hasNewValue = 1;
   30424 let opNewValue = 0;
   30425 let isPseudo = 1;
   30426 let isCodeGenOnly = 1;
   30427 }
   30428 def V6_vasrhv : HInst<
   30429 (outs HvxVR:$Vd32),
   30430 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30431 "$Vd32.h = vasr($Vu32.h,$Vv32.h)",
   30432 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   30433 let Inst{7-5} = 0b011;
   30434 let Inst{13-13} = 0b0;
   30435 let Inst{31-21} = 0b00011111101;
   30436 let hasNewValue = 1;
   30437 let opNewValue = 0;
   30438 let DecoderNamespace = "EXT_mmvec";
   30439 }
   30440 def V6_vasrhv_alt : HInst<
   30441 (outs HvxVR:$Vd32),
   30442 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30443 "$Vd32 = vasrh($Vu32,$Vv32)",
   30444 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30445 let hasNewValue = 1;
   30446 let opNewValue = 0;
   30447 let isPseudo = 1;
   30448 let isCodeGenOnly = 1;
   30449 let DecoderNamespace = "EXT_mmvec";
   30450 }
   30451 def V6_vasruhubrndsat : HInst<
   30452 (outs HvxVR:$Vd32),
   30453 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30454 "$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
   30455 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
   30456 let Inst{7-5} = 0b111;
   30457 let Inst{13-13} = 0b0;
   30458 let Inst{31-24} = 0b00011000;
   30459 let hasNewValue = 1;
   30460 let opNewValue = 0;
   30461 let DecoderNamespace = "EXT_mmvec";
   30462 }
   30463 def V6_vasruhubsat : HInst<
   30464 (outs HvxVR:$Vd32),
   30465 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30466 "$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
   30467 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
   30468 let Inst{7-5} = 0b101;
   30469 let Inst{13-13} = 0b1;
   30470 let Inst{31-24} = 0b00011000;
   30471 let hasNewValue = 1;
   30472 let opNewValue = 0;
   30473 let DecoderNamespace = "EXT_mmvec";
   30474 }
   30475 def V6_vasruwuhrndsat : HInst<
   30476 (outs HvxVR:$Vd32),
   30477 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30478 "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
   30479 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
   30480 let Inst{7-5} = 0b001;
   30481 let Inst{13-13} = 0b0;
   30482 let Inst{31-24} = 0b00011000;
   30483 let hasNewValue = 1;
   30484 let opNewValue = 0;
   30485 let DecoderNamespace = "EXT_mmvec";
   30486 }
   30487 def V6_vasruwuhsat : HInst<
   30488 (outs HvxVR:$Vd32),
   30489 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30490 "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
   30491 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
   30492 let Inst{7-5} = 0b100;
   30493 let Inst{13-13} = 0b1;
   30494 let Inst{31-24} = 0b00011000;
   30495 let hasNewValue = 1;
   30496 let opNewValue = 0;
   30497 let DecoderNamespace = "EXT_mmvec";
   30498 }
   30499 def V6_vasrw : HInst<
   30500 (outs HvxVR:$Vd32),
   30501 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30502 "$Vd32.w = vasr($Vu32.w,$Rt32)",
   30503 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   30504 let Inst{7-5} = 0b101;
   30505 let Inst{13-13} = 0b0;
   30506 let Inst{31-21} = 0b00011001011;
   30507 let hasNewValue = 1;
   30508 let opNewValue = 0;
   30509 let DecoderNamespace = "EXT_mmvec";
   30510 }
   30511 def V6_vasrw_acc : HInst<
   30512 (outs HvxVR:$Vx32),
   30513 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30514 "$Vx32.w += vasr($Vu32.w,$Rt32)",
   30515 tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
   30516 let Inst{7-5} = 0b101;
   30517 let Inst{13-13} = 0b1;
   30518 let Inst{31-21} = 0b00011001011;
   30519 let hasNewValue = 1;
   30520 let opNewValue = 0;
   30521 let isAccumulator = 1;
   30522 let DecoderNamespace = "EXT_mmvec";
   30523 let Constraints = "$Vx32 = $Vx32in";
   30524 }
   30525 def V6_vasrw_acc_alt : HInst<
   30526 (outs HvxVR:$Vx32),
   30527 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   30528 "$Vx32 += vasrw($Vu32,$Rt32)",
   30529 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30530 let hasNewValue = 1;
   30531 let opNewValue = 0;
   30532 let isAccumulator = 1;
   30533 let isPseudo = 1;
   30534 let isCodeGenOnly = 1;
   30535 let DecoderNamespace = "EXT_mmvec";
   30536 let Constraints = "$Vx32 = $Vx32in";
   30537 }
   30538 def V6_vasrw_alt : HInst<
   30539 (outs HvxVR:$Vd32),
   30540 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   30541 "$Vd32 = vasrw($Vu32,$Rt32)",
   30542 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30543 let hasNewValue = 1;
   30544 let opNewValue = 0;
   30545 let isPseudo = 1;
   30546 let isCodeGenOnly = 1;
   30547 let DecoderNamespace = "EXT_mmvec";
   30548 }
   30549 def V6_vasrwh : HInst<
   30550 (outs HvxVR:$Vd32),
   30551 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30552 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
   30553 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30554 let Inst{7-5} = 0b010;
   30555 let Inst{13-13} = 0b0;
   30556 let Inst{31-24} = 0b00011011;
   30557 let hasNewValue = 1;
   30558 let opNewValue = 0;
   30559 let DecoderNamespace = "EXT_mmvec";
   30560 }
   30561 def V6_vasrwh_alt : HInst<
   30562 (outs HvxVR:$Vd32),
   30563 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30564 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)",
   30565 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30566 let hasNewValue = 1;
   30567 let opNewValue = 0;
   30568 let isPseudo = 1;
   30569 let isCodeGenOnly = 1;
   30570 }
   30571 def V6_vasrwhrndsat : HInst<
   30572 (outs HvxVR:$Vd32),
   30573 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30574 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
   30575 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30576 let Inst{7-5} = 0b100;
   30577 let Inst{13-13} = 0b0;
   30578 let Inst{31-24} = 0b00011011;
   30579 let hasNewValue = 1;
   30580 let opNewValue = 0;
   30581 let DecoderNamespace = "EXT_mmvec";
   30582 }
   30583 def V6_vasrwhrndsat_alt : HInst<
   30584 (outs HvxVR:$Vd32),
   30585 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30586 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat",
   30587 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30588 let hasNewValue = 1;
   30589 let opNewValue = 0;
   30590 let isPseudo = 1;
   30591 let isCodeGenOnly = 1;
   30592 }
   30593 def V6_vasrwhsat : HInst<
   30594 (outs HvxVR:$Vd32),
   30595 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30596 "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
   30597 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30598 let Inst{7-5} = 0b011;
   30599 let Inst{13-13} = 0b0;
   30600 let Inst{31-24} = 0b00011011;
   30601 let hasNewValue = 1;
   30602 let opNewValue = 0;
   30603 let DecoderNamespace = "EXT_mmvec";
   30604 }
   30605 def V6_vasrwhsat_alt : HInst<
   30606 (outs HvxVR:$Vd32),
   30607 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30608 "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat",
   30609 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30610 let hasNewValue = 1;
   30611 let opNewValue = 0;
   30612 let isPseudo = 1;
   30613 let isCodeGenOnly = 1;
   30614 }
   30615 def V6_vasrwuhrndsat : HInst<
   30616 (outs HvxVR:$Vd32),
   30617 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30618 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
   30619 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
   30620 let Inst{7-5} = 0b010;
   30621 let Inst{13-13} = 0b0;
   30622 let Inst{31-24} = 0b00011000;
   30623 let hasNewValue = 1;
   30624 let opNewValue = 0;
   30625 let DecoderNamespace = "EXT_mmvec";
   30626 }
   30627 def V6_vasrwuhsat : HInst<
   30628 (outs HvxVR:$Vd32),
   30629 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30630 "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
   30631 tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
   30632 let Inst{7-5} = 0b101;
   30633 let Inst{13-13} = 0b0;
   30634 let Inst{31-24} = 0b00011011;
   30635 let hasNewValue = 1;
   30636 let opNewValue = 0;
   30637 let DecoderNamespace = "EXT_mmvec";
   30638 }
   30639 def V6_vasrwuhsat_alt : HInst<
   30640 (outs HvxVR:$Vd32),
   30641 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   30642 "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat",
   30643 tc_7fa8b40f, TypeMAPPING>, Requires<[HasV60]> {
   30644 let hasNewValue = 1;
   30645 let opNewValue = 0;
   30646 let isPseudo = 1;
   30647 let isCodeGenOnly = 1;
   30648 }
   30649 def V6_vasrwv : HInst<
   30650 (outs HvxVR:$Vd32),
   30651 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30652 "$Vd32.w = vasr($Vu32.w,$Vv32.w)",
   30653 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   30654 let Inst{7-5} = 0b000;
   30655 let Inst{13-13} = 0b0;
   30656 let Inst{31-21} = 0b00011111101;
   30657 let hasNewValue = 1;
   30658 let opNewValue = 0;
   30659 let DecoderNamespace = "EXT_mmvec";
   30660 }
   30661 def V6_vasrwv_alt : HInst<
   30662 (outs HvxVR:$Vd32),
   30663 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30664 "$Vd32 = vasrw($Vu32,$Vv32)",
   30665 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30666 let hasNewValue = 1;
   30667 let opNewValue = 0;
   30668 let isPseudo = 1;
   30669 let isCodeGenOnly = 1;
   30670 let DecoderNamespace = "EXT_mmvec";
   30671 }
   30672 def V6_vassign : HInst<
   30673 (outs HvxVR:$Vd32),
   30674 (ins HvxVR:$Vu32),
   30675 "$Vd32 = $Vu32",
   30676 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   30677 let Inst{7-5} = 0b111;
   30678 let Inst{13-13} = 0b1;
   30679 let Inst{31-16} = 0b0001111000000011;
   30680 let hasNewValue = 1;
   30681 let opNewValue = 0;
   30682 let DecoderNamespace = "EXT_mmvec";
   30683 }
   30684 def V6_vassignp : HInst<
   30685 (outs HvxWR:$Vdd32),
   30686 (ins HvxWR:$Vuu32),
   30687 "$Vdd32 = $Vuu32",
   30688 CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
   30689 let hasNewValue = 1;
   30690 let opNewValue = 0;
   30691 let isPseudo = 1;
   30692 let DecoderNamespace = "EXT_mmvec";
   30693 }
   30694 def V6_vavgb : HInst<
   30695 (outs HvxVR:$Vd32),
   30696 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30697 "$Vd32.b = vavg($Vu32.b,$Vv32.b)",
   30698 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
   30699 let Inst{7-5} = 0b100;
   30700 let Inst{13-13} = 0b1;
   30701 let Inst{31-21} = 0b00011111000;
   30702 let hasNewValue = 1;
   30703 let opNewValue = 0;
   30704 let DecoderNamespace = "EXT_mmvec";
   30705 }
   30706 def V6_vavgb_alt : HInst<
   30707 (outs HvxVR:$Vd32),
   30708 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30709 "$Vd32 = vavgb($Vu32,$Vv32)",
   30710 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30711 let hasNewValue = 1;
   30712 let opNewValue = 0;
   30713 let isPseudo = 1;
   30714 let isCodeGenOnly = 1;
   30715 let DecoderNamespace = "EXT_mmvec";
   30716 }
   30717 def V6_vavgbrnd : HInst<
   30718 (outs HvxVR:$Vd32),
   30719 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30720 "$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
   30721 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
   30722 let Inst{7-5} = 0b101;
   30723 let Inst{13-13} = 0b1;
   30724 let Inst{31-21} = 0b00011111000;
   30725 let hasNewValue = 1;
   30726 let opNewValue = 0;
   30727 let DecoderNamespace = "EXT_mmvec";
   30728 }
   30729 def V6_vavgbrnd_alt : HInst<
   30730 (outs HvxVR:$Vd32),
   30731 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30732 "$Vd32 = vavgb($Vu32,$Vv32):rnd",
   30733 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30734 let hasNewValue = 1;
   30735 let opNewValue = 0;
   30736 let isPseudo = 1;
   30737 let isCodeGenOnly = 1;
   30738 let DecoderNamespace = "EXT_mmvec";
   30739 }
   30740 def V6_vavgh : HInst<
   30741 (outs HvxVR:$Vd32),
   30742 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30743 "$Vd32.h = vavg($Vu32.h,$Vv32.h)",
   30744 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30745 let Inst{7-5} = 0b110;
   30746 let Inst{13-13} = 0b0;
   30747 let Inst{31-21} = 0b00011100110;
   30748 let hasNewValue = 1;
   30749 let opNewValue = 0;
   30750 let DecoderNamespace = "EXT_mmvec";
   30751 }
   30752 def V6_vavgh_alt : HInst<
   30753 (outs HvxVR:$Vd32),
   30754 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30755 "$Vd32 = vavgh($Vu32,$Vv32)",
   30756 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30757 let hasNewValue = 1;
   30758 let opNewValue = 0;
   30759 let isPseudo = 1;
   30760 let isCodeGenOnly = 1;
   30761 let DecoderNamespace = "EXT_mmvec";
   30762 }
   30763 def V6_vavghrnd : HInst<
   30764 (outs HvxVR:$Vd32),
   30765 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30766 "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
   30767 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30768 let Inst{7-5} = 0b101;
   30769 let Inst{13-13} = 0b0;
   30770 let Inst{31-21} = 0b00011100111;
   30771 let hasNewValue = 1;
   30772 let opNewValue = 0;
   30773 let DecoderNamespace = "EXT_mmvec";
   30774 }
   30775 def V6_vavghrnd_alt : HInst<
   30776 (outs HvxVR:$Vd32),
   30777 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30778 "$Vd32 = vavgh($Vu32,$Vv32):rnd",
   30779 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30780 let hasNewValue = 1;
   30781 let opNewValue = 0;
   30782 let isPseudo = 1;
   30783 let isCodeGenOnly = 1;
   30784 let DecoderNamespace = "EXT_mmvec";
   30785 }
   30786 def V6_vavgub : HInst<
   30787 (outs HvxVR:$Vd32),
   30788 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30789 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
   30790 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30791 let Inst{7-5} = 0b100;
   30792 let Inst{13-13} = 0b0;
   30793 let Inst{31-21} = 0b00011100110;
   30794 let hasNewValue = 1;
   30795 let opNewValue = 0;
   30796 let DecoderNamespace = "EXT_mmvec";
   30797 }
   30798 def V6_vavgub_alt : HInst<
   30799 (outs HvxVR:$Vd32),
   30800 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30801 "$Vd32 = vavgub($Vu32,$Vv32)",
   30802 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30803 let hasNewValue = 1;
   30804 let opNewValue = 0;
   30805 let isPseudo = 1;
   30806 let isCodeGenOnly = 1;
   30807 let DecoderNamespace = "EXT_mmvec";
   30808 }
   30809 def V6_vavgubrnd : HInst<
   30810 (outs HvxVR:$Vd32),
   30811 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30812 "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
   30813 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30814 let Inst{7-5} = 0b011;
   30815 let Inst{13-13} = 0b0;
   30816 let Inst{31-21} = 0b00011100111;
   30817 let hasNewValue = 1;
   30818 let opNewValue = 0;
   30819 let DecoderNamespace = "EXT_mmvec";
   30820 }
   30821 def V6_vavgubrnd_alt : HInst<
   30822 (outs HvxVR:$Vd32),
   30823 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30824 "$Vd32 = vavgub($Vu32,$Vv32):rnd",
   30825 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30826 let hasNewValue = 1;
   30827 let opNewValue = 0;
   30828 let isPseudo = 1;
   30829 let isCodeGenOnly = 1;
   30830 let DecoderNamespace = "EXT_mmvec";
   30831 }
   30832 def V6_vavguh : HInst<
   30833 (outs HvxVR:$Vd32),
   30834 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30835 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
   30836 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30837 let Inst{7-5} = 0b101;
   30838 let Inst{13-13} = 0b0;
   30839 let Inst{31-21} = 0b00011100110;
   30840 let hasNewValue = 1;
   30841 let opNewValue = 0;
   30842 let DecoderNamespace = "EXT_mmvec";
   30843 }
   30844 def V6_vavguh_alt : HInst<
   30845 (outs HvxVR:$Vd32),
   30846 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30847 "$Vd32 = vavguh($Vu32,$Vv32)",
   30848 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30849 let hasNewValue = 1;
   30850 let opNewValue = 0;
   30851 let isPseudo = 1;
   30852 let isCodeGenOnly = 1;
   30853 let DecoderNamespace = "EXT_mmvec";
   30854 }
   30855 def V6_vavguhrnd : HInst<
   30856 (outs HvxVR:$Vd32),
   30857 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30858 "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
   30859 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30860 let Inst{7-5} = 0b100;
   30861 let Inst{13-13} = 0b0;
   30862 let Inst{31-21} = 0b00011100111;
   30863 let hasNewValue = 1;
   30864 let opNewValue = 0;
   30865 let DecoderNamespace = "EXT_mmvec";
   30866 }
   30867 def V6_vavguhrnd_alt : HInst<
   30868 (outs HvxVR:$Vd32),
   30869 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30870 "$Vd32 = vavguh($Vu32,$Vv32):rnd",
   30871 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30872 let hasNewValue = 1;
   30873 let opNewValue = 0;
   30874 let isPseudo = 1;
   30875 let isCodeGenOnly = 1;
   30876 let DecoderNamespace = "EXT_mmvec";
   30877 }
   30878 def V6_vavguw : HInst<
   30879 (outs HvxVR:$Vd32),
   30880 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30881 "$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
   30882 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
   30883 let Inst{7-5} = 0b010;
   30884 let Inst{13-13} = 0b1;
   30885 let Inst{31-21} = 0b00011111000;
   30886 let hasNewValue = 1;
   30887 let opNewValue = 0;
   30888 let DecoderNamespace = "EXT_mmvec";
   30889 }
   30890 def V6_vavguw_alt : HInst<
   30891 (outs HvxVR:$Vd32),
   30892 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30893 "$Vd32 = vavguw($Vu32,$Vv32)",
   30894 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30895 let hasNewValue = 1;
   30896 let opNewValue = 0;
   30897 let isPseudo = 1;
   30898 let isCodeGenOnly = 1;
   30899 let DecoderNamespace = "EXT_mmvec";
   30900 }
   30901 def V6_vavguwrnd : HInst<
   30902 (outs HvxVR:$Vd32),
   30903 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30904 "$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
   30905 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
   30906 let Inst{7-5} = 0b011;
   30907 let Inst{13-13} = 0b1;
   30908 let Inst{31-21} = 0b00011111000;
   30909 let hasNewValue = 1;
   30910 let opNewValue = 0;
   30911 let DecoderNamespace = "EXT_mmvec";
   30912 }
   30913 def V6_vavguwrnd_alt : HInst<
   30914 (outs HvxVR:$Vd32),
   30915 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30916 "$Vd32 = vavguw($Vu32,$Vv32):rnd",
   30917 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   30918 let hasNewValue = 1;
   30919 let opNewValue = 0;
   30920 let isPseudo = 1;
   30921 let isCodeGenOnly = 1;
   30922 let DecoderNamespace = "EXT_mmvec";
   30923 }
   30924 def V6_vavgw : HInst<
   30925 (outs HvxVR:$Vd32),
   30926 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30927 "$Vd32.w = vavg($Vu32.w,$Vv32.w)",
   30928 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30929 let Inst{7-5} = 0b111;
   30930 let Inst{13-13} = 0b0;
   30931 let Inst{31-21} = 0b00011100110;
   30932 let hasNewValue = 1;
   30933 let opNewValue = 0;
   30934 let DecoderNamespace = "EXT_mmvec";
   30935 }
   30936 def V6_vavgw_alt : HInst<
   30937 (outs HvxVR:$Vd32),
   30938 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30939 "$Vd32 = vavgw($Vu32,$Vv32)",
   30940 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30941 let hasNewValue = 1;
   30942 let opNewValue = 0;
   30943 let isPseudo = 1;
   30944 let isCodeGenOnly = 1;
   30945 let DecoderNamespace = "EXT_mmvec";
   30946 }
   30947 def V6_vavgwrnd : HInst<
   30948 (outs HvxVR:$Vd32),
   30949 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30950 "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
   30951 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   30952 let Inst{7-5} = 0b110;
   30953 let Inst{13-13} = 0b0;
   30954 let Inst{31-21} = 0b00011100111;
   30955 let hasNewValue = 1;
   30956 let opNewValue = 0;
   30957 let DecoderNamespace = "EXT_mmvec";
   30958 }
   30959 def V6_vavgwrnd_alt : HInst<
   30960 (outs HvxVR:$Vd32),
   30961 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   30962 "$Vd32 = vavgw($Vu32,$Vv32):rnd",
   30963 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   30964 let hasNewValue = 1;
   30965 let opNewValue = 0;
   30966 let isPseudo = 1;
   30967 let isCodeGenOnly = 1;
   30968 let DecoderNamespace = "EXT_mmvec";
   30969 }
   30970 def V6_vccombine : HInst<
   30971 (outs HvxWR:$Vdd32),
   30972 (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
   30973 "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
   30974 tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
   30975 let Inst{7-7} = 0b0;
   30976 let Inst{13-13} = 0b0;
   30977 let Inst{31-21} = 0b00011010011;
   30978 let isPredicated = 1;
   30979 let hasNewValue = 1;
   30980 let opNewValue = 0;
   30981 let DecoderNamespace = "EXT_mmvec";
   30982 }
   30983 def V6_vcl0h : HInst<
   30984 (outs HvxVR:$Vd32),
   30985 (ins HvxVR:$Vu32),
   30986 "$Vd32.uh = vcl0($Vu32.uh)",
   30987 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
   30988 let Inst{7-5} = 0b111;
   30989 let Inst{13-13} = 0b0;
   30990 let Inst{31-16} = 0b0001111000000010;
   30991 let hasNewValue = 1;
   30992 let opNewValue = 0;
   30993 let DecoderNamespace = "EXT_mmvec";
   30994 }
   30995 def V6_vcl0h_alt : HInst<
   30996 (outs HvxVR:$Vd32),
   30997 (ins HvxVR:$Vu32),
   30998 "$Vd32 = vcl0h($Vu32)",
   30999 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31000 let hasNewValue = 1;
   31001 let opNewValue = 0;
   31002 let isPseudo = 1;
   31003 let isCodeGenOnly = 1;
   31004 let DecoderNamespace = "EXT_mmvec";
   31005 }
   31006 def V6_vcl0w : HInst<
   31007 (outs HvxVR:$Vd32),
   31008 (ins HvxVR:$Vu32),
   31009 "$Vd32.uw = vcl0($Vu32.uw)",
   31010 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
   31011 let Inst{7-5} = 0b101;
   31012 let Inst{13-13} = 0b0;
   31013 let Inst{31-16} = 0b0001111000000010;
   31014 let hasNewValue = 1;
   31015 let opNewValue = 0;
   31016 let DecoderNamespace = "EXT_mmvec";
   31017 }
   31018 def V6_vcl0w_alt : HInst<
   31019 (outs HvxVR:$Vd32),
   31020 (ins HvxVR:$Vu32),
   31021 "$Vd32 = vcl0w($Vu32)",
   31022 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31023 let hasNewValue = 1;
   31024 let opNewValue = 0;
   31025 let isPseudo = 1;
   31026 let isCodeGenOnly = 1;
   31027 let DecoderNamespace = "EXT_mmvec";
   31028 }
   31029 def V6_vcmov : HInst<
   31030 (outs HvxVR:$Vd32),
   31031 (ins PredRegs:$Ps4, HvxVR:$Vu32),
   31032 "if ($Ps4) $Vd32 = $Vu32",
   31033 tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
   31034 let Inst{7-7} = 0b0;
   31035 let Inst{13-13} = 0b0;
   31036 let Inst{31-16} = 0b0001101000000000;
   31037 let isPredicated = 1;
   31038 let hasNewValue = 1;
   31039 let opNewValue = 0;
   31040 let DecoderNamespace = "EXT_mmvec";
   31041 }
   31042 def V6_vcombine : HInst<
   31043 (outs HvxWR:$Vdd32),
   31044 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31045 "$Vdd32 = vcombine($Vu32,$Vv32)",
   31046 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   31047 let Inst{7-5} = 0b111;
   31048 let Inst{13-13} = 0b0;
   31049 let Inst{31-21} = 0b00011111010;
   31050 let hasNewValue = 1;
   31051 let opNewValue = 0;
   31052 let isRegSequence = 1;
   31053 let DecoderNamespace = "EXT_mmvec";
   31054 }
   31055 def V6_vd0 : HInst<
   31056 (outs HvxVR:$Vd32),
   31057 (ins),
   31058 "$Vd32 = #0",
   31059 CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
   31060 let hasNewValue = 1;
   31061 let opNewValue = 0;
   31062 let isPseudo = 1;
   31063 let isCodeGenOnly = 1;
   31064 let DecoderNamespace = "EXT_mmvec";
   31065 }
   31066 def V6_vdd0 : HInst<
   31067 (outs HvxWR:$Vdd32),
   31068 (ins),
   31069 "$Vdd32 = #0",
   31070 tc_8a6eb39a, TypeMAPPING>, Requires<[UseHVXV65]> {
   31071 let hasNewValue = 1;
   31072 let opNewValue = 0;
   31073 let isPseudo = 1;
   31074 let isCodeGenOnly = 1;
   31075 let DecoderNamespace = "EXT_mmvec";
   31076 }
   31077 def V6_vdeal : HInst<
   31078 (outs HvxVR:$Vy32, HvxVR:$Vx32),
   31079 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
   31080 "vdeal($Vy32,$Vx32,$Rt32)",
   31081 tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
   31082 let Inst{7-5} = 0b010;
   31083 let Inst{13-13} = 0b1;
   31084 let Inst{31-21} = 0b00011001111;
   31085 let hasNewValue = 1;
   31086 let opNewValue = 0;
   31087 let hasNewValue2 = 1;
   31088 let opNewValue2 = 1;
   31089 let DecoderNamespace = "EXT_mmvec";
   31090 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
   31091 }
   31092 def V6_vdealb : HInst<
   31093 (outs HvxVR:$Vd32),
   31094 (ins HvxVR:$Vu32),
   31095 "$Vd32.b = vdeal($Vu32.b)",
   31096 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
   31097 let Inst{7-5} = 0b111;
   31098 let Inst{13-13} = 0b0;
   31099 let Inst{31-16} = 0b0001111000000000;
   31100 let hasNewValue = 1;
   31101 let opNewValue = 0;
   31102 let DecoderNamespace = "EXT_mmvec";
   31103 }
   31104 def V6_vdealb4w : HInst<
   31105 (outs HvxVR:$Vd32),
   31106 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31107 "$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
   31108 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   31109 let Inst{7-5} = 0b111;
   31110 let Inst{13-13} = 0b0;
   31111 let Inst{31-21} = 0b00011111001;
   31112 let hasNewValue = 1;
   31113 let opNewValue = 0;
   31114 let DecoderNamespace = "EXT_mmvec";
   31115 }
   31116 def V6_vdealb4w_alt : HInst<
   31117 (outs HvxVR:$Vd32),
   31118 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31119 "$Vd32 = vdealb4w($Vu32,$Vv32)",
   31120 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31121 let hasNewValue = 1;
   31122 let opNewValue = 0;
   31123 let isPseudo = 1;
   31124 let isCodeGenOnly = 1;
   31125 let DecoderNamespace = "EXT_mmvec";
   31126 }
   31127 def V6_vdealb_alt : HInst<
   31128 (outs HvxVR:$Vd32),
   31129 (ins HvxVR:$Vu32),
   31130 "$Vd32 = vdealb($Vu32)",
   31131 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31132 let hasNewValue = 1;
   31133 let opNewValue = 0;
   31134 let isPseudo = 1;
   31135 let isCodeGenOnly = 1;
   31136 let DecoderNamespace = "EXT_mmvec";
   31137 }
   31138 def V6_vdealh : HInst<
   31139 (outs HvxVR:$Vd32),
   31140 (ins HvxVR:$Vu32),
   31141 "$Vd32.h = vdeal($Vu32.h)",
   31142 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
   31143 let Inst{7-5} = 0b110;
   31144 let Inst{13-13} = 0b0;
   31145 let Inst{31-16} = 0b0001111000000000;
   31146 let hasNewValue = 1;
   31147 let opNewValue = 0;
   31148 let DecoderNamespace = "EXT_mmvec";
   31149 }
   31150 def V6_vdealh_alt : HInst<
   31151 (outs HvxVR:$Vd32),
   31152 (ins HvxVR:$Vu32),
   31153 "$Vd32 = vdealh($Vu32)",
   31154 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31155 let hasNewValue = 1;
   31156 let opNewValue = 0;
   31157 let isPseudo = 1;
   31158 let isCodeGenOnly = 1;
   31159 let DecoderNamespace = "EXT_mmvec";
   31160 }
   31161 def V6_vdealvdd : HInst<
   31162 (outs HvxWR:$Vdd32),
   31163 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   31164 "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
   31165 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
   31166 let Inst{7-5} = 0b100;
   31167 let Inst{13-13} = 0b1;
   31168 let Inst{31-24} = 0b00011011;
   31169 let hasNewValue = 1;
   31170 let opNewValue = 0;
   31171 let DecoderNamespace = "EXT_mmvec";
   31172 }
   31173 def V6_vdelta : HInst<
   31174 (outs HvxVR:$Vd32),
   31175 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31176 "$Vd32 = vdelta($Vu32,$Vv32)",
   31177 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   31178 let Inst{7-5} = 0b001;
   31179 let Inst{13-13} = 0b0;
   31180 let Inst{31-21} = 0b00011111001;
   31181 let hasNewValue = 1;
   31182 let opNewValue = 0;
   31183 let DecoderNamespace = "EXT_mmvec";
   31184 }
   31185 def V6_vdmpybus : HInst<
   31186 (outs HvxVR:$Vd32),
   31187 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31188 "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
   31189 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   31190 let Inst{7-5} = 0b110;
   31191 let Inst{13-13} = 0b0;
   31192 let Inst{31-21} = 0b00011001000;
   31193 let hasNewValue = 1;
   31194 let opNewValue = 0;
   31195 let DecoderNamespace = "EXT_mmvec";
   31196 }
   31197 def V6_vdmpybus_acc : HInst<
   31198 (outs HvxVR:$Vx32),
   31199 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31200 "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
   31201 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   31202 let Inst{7-5} = 0b110;
   31203 let Inst{13-13} = 0b1;
   31204 let Inst{31-21} = 0b00011001000;
   31205 let hasNewValue = 1;
   31206 let opNewValue = 0;
   31207 let isAccumulator = 1;
   31208 let DecoderNamespace = "EXT_mmvec";
   31209 let Constraints = "$Vx32 = $Vx32in";
   31210 }
   31211 def V6_vdmpybus_acc_alt : HInst<
   31212 (outs HvxVR:$Vx32),
   31213 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31214 "$Vx32 += vdmpybus($Vu32,$Rt32)",
   31215 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31216 let hasNewValue = 1;
   31217 let opNewValue = 0;
   31218 let isAccumulator = 1;
   31219 let isPseudo = 1;
   31220 let isCodeGenOnly = 1;
   31221 let DecoderNamespace = "EXT_mmvec";
   31222 let Constraints = "$Vx32 = $Vx32in";
   31223 }
   31224 def V6_vdmpybus_alt : HInst<
   31225 (outs HvxVR:$Vd32),
   31226 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31227 "$Vd32 = vdmpybus($Vu32,$Rt32)",
   31228 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31229 let hasNewValue = 1;
   31230 let opNewValue = 0;
   31231 let isPseudo = 1;
   31232 let isCodeGenOnly = 1;
   31233 let DecoderNamespace = "EXT_mmvec";
   31234 }
   31235 def V6_vdmpybus_dv : HInst<
   31236 (outs HvxWR:$Vdd32),
   31237 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31238 "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
   31239 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   31240 let Inst{7-5} = 0b111;
   31241 let Inst{13-13} = 0b0;
   31242 let Inst{31-21} = 0b00011001000;
   31243 let hasNewValue = 1;
   31244 let opNewValue = 0;
   31245 let DecoderNamespace = "EXT_mmvec";
   31246 }
   31247 def V6_vdmpybus_dv_acc : HInst<
   31248 (outs HvxWR:$Vxx32),
   31249 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31250 "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
   31251 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   31252 let Inst{7-5} = 0b111;
   31253 let Inst{13-13} = 0b1;
   31254 let Inst{31-21} = 0b00011001000;
   31255 let hasNewValue = 1;
   31256 let opNewValue = 0;
   31257 let isAccumulator = 1;
   31258 let DecoderNamespace = "EXT_mmvec";
   31259 let Constraints = "$Vxx32 = $Vxx32in";
   31260 }
   31261 def V6_vdmpybus_dv_acc_alt : HInst<
   31262 (outs HvxWR:$Vxx32),
   31263 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31264 "$Vxx32 += vdmpybus($Vuu32,$Rt32)",
   31265 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31266 let hasNewValue = 1;
   31267 let opNewValue = 0;
   31268 let isAccumulator = 1;
   31269 let isPseudo = 1;
   31270 let isCodeGenOnly = 1;
   31271 let DecoderNamespace = "EXT_mmvec";
   31272 let Constraints = "$Vxx32 = $Vxx32in";
   31273 }
   31274 def V6_vdmpybus_dv_alt : HInst<
   31275 (outs HvxWR:$Vdd32),
   31276 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31277 "$Vdd32 = vdmpybus($Vuu32,$Rt32)",
   31278 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31279 let hasNewValue = 1;
   31280 let opNewValue = 0;
   31281 let isPseudo = 1;
   31282 let isCodeGenOnly = 1;
   31283 let DecoderNamespace = "EXT_mmvec";
   31284 }
   31285 def V6_vdmpyhb : HInst<
   31286 (outs HvxVR:$Vd32),
   31287 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31288 "$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
   31289 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   31290 let Inst{7-5} = 0b010;
   31291 let Inst{13-13} = 0b0;
   31292 let Inst{31-21} = 0b00011001000;
   31293 let hasNewValue = 1;
   31294 let opNewValue = 0;
   31295 let DecoderNamespace = "EXT_mmvec";
   31296 }
   31297 def V6_vdmpyhb_acc : HInst<
   31298 (outs HvxVR:$Vx32),
   31299 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31300 "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
   31301 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   31302 let Inst{7-5} = 0b011;
   31303 let Inst{13-13} = 0b1;
   31304 let Inst{31-21} = 0b00011001000;
   31305 let hasNewValue = 1;
   31306 let opNewValue = 0;
   31307 let isAccumulator = 1;
   31308 let DecoderNamespace = "EXT_mmvec";
   31309 let Constraints = "$Vx32 = $Vx32in";
   31310 }
   31311 def V6_vdmpyhb_acc_alt : HInst<
   31312 (outs HvxVR:$Vx32),
   31313 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31314 "$Vx32 += vdmpyhb($Vu32,$Rt32)",
   31315 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31316 let hasNewValue = 1;
   31317 let opNewValue = 0;
   31318 let isAccumulator = 1;
   31319 let isPseudo = 1;
   31320 let isCodeGenOnly = 1;
   31321 let DecoderNamespace = "EXT_mmvec";
   31322 let Constraints = "$Vx32 = $Vx32in";
   31323 }
   31324 def V6_vdmpyhb_alt : HInst<
   31325 (outs HvxVR:$Vd32),
   31326 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31327 "$Vd32 = vdmpyhb($Vu32,$Rt32)",
   31328 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31329 let hasNewValue = 1;
   31330 let opNewValue = 0;
   31331 let isPseudo = 1;
   31332 let isCodeGenOnly = 1;
   31333 let DecoderNamespace = "EXT_mmvec";
   31334 }
   31335 def V6_vdmpyhb_dv : HInst<
   31336 (outs HvxWR:$Vdd32),
   31337 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31338 "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
   31339 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   31340 let Inst{7-5} = 0b100;
   31341 let Inst{13-13} = 0b0;
   31342 let Inst{31-21} = 0b00011001001;
   31343 let hasNewValue = 1;
   31344 let opNewValue = 0;
   31345 let DecoderNamespace = "EXT_mmvec";
   31346 }
   31347 def V6_vdmpyhb_dv_acc : HInst<
   31348 (outs HvxWR:$Vxx32),
   31349 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31350 "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
   31351 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   31352 let Inst{7-5} = 0b100;
   31353 let Inst{13-13} = 0b1;
   31354 let Inst{31-21} = 0b00011001001;
   31355 let hasNewValue = 1;
   31356 let opNewValue = 0;
   31357 let isAccumulator = 1;
   31358 let DecoderNamespace = "EXT_mmvec";
   31359 let Constraints = "$Vxx32 = $Vxx32in";
   31360 }
   31361 def V6_vdmpyhb_dv_acc_alt : HInst<
   31362 (outs HvxWR:$Vxx32),
   31363 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31364 "$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
   31365 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31366 let hasNewValue = 1;
   31367 let opNewValue = 0;
   31368 let isAccumulator = 1;
   31369 let isPseudo = 1;
   31370 let isCodeGenOnly = 1;
   31371 let DecoderNamespace = "EXT_mmvec";
   31372 let Constraints = "$Vxx32 = $Vxx32in";
   31373 }
   31374 def V6_vdmpyhb_dv_alt : HInst<
   31375 (outs HvxWR:$Vdd32),
   31376 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31377 "$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
   31378 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31379 let hasNewValue = 1;
   31380 let opNewValue = 0;
   31381 let isPseudo = 1;
   31382 let isCodeGenOnly = 1;
   31383 let DecoderNamespace = "EXT_mmvec";
   31384 }
   31385 def V6_vdmpyhisat : HInst<
   31386 (outs HvxVR:$Vd32),
   31387 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31388 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
   31389 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
   31390 let Inst{7-5} = 0b011;
   31391 let Inst{13-13} = 0b0;
   31392 let Inst{31-21} = 0b00011001001;
   31393 let hasNewValue = 1;
   31394 let opNewValue = 0;
   31395 let DecoderNamespace = "EXT_mmvec";
   31396 }
   31397 def V6_vdmpyhisat_acc : HInst<
   31398 (outs HvxVR:$Vx32),
   31399 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31400 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
   31401 tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
   31402 let Inst{7-5} = 0b010;
   31403 let Inst{13-13} = 0b1;
   31404 let Inst{31-21} = 0b00011001001;
   31405 let hasNewValue = 1;
   31406 let opNewValue = 0;
   31407 let isAccumulator = 1;
   31408 let DecoderNamespace = "EXT_mmvec";
   31409 let Constraints = "$Vx32 = $Vx32in";
   31410 }
   31411 def V6_vdmpyhisat_acc_alt : HInst<
   31412 (outs HvxVR:$Vx32),
   31413 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31414 "$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
   31415 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31416 let hasNewValue = 1;
   31417 let opNewValue = 0;
   31418 let isAccumulator = 1;
   31419 let isPseudo = 1;
   31420 let isCodeGenOnly = 1;
   31421 let DecoderNamespace = "EXT_mmvec";
   31422 let Constraints = "$Vx32 = $Vx32in";
   31423 }
   31424 def V6_vdmpyhisat_alt : HInst<
   31425 (outs HvxVR:$Vd32),
   31426 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31427 "$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
   31428 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31429 let hasNewValue = 1;
   31430 let opNewValue = 0;
   31431 let isPseudo = 1;
   31432 let isCodeGenOnly = 1;
   31433 let DecoderNamespace = "EXT_mmvec";
   31434 }
   31435 def V6_vdmpyhsat : HInst<
   31436 (outs HvxVR:$Vd32),
   31437 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31438 "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
   31439 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
   31440 let Inst{7-5} = 0b010;
   31441 let Inst{13-13} = 0b0;
   31442 let Inst{31-21} = 0b00011001001;
   31443 let hasNewValue = 1;
   31444 let opNewValue = 0;
   31445 let DecoderNamespace = "EXT_mmvec";
   31446 }
   31447 def V6_vdmpyhsat_acc : HInst<
   31448 (outs HvxVR:$Vx32),
   31449 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31450 "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
   31451 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
   31452 let Inst{7-5} = 0b011;
   31453 let Inst{13-13} = 0b1;
   31454 let Inst{31-21} = 0b00011001001;
   31455 let hasNewValue = 1;
   31456 let opNewValue = 0;
   31457 let isAccumulator = 1;
   31458 let DecoderNamespace = "EXT_mmvec";
   31459 let Constraints = "$Vx32 = $Vx32in";
   31460 }
   31461 def V6_vdmpyhsat_acc_alt : HInst<
   31462 (outs HvxVR:$Vx32),
   31463 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31464 "$Vx32 += vdmpyh($Vu32,$Rt32):sat",
   31465 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31466 let hasNewValue = 1;
   31467 let opNewValue = 0;
   31468 let isAccumulator = 1;
   31469 let isPseudo = 1;
   31470 let isCodeGenOnly = 1;
   31471 let DecoderNamespace = "EXT_mmvec";
   31472 let Constraints = "$Vx32 = $Vx32in";
   31473 }
   31474 def V6_vdmpyhsat_alt : HInst<
   31475 (outs HvxVR:$Vd32),
   31476 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31477 "$Vd32 = vdmpyh($Vu32,$Rt32):sat",
   31478 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31479 let hasNewValue = 1;
   31480 let opNewValue = 0;
   31481 let isPseudo = 1;
   31482 let isCodeGenOnly = 1;
   31483 let DecoderNamespace = "EXT_mmvec";
   31484 }
   31485 def V6_vdmpyhsuisat : HInst<
   31486 (outs HvxVR:$Vd32),
   31487 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31488 "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
   31489 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
   31490 let Inst{7-5} = 0b001;
   31491 let Inst{13-13} = 0b0;
   31492 let Inst{31-21} = 0b00011001001;
   31493 let hasNewValue = 1;
   31494 let opNewValue = 0;
   31495 let DecoderNamespace = "EXT_mmvec";
   31496 }
   31497 def V6_vdmpyhsuisat_acc : HInst<
   31498 (outs HvxVR:$Vx32),
   31499 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31500 "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
   31501 tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
   31502 let Inst{7-5} = 0b001;
   31503 let Inst{13-13} = 0b1;
   31504 let Inst{31-21} = 0b00011001001;
   31505 let hasNewValue = 1;
   31506 let opNewValue = 0;
   31507 let isAccumulator = 1;
   31508 let DecoderNamespace = "EXT_mmvec";
   31509 let Constraints = "$Vx32 = $Vx32in";
   31510 }
   31511 def V6_vdmpyhsuisat_acc_alt : HInst<
   31512 (outs HvxVR:$Vx32),
   31513 (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31514 "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
   31515 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31516 let hasNewValue = 1;
   31517 let opNewValue = 0;
   31518 let isAccumulator = 1;
   31519 let isPseudo = 1;
   31520 let isCodeGenOnly = 1;
   31521 let DecoderNamespace = "EXT_mmvec";
   31522 let Constraints = "$Vx32 = $Vx32in";
   31523 }
   31524 def V6_vdmpyhsuisat_alt : HInst<
   31525 (outs HvxVR:$Vd32),
   31526 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31527 "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
   31528 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31529 let hasNewValue = 1;
   31530 let opNewValue = 0;
   31531 let isPseudo = 1;
   31532 let isCodeGenOnly = 1;
   31533 let DecoderNamespace = "EXT_mmvec";
   31534 }
   31535 def V6_vdmpyhsusat : HInst<
   31536 (outs HvxVR:$Vd32),
   31537 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31538 "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
   31539 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
   31540 let Inst{7-5} = 0b000;
   31541 let Inst{13-13} = 0b0;
   31542 let Inst{31-21} = 0b00011001001;
   31543 let hasNewValue = 1;
   31544 let opNewValue = 0;
   31545 let DecoderNamespace = "EXT_mmvec";
   31546 }
   31547 def V6_vdmpyhsusat_acc : HInst<
   31548 (outs HvxVR:$Vx32),
   31549 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31550 "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
   31551 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
   31552 let Inst{7-5} = 0b000;
   31553 let Inst{13-13} = 0b1;
   31554 let Inst{31-21} = 0b00011001001;
   31555 let hasNewValue = 1;
   31556 let opNewValue = 0;
   31557 let isAccumulator = 1;
   31558 let DecoderNamespace = "EXT_mmvec";
   31559 let Constraints = "$Vx32 = $Vx32in";
   31560 }
   31561 def V6_vdmpyhsusat_acc_alt : HInst<
   31562 (outs HvxVR:$Vx32),
   31563 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   31564 "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
   31565 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31566 let hasNewValue = 1;
   31567 let opNewValue = 0;
   31568 let isAccumulator = 1;
   31569 let isPseudo = 1;
   31570 let isCodeGenOnly = 1;
   31571 let DecoderNamespace = "EXT_mmvec";
   31572 let Constraints = "$Vx32 = $Vx32in";
   31573 }
   31574 def V6_vdmpyhsusat_alt : HInst<
   31575 (outs HvxVR:$Vd32),
   31576 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   31577 "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
   31578 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31579 let hasNewValue = 1;
   31580 let opNewValue = 0;
   31581 let isPseudo = 1;
   31582 let isCodeGenOnly = 1;
   31583 let DecoderNamespace = "EXT_mmvec";
   31584 }
   31585 def V6_vdmpyhvsat : HInst<
   31586 (outs HvxVR:$Vd32),
   31587 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31588 "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
   31589 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   31590 let Inst{7-5} = 0b011;
   31591 let Inst{13-13} = 0b0;
   31592 let Inst{31-21} = 0b00011100000;
   31593 let hasNewValue = 1;
   31594 let opNewValue = 0;
   31595 let DecoderNamespace = "EXT_mmvec";
   31596 }
   31597 def V6_vdmpyhvsat_acc : HInst<
   31598 (outs HvxVR:$Vx32),
   31599 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   31600 "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
   31601 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   31602 let Inst{7-5} = 0b011;
   31603 let Inst{13-13} = 0b1;
   31604 let Inst{31-21} = 0b00011100000;
   31605 let hasNewValue = 1;
   31606 let opNewValue = 0;
   31607 let isAccumulator = 1;
   31608 let DecoderNamespace = "EXT_mmvec";
   31609 let Constraints = "$Vx32 = $Vx32in";
   31610 }
   31611 def V6_vdmpyhvsat_acc_alt : HInst<
   31612 (outs HvxVR:$Vx32),
   31613 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   31614 "$Vx32 += vdmpyh($Vu32,$Vv32):sat",
   31615 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31616 let hasNewValue = 1;
   31617 let opNewValue = 0;
   31618 let isAccumulator = 1;
   31619 let isPseudo = 1;
   31620 let isCodeGenOnly = 1;
   31621 let DecoderNamespace = "EXT_mmvec";
   31622 let Constraints = "$Vx32 = $Vx32in";
   31623 }
   31624 def V6_vdmpyhvsat_alt : HInst<
   31625 (outs HvxVR:$Vd32),
   31626 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31627 "$Vd32 = vdmpyh($Vu32,$Vv32):sat",
   31628 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31629 let hasNewValue = 1;
   31630 let opNewValue = 0;
   31631 let isPseudo = 1;
   31632 let isCodeGenOnly = 1;
   31633 let DecoderNamespace = "EXT_mmvec";
   31634 }
   31635 def V6_vdsaduh : HInst<
   31636 (outs HvxWR:$Vdd32),
   31637 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31638 "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
   31639 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   31640 let Inst{7-5} = 0b101;
   31641 let Inst{13-13} = 0b0;
   31642 let Inst{31-21} = 0b00011001000;
   31643 let hasNewValue = 1;
   31644 let opNewValue = 0;
   31645 let DecoderNamespace = "EXT_mmvec";
   31646 }
   31647 def V6_vdsaduh_acc : HInst<
   31648 (outs HvxWR:$Vxx32),
   31649 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31650 "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
   31651 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   31652 let Inst{7-5} = 0b000;
   31653 let Inst{13-13} = 0b1;
   31654 let Inst{31-21} = 0b00011001011;
   31655 let hasNewValue = 1;
   31656 let opNewValue = 0;
   31657 let isAccumulator = 1;
   31658 let DecoderNamespace = "EXT_mmvec";
   31659 let Constraints = "$Vxx32 = $Vxx32in";
   31660 }
   31661 def V6_vdsaduh_acc_alt : HInst<
   31662 (outs HvxWR:$Vxx32),
   31663 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   31664 "$Vxx32 += vdsaduh($Vuu32,$Rt32)",
   31665 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31666 let hasNewValue = 1;
   31667 let opNewValue = 0;
   31668 let isAccumulator = 1;
   31669 let isPseudo = 1;
   31670 let isCodeGenOnly = 1;
   31671 let DecoderNamespace = "EXT_mmvec";
   31672 let Constraints = "$Vxx32 = $Vxx32in";
   31673 }
   31674 def V6_vdsaduh_alt : HInst<
   31675 (outs HvxWR:$Vdd32),
   31676 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   31677 "$Vdd32 = vdsaduh($Vuu32,$Rt32)",
   31678 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   31679 let hasNewValue = 1;
   31680 let opNewValue = 0;
   31681 let isPseudo = 1;
   31682 let isCodeGenOnly = 1;
   31683 let DecoderNamespace = "EXT_mmvec";
   31684 }
   31685 def V6_veqb : HInst<
   31686 (outs HvxQR:$Qd4),
   31687 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31688 "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
   31689 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   31690 let Inst{7-2} = 0b000000;
   31691 let Inst{13-13} = 0b0;
   31692 let Inst{31-21} = 0b00011111100;
   31693 let hasNewValue = 1;
   31694 let opNewValue = 0;
   31695 let DecoderNamespace = "EXT_mmvec";
   31696 }
   31697 def V6_veqb_and : HInst<
   31698 (outs HvxQR:$Qx4),
   31699 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31700 "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
   31701 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31702 let Inst{7-2} = 0b000000;
   31703 let Inst{13-13} = 0b1;
   31704 let Inst{31-21} = 0b00011100100;
   31705 let DecoderNamespace = "EXT_mmvec";
   31706 let Constraints = "$Qx4 = $Qx4in";
   31707 }
   31708 def V6_veqb_or : HInst<
   31709 (outs HvxQR:$Qx4),
   31710 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31711 "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
   31712 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31713 let Inst{7-2} = 0b010000;
   31714 let Inst{13-13} = 0b1;
   31715 let Inst{31-21} = 0b00011100100;
   31716 let isAccumulator = 1;
   31717 let DecoderNamespace = "EXT_mmvec";
   31718 let Constraints = "$Qx4 = $Qx4in";
   31719 }
   31720 def V6_veqb_xor : HInst<
   31721 (outs HvxQR:$Qx4),
   31722 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31723 "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
   31724 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31725 let Inst{7-2} = 0b100000;
   31726 let Inst{13-13} = 0b1;
   31727 let Inst{31-21} = 0b00011100100;
   31728 let DecoderNamespace = "EXT_mmvec";
   31729 let Constraints = "$Qx4 = $Qx4in";
   31730 }
   31731 def V6_veqh : HInst<
   31732 (outs HvxQR:$Qd4),
   31733 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31734 "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
   31735 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   31736 let Inst{7-2} = 0b000001;
   31737 let Inst{13-13} = 0b0;
   31738 let Inst{31-21} = 0b00011111100;
   31739 let hasNewValue = 1;
   31740 let opNewValue = 0;
   31741 let DecoderNamespace = "EXT_mmvec";
   31742 }
   31743 def V6_veqh_and : HInst<
   31744 (outs HvxQR:$Qx4),
   31745 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31746 "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
   31747 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31748 let Inst{7-2} = 0b000001;
   31749 let Inst{13-13} = 0b1;
   31750 let Inst{31-21} = 0b00011100100;
   31751 let DecoderNamespace = "EXT_mmvec";
   31752 let Constraints = "$Qx4 = $Qx4in";
   31753 }
   31754 def V6_veqh_or : HInst<
   31755 (outs HvxQR:$Qx4),
   31756 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31757 "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
   31758 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31759 let Inst{7-2} = 0b010001;
   31760 let Inst{13-13} = 0b1;
   31761 let Inst{31-21} = 0b00011100100;
   31762 let isAccumulator = 1;
   31763 let DecoderNamespace = "EXT_mmvec";
   31764 let Constraints = "$Qx4 = $Qx4in";
   31765 }
   31766 def V6_veqh_xor : HInst<
   31767 (outs HvxQR:$Qx4),
   31768 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31769 "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
   31770 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31771 let Inst{7-2} = 0b100001;
   31772 let Inst{13-13} = 0b1;
   31773 let Inst{31-21} = 0b00011100100;
   31774 let DecoderNamespace = "EXT_mmvec";
   31775 let Constraints = "$Qx4 = $Qx4in";
   31776 }
   31777 def V6_veqw : HInst<
   31778 (outs HvxQR:$Qd4),
   31779 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31780 "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
   31781 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   31782 let Inst{7-2} = 0b000010;
   31783 let Inst{13-13} = 0b0;
   31784 let Inst{31-21} = 0b00011111100;
   31785 let hasNewValue = 1;
   31786 let opNewValue = 0;
   31787 let DecoderNamespace = "EXT_mmvec";
   31788 }
   31789 def V6_veqw_and : HInst<
   31790 (outs HvxQR:$Qx4),
   31791 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31792 "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
   31793 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31794 let Inst{7-2} = 0b000010;
   31795 let Inst{13-13} = 0b1;
   31796 let Inst{31-21} = 0b00011100100;
   31797 let DecoderNamespace = "EXT_mmvec";
   31798 let Constraints = "$Qx4 = $Qx4in";
   31799 }
   31800 def V6_veqw_or : HInst<
   31801 (outs HvxQR:$Qx4),
   31802 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31803 "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
   31804 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31805 let Inst{7-2} = 0b010010;
   31806 let Inst{13-13} = 0b1;
   31807 let Inst{31-21} = 0b00011100100;
   31808 let isAccumulator = 1;
   31809 let DecoderNamespace = "EXT_mmvec";
   31810 let Constraints = "$Qx4 = $Qx4in";
   31811 }
   31812 def V6_veqw_xor : HInst<
   31813 (outs HvxQR:$Qx4),
   31814 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31815 "$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
   31816 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31817 let Inst{7-2} = 0b100010;
   31818 let Inst{13-13} = 0b1;
   31819 let Inst{31-21} = 0b00011100100;
   31820 let DecoderNamespace = "EXT_mmvec";
   31821 let Constraints = "$Qx4 = $Qx4in";
   31822 }
   31823 def V6_vgathermh : HInst<
   31824 (outs),
   31825 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
   31826 "vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
   31827 tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
   31828 let Inst{12-5} = 0b00001000;
   31829 let Inst{31-21} = 0b00101111000;
   31830 let hasNewValue = 1;
   31831 let opNewValue = 0;
   31832 let accessSize = HalfWordAccess;
   31833 let isCVLoad = 1;
   31834 let hasTmpDst = 1;
   31835 let mayLoad = 1;
   31836 let Defs = [VTMP];
   31837 let DecoderNamespace = "EXT_mmvec";
   31838 }
   31839 def V6_vgathermhq : HInst<
   31840 (outs),
   31841 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
   31842 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
   31843 tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
   31844 let Inst{12-7} = 0b001010;
   31845 let Inst{31-21} = 0b00101111000;
   31846 let hasNewValue = 1;
   31847 let opNewValue = 0;
   31848 let accessSize = HalfWordAccess;
   31849 let isCVLoad = 1;
   31850 let hasTmpDst = 1;
   31851 let mayLoad = 1;
   31852 let Defs = [VTMP];
   31853 let DecoderNamespace = "EXT_mmvec";
   31854 }
   31855 def V6_vgathermhw : HInst<
   31856 (outs),
   31857 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
   31858 "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
   31859 tc_bfe309d5, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> {
   31860 let Inst{12-5} = 0b00010000;
   31861 let Inst{31-21} = 0b00101111000;
   31862 let hasNewValue = 1;
   31863 let opNewValue = 0;
   31864 let accessSize = HalfWordAccess;
   31865 let isCVLoad = 1;
   31866 let hasTmpDst = 1;
   31867 let mayLoad = 1;
   31868 let Defs = [VTMP];
   31869 let DecoderNamespace = "EXT_mmvec";
   31870 }
   31871 def V6_vgathermhwq : HInst<
   31872 (outs),
   31873 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
   31874 "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
   31875 tc_98733e9d, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> {
   31876 let Inst{12-7} = 0b001100;
   31877 let Inst{31-21} = 0b00101111000;
   31878 let hasNewValue = 1;
   31879 let opNewValue = 0;
   31880 let accessSize = HalfWordAccess;
   31881 let isCVLoad = 1;
   31882 let hasTmpDst = 1;
   31883 let mayLoad = 1;
   31884 let Defs = [VTMP];
   31885 let DecoderNamespace = "EXT_mmvec";
   31886 }
   31887 def V6_vgathermw : HInst<
   31888 (outs),
   31889 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
   31890 "vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
   31891 tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
   31892 let Inst{12-5} = 0b00000000;
   31893 let Inst{31-21} = 0b00101111000;
   31894 let hasNewValue = 1;
   31895 let opNewValue = 0;
   31896 let accessSize = WordAccess;
   31897 let isCVLoad = 1;
   31898 let hasTmpDst = 1;
   31899 let mayLoad = 1;
   31900 let Defs = [VTMP];
   31901 let DecoderNamespace = "EXT_mmvec";
   31902 }
   31903 def V6_vgathermwq : HInst<
   31904 (outs),
   31905 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
   31906 "if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
   31907 tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
   31908 let Inst{12-7} = 0b001000;
   31909 let Inst{31-21} = 0b00101111000;
   31910 let hasNewValue = 1;
   31911 let opNewValue = 0;
   31912 let accessSize = WordAccess;
   31913 let isCVLoad = 1;
   31914 let hasTmpDst = 1;
   31915 let mayLoad = 1;
   31916 let Defs = [VTMP];
   31917 let DecoderNamespace = "EXT_mmvec";
   31918 }
   31919 def V6_vgtb : HInst<
   31920 (outs HvxQR:$Qd4),
   31921 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31922 "$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
   31923 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   31924 let Inst{7-2} = 0b000100;
   31925 let Inst{13-13} = 0b0;
   31926 let Inst{31-21} = 0b00011111100;
   31927 let hasNewValue = 1;
   31928 let opNewValue = 0;
   31929 let DecoderNamespace = "EXT_mmvec";
   31930 }
   31931 def V6_vgtb_and : HInst<
   31932 (outs HvxQR:$Qx4),
   31933 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31934 "$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
   31935 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31936 let Inst{7-2} = 0b000100;
   31937 let Inst{13-13} = 0b1;
   31938 let Inst{31-21} = 0b00011100100;
   31939 let DecoderNamespace = "EXT_mmvec";
   31940 let Constraints = "$Qx4 = $Qx4in";
   31941 }
   31942 def V6_vgtb_or : HInst<
   31943 (outs HvxQR:$Qx4),
   31944 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31945 "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
   31946 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31947 let Inst{7-2} = 0b010100;
   31948 let Inst{13-13} = 0b1;
   31949 let Inst{31-21} = 0b00011100100;
   31950 let isAccumulator = 1;
   31951 let DecoderNamespace = "EXT_mmvec";
   31952 let Constraints = "$Qx4 = $Qx4in";
   31953 }
   31954 def V6_vgtb_xor : HInst<
   31955 (outs HvxQR:$Qx4),
   31956 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31957 "$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
   31958 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31959 let Inst{7-2} = 0b100100;
   31960 let Inst{13-13} = 0b1;
   31961 let Inst{31-21} = 0b00011100100;
   31962 let DecoderNamespace = "EXT_mmvec";
   31963 let Constraints = "$Qx4 = $Qx4in";
   31964 }
   31965 def V6_vgth : HInst<
   31966 (outs HvxQR:$Qd4),
   31967 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   31968 "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
   31969 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   31970 let Inst{7-2} = 0b000101;
   31971 let Inst{13-13} = 0b0;
   31972 let Inst{31-21} = 0b00011111100;
   31973 let hasNewValue = 1;
   31974 let opNewValue = 0;
   31975 let DecoderNamespace = "EXT_mmvec";
   31976 }
   31977 def V6_vgth_and : HInst<
   31978 (outs HvxQR:$Qx4),
   31979 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31980 "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
   31981 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31982 let Inst{7-2} = 0b000101;
   31983 let Inst{13-13} = 0b1;
   31984 let Inst{31-21} = 0b00011100100;
   31985 let DecoderNamespace = "EXT_mmvec";
   31986 let Constraints = "$Qx4 = $Qx4in";
   31987 }
   31988 def V6_vgth_or : HInst<
   31989 (outs HvxQR:$Qx4),
   31990 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   31991 "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
   31992 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   31993 let Inst{7-2} = 0b010101;
   31994 let Inst{13-13} = 0b1;
   31995 let Inst{31-21} = 0b00011100100;
   31996 let isAccumulator = 1;
   31997 let DecoderNamespace = "EXT_mmvec";
   31998 let Constraints = "$Qx4 = $Qx4in";
   31999 }
   32000 def V6_vgth_xor : HInst<
   32001 (outs HvxQR:$Qx4),
   32002 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32003 "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
   32004 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32005 let Inst{7-2} = 0b100101;
   32006 let Inst{13-13} = 0b1;
   32007 let Inst{31-21} = 0b00011100100;
   32008 let DecoderNamespace = "EXT_mmvec";
   32009 let Constraints = "$Qx4 = $Qx4in";
   32010 }
   32011 def V6_vgtub : HInst<
   32012 (outs HvxQR:$Qd4),
   32013 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32014 "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
   32015 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   32016 let Inst{7-2} = 0b001000;
   32017 let Inst{13-13} = 0b0;
   32018 let Inst{31-21} = 0b00011111100;
   32019 let hasNewValue = 1;
   32020 let opNewValue = 0;
   32021 let DecoderNamespace = "EXT_mmvec";
   32022 }
   32023 def V6_vgtub_and : HInst<
   32024 (outs HvxQR:$Qx4),
   32025 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32026 "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
   32027 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32028 let Inst{7-2} = 0b001000;
   32029 let Inst{13-13} = 0b1;
   32030 let Inst{31-21} = 0b00011100100;
   32031 let DecoderNamespace = "EXT_mmvec";
   32032 let Constraints = "$Qx4 = $Qx4in";
   32033 }
   32034 def V6_vgtub_or : HInst<
   32035 (outs HvxQR:$Qx4),
   32036 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32037 "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
   32038 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32039 let Inst{7-2} = 0b011000;
   32040 let Inst{13-13} = 0b1;
   32041 let Inst{31-21} = 0b00011100100;
   32042 let isAccumulator = 1;
   32043 let DecoderNamespace = "EXT_mmvec";
   32044 let Constraints = "$Qx4 = $Qx4in";
   32045 }
   32046 def V6_vgtub_xor : HInst<
   32047 (outs HvxQR:$Qx4),
   32048 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32049 "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
   32050 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32051 let Inst{7-2} = 0b101000;
   32052 let Inst{13-13} = 0b1;
   32053 let Inst{31-21} = 0b00011100100;
   32054 let DecoderNamespace = "EXT_mmvec";
   32055 let Constraints = "$Qx4 = $Qx4in";
   32056 }
   32057 def V6_vgtuh : HInst<
   32058 (outs HvxQR:$Qd4),
   32059 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32060 "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
   32061 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   32062 let Inst{7-2} = 0b001001;
   32063 let Inst{13-13} = 0b0;
   32064 let Inst{31-21} = 0b00011111100;
   32065 let hasNewValue = 1;
   32066 let opNewValue = 0;
   32067 let DecoderNamespace = "EXT_mmvec";
   32068 }
   32069 def V6_vgtuh_and : HInst<
   32070 (outs HvxQR:$Qx4),
   32071 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32072 "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
   32073 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32074 let Inst{7-2} = 0b001001;
   32075 let Inst{13-13} = 0b1;
   32076 let Inst{31-21} = 0b00011100100;
   32077 let DecoderNamespace = "EXT_mmvec";
   32078 let Constraints = "$Qx4 = $Qx4in";
   32079 }
   32080 def V6_vgtuh_or : HInst<
   32081 (outs HvxQR:$Qx4),
   32082 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32083 "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
   32084 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32085 let Inst{7-2} = 0b011001;
   32086 let Inst{13-13} = 0b1;
   32087 let Inst{31-21} = 0b00011100100;
   32088 let isAccumulator = 1;
   32089 let DecoderNamespace = "EXT_mmvec";
   32090 let Constraints = "$Qx4 = $Qx4in";
   32091 }
   32092 def V6_vgtuh_xor : HInst<
   32093 (outs HvxQR:$Qx4),
   32094 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32095 "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
   32096 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32097 let Inst{7-2} = 0b101001;
   32098 let Inst{13-13} = 0b1;
   32099 let Inst{31-21} = 0b00011100100;
   32100 let DecoderNamespace = "EXT_mmvec";
   32101 let Constraints = "$Qx4 = $Qx4in";
   32102 }
   32103 def V6_vgtuw : HInst<
   32104 (outs HvxQR:$Qd4),
   32105 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32106 "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
   32107 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   32108 let Inst{7-2} = 0b001010;
   32109 let Inst{13-13} = 0b0;
   32110 let Inst{31-21} = 0b00011111100;
   32111 let hasNewValue = 1;
   32112 let opNewValue = 0;
   32113 let DecoderNamespace = "EXT_mmvec";
   32114 }
   32115 def V6_vgtuw_and : HInst<
   32116 (outs HvxQR:$Qx4),
   32117 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32118 "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
   32119 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32120 let Inst{7-2} = 0b001010;
   32121 let Inst{13-13} = 0b1;
   32122 let Inst{31-21} = 0b00011100100;
   32123 let DecoderNamespace = "EXT_mmvec";
   32124 let Constraints = "$Qx4 = $Qx4in";
   32125 }
   32126 def V6_vgtuw_or : HInst<
   32127 (outs HvxQR:$Qx4),
   32128 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32129 "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
   32130 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32131 let Inst{7-2} = 0b011010;
   32132 let Inst{13-13} = 0b1;
   32133 let Inst{31-21} = 0b00011100100;
   32134 let isAccumulator = 1;
   32135 let DecoderNamespace = "EXT_mmvec";
   32136 let Constraints = "$Qx4 = $Qx4in";
   32137 }
   32138 def V6_vgtuw_xor : HInst<
   32139 (outs HvxQR:$Qx4),
   32140 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32141 "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
   32142 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32143 let Inst{7-2} = 0b101010;
   32144 let Inst{13-13} = 0b1;
   32145 let Inst{31-21} = 0b00011100100;
   32146 let DecoderNamespace = "EXT_mmvec";
   32147 let Constraints = "$Qx4 = $Qx4in";
   32148 }
   32149 def V6_vgtw : HInst<
   32150 (outs HvxQR:$Qd4),
   32151 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32152 "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
   32153 tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
   32154 let Inst{7-2} = 0b000110;
   32155 let Inst{13-13} = 0b0;
   32156 let Inst{31-21} = 0b00011111100;
   32157 let hasNewValue = 1;
   32158 let opNewValue = 0;
   32159 let DecoderNamespace = "EXT_mmvec";
   32160 }
   32161 def V6_vgtw_and : HInst<
   32162 (outs HvxQR:$Qx4),
   32163 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32164 "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
   32165 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32166 let Inst{7-2} = 0b000110;
   32167 let Inst{13-13} = 0b1;
   32168 let Inst{31-21} = 0b00011100100;
   32169 let DecoderNamespace = "EXT_mmvec";
   32170 let Constraints = "$Qx4 = $Qx4in";
   32171 }
   32172 def V6_vgtw_or : HInst<
   32173 (outs HvxQR:$Qx4),
   32174 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32175 "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
   32176 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32177 let Inst{7-2} = 0b010110;
   32178 let Inst{13-13} = 0b1;
   32179 let Inst{31-21} = 0b00011100100;
   32180 let isAccumulator = 1;
   32181 let DecoderNamespace = "EXT_mmvec";
   32182 let Constraints = "$Qx4 = $Qx4in";
   32183 }
   32184 def V6_vgtw_xor : HInst<
   32185 (outs HvxQR:$Qx4),
   32186 (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
   32187 "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
   32188 tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
   32189 let Inst{7-2} = 0b100110;
   32190 let Inst{13-13} = 0b1;
   32191 let Inst{31-21} = 0b00011100100;
   32192 let DecoderNamespace = "EXT_mmvec";
   32193 let Constraints = "$Qx4 = $Qx4in";
   32194 }
   32195 def V6_vhist : HInst<
   32196 (outs),
   32197 (ins),
   32198 "vhist",
   32199 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
   32200 let Inst{13-0} = 0b10000010000000;
   32201 let Inst{31-16} = 0b0001111000000000;
   32202 let DecoderNamespace = "EXT_mmvec";
   32203 }
   32204 def V6_vhistq : HInst<
   32205 (outs),
   32206 (ins HvxQR:$Qv4),
   32207 "vhist($Qv4)",
   32208 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
   32209 let Inst{13-0} = 0b10000010000000;
   32210 let Inst{21-16} = 0b000010;
   32211 let Inst{31-24} = 0b00011110;
   32212 let DecoderNamespace = "EXT_mmvec";
   32213 }
   32214 def V6_vinsertwr : HInst<
   32215 (outs HvxVR:$Vx32),
   32216 (ins HvxVR:$Vx32in, IntRegs:$Rt32),
   32217 "$Vx32.w = vinsert($Rt32)",
   32218 tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
   32219 let Inst{13-5} = 0b100000001;
   32220 let Inst{31-21} = 0b00011001101;
   32221 let hasNewValue = 1;
   32222 let opNewValue = 0;
   32223 let DecoderNamespace = "EXT_mmvec";
   32224 let Constraints = "$Vx32 = $Vx32in";
   32225 }
   32226 def V6_vlalignb : HInst<
   32227 (outs HvxVR:$Vd32),
   32228 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32229 "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
   32230 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
   32231 let Inst{7-5} = 0b001;
   32232 let Inst{13-13} = 0b0;
   32233 let Inst{31-24} = 0b00011011;
   32234 let hasNewValue = 1;
   32235 let opNewValue = 0;
   32236 let DecoderNamespace = "EXT_mmvec";
   32237 }
   32238 def V6_vlalignbi : HInst<
   32239 (outs HvxVR:$Vd32),
   32240 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   32241 "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
   32242 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
   32243 let Inst{13-13} = 0b1;
   32244 let Inst{31-21} = 0b00011110011;
   32245 let hasNewValue = 1;
   32246 let opNewValue = 0;
   32247 let DecoderNamespace = "EXT_mmvec";
   32248 }
   32249 def V6_vlsrb : HInst<
   32250 (outs HvxVR:$Vd32),
   32251 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   32252 "$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
   32253 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
   32254 let Inst{7-5} = 0b011;
   32255 let Inst{13-13} = 0b0;
   32256 let Inst{31-21} = 0b00011001100;
   32257 let hasNewValue = 1;
   32258 let opNewValue = 0;
   32259 let DecoderNamespace = "EXT_mmvec";
   32260 }
   32261 def V6_vlsrh : HInst<
   32262 (outs HvxVR:$Vd32),
   32263 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   32264 "$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
   32265 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   32266 let Inst{7-5} = 0b010;
   32267 let Inst{13-13} = 0b0;
   32268 let Inst{31-21} = 0b00011001100;
   32269 let hasNewValue = 1;
   32270 let opNewValue = 0;
   32271 let DecoderNamespace = "EXT_mmvec";
   32272 }
   32273 def V6_vlsrh_alt : HInst<
   32274 (outs HvxVR:$Vd32),
   32275 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   32276 "$Vd32 = vlsrh($Vu32,$Rt32)",
   32277 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32278 let hasNewValue = 1;
   32279 let opNewValue = 0;
   32280 let isPseudo = 1;
   32281 let isCodeGenOnly = 1;
   32282 let DecoderNamespace = "EXT_mmvec";
   32283 }
   32284 def V6_vlsrhv : HInst<
   32285 (outs HvxVR:$Vd32),
   32286 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32287 "$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
   32288 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   32289 let Inst{7-5} = 0b010;
   32290 let Inst{13-13} = 0b0;
   32291 let Inst{31-21} = 0b00011111101;
   32292 let hasNewValue = 1;
   32293 let opNewValue = 0;
   32294 let DecoderNamespace = "EXT_mmvec";
   32295 }
   32296 def V6_vlsrhv_alt : HInst<
   32297 (outs HvxVR:$Vd32),
   32298 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32299 "$Vd32 = vlsrh($Vu32,$Vv32)",
   32300 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32301 let hasNewValue = 1;
   32302 let opNewValue = 0;
   32303 let isPseudo = 1;
   32304 let isCodeGenOnly = 1;
   32305 let DecoderNamespace = "EXT_mmvec";
   32306 }
   32307 def V6_vlsrw : HInst<
   32308 (outs HvxVR:$Vd32),
   32309 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   32310 "$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
   32311 tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
   32312 let Inst{7-5} = 0b001;
   32313 let Inst{13-13} = 0b0;
   32314 let Inst{31-21} = 0b00011001100;
   32315 let hasNewValue = 1;
   32316 let opNewValue = 0;
   32317 let DecoderNamespace = "EXT_mmvec";
   32318 }
   32319 def V6_vlsrw_alt : HInst<
   32320 (outs HvxVR:$Vd32),
   32321 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   32322 "$Vd32 = vlsrw($Vu32,$Rt32)",
   32323 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32324 let hasNewValue = 1;
   32325 let opNewValue = 0;
   32326 let isPseudo = 1;
   32327 let isCodeGenOnly = 1;
   32328 let DecoderNamespace = "EXT_mmvec";
   32329 }
   32330 def V6_vlsrwv : HInst<
   32331 (outs HvxVR:$Vd32),
   32332 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32333 "$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
   32334 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   32335 let Inst{7-5} = 0b001;
   32336 let Inst{13-13} = 0b0;
   32337 let Inst{31-21} = 0b00011111101;
   32338 let hasNewValue = 1;
   32339 let opNewValue = 0;
   32340 let DecoderNamespace = "EXT_mmvec";
   32341 }
   32342 def V6_vlsrwv_alt : HInst<
   32343 (outs HvxVR:$Vd32),
   32344 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32345 "$Vd32 = vlsrw($Vu32,$Vv32)",
   32346 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32347 let hasNewValue = 1;
   32348 let opNewValue = 0;
   32349 let isPseudo = 1;
   32350 let isCodeGenOnly = 1;
   32351 let DecoderNamespace = "EXT_mmvec";
   32352 }
   32353 def V6_vlut4 : HInst<
   32354 (outs HvxVR:$Vd32),
   32355 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
   32356 "$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
   32357 tc_fa99dc24, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
   32358 let Inst{7-5} = 0b100;
   32359 let Inst{13-13} = 0b0;
   32360 let Inst{31-21} = 0b00011001011;
   32361 let hasNewValue = 1;
   32362 let opNewValue = 0;
   32363 let DecoderNamespace = "EXT_mmvec";
   32364 }
   32365 def V6_vlutvvb : HInst<
   32366 (outs HvxVR:$Vd32),
   32367 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32368 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
   32369 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
   32370 let Inst{7-5} = 0b001;
   32371 let Inst{13-13} = 0b1;
   32372 let Inst{31-24} = 0b00011011;
   32373 let hasNewValue = 1;
   32374 let opNewValue = 0;
   32375 let DecoderNamespace = "EXT_mmvec";
   32376 }
   32377 def V6_vlutvvb_nm : HInst<
   32378 (outs HvxVR:$Vd32),
   32379 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32380 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
   32381 tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
   32382 let Inst{7-5} = 0b011;
   32383 let Inst{13-13} = 0b0;
   32384 let Inst{31-24} = 0b00011000;
   32385 let hasNewValue = 1;
   32386 let opNewValue = 0;
   32387 let DecoderNamespace = "EXT_mmvec";
   32388 }
   32389 def V6_vlutvvb_oracc : HInst<
   32390 (outs HvxVR:$Vx32),
   32391 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32392 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
   32393 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
   32394 let Inst{7-5} = 0b101;
   32395 let Inst{13-13} = 0b1;
   32396 let Inst{31-24} = 0b00011011;
   32397 let hasNewValue = 1;
   32398 let opNewValue = 0;
   32399 let isAccumulator = 1;
   32400 let DecoderNamespace = "EXT_mmvec";
   32401 let Constraints = "$Vx32 = $Vx32in";
   32402 }
   32403 def V6_vlutvvb_oracci : HInst<
   32404 (outs HvxVR:$Vx32),
   32405 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   32406 "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
   32407 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
   32408 let Inst{13-13} = 0b1;
   32409 let Inst{31-21} = 0b00011100110;
   32410 let hasNewValue = 1;
   32411 let opNewValue = 0;
   32412 let isAccumulator = 1;
   32413 let DecoderNamespace = "EXT_mmvec";
   32414 let Constraints = "$Vx32 = $Vx32in";
   32415 }
   32416 def V6_vlutvvbi : HInst<
   32417 (outs HvxVR:$Vd32),
   32418 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   32419 "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
   32420 tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
   32421 let Inst{13-13} = 0b0;
   32422 let Inst{31-21} = 0b00011110001;
   32423 let hasNewValue = 1;
   32424 let opNewValue = 0;
   32425 let DecoderNamespace = "EXT_mmvec";
   32426 }
   32427 def V6_vlutvwh : HInst<
   32428 (outs HvxWR:$Vdd32),
   32429 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32430 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
   32431 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
   32432 let Inst{7-5} = 0b110;
   32433 let Inst{13-13} = 0b1;
   32434 let Inst{31-24} = 0b00011011;
   32435 let hasNewValue = 1;
   32436 let opNewValue = 0;
   32437 let DecoderNamespace = "EXT_mmvec";
   32438 }
   32439 def V6_vlutvwh_nm : HInst<
   32440 (outs HvxWR:$Vdd32),
   32441 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32442 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
   32443 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
   32444 let Inst{7-5} = 0b100;
   32445 let Inst{13-13} = 0b0;
   32446 let Inst{31-24} = 0b00011000;
   32447 let hasNewValue = 1;
   32448 let opNewValue = 0;
   32449 let DecoderNamespace = "EXT_mmvec";
   32450 }
   32451 def V6_vlutvwh_oracc : HInst<
   32452 (outs HvxWR:$Vxx32),
   32453 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   32454 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
   32455 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
   32456 let Inst{7-5} = 0b111;
   32457 let Inst{13-13} = 0b1;
   32458 let Inst{31-24} = 0b00011011;
   32459 let hasNewValue = 1;
   32460 let opNewValue = 0;
   32461 let isAccumulator = 1;
   32462 let DecoderNamespace = "EXT_mmvec";
   32463 let Constraints = "$Vxx32 = $Vxx32in";
   32464 }
   32465 def V6_vlutvwh_oracci : HInst<
   32466 (outs HvxWR:$Vxx32),
   32467 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   32468 "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
   32469 tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
   32470 let Inst{13-13} = 0b1;
   32471 let Inst{31-21} = 0b00011100111;
   32472 let hasNewValue = 1;
   32473 let opNewValue = 0;
   32474 let isAccumulator = 1;
   32475 let DecoderNamespace = "EXT_mmvec";
   32476 let Constraints = "$Vxx32 = $Vxx32in";
   32477 }
   32478 def V6_vlutvwhi : HInst<
   32479 (outs HvxWR:$Vdd32),
   32480 (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
   32481 "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
   32482 tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
   32483 let Inst{13-13} = 0b0;
   32484 let Inst{31-21} = 0b00011110011;
   32485 let hasNewValue = 1;
   32486 let opNewValue = 0;
   32487 let DecoderNamespace = "EXT_mmvec";
   32488 }
   32489 def V6_vmaxb : HInst<
   32490 (outs HvxVR:$Vd32),
   32491 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32492 "$Vd32.b = vmax($Vu32.b,$Vv32.b)",
   32493 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   32494 let Inst{7-5} = 0b101;
   32495 let Inst{13-13} = 0b0;
   32496 let Inst{31-21} = 0b00011111001;
   32497 let hasNewValue = 1;
   32498 let opNewValue = 0;
   32499 let DecoderNamespace = "EXT_mmvec";
   32500 }
   32501 def V6_vmaxb_alt : HInst<
   32502 (outs HvxVR:$Vd32),
   32503 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32504 "$Vd32 = vmaxb($Vu32,$Vv32)",
   32505 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   32506 let hasNewValue = 1;
   32507 let opNewValue = 0;
   32508 let isPseudo = 1;
   32509 let isCodeGenOnly = 1;
   32510 let DecoderNamespace = "EXT_mmvec";
   32511 }
   32512 def V6_vmaxh : HInst<
   32513 (outs HvxVR:$Vd32),
   32514 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32515 "$Vd32.h = vmax($Vu32.h,$Vv32.h)",
   32516 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32517 let Inst{7-5} = 0b111;
   32518 let Inst{13-13} = 0b0;
   32519 let Inst{31-21} = 0b00011111000;
   32520 let hasNewValue = 1;
   32521 let opNewValue = 0;
   32522 let DecoderNamespace = "EXT_mmvec";
   32523 }
   32524 def V6_vmaxh_alt : HInst<
   32525 (outs HvxVR:$Vd32),
   32526 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32527 "$Vd32 = vmaxh($Vu32,$Vv32)",
   32528 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32529 let hasNewValue = 1;
   32530 let opNewValue = 0;
   32531 let isPseudo = 1;
   32532 let isCodeGenOnly = 1;
   32533 let DecoderNamespace = "EXT_mmvec";
   32534 }
   32535 def V6_vmaxub : HInst<
   32536 (outs HvxVR:$Vd32),
   32537 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32538 "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
   32539 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32540 let Inst{7-5} = 0b101;
   32541 let Inst{13-13} = 0b0;
   32542 let Inst{31-21} = 0b00011111000;
   32543 let hasNewValue = 1;
   32544 let opNewValue = 0;
   32545 let DecoderNamespace = "EXT_mmvec";
   32546 }
   32547 def V6_vmaxub_alt : HInst<
   32548 (outs HvxVR:$Vd32),
   32549 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32550 "$Vd32 = vmaxub($Vu32,$Vv32)",
   32551 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32552 let hasNewValue = 1;
   32553 let opNewValue = 0;
   32554 let isPseudo = 1;
   32555 let isCodeGenOnly = 1;
   32556 let DecoderNamespace = "EXT_mmvec";
   32557 }
   32558 def V6_vmaxuh : HInst<
   32559 (outs HvxVR:$Vd32),
   32560 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32561 "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
   32562 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32563 let Inst{7-5} = 0b110;
   32564 let Inst{13-13} = 0b0;
   32565 let Inst{31-21} = 0b00011111000;
   32566 let hasNewValue = 1;
   32567 let opNewValue = 0;
   32568 let DecoderNamespace = "EXT_mmvec";
   32569 }
   32570 def V6_vmaxuh_alt : HInst<
   32571 (outs HvxVR:$Vd32),
   32572 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32573 "$Vd32 = vmaxuh($Vu32,$Vv32)",
   32574 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32575 let hasNewValue = 1;
   32576 let opNewValue = 0;
   32577 let isPseudo = 1;
   32578 let isCodeGenOnly = 1;
   32579 let DecoderNamespace = "EXT_mmvec";
   32580 }
   32581 def V6_vmaxw : HInst<
   32582 (outs HvxVR:$Vd32),
   32583 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32584 "$Vd32.w = vmax($Vu32.w,$Vv32.w)",
   32585 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32586 let Inst{7-5} = 0b000;
   32587 let Inst{13-13} = 0b0;
   32588 let Inst{31-21} = 0b00011111001;
   32589 let hasNewValue = 1;
   32590 let opNewValue = 0;
   32591 let DecoderNamespace = "EXT_mmvec";
   32592 }
   32593 def V6_vmaxw_alt : HInst<
   32594 (outs HvxVR:$Vd32),
   32595 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32596 "$Vd32 = vmaxw($Vu32,$Vv32)",
   32597 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32598 let hasNewValue = 1;
   32599 let opNewValue = 0;
   32600 let isPseudo = 1;
   32601 let isCodeGenOnly = 1;
   32602 let DecoderNamespace = "EXT_mmvec";
   32603 }
   32604 def V6_vminb : HInst<
   32605 (outs HvxVR:$Vd32),
   32606 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32607 "$Vd32.b = vmin($Vu32.b,$Vv32.b)",
   32608 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   32609 let Inst{7-5} = 0b100;
   32610 let Inst{13-13} = 0b0;
   32611 let Inst{31-21} = 0b00011111001;
   32612 let hasNewValue = 1;
   32613 let opNewValue = 0;
   32614 let DecoderNamespace = "EXT_mmvec";
   32615 }
   32616 def V6_vminb_alt : HInst<
   32617 (outs HvxVR:$Vd32),
   32618 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32619 "$Vd32 = vminb($Vu32,$Vv32)",
   32620 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   32621 let hasNewValue = 1;
   32622 let opNewValue = 0;
   32623 let isPseudo = 1;
   32624 let isCodeGenOnly = 1;
   32625 let DecoderNamespace = "EXT_mmvec";
   32626 }
   32627 def V6_vminh : HInst<
   32628 (outs HvxVR:$Vd32),
   32629 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32630 "$Vd32.h = vmin($Vu32.h,$Vv32.h)",
   32631 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32632 let Inst{7-5} = 0b011;
   32633 let Inst{13-13} = 0b0;
   32634 let Inst{31-21} = 0b00011111000;
   32635 let hasNewValue = 1;
   32636 let opNewValue = 0;
   32637 let DecoderNamespace = "EXT_mmvec";
   32638 }
   32639 def V6_vminh_alt : HInst<
   32640 (outs HvxVR:$Vd32),
   32641 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32642 "$Vd32 = vminh($Vu32,$Vv32)",
   32643 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32644 let hasNewValue = 1;
   32645 let opNewValue = 0;
   32646 let isPseudo = 1;
   32647 let isCodeGenOnly = 1;
   32648 let DecoderNamespace = "EXT_mmvec";
   32649 }
   32650 def V6_vminub : HInst<
   32651 (outs HvxVR:$Vd32),
   32652 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32653 "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
   32654 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32655 let Inst{7-5} = 0b001;
   32656 let Inst{13-13} = 0b0;
   32657 let Inst{31-21} = 0b00011111000;
   32658 let hasNewValue = 1;
   32659 let opNewValue = 0;
   32660 let DecoderNamespace = "EXT_mmvec";
   32661 }
   32662 def V6_vminub_alt : HInst<
   32663 (outs HvxVR:$Vd32),
   32664 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32665 "$Vd32 = vminub($Vu32,$Vv32)",
   32666 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32667 let hasNewValue = 1;
   32668 let opNewValue = 0;
   32669 let isPseudo = 1;
   32670 let isCodeGenOnly = 1;
   32671 let DecoderNamespace = "EXT_mmvec";
   32672 }
   32673 def V6_vminuh : HInst<
   32674 (outs HvxVR:$Vd32),
   32675 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32676 "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
   32677 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32678 let Inst{7-5} = 0b010;
   32679 let Inst{13-13} = 0b0;
   32680 let Inst{31-21} = 0b00011111000;
   32681 let hasNewValue = 1;
   32682 let opNewValue = 0;
   32683 let DecoderNamespace = "EXT_mmvec";
   32684 }
   32685 def V6_vminuh_alt : HInst<
   32686 (outs HvxVR:$Vd32),
   32687 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32688 "$Vd32 = vminuh($Vu32,$Vv32)",
   32689 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32690 let hasNewValue = 1;
   32691 let opNewValue = 0;
   32692 let isPseudo = 1;
   32693 let isCodeGenOnly = 1;
   32694 let DecoderNamespace = "EXT_mmvec";
   32695 }
   32696 def V6_vminw : HInst<
   32697 (outs HvxVR:$Vd32),
   32698 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32699 "$Vd32.w = vmin($Vu32.w,$Vv32.w)",
   32700 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   32701 let Inst{7-5} = 0b100;
   32702 let Inst{13-13} = 0b0;
   32703 let Inst{31-21} = 0b00011111000;
   32704 let hasNewValue = 1;
   32705 let opNewValue = 0;
   32706 let DecoderNamespace = "EXT_mmvec";
   32707 }
   32708 def V6_vminw_alt : HInst<
   32709 (outs HvxVR:$Vd32),
   32710 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   32711 "$Vd32 = vminw($Vu32,$Vv32)",
   32712 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32713 let hasNewValue = 1;
   32714 let opNewValue = 0;
   32715 let isPseudo = 1;
   32716 let isCodeGenOnly = 1;
   32717 let DecoderNamespace = "EXT_mmvec";
   32718 }
   32719 def V6_vmpabus : HInst<
   32720 (outs HvxWR:$Vdd32),
   32721 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32722 "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
   32723 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   32724 let Inst{7-5} = 0b110;
   32725 let Inst{13-13} = 0b0;
   32726 let Inst{31-21} = 0b00011001001;
   32727 let hasNewValue = 1;
   32728 let opNewValue = 0;
   32729 let DecoderNamespace = "EXT_mmvec";
   32730 }
   32731 def V6_vmpabus_acc : HInst<
   32732 (outs HvxWR:$Vxx32),
   32733 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32734 "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
   32735 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   32736 let Inst{7-5} = 0b110;
   32737 let Inst{13-13} = 0b1;
   32738 let Inst{31-21} = 0b00011001001;
   32739 let hasNewValue = 1;
   32740 let opNewValue = 0;
   32741 let isAccumulator = 1;
   32742 let DecoderNamespace = "EXT_mmvec";
   32743 let Constraints = "$Vxx32 = $Vxx32in";
   32744 }
   32745 def V6_vmpabus_acc_alt : HInst<
   32746 (outs HvxWR:$Vxx32),
   32747 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32748 "$Vxx32 += vmpabus($Vuu32,$Rt32)",
   32749 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32750 let hasNewValue = 1;
   32751 let opNewValue = 0;
   32752 let isAccumulator = 1;
   32753 let isPseudo = 1;
   32754 let isCodeGenOnly = 1;
   32755 let DecoderNamespace = "EXT_mmvec";
   32756 let Constraints = "$Vxx32 = $Vxx32in";
   32757 }
   32758 def V6_vmpabus_alt : HInst<
   32759 (outs HvxWR:$Vdd32),
   32760 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32761 "$Vdd32 = vmpabus($Vuu32,$Rt32)",
   32762 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32763 let hasNewValue = 1;
   32764 let opNewValue = 0;
   32765 let isPseudo = 1;
   32766 let isCodeGenOnly = 1;
   32767 let DecoderNamespace = "EXT_mmvec";
   32768 }
   32769 def V6_vmpabusv : HInst<
   32770 (outs HvxWR:$Vdd32),
   32771 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   32772 "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
   32773 tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   32774 let Inst{7-5} = 0b011;
   32775 let Inst{13-13} = 0b0;
   32776 let Inst{31-21} = 0b00011100001;
   32777 let hasNewValue = 1;
   32778 let opNewValue = 0;
   32779 let DecoderNamespace = "EXT_mmvec";
   32780 }
   32781 def V6_vmpabusv_alt : HInst<
   32782 (outs HvxWR:$Vdd32),
   32783 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   32784 "$Vdd32 = vmpabus($Vuu32,$Vvv32)",
   32785 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32786 let hasNewValue = 1;
   32787 let opNewValue = 0;
   32788 let isPseudo = 1;
   32789 let isCodeGenOnly = 1;
   32790 let DecoderNamespace = "EXT_mmvec";
   32791 }
   32792 def V6_vmpabuu : HInst<
   32793 (outs HvxWR:$Vdd32),
   32794 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32795 "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
   32796 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
   32797 let Inst{7-5} = 0b011;
   32798 let Inst{13-13} = 0b0;
   32799 let Inst{31-21} = 0b00011001011;
   32800 let hasNewValue = 1;
   32801 let opNewValue = 0;
   32802 let DecoderNamespace = "EXT_mmvec";
   32803 }
   32804 def V6_vmpabuu_acc : HInst<
   32805 (outs HvxWR:$Vxx32),
   32806 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32807 "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
   32808 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
   32809 let Inst{7-5} = 0b100;
   32810 let Inst{13-13} = 0b1;
   32811 let Inst{31-21} = 0b00011001101;
   32812 let hasNewValue = 1;
   32813 let opNewValue = 0;
   32814 let isAccumulator = 1;
   32815 let DecoderNamespace = "EXT_mmvec";
   32816 let Constraints = "$Vxx32 = $Vxx32in";
   32817 }
   32818 def V6_vmpabuu_acc_alt : HInst<
   32819 (outs HvxWR:$Vxx32),
   32820 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32821 "$Vxx32 += vmpabuu($Vuu32,$Rt32)",
   32822 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   32823 let hasNewValue = 1;
   32824 let opNewValue = 0;
   32825 let isAccumulator = 1;
   32826 let isPseudo = 1;
   32827 let isCodeGenOnly = 1;
   32828 let DecoderNamespace = "EXT_mmvec";
   32829 let Constraints = "$Vxx32 = $Vxx32in";
   32830 }
   32831 def V6_vmpabuu_alt : HInst<
   32832 (outs HvxWR:$Vdd32),
   32833 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32834 "$Vdd32 = vmpabuu($Vuu32,$Rt32)",
   32835 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   32836 let hasNewValue = 1;
   32837 let opNewValue = 0;
   32838 let isPseudo = 1;
   32839 let isCodeGenOnly = 1;
   32840 let DecoderNamespace = "EXT_mmvec";
   32841 }
   32842 def V6_vmpabuuv : HInst<
   32843 (outs HvxWR:$Vdd32),
   32844 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   32845 "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
   32846 tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   32847 let Inst{7-5} = 0b111;
   32848 let Inst{13-13} = 0b0;
   32849 let Inst{31-21} = 0b00011100111;
   32850 let hasNewValue = 1;
   32851 let opNewValue = 0;
   32852 let DecoderNamespace = "EXT_mmvec";
   32853 }
   32854 def V6_vmpabuuv_alt : HInst<
   32855 (outs HvxWR:$Vdd32),
   32856 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   32857 "$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
   32858 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32859 let hasNewValue = 1;
   32860 let opNewValue = 0;
   32861 let isPseudo = 1;
   32862 let isCodeGenOnly = 1;
   32863 let DecoderNamespace = "EXT_mmvec";
   32864 }
   32865 def V6_vmpahb : HInst<
   32866 (outs HvxWR:$Vdd32),
   32867 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32868 "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
   32869 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   32870 let Inst{7-5} = 0b111;
   32871 let Inst{13-13} = 0b0;
   32872 let Inst{31-21} = 0b00011001001;
   32873 let hasNewValue = 1;
   32874 let opNewValue = 0;
   32875 let DecoderNamespace = "EXT_mmvec";
   32876 }
   32877 def V6_vmpahb_acc : HInst<
   32878 (outs HvxWR:$Vxx32),
   32879 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32880 "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
   32881 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   32882 let Inst{7-5} = 0b111;
   32883 let Inst{13-13} = 0b1;
   32884 let Inst{31-21} = 0b00011001001;
   32885 let hasNewValue = 1;
   32886 let opNewValue = 0;
   32887 let isAccumulator = 1;
   32888 let DecoderNamespace = "EXT_mmvec";
   32889 let Constraints = "$Vxx32 = $Vxx32in";
   32890 }
   32891 def V6_vmpahb_acc_alt : HInst<
   32892 (outs HvxWR:$Vxx32),
   32893 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32894 "$Vxx32 += vmpahb($Vuu32,$Rt32)",
   32895 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32896 let hasNewValue = 1;
   32897 let opNewValue = 0;
   32898 let isAccumulator = 1;
   32899 let isPseudo = 1;
   32900 let isCodeGenOnly = 1;
   32901 let DecoderNamespace = "EXT_mmvec";
   32902 let Constraints = "$Vxx32 = $Vxx32in";
   32903 }
   32904 def V6_vmpahb_alt : HInst<
   32905 (outs HvxWR:$Vdd32),
   32906 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32907 "$Vdd32 = vmpahb($Vuu32,$Rt32)",
   32908 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   32909 let hasNewValue = 1;
   32910 let opNewValue = 0;
   32911 let isPseudo = 1;
   32912 let isCodeGenOnly = 1;
   32913 let DecoderNamespace = "EXT_mmvec";
   32914 }
   32915 def V6_vmpahhsat : HInst<
   32916 (outs HvxVR:$Vx32),
   32917 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   32918 "$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
   32919 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
   32920 let Inst{7-5} = 0b100;
   32921 let Inst{13-13} = 0b1;
   32922 let Inst{31-21} = 0b00011001100;
   32923 let hasNewValue = 1;
   32924 let opNewValue = 0;
   32925 let DecoderNamespace = "EXT_mmvec";
   32926 let Constraints = "$Vx32 = $Vx32in";
   32927 }
   32928 def V6_vmpauhb : HInst<
   32929 (outs HvxWR:$Vdd32),
   32930 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32931 "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
   32932 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
   32933 let Inst{7-5} = 0b101;
   32934 let Inst{13-13} = 0b0;
   32935 let Inst{31-21} = 0b00011001100;
   32936 let hasNewValue = 1;
   32937 let opNewValue = 0;
   32938 let DecoderNamespace = "EXT_mmvec";
   32939 }
   32940 def V6_vmpauhb_acc : HInst<
   32941 (outs HvxWR:$Vxx32),
   32942 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32943 "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
   32944 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
   32945 let Inst{7-5} = 0b010;
   32946 let Inst{13-13} = 0b1;
   32947 let Inst{31-21} = 0b00011001100;
   32948 let hasNewValue = 1;
   32949 let opNewValue = 0;
   32950 let isAccumulator = 1;
   32951 let DecoderNamespace = "EXT_mmvec";
   32952 let Constraints = "$Vxx32 = $Vxx32in";
   32953 }
   32954 def V6_vmpauhb_acc_alt : HInst<
   32955 (outs HvxWR:$Vxx32),
   32956 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   32957 "$Vxx32 += vmpauhb($Vuu32,$Rt32)",
   32958 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   32959 let hasNewValue = 1;
   32960 let opNewValue = 0;
   32961 let isAccumulator = 1;
   32962 let isPseudo = 1;
   32963 let isCodeGenOnly = 1;
   32964 let DecoderNamespace = "EXT_mmvec";
   32965 let Constraints = "$Vxx32 = $Vxx32in";
   32966 }
   32967 def V6_vmpauhb_alt : HInst<
   32968 (outs HvxWR:$Vdd32),
   32969 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   32970 "$Vdd32 = vmpauhb($Vuu32,$Rt32)",
   32971 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   32972 let hasNewValue = 1;
   32973 let opNewValue = 0;
   32974 let isPseudo = 1;
   32975 let isCodeGenOnly = 1;
   32976 let DecoderNamespace = "EXT_mmvec";
   32977 }
   32978 def V6_vmpauhuhsat : HInst<
   32979 (outs HvxVR:$Vx32),
   32980 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   32981 "$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
   32982 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
   32983 let Inst{7-5} = 0b101;
   32984 let Inst{13-13} = 0b1;
   32985 let Inst{31-21} = 0b00011001100;
   32986 let hasNewValue = 1;
   32987 let opNewValue = 0;
   32988 let DecoderNamespace = "EXT_mmvec";
   32989 let Constraints = "$Vx32 = $Vx32in";
   32990 }
   32991 def V6_vmpsuhuhsat : HInst<
   32992 (outs HvxVR:$Vx32),
   32993 (ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   32994 "$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
   32995 tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
   32996 let Inst{7-5} = 0b110;
   32997 let Inst{13-13} = 0b1;
   32998 let Inst{31-21} = 0b00011001100;
   32999 let hasNewValue = 1;
   33000 let opNewValue = 0;
   33001 let DecoderNamespace = "EXT_mmvec";
   33002 let Constraints = "$Vx32 = $Vx32in";
   33003 }
   33004 def V6_vmpybus : HInst<
   33005 (outs HvxWR:$Vdd32),
   33006 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33007 "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
   33008 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
   33009 let Inst{7-5} = 0b101;
   33010 let Inst{13-13} = 0b0;
   33011 let Inst{31-21} = 0b00011001001;
   33012 let hasNewValue = 1;
   33013 let opNewValue = 0;
   33014 let DecoderNamespace = "EXT_mmvec";
   33015 }
   33016 def V6_vmpybus_acc : HInst<
   33017 (outs HvxWR:$Vxx32),
   33018 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33019 "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
   33020 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
   33021 let Inst{7-5} = 0b101;
   33022 let Inst{13-13} = 0b1;
   33023 let Inst{31-21} = 0b00011001001;
   33024 let hasNewValue = 1;
   33025 let opNewValue = 0;
   33026 let isAccumulator = 1;
   33027 let DecoderNamespace = "EXT_mmvec";
   33028 let Constraints = "$Vxx32 = $Vxx32in";
   33029 }
   33030 def V6_vmpybus_acc_alt : HInst<
   33031 (outs HvxWR:$Vxx32),
   33032 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33033 "$Vxx32 += vmpybus($Vu32,$Rt32)",
   33034 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33035 let hasNewValue = 1;
   33036 let opNewValue = 0;
   33037 let isAccumulator = 1;
   33038 let isPseudo = 1;
   33039 let isCodeGenOnly = 1;
   33040 let DecoderNamespace = "EXT_mmvec";
   33041 let Constraints = "$Vxx32 = $Vxx32in";
   33042 }
   33043 def V6_vmpybus_alt : HInst<
   33044 (outs HvxWR:$Vdd32),
   33045 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33046 "$Vdd32 = vmpybus($Vu32,$Rt32)",
   33047 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33048 let hasNewValue = 1;
   33049 let opNewValue = 0;
   33050 let isPseudo = 1;
   33051 let isCodeGenOnly = 1;
   33052 let DecoderNamespace = "EXT_mmvec";
   33053 }
   33054 def V6_vmpybusv : HInst<
   33055 (outs HvxWR:$Vdd32),
   33056 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33057 "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
   33058 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   33059 let Inst{7-5} = 0b110;
   33060 let Inst{13-13} = 0b0;
   33061 let Inst{31-21} = 0b00011100000;
   33062 let hasNewValue = 1;
   33063 let opNewValue = 0;
   33064 let DecoderNamespace = "EXT_mmvec";
   33065 }
   33066 def V6_vmpybusv_acc : HInst<
   33067 (outs HvxWR:$Vxx32),
   33068 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33069 "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
   33070 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   33071 let Inst{7-5} = 0b110;
   33072 let Inst{13-13} = 0b1;
   33073 let Inst{31-21} = 0b00011100000;
   33074 let hasNewValue = 1;
   33075 let opNewValue = 0;
   33076 let isAccumulator = 1;
   33077 let DecoderNamespace = "EXT_mmvec";
   33078 let Constraints = "$Vxx32 = $Vxx32in";
   33079 }
   33080 def V6_vmpybusv_acc_alt : HInst<
   33081 (outs HvxWR:$Vxx32),
   33082 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33083 "$Vxx32 += vmpybus($Vu32,$Vv32)",
   33084 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33085 let hasNewValue = 1;
   33086 let opNewValue = 0;
   33087 let isAccumulator = 1;
   33088 let isPseudo = 1;
   33089 let isCodeGenOnly = 1;
   33090 let DecoderNamespace = "EXT_mmvec";
   33091 let Constraints = "$Vxx32 = $Vxx32in";
   33092 }
   33093 def V6_vmpybusv_alt : HInst<
   33094 (outs HvxWR:$Vdd32),
   33095 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33096 "$Vdd32 = vmpybus($Vu32,$Vv32)",
   33097 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33098 let hasNewValue = 1;
   33099 let opNewValue = 0;
   33100 let isPseudo = 1;
   33101 let isCodeGenOnly = 1;
   33102 let DecoderNamespace = "EXT_mmvec";
   33103 }
   33104 def V6_vmpybv : HInst<
   33105 (outs HvxWR:$Vdd32),
   33106 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33107 "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
   33108 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   33109 let Inst{7-5} = 0b100;
   33110 let Inst{13-13} = 0b0;
   33111 let Inst{31-21} = 0b00011100000;
   33112 let hasNewValue = 1;
   33113 let opNewValue = 0;
   33114 let DecoderNamespace = "EXT_mmvec";
   33115 }
   33116 def V6_vmpybv_acc : HInst<
   33117 (outs HvxWR:$Vxx32),
   33118 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33119 "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
   33120 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   33121 let Inst{7-5} = 0b100;
   33122 let Inst{13-13} = 0b1;
   33123 let Inst{31-21} = 0b00011100000;
   33124 let hasNewValue = 1;
   33125 let opNewValue = 0;
   33126 let isAccumulator = 1;
   33127 let DecoderNamespace = "EXT_mmvec";
   33128 let Constraints = "$Vxx32 = $Vxx32in";
   33129 }
   33130 def V6_vmpybv_acc_alt : HInst<
   33131 (outs HvxWR:$Vxx32),
   33132 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33133 "$Vxx32 += vmpyb($Vu32,$Vv32)",
   33134 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33135 let hasNewValue = 1;
   33136 let opNewValue = 0;
   33137 let isAccumulator = 1;
   33138 let isPseudo = 1;
   33139 let isCodeGenOnly = 1;
   33140 let DecoderNamespace = "EXT_mmvec";
   33141 let Constraints = "$Vxx32 = $Vxx32in";
   33142 }
   33143 def V6_vmpybv_alt : HInst<
   33144 (outs HvxWR:$Vdd32),
   33145 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33146 "$Vdd32 = vmpyb($Vu32,$Vv32)",
   33147 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33148 let hasNewValue = 1;
   33149 let opNewValue = 0;
   33150 let isPseudo = 1;
   33151 let isCodeGenOnly = 1;
   33152 let DecoderNamespace = "EXT_mmvec";
   33153 }
   33154 def V6_vmpyewuh : HInst<
   33155 (outs HvxVR:$Vd32),
   33156 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33157 "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
   33158 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33159 let Inst{7-5} = 0b101;
   33160 let Inst{13-13} = 0b0;
   33161 let Inst{31-21} = 0b00011111111;
   33162 let hasNewValue = 1;
   33163 let opNewValue = 0;
   33164 let DecoderNamespace = "EXT_mmvec";
   33165 }
   33166 def V6_vmpyewuh_64 : HInst<
   33167 (outs HvxWR:$Vdd32),
   33168 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33169 "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
   33170 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
   33171 let Inst{7-5} = 0b110;
   33172 let Inst{13-13} = 0b0;
   33173 let Inst{31-21} = 0b00011110101;
   33174 let hasNewValue = 1;
   33175 let opNewValue = 0;
   33176 let DecoderNamespace = "EXT_mmvec";
   33177 }
   33178 def V6_vmpyewuh_alt : HInst<
   33179 (outs HvxVR:$Vd32),
   33180 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33181 "$Vd32 = vmpyewuh($Vu32,$Vv32)",
   33182 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33183 let hasNewValue = 1;
   33184 let opNewValue = 0;
   33185 let isPseudo = 1;
   33186 let isCodeGenOnly = 1;
   33187 let DecoderNamespace = "EXT_mmvec";
   33188 }
   33189 def V6_vmpyh : HInst<
   33190 (outs HvxWR:$Vdd32),
   33191 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33192 "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
   33193 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
   33194 let Inst{7-5} = 0b000;
   33195 let Inst{13-13} = 0b0;
   33196 let Inst{31-21} = 0b00011001010;
   33197 let hasNewValue = 1;
   33198 let opNewValue = 0;
   33199 let DecoderNamespace = "EXT_mmvec";
   33200 }
   33201 def V6_vmpyh_acc : HInst<
   33202 (outs HvxWR:$Vxx32),
   33203 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33204 "$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
   33205 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
   33206 let Inst{7-5} = 0b110;
   33207 let Inst{13-13} = 0b1;
   33208 let Inst{31-21} = 0b00011001101;
   33209 let hasNewValue = 1;
   33210 let opNewValue = 0;
   33211 let isAccumulator = 1;
   33212 let DecoderNamespace = "EXT_mmvec";
   33213 let Constraints = "$Vxx32 = $Vxx32in";
   33214 }
   33215 def V6_vmpyh_acc_alt : HInst<
   33216 (outs HvxWR:$Vxx32),
   33217 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33218 "$Vxx32 += vmpyh($Vu32,$Rt32)",
   33219 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   33220 let hasNewValue = 1;
   33221 let opNewValue = 0;
   33222 let isAccumulator = 1;
   33223 let isPseudo = 1;
   33224 let isCodeGenOnly = 1;
   33225 let DecoderNamespace = "EXT_mmvec";
   33226 let Constraints = "$Vxx32 = $Vxx32in";
   33227 }
   33228 def V6_vmpyh_alt : HInst<
   33229 (outs HvxWR:$Vdd32),
   33230 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33231 "$Vdd32 = vmpyh($Vu32,$Rt32)",
   33232 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33233 let hasNewValue = 1;
   33234 let opNewValue = 0;
   33235 let isPseudo = 1;
   33236 let isCodeGenOnly = 1;
   33237 let DecoderNamespace = "EXT_mmvec";
   33238 }
   33239 def V6_vmpyhsat_acc : HInst<
   33240 (outs HvxWR:$Vxx32),
   33241 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33242 "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
   33243 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
   33244 let Inst{7-5} = 0b000;
   33245 let Inst{13-13} = 0b1;
   33246 let Inst{31-21} = 0b00011001010;
   33247 let hasNewValue = 1;
   33248 let opNewValue = 0;
   33249 let isAccumulator = 1;
   33250 let DecoderNamespace = "EXT_mmvec";
   33251 let Constraints = "$Vxx32 = $Vxx32in";
   33252 }
   33253 def V6_vmpyhsat_acc_alt : HInst<
   33254 (outs HvxWR:$Vxx32),
   33255 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33256 "$Vxx32 += vmpyh($Vu32,$Rt32):sat",
   33257 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33258 let hasNewValue = 1;
   33259 let opNewValue = 0;
   33260 let isAccumulator = 1;
   33261 let isPseudo = 1;
   33262 let isCodeGenOnly = 1;
   33263 let DecoderNamespace = "EXT_mmvec";
   33264 let Constraints = "$Vxx32 = $Vxx32in";
   33265 }
   33266 def V6_vmpyhsrs : HInst<
   33267 (outs HvxVR:$Vd32),
   33268 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33269 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
   33270 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
   33271 let Inst{7-5} = 0b010;
   33272 let Inst{13-13} = 0b0;
   33273 let Inst{31-21} = 0b00011001010;
   33274 let hasNewValue = 1;
   33275 let opNewValue = 0;
   33276 let DecoderNamespace = "EXT_mmvec";
   33277 }
   33278 def V6_vmpyhsrs_alt : HInst<
   33279 (outs HvxVR:$Vd32),
   33280 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33281 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
   33282 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33283 let hasNewValue = 1;
   33284 let opNewValue = 0;
   33285 let isPseudo = 1;
   33286 let isCodeGenOnly = 1;
   33287 let DecoderNamespace = "EXT_mmvec";
   33288 }
   33289 def V6_vmpyhss : HInst<
   33290 (outs HvxVR:$Vd32),
   33291 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33292 "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
   33293 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
   33294 let Inst{7-5} = 0b001;
   33295 let Inst{13-13} = 0b0;
   33296 let Inst{31-21} = 0b00011001010;
   33297 let hasNewValue = 1;
   33298 let opNewValue = 0;
   33299 let DecoderNamespace = "EXT_mmvec";
   33300 }
   33301 def V6_vmpyhss_alt : HInst<
   33302 (outs HvxVR:$Vd32),
   33303 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33304 "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
   33305 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33306 let hasNewValue = 1;
   33307 let opNewValue = 0;
   33308 let isPseudo = 1;
   33309 let isCodeGenOnly = 1;
   33310 let DecoderNamespace = "EXT_mmvec";
   33311 }
   33312 def V6_vmpyhus : HInst<
   33313 (outs HvxWR:$Vdd32),
   33314 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33315 "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
   33316 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   33317 let Inst{7-5} = 0b010;
   33318 let Inst{13-13} = 0b0;
   33319 let Inst{31-21} = 0b00011100001;
   33320 let hasNewValue = 1;
   33321 let opNewValue = 0;
   33322 let DecoderNamespace = "EXT_mmvec";
   33323 }
   33324 def V6_vmpyhus_acc : HInst<
   33325 (outs HvxWR:$Vxx32),
   33326 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33327 "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
   33328 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   33329 let Inst{7-5} = 0b001;
   33330 let Inst{13-13} = 0b1;
   33331 let Inst{31-21} = 0b00011100001;
   33332 let hasNewValue = 1;
   33333 let opNewValue = 0;
   33334 let isAccumulator = 1;
   33335 let DecoderNamespace = "EXT_mmvec";
   33336 let Constraints = "$Vxx32 = $Vxx32in";
   33337 }
   33338 def V6_vmpyhus_acc_alt : HInst<
   33339 (outs HvxWR:$Vxx32),
   33340 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33341 "$Vxx32 += vmpyhus($Vu32,$Vv32)",
   33342 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33343 let hasNewValue = 1;
   33344 let opNewValue = 0;
   33345 let isAccumulator = 1;
   33346 let isPseudo = 1;
   33347 let isCodeGenOnly = 1;
   33348 let DecoderNamespace = "EXT_mmvec";
   33349 let Constraints = "$Vxx32 = $Vxx32in";
   33350 }
   33351 def V6_vmpyhus_alt : HInst<
   33352 (outs HvxWR:$Vdd32),
   33353 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33354 "$Vdd32 = vmpyhus($Vu32,$Vv32)",
   33355 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33356 let hasNewValue = 1;
   33357 let opNewValue = 0;
   33358 let isPseudo = 1;
   33359 let isCodeGenOnly = 1;
   33360 let DecoderNamespace = "EXT_mmvec";
   33361 }
   33362 def V6_vmpyhv : HInst<
   33363 (outs HvxWR:$Vdd32),
   33364 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33365 "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
   33366 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   33367 let Inst{7-5} = 0b111;
   33368 let Inst{13-13} = 0b0;
   33369 let Inst{31-21} = 0b00011100000;
   33370 let hasNewValue = 1;
   33371 let opNewValue = 0;
   33372 let DecoderNamespace = "EXT_mmvec";
   33373 }
   33374 def V6_vmpyhv_acc : HInst<
   33375 (outs HvxWR:$Vxx32),
   33376 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33377 "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
   33378 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   33379 let Inst{7-5} = 0b111;
   33380 let Inst{13-13} = 0b1;
   33381 let Inst{31-21} = 0b00011100000;
   33382 let hasNewValue = 1;
   33383 let opNewValue = 0;
   33384 let isAccumulator = 1;
   33385 let DecoderNamespace = "EXT_mmvec";
   33386 let Constraints = "$Vxx32 = $Vxx32in";
   33387 }
   33388 def V6_vmpyhv_acc_alt : HInst<
   33389 (outs HvxWR:$Vxx32),
   33390 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33391 "$Vxx32 += vmpyh($Vu32,$Vv32)",
   33392 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33393 let hasNewValue = 1;
   33394 let opNewValue = 0;
   33395 let isAccumulator = 1;
   33396 let isPseudo = 1;
   33397 let isCodeGenOnly = 1;
   33398 let DecoderNamespace = "EXT_mmvec";
   33399 let Constraints = "$Vxx32 = $Vxx32in";
   33400 }
   33401 def V6_vmpyhv_alt : HInst<
   33402 (outs HvxWR:$Vdd32),
   33403 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33404 "$Vdd32 = vmpyh($Vu32,$Vv32)",
   33405 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33406 let hasNewValue = 1;
   33407 let opNewValue = 0;
   33408 let isPseudo = 1;
   33409 let isCodeGenOnly = 1;
   33410 let DecoderNamespace = "EXT_mmvec";
   33411 }
   33412 def V6_vmpyhvsrs : HInst<
   33413 (outs HvxVR:$Vd32),
   33414 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33415 "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
   33416 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33417 let Inst{7-5} = 0b001;
   33418 let Inst{13-13} = 0b0;
   33419 let Inst{31-21} = 0b00011100001;
   33420 let hasNewValue = 1;
   33421 let opNewValue = 0;
   33422 let DecoderNamespace = "EXT_mmvec";
   33423 }
   33424 def V6_vmpyhvsrs_alt : HInst<
   33425 (outs HvxVR:$Vd32),
   33426 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33427 "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
   33428 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33429 let hasNewValue = 1;
   33430 let opNewValue = 0;
   33431 let isPseudo = 1;
   33432 let isCodeGenOnly = 1;
   33433 let DecoderNamespace = "EXT_mmvec";
   33434 }
   33435 def V6_vmpyieoh : HInst<
   33436 (outs HvxVR:$Vd32),
   33437 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33438 "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
   33439 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   33440 let Inst{7-5} = 0b000;
   33441 let Inst{13-13} = 0b0;
   33442 let Inst{31-21} = 0b00011111011;
   33443 let hasNewValue = 1;
   33444 let opNewValue = 0;
   33445 let DecoderNamespace = "EXT_mmvec";
   33446 }
   33447 def V6_vmpyiewh_acc : HInst<
   33448 (outs HvxVR:$Vx32),
   33449 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33450 "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
   33451 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   33452 let Inst{7-5} = 0b000;
   33453 let Inst{13-13} = 0b1;
   33454 let Inst{31-21} = 0b00011100010;
   33455 let hasNewValue = 1;
   33456 let opNewValue = 0;
   33457 let isAccumulator = 1;
   33458 let DecoderNamespace = "EXT_mmvec";
   33459 let Constraints = "$Vx32 = $Vx32in";
   33460 }
   33461 def V6_vmpyiewh_acc_alt : HInst<
   33462 (outs HvxVR:$Vx32),
   33463 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33464 "$Vx32 += vmpyiewh($Vu32,$Vv32)",
   33465 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33466 let hasNewValue = 1;
   33467 let opNewValue = 0;
   33468 let isAccumulator = 1;
   33469 let isPseudo = 1;
   33470 let isCodeGenOnly = 1;
   33471 let DecoderNamespace = "EXT_mmvec";
   33472 let Constraints = "$Vx32 = $Vx32in";
   33473 }
   33474 def V6_vmpyiewuh : HInst<
   33475 (outs HvxVR:$Vd32),
   33476 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33477 "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
   33478 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33479 let Inst{7-5} = 0b000;
   33480 let Inst{13-13} = 0b0;
   33481 let Inst{31-21} = 0b00011111110;
   33482 let hasNewValue = 1;
   33483 let opNewValue = 0;
   33484 let DecoderNamespace = "EXT_mmvec";
   33485 }
   33486 def V6_vmpyiewuh_acc : HInst<
   33487 (outs HvxVR:$Vx32),
   33488 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33489 "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
   33490 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   33491 let Inst{7-5} = 0b101;
   33492 let Inst{13-13} = 0b1;
   33493 let Inst{31-21} = 0b00011100001;
   33494 let hasNewValue = 1;
   33495 let opNewValue = 0;
   33496 let isAccumulator = 1;
   33497 let DecoderNamespace = "EXT_mmvec";
   33498 let Constraints = "$Vx32 = $Vx32in";
   33499 }
   33500 def V6_vmpyiewuh_acc_alt : HInst<
   33501 (outs HvxVR:$Vx32),
   33502 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33503 "$Vx32 += vmpyiewuh($Vu32,$Vv32)",
   33504 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33505 let hasNewValue = 1;
   33506 let opNewValue = 0;
   33507 let isAccumulator = 1;
   33508 let isPseudo = 1;
   33509 let isCodeGenOnly = 1;
   33510 let DecoderNamespace = "EXT_mmvec";
   33511 let Constraints = "$Vx32 = $Vx32in";
   33512 }
   33513 def V6_vmpyiewuh_alt : HInst<
   33514 (outs HvxVR:$Vd32),
   33515 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33516 "$Vd32 = vmpyiewuh($Vu32,$Vv32)",
   33517 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33518 let hasNewValue = 1;
   33519 let opNewValue = 0;
   33520 let isPseudo = 1;
   33521 let isCodeGenOnly = 1;
   33522 let DecoderNamespace = "EXT_mmvec";
   33523 }
   33524 def V6_vmpyih : HInst<
   33525 (outs HvxVR:$Vd32),
   33526 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33527 "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
   33528 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33529 let Inst{7-5} = 0b100;
   33530 let Inst{13-13} = 0b0;
   33531 let Inst{31-21} = 0b00011100001;
   33532 let hasNewValue = 1;
   33533 let opNewValue = 0;
   33534 let DecoderNamespace = "EXT_mmvec";
   33535 }
   33536 def V6_vmpyih_acc : HInst<
   33537 (outs HvxVR:$Vx32),
   33538 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33539 "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
   33540 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   33541 let Inst{7-5} = 0b100;
   33542 let Inst{13-13} = 0b1;
   33543 let Inst{31-21} = 0b00011100001;
   33544 let hasNewValue = 1;
   33545 let opNewValue = 0;
   33546 let isAccumulator = 1;
   33547 let DecoderNamespace = "EXT_mmvec";
   33548 let Constraints = "$Vx32 = $Vx32in";
   33549 }
   33550 def V6_vmpyih_acc_alt : HInst<
   33551 (outs HvxVR:$Vx32),
   33552 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33553 "$Vx32 += vmpyih($Vu32,$Vv32)",
   33554 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33555 let hasNewValue = 1;
   33556 let opNewValue = 0;
   33557 let isAccumulator = 1;
   33558 let isPseudo = 1;
   33559 let isCodeGenOnly = 1;
   33560 let DecoderNamespace = "EXT_mmvec";
   33561 let Constraints = "$Vx32 = $Vx32in";
   33562 }
   33563 def V6_vmpyih_alt : HInst<
   33564 (outs HvxVR:$Vd32),
   33565 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33566 "$Vd32 = vmpyih($Vu32,$Vv32)",
   33567 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33568 let hasNewValue = 1;
   33569 let opNewValue = 0;
   33570 let isPseudo = 1;
   33571 let isCodeGenOnly = 1;
   33572 let DecoderNamespace = "EXT_mmvec";
   33573 }
   33574 def V6_vmpyihb : HInst<
   33575 (outs HvxVR:$Vd32),
   33576 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33577 "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
   33578 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   33579 let Inst{7-5} = 0b000;
   33580 let Inst{13-13} = 0b0;
   33581 let Inst{31-21} = 0b00011001011;
   33582 let hasNewValue = 1;
   33583 let opNewValue = 0;
   33584 let DecoderNamespace = "EXT_mmvec";
   33585 }
   33586 def V6_vmpyihb_acc : HInst<
   33587 (outs HvxVR:$Vx32),
   33588 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33589 "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
   33590 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   33591 let Inst{7-5} = 0b001;
   33592 let Inst{13-13} = 0b1;
   33593 let Inst{31-21} = 0b00011001011;
   33594 let hasNewValue = 1;
   33595 let opNewValue = 0;
   33596 let isAccumulator = 1;
   33597 let DecoderNamespace = "EXT_mmvec";
   33598 let Constraints = "$Vx32 = $Vx32in";
   33599 }
   33600 def V6_vmpyihb_acc_alt : HInst<
   33601 (outs HvxVR:$Vx32),
   33602 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33603 "$Vx32 += vmpyihb($Vu32,$Rt32)",
   33604 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33605 let hasNewValue = 1;
   33606 let opNewValue = 0;
   33607 let isAccumulator = 1;
   33608 let isPseudo = 1;
   33609 let isCodeGenOnly = 1;
   33610 let DecoderNamespace = "EXT_mmvec";
   33611 let Constraints = "$Vx32 = $Vx32in";
   33612 }
   33613 def V6_vmpyihb_alt : HInst<
   33614 (outs HvxVR:$Vd32),
   33615 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33616 "$Vd32 = vmpyihb($Vu32,$Rt32)",
   33617 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33618 let hasNewValue = 1;
   33619 let opNewValue = 0;
   33620 let isPseudo = 1;
   33621 let isCodeGenOnly = 1;
   33622 let DecoderNamespace = "EXT_mmvec";
   33623 }
   33624 def V6_vmpyiowh : HInst<
   33625 (outs HvxVR:$Vd32),
   33626 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33627 "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
   33628 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33629 let Inst{7-5} = 0b001;
   33630 let Inst{13-13} = 0b0;
   33631 let Inst{31-21} = 0b00011111110;
   33632 let hasNewValue = 1;
   33633 let opNewValue = 0;
   33634 let DecoderNamespace = "EXT_mmvec";
   33635 }
   33636 def V6_vmpyiowh_alt : HInst<
   33637 (outs HvxVR:$Vd32),
   33638 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33639 "$Vd32 = vmpyiowh($Vu32,$Vv32)",
   33640 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33641 let hasNewValue = 1;
   33642 let opNewValue = 0;
   33643 let isPseudo = 1;
   33644 let isCodeGenOnly = 1;
   33645 let DecoderNamespace = "EXT_mmvec";
   33646 }
   33647 def V6_vmpyiwb : HInst<
   33648 (outs HvxVR:$Vd32),
   33649 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33650 "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
   33651 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   33652 let Inst{7-5} = 0b000;
   33653 let Inst{13-13} = 0b0;
   33654 let Inst{31-21} = 0b00011001101;
   33655 let hasNewValue = 1;
   33656 let opNewValue = 0;
   33657 let DecoderNamespace = "EXT_mmvec";
   33658 }
   33659 def V6_vmpyiwb_acc : HInst<
   33660 (outs HvxVR:$Vx32),
   33661 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33662 "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
   33663 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   33664 let Inst{7-5} = 0b010;
   33665 let Inst{13-13} = 0b1;
   33666 let Inst{31-21} = 0b00011001010;
   33667 let hasNewValue = 1;
   33668 let opNewValue = 0;
   33669 let isAccumulator = 1;
   33670 let DecoderNamespace = "EXT_mmvec";
   33671 let Constraints = "$Vx32 = $Vx32in";
   33672 }
   33673 def V6_vmpyiwb_acc_alt : HInst<
   33674 (outs HvxVR:$Vx32),
   33675 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33676 "$Vx32 += vmpyiwb($Vu32,$Rt32)",
   33677 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33678 let hasNewValue = 1;
   33679 let opNewValue = 0;
   33680 let isAccumulator = 1;
   33681 let isPseudo = 1;
   33682 let isCodeGenOnly = 1;
   33683 let DecoderNamespace = "EXT_mmvec";
   33684 let Constraints = "$Vx32 = $Vx32in";
   33685 }
   33686 def V6_vmpyiwb_alt : HInst<
   33687 (outs HvxVR:$Vd32),
   33688 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33689 "$Vd32 = vmpyiwb($Vu32,$Rt32)",
   33690 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33691 let hasNewValue = 1;
   33692 let opNewValue = 0;
   33693 let isPseudo = 1;
   33694 let isCodeGenOnly = 1;
   33695 let DecoderNamespace = "EXT_mmvec";
   33696 }
   33697 def V6_vmpyiwh : HInst<
   33698 (outs HvxVR:$Vd32),
   33699 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33700 "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
   33701 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
   33702 let Inst{7-5} = 0b111;
   33703 let Inst{13-13} = 0b0;
   33704 let Inst{31-21} = 0b00011001100;
   33705 let hasNewValue = 1;
   33706 let opNewValue = 0;
   33707 let DecoderNamespace = "EXT_mmvec";
   33708 }
   33709 def V6_vmpyiwh_acc : HInst<
   33710 (outs HvxVR:$Vx32),
   33711 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33712 "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
   33713 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
   33714 let Inst{7-5} = 0b011;
   33715 let Inst{13-13} = 0b1;
   33716 let Inst{31-21} = 0b00011001010;
   33717 let hasNewValue = 1;
   33718 let opNewValue = 0;
   33719 let isAccumulator = 1;
   33720 let DecoderNamespace = "EXT_mmvec";
   33721 let Constraints = "$Vx32 = $Vx32in";
   33722 }
   33723 def V6_vmpyiwh_acc_alt : HInst<
   33724 (outs HvxVR:$Vx32),
   33725 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33726 "$Vx32 += vmpyiwh($Vu32,$Rt32)",
   33727 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33728 let hasNewValue = 1;
   33729 let opNewValue = 0;
   33730 let isAccumulator = 1;
   33731 let isPseudo = 1;
   33732 let isCodeGenOnly = 1;
   33733 let DecoderNamespace = "EXT_mmvec";
   33734 let Constraints = "$Vx32 = $Vx32in";
   33735 }
   33736 def V6_vmpyiwh_alt : HInst<
   33737 (outs HvxVR:$Vd32),
   33738 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33739 "$Vd32 = vmpyiwh($Vu32,$Rt32)",
   33740 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33741 let hasNewValue = 1;
   33742 let opNewValue = 0;
   33743 let isPseudo = 1;
   33744 let isCodeGenOnly = 1;
   33745 let DecoderNamespace = "EXT_mmvec";
   33746 }
   33747 def V6_vmpyiwub : HInst<
   33748 (outs HvxVR:$Vd32),
   33749 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33750 "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
   33751 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
   33752 let Inst{7-5} = 0b110;
   33753 let Inst{13-13} = 0b0;
   33754 let Inst{31-21} = 0b00011001100;
   33755 let hasNewValue = 1;
   33756 let opNewValue = 0;
   33757 let DecoderNamespace = "EXT_mmvec";
   33758 }
   33759 def V6_vmpyiwub_acc : HInst<
   33760 (outs HvxVR:$Vx32),
   33761 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33762 "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
   33763 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
   33764 let Inst{7-5} = 0b001;
   33765 let Inst{13-13} = 0b1;
   33766 let Inst{31-21} = 0b00011001100;
   33767 let hasNewValue = 1;
   33768 let opNewValue = 0;
   33769 let isAccumulator = 1;
   33770 let DecoderNamespace = "EXT_mmvec";
   33771 let Constraints = "$Vx32 = $Vx32in";
   33772 }
   33773 def V6_vmpyiwub_acc_alt : HInst<
   33774 (outs HvxVR:$Vx32),
   33775 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33776 "$Vx32 += vmpyiwub($Vu32,$Rt32)",
   33777 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   33778 let hasNewValue = 1;
   33779 let opNewValue = 0;
   33780 let isAccumulator = 1;
   33781 let isPseudo = 1;
   33782 let isCodeGenOnly = 1;
   33783 let DecoderNamespace = "EXT_mmvec";
   33784 let Constraints = "$Vx32 = $Vx32in";
   33785 }
   33786 def V6_vmpyiwub_alt : HInst<
   33787 (outs HvxVR:$Vd32),
   33788 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33789 "$Vd32 = vmpyiwub($Vu32,$Rt32)",
   33790 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   33791 let hasNewValue = 1;
   33792 let opNewValue = 0;
   33793 let isPseudo = 1;
   33794 let isCodeGenOnly = 1;
   33795 let DecoderNamespace = "EXT_mmvec";
   33796 }
   33797 def V6_vmpyowh : HInst<
   33798 (outs HvxVR:$Vd32),
   33799 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33800 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
   33801 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33802 let Inst{7-5} = 0b111;
   33803 let Inst{13-13} = 0b0;
   33804 let Inst{31-21} = 0b00011111111;
   33805 let hasNewValue = 1;
   33806 let opNewValue = 0;
   33807 let DecoderNamespace = "EXT_mmvec";
   33808 }
   33809 def V6_vmpyowh_64_acc : HInst<
   33810 (outs HvxWR:$Vxx32),
   33811 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33812 "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
   33813 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
   33814 let Inst{7-5} = 0b011;
   33815 let Inst{13-13} = 0b1;
   33816 let Inst{31-21} = 0b00011100001;
   33817 let hasNewValue = 1;
   33818 let opNewValue = 0;
   33819 let isAccumulator = 1;
   33820 let DecoderNamespace = "EXT_mmvec";
   33821 let Constraints = "$Vxx32 = $Vxx32in";
   33822 }
   33823 def V6_vmpyowh_alt : HInst<
   33824 (outs HvxVR:$Vd32),
   33825 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33826 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
   33827 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33828 let hasNewValue = 1;
   33829 let opNewValue = 0;
   33830 let isPseudo = 1;
   33831 let isCodeGenOnly = 1;
   33832 let DecoderNamespace = "EXT_mmvec";
   33833 }
   33834 def V6_vmpyowh_rnd : HInst<
   33835 (outs HvxVR:$Vd32),
   33836 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33837 "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
   33838 tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
   33839 let Inst{7-5} = 0b000;
   33840 let Inst{13-13} = 0b0;
   33841 let Inst{31-21} = 0b00011111010;
   33842 let hasNewValue = 1;
   33843 let opNewValue = 0;
   33844 let DecoderNamespace = "EXT_mmvec";
   33845 }
   33846 def V6_vmpyowh_rnd_alt : HInst<
   33847 (outs HvxVR:$Vd32),
   33848 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33849 "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
   33850 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33851 let hasNewValue = 1;
   33852 let opNewValue = 0;
   33853 let isPseudo = 1;
   33854 let isCodeGenOnly = 1;
   33855 let DecoderNamespace = "EXT_mmvec";
   33856 }
   33857 def V6_vmpyowh_rnd_sacc : HInst<
   33858 (outs HvxVR:$Vx32),
   33859 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33860 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
   33861 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   33862 let Inst{7-5} = 0b111;
   33863 let Inst{13-13} = 0b1;
   33864 let Inst{31-21} = 0b00011100001;
   33865 let hasNewValue = 1;
   33866 let opNewValue = 0;
   33867 let isAccumulator = 1;
   33868 let DecoderNamespace = "EXT_mmvec";
   33869 let Constraints = "$Vx32 = $Vx32in";
   33870 }
   33871 def V6_vmpyowh_rnd_sacc_alt : HInst<
   33872 (outs HvxVR:$Vx32),
   33873 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33874 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
   33875 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33876 let hasNewValue = 1;
   33877 let opNewValue = 0;
   33878 let isAccumulator = 1;
   33879 let isPseudo = 1;
   33880 let DecoderNamespace = "EXT_mmvec";
   33881 let Constraints = "$Vx32 = $Vx32in";
   33882 }
   33883 def V6_vmpyowh_sacc : HInst<
   33884 (outs HvxVR:$Vx32),
   33885 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33886 "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
   33887 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   33888 let Inst{7-5} = 0b110;
   33889 let Inst{13-13} = 0b1;
   33890 let Inst{31-21} = 0b00011100001;
   33891 let hasNewValue = 1;
   33892 let opNewValue = 0;
   33893 let isAccumulator = 1;
   33894 let DecoderNamespace = "EXT_mmvec";
   33895 let Constraints = "$Vx32 = $Vx32in";
   33896 }
   33897 def V6_vmpyowh_sacc_alt : HInst<
   33898 (outs HvxVR:$Vx32),
   33899 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33900 "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
   33901 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33902 let hasNewValue = 1;
   33903 let opNewValue = 0;
   33904 let isAccumulator = 1;
   33905 let isPseudo = 1;
   33906 let DecoderNamespace = "EXT_mmvec";
   33907 let Constraints = "$Vx32 = $Vx32in";
   33908 }
   33909 def V6_vmpyub : HInst<
   33910 (outs HvxWR:$Vdd32),
   33911 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33912 "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
   33913 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
   33914 let Inst{7-5} = 0b000;
   33915 let Inst{13-13} = 0b0;
   33916 let Inst{31-21} = 0b00011001110;
   33917 let hasNewValue = 1;
   33918 let opNewValue = 0;
   33919 let DecoderNamespace = "EXT_mmvec";
   33920 }
   33921 def V6_vmpyub_acc : HInst<
   33922 (outs HvxWR:$Vxx32),
   33923 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33924 "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
   33925 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
   33926 let Inst{7-5} = 0b000;
   33927 let Inst{13-13} = 0b1;
   33928 let Inst{31-21} = 0b00011001100;
   33929 let hasNewValue = 1;
   33930 let opNewValue = 0;
   33931 let isAccumulator = 1;
   33932 let DecoderNamespace = "EXT_mmvec";
   33933 let Constraints = "$Vxx32 = $Vxx32in";
   33934 }
   33935 def V6_vmpyub_acc_alt : HInst<
   33936 (outs HvxWR:$Vxx32),
   33937 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   33938 "$Vxx32 += vmpyub($Vu32,$Rt32)",
   33939 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33940 let hasNewValue = 1;
   33941 let opNewValue = 0;
   33942 let isAccumulator = 1;
   33943 let isPseudo = 1;
   33944 let isCodeGenOnly = 1;
   33945 let DecoderNamespace = "EXT_mmvec";
   33946 let Constraints = "$Vxx32 = $Vxx32in";
   33947 }
   33948 def V6_vmpyub_alt : HInst<
   33949 (outs HvxWR:$Vdd32),
   33950 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   33951 "$Vdd32 = vmpyub($Vu32,$Rt32)",
   33952 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33953 let hasNewValue = 1;
   33954 let opNewValue = 0;
   33955 let isPseudo = 1;
   33956 let isCodeGenOnly = 1;
   33957 let DecoderNamespace = "EXT_mmvec";
   33958 }
   33959 def V6_vmpyubv : HInst<
   33960 (outs HvxWR:$Vdd32),
   33961 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   33962 "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
   33963 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   33964 let Inst{7-5} = 0b101;
   33965 let Inst{13-13} = 0b0;
   33966 let Inst{31-21} = 0b00011100000;
   33967 let hasNewValue = 1;
   33968 let opNewValue = 0;
   33969 let DecoderNamespace = "EXT_mmvec";
   33970 }
   33971 def V6_vmpyubv_acc : HInst<
   33972 (outs HvxWR:$Vxx32),
   33973 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33974 "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
   33975 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   33976 let Inst{7-5} = 0b101;
   33977 let Inst{13-13} = 0b1;
   33978 let Inst{31-21} = 0b00011100000;
   33979 let hasNewValue = 1;
   33980 let opNewValue = 0;
   33981 let isAccumulator = 1;
   33982 let DecoderNamespace = "EXT_mmvec";
   33983 let Constraints = "$Vxx32 = $Vxx32in";
   33984 }
   33985 def V6_vmpyubv_acc_alt : HInst<
   33986 (outs HvxWR:$Vxx32),
   33987 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   33988 "$Vxx32 += vmpyub($Vu32,$Vv32)",
   33989 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   33990 let hasNewValue = 1;
   33991 let opNewValue = 0;
   33992 let isAccumulator = 1;
   33993 let isPseudo = 1;
   33994 let isCodeGenOnly = 1;
   33995 let DecoderNamespace = "EXT_mmvec";
   33996 let Constraints = "$Vxx32 = $Vxx32in";
   33997 }
   33998 def V6_vmpyubv_alt : HInst<
   33999 (outs HvxWR:$Vdd32),
   34000 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34001 "$Vdd32 = vmpyub($Vu32,$Vv32)",
   34002 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34003 let hasNewValue = 1;
   34004 let opNewValue = 0;
   34005 let isPseudo = 1;
   34006 let isCodeGenOnly = 1;
   34007 let DecoderNamespace = "EXT_mmvec";
   34008 }
   34009 def V6_vmpyuh : HInst<
   34010 (outs HvxWR:$Vdd32),
   34011 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34012 "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
   34013 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
   34014 let Inst{7-5} = 0b011;
   34015 let Inst{13-13} = 0b0;
   34016 let Inst{31-21} = 0b00011001010;
   34017 let hasNewValue = 1;
   34018 let opNewValue = 0;
   34019 let DecoderNamespace = "EXT_mmvec";
   34020 }
   34021 def V6_vmpyuh_acc : HInst<
   34022 (outs HvxWR:$Vxx32),
   34023 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34024 "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
   34025 tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
   34026 let Inst{7-5} = 0b001;
   34027 let Inst{13-13} = 0b1;
   34028 let Inst{31-21} = 0b00011001010;
   34029 let hasNewValue = 1;
   34030 let opNewValue = 0;
   34031 let isAccumulator = 1;
   34032 let DecoderNamespace = "EXT_mmvec";
   34033 let Constraints = "$Vxx32 = $Vxx32in";
   34034 }
   34035 def V6_vmpyuh_acc_alt : HInst<
   34036 (outs HvxWR:$Vxx32),
   34037 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34038 "$Vxx32 += vmpyuh($Vu32,$Rt32)",
   34039 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34040 let hasNewValue = 1;
   34041 let opNewValue = 0;
   34042 let isAccumulator = 1;
   34043 let isPseudo = 1;
   34044 let isCodeGenOnly = 1;
   34045 let DecoderNamespace = "EXT_mmvec";
   34046 let Constraints = "$Vxx32 = $Vxx32in";
   34047 }
   34048 def V6_vmpyuh_alt : HInst<
   34049 (outs HvxWR:$Vdd32),
   34050 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34051 "$Vdd32 = vmpyuh($Vu32,$Rt32)",
   34052 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34053 let hasNewValue = 1;
   34054 let opNewValue = 0;
   34055 let isPseudo = 1;
   34056 let isCodeGenOnly = 1;
   34057 let DecoderNamespace = "EXT_mmvec";
   34058 }
   34059 def V6_vmpyuhe : HInst<
   34060 (outs HvxVR:$Vd32),
   34061 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34062 "$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
   34063 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
   34064 let Inst{7-5} = 0b010;
   34065 let Inst{13-13} = 0b0;
   34066 let Inst{31-21} = 0b00011001011;
   34067 let hasNewValue = 1;
   34068 let opNewValue = 0;
   34069 let DecoderNamespace = "EXT_mmvec";
   34070 }
   34071 def V6_vmpyuhe_acc : HInst<
   34072 (outs HvxVR:$Vx32),
   34073 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34074 "$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
   34075 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
   34076 let Inst{7-5} = 0b011;
   34077 let Inst{13-13} = 0b1;
   34078 let Inst{31-21} = 0b00011001100;
   34079 let hasNewValue = 1;
   34080 let opNewValue = 0;
   34081 let isAccumulator = 1;
   34082 let DecoderNamespace = "EXT_mmvec";
   34083 let Constraints = "$Vx32 = $Vx32in";
   34084 }
   34085 def V6_vmpyuhv : HInst<
   34086 (outs HvxWR:$Vdd32),
   34087 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34088 "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
   34089 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   34090 let Inst{7-5} = 0b000;
   34091 let Inst{13-13} = 0b0;
   34092 let Inst{31-21} = 0b00011100001;
   34093 let hasNewValue = 1;
   34094 let opNewValue = 0;
   34095 let DecoderNamespace = "EXT_mmvec";
   34096 }
   34097 def V6_vmpyuhv_acc : HInst<
   34098 (outs HvxWR:$Vxx32),
   34099 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34100 "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
   34101 tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
   34102 let Inst{7-5} = 0b000;
   34103 let Inst{13-13} = 0b1;
   34104 let Inst{31-21} = 0b00011100001;
   34105 let hasNewValue = 1;
   34106 let opNewValue = 0;
   34107 let isAccumulator = 1;
   34108 let DecoderNamespace = "EXT_mmvec";
   34109 let Constraints = "$Vxx32 = $Vxx32in";
   34110 }
   34111 def V6_vmpyuhv_acc_alt : HInst<
   34112 (outs HvxWR:$Vxx32),
   34113 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34114 "$Vxx32 += vmpyuh($Vu32,$Vv32)",
   34115 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34116 let hasNewValue = 1;
   34117 let opNewValue = 0;
   34118 let isAccumulator = 1;
   34119 let isPseudo = 1;
   34120 let isCodeGenOnly = 1;
   34121 let DecoderNamespace = "EXT_mmvec";
   34122 let Constraints = "$Vxx32 = $Vxx32in";
   34123 }
   34124 def V6_vmpyuhv_alt : HInst<
   34125 (outs HvxWR:$Vdd32),
   34126 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34127 "$Vdd32 = vmpyuh($Vu32,$Vv32)",
   34128 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34129 let hasNewValue = 1;
   34130 let opNewValue = 0;
   34131 let isPseudo = 1;
   34132 let isCodeGenOnly = 1;
   34133 let DecoderNamespace = "EXT_mmvec";
   34134 }
   34135 def V6_vmux : HInst<
   34136 (outs HvxVR:$Vd32),
   34137 (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
   34138 "$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
   34139 tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
   34140 let Inst{7-7} = 0b0;
   34141 let Inst{13-13} = 0b1;
   34142 let Inst{31-21} = 0b00011110111;
   34143 let hasNewValue = 1;
   34144 let opNewValue = 0;
   34145 let DecoderNamespace = "EXT_mmvec";
   34146 }
   34147 def V6_vnavgb : HInst<
   34148 (outs HvxVR:$Vd32),
   34149 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34150 "$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
   34151 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
   34152 let Inst{7-5} = 0b110;
   34153 let Inst{13-13} = 0b1;
   34154 let Inst{31-21} = 0b00011111000;
   34155 let hasNewValue = 1;
   34156 let opNewValue = 0;
   34157 let DecoderNamespace = "EXT_mmvec";
   34158 }
   34159 def V6_vnavgb_alt : HInst<
   34160 (outs HvxVR:$Vd32),
   34161 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34162 "$Vd32 = vnavgb($Vu32,$Vv32)",
   34163 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   34164 let hasNewValue = 1;
   34165 let opNewValue = 0;
   34166 let isPseudo = 1;
   34167 let isCodeGenOnly = 1;
   34168 let DecoderNamespace = "EXT_mmvec";
   34169 }
   34170 def V6_vnavgh : HInst<
   34171 (outs HvxVR:$Vd32),
   34172 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34173 "$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
   34174 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   34175 let Inst{7-5} = 0b001;
   34176 let Inst{13-13} = 0b0;
   34177 let Inst{31-21} = 0b00011100111;
   34178 let hasNewValue = 1;
   34179 let opNewValue = 0;
   34180 let DecoderNamespace = "EXT_mmvec";
   34181 }
   34182 def V6_vnavgh_alt : HInst<
   34183 (outs HvxVR:$Vd32),
   34184 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34185 "$Vd32 = vnavgh($Vu32,$Vv32)",
   34186 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34187 let hasNewValue = 1;
   34188 let opNewValue = 0;
   34189 let isPseudo = 1;
   34190 let isCodeGenOnly = 1;
   34191 let DecoderNamespace = "EXT_mmvec";
   34192 }
   34193 def V6_vnavgub : HInst<
   34194 (outs HvxVR:$Vd32),
   34195 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34196 "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
   34197 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   34198 let Inst{7-5} = 0b000;
   34199 let Inst{13-13} = 0b0;
   34200 let Inst{31-21} = 0b00011100111;
   34201 let hasNewValue = 1;
   34202 let opNewValue = 0;
   34203 let DecoderNamespace = "EXT_mmvec";
   34204 }
   34205 def V6_vnavgub_alt : HInst<
   34206 (outs HvxVR:$Vd32),
   34207 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34208 "$Vd32 = vnavgub($Vu32,$Vv32)",
   34209 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34210 let hasNewValue = 1;
   34211 let opNewValue = 0;
   34212 let isPseudo = 1;
   34213 let isCodeGenOnly = 1;
   34214 let DecoderNamespace = "EXT_mmvec";
   34215 }
   34216 def V6_vnavgw : HInst<
   34217 (outs HvxVR:$Vd32),
   34218 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34219 "$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
   34220 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   34221 let Inst{7-5} = 0b010;
   34222 let Inst{13-13} = 0b0;
   34223 let Inst{31-21} = 0b00011100111;
   34224 let hasNewValue = 1;
   34225 let opNewValue = 0;
   34226 let DecoderNamespace = "EXT_mmvec";
   34227 }
   34228 def V6_vnavgw_alt : HInst<
   34229 (outs HvxVR:$Vd32),
   34230 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34231 "$Vd32 = vnavgw($Vu32,$Vv32)",
   34232 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34233 let hasNewValue = 1;
   34234 let opNewValue = 0;
   34235 let isPseudo = 1;
   34236 let isCodeGenOnly = 1;
   34237 let DecoderNamespace = "EXT_mmvec";
   34238 }
   34239 def V6_vnccombine : HInst<
   34240 (outs HvxWR:$Vdd32),
   34241 (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
   34242 "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
   34243 tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
   34244 let Inst{7-7} = 0b0;
   34245 let Inst{13-13} = 0b0;
   34246 let Inst{31-21} = 0b00011010010;
   34247 let isPredicated = 1;
   34248 let isPredicatedFalse = 1;
   34249 let hasNewValue = 1;
   34250 let opNewValue = 0;
   34251 let DecoderNamespace = "EXT_mmvec";
   34252 }
   34253 def V6_vncmov : HInst<
   34254 (outs HvxVR:$Vd32),
   34255 (ins PredRegs:$Ps4, HvxVR:$Vu32),
   34256 "if (!$Ps4) $Vd32 = $Vu32",
   34257 tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
   34258 let Inst{7-7} = 0b0;
   34259 let Inst{13-13} = 0b0;
   34260 let Inst{31-16} = 0b0001101000100000;
   34261 let isPredicated = 1;
   34262 let isPredicatedFalse = 1;
   34263 let hasNewValue = 1;
   34264 let opNewValue = 0;
   34265 let DecoderNamespace = "EXT_mmvec";
   34266 }
   34267 def V6_vnormamth : HInst<
   34268 (outs HvxVR:$Vd32),
   34269 (ins HvxVR:$Vu32),
   34270 "$Vd32.h = vnormamt($Vu32.h)",
   34271 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
   34272 let Inst{7-5} = 0b101;
   34273 let Inst{13-13} = 0b0;
   34274 let Inst{31-16} = 0b0001111000000011;
   34275 let hasNewValue = 1;
   34276 let opNewValue = 0;
   34277 let DecoderNamespace = "EXT_mmvec";
   34278 }
   34279 def V6_vnormamth_alt : HInst<
   34280 (outs HvxVR:$Vd32),
   34281 (ins HvxVR:$Vu32),
   34282 "$Vd32 = vnormamth($Vu32)",
   34283 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34284 let hasNewValue = 1;
   34285 let opNewValue = 0;
   34286 let isPseudo = 1;
   34287 let isCodeGenOnly = 1;
   34288 let DecoderNamespace = "EXT_mmvec";
   34289 }
   34290 def V6_vnormamtw : HInst<
   34291 (outs HvxVR:$Vd32),
   34292 (ins HvxVR:$Vu32),
   34293 "$Vd32.w = vnormamt($Vu32.w)",
   34294 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
   34295 let Inst{7-5} = 0b100;
   34296 let Inst{13-13} = 0b0;
   34297 let Inst{31-16} = 0b0001111000000011;
   34298 let hasNewValue = 1;
   34299 let opNewValue = 0;
   34300 let DecoderNamespace = "EXT_mmvec";
   34301 }
   34302 def V6_vnormamtw_alt : HInst<
   34303 (outs HvxVR:$Vd32),
   34304 (ins HvxVR:$Vu32),
   34305 "$Vd32 = vnormamtw($Vu32)",
   34306 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34307 let hasNewValue = 1;
   34308 let opNewValue = 0;
   34309 let isPseudo = 1;
   34310 let isCodeGenOnly = 1;
   34311 let DecoderNamespace = "EXT_mmvec";
   34312 }
   34313 def V6_vnot : HInst<
   34314 (outs HvxVR:$Vd32),
   34315 (ins HvxVR:$Vu32),
   34316 "$Vd32 = vnot($Vu32)",
   34317 tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
   34318 let Inst{7-5} = 0b100;
   34319 let Inst{13-13} = 0b0;
   34320 let Inst{31-16} = 0b0001111000000000;
   34321 let hasNewValue = 1;
   34322 let opNewValue = 0;
   34323 let DecoderNamespace = "EXT_mmvec";
   34324 }
   34325 def V6_vor : HInst<
   34326 (outs HvxVR:$Vd32),
   34327 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34328 "$Vd32 = vor($Vu32,$Vv32)",
   34329 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   34330 let Inst{7-5} = 0b110;
   34331 let Inst{13-13} = 0b0;
   34332 let Inst{31-21} = 0b00011100001;
   34333 let hasNewValue = 1;
   34334 let opNewValue = 0;
   34335 let DecoderNamespace = "EXT_mmvec";
   34336 }
   34337 def V6_vpackeb : HInst<
   34338 (outs HvxVR:$Vd32),
   34339 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34340 "$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
   34341 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34342 let Inst{7-5} = 0b010;
   34343 let Inst{13-13} = 0b0;
   34344 let Inst{31-21} = 0b00011111110;
   34345 let hasNewValue = 1;
   34346 let opNewValue = 0;
   34347 let DecoderNamespace = "EXT_mmvec";
   34348 }
   34349 def V6_vpackeb_alt : HInst<
   34350 (outs HvxVR:$Vd32),
   34351 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34352 "$Vd32 = vpackeb($Vu32,$Vv32)",
   34353 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34354 let hasNewValue = 1;
   34355 let opNewValue = 0;
   34356 let isPseudo = 1;
   34357 let isCodeGenOnly = 1;
   34358 let DecoderNamespace = "EXT_mmvec";
   34359 }
   34360 def V6_vpackeh : HInst<
   34361 (outs HvxVR:$Vd32),
   34362 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34363 "$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
   34364 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34365 let Inst{7-5} = 0b011;
   34366 let Inst{13-13} = 0b0;
   34367 let Inst{31-21} = 0b00011111110;
   34368 let hasNewValue = 1;
   34369 let opNewValue = 0;
   34370 let DecoderNamespace = "EXT_mmvec";
   34371 }
   34372 def V6_vpackeh_alt : HInst<
   34373 (outs HvxVR:$Vd32),
   34374 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34375 "$Vd32 = vpackeh($Vu32,$Vv32)",
   34376 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34377 let hasNewValue = 1;
   34378 let opNewValue = 0;
   34379 let isPseudo = 1;
   34380 let isCodeGenOnly = 1;
   34381 let DecoderNamespace = "EXT_mmvec";
   34382 }
   34383 def V6_vpackhb_sat : HInst<
   34384 (outs HvxVR:$Vd32),
   34385 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34386 "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
   34387 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34388 let Inst{7-5} = 0b110;
   34389 let Inst{13-13} = 0b0;
   34390 let Inst{31-21} = 0b00011111110;
   34391 let hasNewValue = 1;
   34392 let opNewValue = 0;
   34393 let DecoderNamespace = "EXT_mmvec";
   34394 }
   34395 def V6_vpackhb_sat_alt : HInst<
   34396 (outs HvxVR:$Vd32),
   34397 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34398 "$Vd32 = vpackhb($Vu32,$Vv32):sat",
   34399 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34400 let hasNewValue = 1;
   34401 let opNewValue = 0;
   34402 let isPseudo = 1;
   34403 let isCodeGenOnly = 1;
   34404 let DecoderNamespace = "EXT_mmvec";
   34405 }
   34406 def V6_vpackhub_sat : HInst<
   34407 (outs HvxVR:$Vd32),
   34408 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34409 "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
   34410 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34411 let Inst{7-5} = 0b101;
   34412 let Inst{13-13} = 0b0;
   34413 let Inst{31-21} = 0b00011111110;
   34414 let hasNewValue = 1;
   34415 let opNewValue = 0;
   34416 let DecoderNamespace = "EXT_mmvec";
   34417 }
   34418 def V6_vpackhub_sat_alt : HInst<
   34419 (outs HvxVR:$Vd32),
   34420 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34421 "$Vd32 = vpackhub($Vu32,$Vv32):sat",
   34422 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34423 let hasNewValue = 1;
   34424 let opNewValue = 0;
   34425 let isPseudo = 1;
   34426 let isCodeGenOnly = 1;
   34427 let DecoderNamespace = "EXT_mmvec";
   34428 }
   34429 def V6_vpackob : HInst<
   34430 (outs HvxVR:$Vd32),
   34431 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34432 "$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
   34433 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34434 let Inst{7-5} = 0b001;
   34435 let Inst{13-13} = 0b0;
   34436 let Inst{31-21} = 0b00011111111;
   34437 let hasNewValue = 1;
   34438 let opNewValue = 0;
   34439 let DecoderNamespace = "EXT_mmvec";
   34440 }
   34441 def V6_vpackob_alt : HInst<
   34442 (outs HvxVR:$Vd32),
   34443 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34444 "$Vd32 = vpackob($Vu32,$Vv32)",
   34445 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34446 let hasNewValue = 1;
   34447 let opNewValue = 0;
   34448 let isPseudo = 1;
   34449 let isCodeGenOnly = 1;
   34450 let DecoderNamespace = "EXT_mmvec";
   34451 }
   34452 def V6_vpackoh : HInst<
   34453 (outs HvxVR:$Vd32),
   34454 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34455 "$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
   34456 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34457 let Inst{7-5} = 0b010;
   34458 let Inst{13-13} = 0b0;
   34459 let Inst{31-21} = 0b00011111111;
   34460 let hasNewValue = 1;
   34461 let opNewValue = 0;
   34462 let DecoderNamespace = "EXT_mmvec";
   34463 }
   34464 def V6_vpackoh_alt : HInst<
   34465 (outs HvxVR:$Vd32),
   34466 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34467 "$Vd32 = vpackoh($Vu32,$Vv32)",
   34468 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34469 let hasNewValue = 1;
   34470 let opNewValue = 0;
   34471 let isPseudo = 1;
   34472 let isCodeGenOnly = 1;
   34473 let DecoderNamespace = "EXT_mmvec";
   34474 }
   34475 def V6_vpackwh_sat : HInst<
   34476 (outs HvxVR:$Vd32),
   34477 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34478 "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
   34479 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34480 let Inst{7-5} = 0b000;
   34481 let Inst{13-13} = 0b0;
   34482 let Inst{31-21} = 0b00011111111;
   34483 let hasNewValue = 1;
   34484 let opNewValue = 0;
   34485 let DecoderNamespace = "EXT_mmvec";
   34486 }
   34487 def V6_vpackwh_sat_alt : HInst<
   34488 (outs HvxVR:$Vd32),
   34489 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34490 "$Vd32 = vpackwh($Vu32,$Vv32):sat",
   34491 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34492 let hasNewValue = 1;
   34493 let opNewValue = 0;
   34494 let isPseudo = 1;
   34495 let isCodeGenOnly = 1;
   34496 let DecoderNamespace = "EXT_mmvec";
   34497 }
   34498 def V6_vpackwuh_sat : HInst<
   34499 (outs HvxVR:$Vd32),
   34500 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34501 "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
   34502 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34503 let Inst{7-5} = 0b111;
   34504 let Inst{13-13} = 0b0;
   34505 let Inst{31-21} = 0b00011111110;
   34506 let hasNewValue = 1;
   34507 let opNewValue = 0;
   34508 let DecoderNamespace = "EXT_mmvec";
   34509 }
   34510 def V6_vpackwuh_sat_alt : HInst<
   34511 (outs HvxVR:$Vd32),
   34512 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34513 "$Vd32 = vpackwuh($Vu32,$Vv32):sat",
   34514 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34515 let hasNewValue = 1;
   34516 let opNewValue = 0;
   34517 let isPseudo = 1;
   34518 let isCodeGenOnly = 1;
   34519 let DecoderNamespace = "EXT_mmvec";
   34520 }
   34521 def V6_vpopcounth : HInst<
   34522 (outs HvxVR:$Vd32),
   34523 (ins HvxVR:$Vu32),
   34524 "$Vd32.h = vpopcount($Vu32.h)",
   34525 tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
   34526 let Inst{7-5} = 0b110;
   34527 let Inst{13-13} = 0b0;
   34528 let Inst{31-16} = 0b0001111000000010;
   34529 let hasNewValue = 1;
   34530 let opNewValue = 0;
   34531 let DecoderNamespace = "EXT_mmvec";
   34532 }
   34533 def V6_vpopcounth_alt : HInst<
   34534 (outs HvxVR:$Vd32),
   34535 (ins HvxVR:$Vu32),
   34536 "$Vd32 = vpopcounth($Vu32)",
   34537 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34538 let hasNewValue = 1;
   34539 let opNewValue = 0;
   34540 let isPseudo = 1;
   34541 let isCodeGenOnly = 1;
   34542 let DecoderNamespace = "EXT_mmvec";
   34543 }
   34544 def V6_vprefixqb : HInst<
   34545 (outs HvxVR:$Vd32),
   34546 (ins HvxQR:$Qv4),
   34547 "$Vd32.b = prefixsum($Qv4)",
   34548 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
   34549 let Inst{13-5} = 0b100000010;
   34550 let Inst{21-16} = 0b000011;
   34551 let Inst{31-24} = 0b00011110;
   34552 let hasNewValue = 1;
   34553 let opNewValue = 0;
   34554 let DecoderNamespace = "EXT_mmvec";
   34555 }
   34556 def V6_vprefixqh : HInst<
   34557 (outs HvxVR:$Vd32),
   34558 (ins HvxQR:$Qv4),
   34559 "$Vd32.h = prefixsum($Qv4)",
   34560 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
   34561 let Inst{13-5} = 0b100001010;
   34562 let Inst{21-16} = 0b000011;
   34563 let Inst{31-24} = 0b00011110;
   34564 let hasNewValue = 1;
   34565 let opNewValue = 0;
   34566 let DecoderNamespace = "EXT_mmvec";
   34567 }
   34568 def V6_vprefixqw : HInst<
   34569 (outs HvxVR:$Vd32),
   34570 (ins HvxQR:$Qv4),
   34571 "$Vd32.w = prefixsum($Qv4)",
   34572 tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
   34573 let Inst{13-5} = 0b100010010;
   34574 let Inst{21-16} = 0b000011;
   34575 let Inst{31-24} = 0b00011110;
   34576 let hasNewValue = 1;
   34577 let opNewValue = 0;
   34578 let DecoderNamespace = "EXT_mmvec";
   34579 }
   34580 def V6_vrdelta : HInst<
   34581 (outs HvxVR:$Vd32),
   34582 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34583 "$Vd32 = vrdelta($Vu32,$Vv32)",
   34584 tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
   34585 let Inst{7-5} = 0b011;
   34586 let Inst{13-13} = 0b0;
   34587 let Inst{31-21} = 0b00011111001;
   34588 let hasNewValue = 1;
   34589 let opNewValue = 0;
   34590 let DecoderNamespace = "EXT_mmvec";
   34591 }
   34592 def V6_vrmpybub_rtt : HInst<
   34593 (outs HvxWR:$Vdd32),
   34594 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34595 "$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
   34596 tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
   34597 let Inst{7-5} = 0b101;
   34598 let Inst{13-13} = 0b0;
   34599 let Inst{31-21} = 0b00011001110;
   34600 let hasNewValue = 1;
   34601 let opNewValue = 0;
   34602 let DecoderNamespace = "EXT_mmvec";
   34603 }
   34604 def V6_vrmpybub_rtt_acc : HInst<
   34605 (outs HvxWR:$Vxx32),
   34606 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34607 "$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
   34608 tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
   34609 let Inst{7-5} = 0b000;
   34610 let Inst{13-13} = 0b1;
   34611 let Inst{31-21} = 0b00011001101;
   34612 let hasNewValue = 1;
   34613 let opNewValue = 0;
   34614 let isAccumulator = 1;
   34615 let DecoderNamespace = "EXT_mmvec";
   34616 let Constraints = "$Vxx32 = $Vxx32in";
   34617 }
   34618 def V6_vrmpybub_rtt_acc_alt : HInst<
   34619 (outs HvxWR:$Vxx32),
   34620 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34621 "$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
   34622 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   34623 let hasNewValue = 1;
   34624 let opNewValue = 0;
   34625 let isAccumulator = 1;
   34626 let isPseudo = 1;
   34627 let isCodeGenOnly = 1;
   34628 let DecoderNamespace = "EXT_mmvec";
   34629 let Constraints = "$Vxx32 = $Vxx32in";
   34630 }
   34631 def V6_vrmpybub_rtt_alt : HInst<
   34632 (outs HvxWR:$Vdd32),
   34633 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34634 "$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
   34635 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   34636 let hasNewValue = 1;
   34637 let opNewValue = 0;
   34638 let isPseudo = 1;
   34639 let isCodeGenOnly = 1;
   34640 let DecoderNamespace = "EXT_mmvec";
   34641 }
   34642 def V6_vrmpybus : HInst<
   34643 (outs HvxVR:$Vd32),
   34644 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34645 "$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
   34646 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   34647 let Inst{7-5} = 0b100;
   34648 let Inst{13-13} = 0b0;
   34649 let Inst{31-21} = 0b00011001000;
   34650 let hasNewValue = 1;
   34651 let opNewValue = 0;
   34652 let DecoderNamespace = "EXT_mmvec";
   34653 }
   34654 def V6_vrmpybus_acc : HInst<
   34655 (outs HvxVR:$Vx32),
   34656 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34657 "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
   34658 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   34659 let Inst{7-5} = 0b101;
   34660 let Inst{13-13} = 0b1;
   34661 let Inst{31-21} = 0b00011001000;
   34662 let hasNewValue = 1;
   34663 let opNewValue = 0;
   34664 let isAccumulator = 1;
   34665 let DecoderNamespace = "EXT_mmvec";
   34666 let Constraints = "$Vx32 = $Vx32in";
   34667 }
   34668 def V6_vrmpybus_acc_alt : HInst<
   34669 (outs HvxVR:$Vx32),
   34670 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34671 "$Vx32 += vrmpybus($Vu32,$Rt32)",
   34672 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34673 let hasNewValue = 1;
   34674 let opNewValue = 0;
   34675 let isAccumulator = 1;
   34676 let isPseudo = 1;
   34677 let isCodeGenOnly = 1;
   34678 let DecoderNamespace = "EXT_mmvec";
   34679 let Constraints = "$Vx32 = $Vx32in";
   34680 }
   34681 def V6_vrmpybus_alt : HInst<
   34682 (outs HvxVR:$Vd32),
   34683 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34684 "$Vd32 = vrmpybus($Vu32,$Rt32)",
   34685 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34686 let hasNewValue = 1;
   34687 let opNewValue = 0;
   34688 let isPseudo = 1;
   34689 let isCodeGenOnly = 1;
   34690 let DecoderNamespace = "EXT_mmvec";
   34691 }
   34692 def V6_vrmpybusi : HInst<
   34693 (outs HvxWR:$Vdd32),
   34694 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34695 "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
   34696 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
   34697 let Inst{7-6} = 0b10;
   34698 let Inst{13-13} = 0b0;
   34699 let Inst{31-21} = 0b00011001010;
   34700 let hasNewValue = 1;
   34701 let opNewValue = 0;
   34702 let DecoderNamespace = "EXT_mmvec";
   34703 }
   34704 def V6_vrmpybusi_acc : HInst<
   34705 (outs HvxWR:$Vxx32),
   34706 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34707 "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
   34708 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
   34709 let Inst{7-6} = 0b10;
   34710 let Inst{13-13} = 0b1;
   34711 let Inst{31-21} = 0b00011001010;
   34712 let hasNewValue = 1;
   34713 let opNewValue = 0;
   34714 let isAccumulator = 1;
   34715 let DecoderNamespace = "EXT_mmvec";
   34716 let Constraints = "$Vxx32 = $Vxx32in";
   34717 }
   34718 def V6_vrmpybusi_acc_alt : HInst<
   34719 (outs HvxWR:$Vxx32),
   34720 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34721 "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
   34722 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34723 let hasNewValue = 1;
   34724 let opNewValue = 0;
   34725 let isAccumulator = 1;
   34726 let isPseudo = 1;
   34727 let isCodeGenOnly = 1;
   34728 let DecoderNamespace = "EXT_mmvec";
   34729 let Constraints = "$Vxx32 = $Vxx32in";
   34730 }
   34731 def V6_vrmpybusi_alt : HInst<
   34732 (outs HvxWR:$Vdd32),
   34733 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34734 "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
   34735 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34736 let hasNewValue = 1;
   34737 let opNewValue = 0;
   34738 let isPseudo = 1;
   34739 let isCodeGenOnly = 1;
   34740 let DecoderNamespace = "EXT_mmvec";
   34741 }
   34742 def V6_vrmpybusv : HInst<
   34743 (outs HvxVR:$Vd32),
   34744 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34745 "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
   34746 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   34747 let Inst{7-5} = 0b010;
   34748 let Inst{13-13} = 0b0;
   34749 let Inst{31-21} = 0b00011100000;
   34750 let hasNewValue = 1;
   34751 let opNewValue = 0;
   34752 let DecoderNamespace = "EXT_mmvec";
   34753 }
   34754 def V6_vrmpybusv_acc : HInst<
   34755 (outs HvxVR:$Vx32),
   34756 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34757 "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
   34758 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   34759 let Inst{7-5} = 0b010;
   34760 let Inst{13-13} = 0b1;
   34761 let Inst{31-21} = 0b00011100000;
   34762 let hasNewValue = 1;
   34763 let opNewValue = 0;
   34764 let isAccumulator = 1;
   34765 let DecoderNamespace = "EXT_mmvec";
   34766 let Constraints = "$Vx32 = $Vx32in";
   34767 }
   34768 def V6_vrmpybusv_acc_alt : HInst<
   34769 (outs HvxVR:$Vx32),
   34770 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34771 "$Vx32 += vrmpybus($Vu32,$Vv32)",
   34772 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34773 let hasNewValue = 1;
   34774 let opNewValue = 0;
   34775 let isAccumulator = 1;
   34776 let isPseudo = 1;
   34777 let isCodeGenOnly = 1;
   34778 let DecoderNamespace = "EXT_mmvec";
   34779 let Constraints = "$Vx32 = $Vx32in";
   34780 }
   34781 def V6_vrmpybusv_alt : HInst<
   34782 (outs HvxVR:$Vd32),
   34783 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34784 "$Vd32 = vrmpybus($Vu32,$Vv32)",
   34785 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34786 let hasNewValue = 1;
   34787 let opNewValue = 0;
   34788 let isPseudo = 1;
   34789 let isCodeGenOnly = 1;
   34790 let DecoderNamespace = "EXT_mmvec";
   34791 }
   34792 def V6_vrmpybv : HInst<
   34793 (outs HvxVR:$Vd32),
   34794 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34795 "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
   34796 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   34797 let Inst{7-5} = 0b001;
   34798 let Inst{13-13} = 0b0;
   34799 let Inst{31-21} = 0b00011100000;
   34800 let hasNewValue = 1;
   34801 let opNewValue = 0;
   34802 let DecoderNamespace = "EXT_mmvec";
   34803 }
   34804 def V6_vrmpybv_acc : HInst<
   34805 (outs HvxVR:$Vx32),
   34806 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34807 "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
   34808 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   34809 let Inst{7-5} = 0b001;
   34810 let Inst{13-13} = 0b1;
   34811 let Inst{31-21} = 0b00011100000;
   34812 let hasNewValue = 1;
   34813 let opNewValue = 0;
   34814 let isAccumulator = 1;
   34815 let DecoderNamespace = "EXT_mmvec";
   34816 let Constraints = "$Vx32 = $Vx32in";
   34817 }
   34818 def V6_vrmpybv_acc_alt : HInst<
   34819 (outs HvxVR:$Vx32),
   34820 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   34821 "$Vx32 += vrmpyb($Vu32,$Vv32)",
   34822 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34823 let hasNewValue = 1;
   34824 let opNewValue = 0;
   34825 let isAccumulator = 1;
   34826 let isPseudo = 1;
   34827 let isCodeGenOnly = 1;
   34828 let DecoderNamespace = "EXT_mmvec";
   34829 let Constraints = "$Vx32 = $Vx32in";
   34830 }
   34831 def V6_vrmpybv_alt : HInst<
   34832 (outs HvxVR:$Vd32),
   34833 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34834 "$Vd32 = vrmpyb($Vu32,$Vv32)",
   34835 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34836 let hasNewValue = 1;
   34837 let opNewValue = 0;
   34838 let isPseudo = 1;
   34839 let isCodeGenOnly = 1;
   34840 let DecoderNamespace = "EXT_mmvec";
   34841 }
   34842 def V6_vrmpyub : HInst<
   34843 (outs HvxVR:$Vd32),
   34844 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34845 "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
   34846 tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
   34847 let Inst{7-5} = 0b011;
   34848 let Inst{13-13} = 0b0;
   34849 let Inst{31-21} = 0b00011001000;
   34850 let hasNewValue = 1;
   34851 let opNewValue = 0;
   34852 let DecoderNamespace = "EXT_mmvec";
   34853 }
   34854 def V6_vrmpyub_acc : HInst<
   34855 (outs HvxVR:$Vx32),
   34856 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34857 "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
   34858 tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
   34859 let Inst{7-5} = 0b100;
   34860 let Inst{13-13} = 0b1;
   34861 let Inst{31-21} = 0b00011001000;
   34862 let hasNewValue = 1;
   34863 let opNewValue = 0;
   34864 let isAccumulator = 1;
   34865 let DecoderNamespace = "EXT_mmvec";
   34866 let Constraints = "$Vx32 = $Vx32in";
   34867 }
   34868 def V6_vrmpyub_acc_alt : HInst<
   34869 (outs HvxVR:$Vx32),
   34870 (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
   34871 "$Vx32 += vrmpyub($Vu32,$Rt32)",
   34872 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34873 let hasNewValue = 1;
   34874 let opNewValue = 0;
   34875 let isAccumulator = 1;
   34876 let isPseudo = 1;
   34877 let isCodeGenOnly = 1;
   34878 let DecoderNamespace = "EXT_mmvec";
   34879 let Constraints = "$Vx32 = $Vx32in";
   34880 }
   34881 def V6_vrmpyub_alt : HInst<
   34882 (outs HvxVR:$Vd32),
   34883 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   34884 "$Vd32 = vrmpyub($Vu32,$Rt32)",
   34885 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34886 let hasNewValue = 1;
   34887 let opNewValue = 0;
   34888 let isPseudo = 1;
   34889 let isCodeGenOnly = 1;
   34890 let DecoderNamespace = "EXT_mmvec";
   34891 }
   34892 def V6_vrmpyub_rtt : HInst<
   34893 (outs HvxWR:$Vdd32),
   34894 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34895 "$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
   34896 tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
   34897 let Inst{7-5} = 0b100;
   34898 let Inst{13-13} = 0b0;
   34899 let Inst{31-21} = 0b00011001110;
   34900 let hasNewValue = 1;
   34901 let opNewValue = 0;
   34902 let DecoderNamespace = "EXT_mmvec";
   34903 }
   34904 def V6_vrmpyub_rtt_acc : HInst<
   34905 (outs HvxWR:$Vxx32),
   34906 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34907 "$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
   34908 tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
   34909 let Inst{7-5} = 0b111;
   34910 let Inst{13-13} = 0b1;
   34911 let Inst{31-21} = 0b00011001101;
   34912 let hasNewValue = 1;
   34913 let opNewValue = 0;
   34914 let isAccumulator = 1;
   34915 let DecoderNamespace = "EXT_mmvec";
   34916 let Constraints = "$Vxx32 = $Vxx32in";
   34917 }
   34918 def V6_vrmpyub_rtt_acc_alt : HInst<
   34919 (outs HvxWR:$Vxx32),
   34920 (ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34921 "$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
   34922 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   34923 let hasNewValue = 1;
   34924 let opNewValue = 0;
   34925 let isAccumulator = 1;
   34926 let isPseudo = 1;
   34927 let isCodeGenOnly = 1;
   34928 let DecoderNamespace = "EXT_mmvec";
   34929 let Constraints = "$Vxx32 = $Vxx32in";
   34930 }
   34931 def V6_vrmpyub_rtt_alt : HInst<
   34932 (outs HvxWR:$Vdd32),
   34933 (ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
   34934 "$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
   34935 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   34936 let hasNewValue = 1;
   34937 let opNewValue = 0;
   34938 let isPseudo = 1;
   34939 let isCodeGenOnly = 1;
   34940 let DecoderNamespace = "EXT_mmvec";
   34941 }
   34942 def V6_vrmpyubi : HInst<
   34943 (outs HvxWR:$Vdd32),
   34944 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34945 "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
   34946 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
   34947 let Inst{7-6} = 0b11;
   34948 let Inst{13-13} = 0b0;
   34949 let Inst{31-21} = 0b00011001101;
   34950 let hasNewValue = 1;
   34951 let opNewValue = 0;
   34952 let DecoderNamespace = "EXT_mmvec";
   34953 }
   34954 def V6_vrmpyubi_acc : HInst<
   34955 (outs HvxWR:$Vxx32),
   34956 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34957 "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
   34958 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
   34959 let Inst{7-6} = 0b11;
   34960 let Inst{13-13} = 0b1;
   34961 let Inst{31-21} = 0b00011001011;
   34962 let hasNewValue = 1;
   34963 let opNewValue = 0;
   34964 let isAccumulator = 1;
   34965 let DecoderNamespace = "EXT_mmvec";
   34966 let Constraints = "$Vxx32 = $Vxx32in";
   34967 }
   34968 def V6_vrmpyubi_acc_alt : HInst<
   34969 (outs HvxWR:$Vxx32),
   34970 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34971 "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
   34972 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34973 let hasNewValue = 1;
   34974 let opNewValue = 0;
   34975 let isAccumulator = 1;
   34976 let isPseudo = 1;
   34977 let isCodeGenOnly = 1;
   34978 let DecoderNamespace = "EXT_mmvec";
   34979 let Constraints = "$Vxx32 = $Vxx32in";
   34980 }
   34981 def V6_vrmpyubi_alt : HInst<
   34982 (outs HvxWR:$Vdd32),
   34983 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   34984 "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
   34985 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   34986 let hasNewValue = 1;
   34987 let opNewValue = 0;
   34988 let isPseudo = 1;
   34989 let isCodeGenOnly = 1;
   34990 let DecoderNamespace = "EXT_mmvec";
   34991 }
   34992 def V6_vrmpyubv : HInst<
   34993 (outs HvxVR:$Vd32),
   34994 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   34995 "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
   34996 tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
   34997 let Inst{7-5} = 0b000;
   34998 let Inst{13-13} = 0b0;
   34999 let Inst{31-21} = 0b00011100000;
   35000 let hasNewValue = 1;
   35001 let opNewValue = 0;
   35002 let DecoderNamespace = "EXT_mmvec";
   35003 }
   35004 def V6_vrmpyubv_acc : HInst<
   35005 (outs HvxVR:$Vx32),
   35006 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   35007 "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
   35008 tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
   35009 let Inst{7-5} = 0b000;
   35010 let Inst{13-13} = 0b1;
   35011 let Inst{31-21} = 0b00011100000;
   35012 let hasNewValue = 1;
   35013 let opNewValue = 0;
   35014 let isAccumulator = 1;
   35015 let DecoderNamespace = "EXT_mmvec";
   35016 let Constraints = "$Vx32 = $Vx32in";
   35017 }
   35018 def V6_vrmpyubv_acc_alt : HInst<
   35019 (outs HvxVR:$Vx32),
   35020 (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
   35021 "$Vx32 += vrmpyub($Vu32,$Vv32)",
   35022 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35023 let hasNewValue = 1;
   35024 let opNewValue = 0;
   35025 let isAccumulator = 1;
   35026 let isPseudo = 1;
   35027 let isCodeGenOnly = 1;
   35028 let DecoderNamespace = "EXT_mmvec";
   35029 let Constraints = "$Vx32 = $Vx32in";
   35030 }
   35031 def V6_vrmpyubv_alt : HInst<
   35032 (outs HvxVR:$Vd32),
   35033 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35034 "$Vd32 = vrmpyub($Vu32,$Vv32)",
   35035 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35036 let hasNewValue = 1;
   35037 let opNewValue = 0;
   35038 let isPseudo = 1;
   35039 let isCodeGenOnly = 1;
   35040 let DecoderNamespace = "EXT_mmvec";
   35041 }
   35042 def V6_vror : HInst<
   35043 (outs HvxVR:$Vd32),
   35044 (ins HvxVR:$Vu32, IntRegs:$Rt32),
   35045 "$Vd32 = vror($Vu32,$Rt32)",
   35046 tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
   35047 let Inst{7-5} = 0b001;
   35048 let Inst{13-13} = 0b0;
   35049 let Inst{31-21} = 0b00011001011;
   35050 let hasNewValue = 1;
   35051 let opNewValue = 0;
   35052 let DecoderNamespace = "EXT_mmvec";
   35053 }
   35054 def V6_vroundhb : HInst<
   35055 (outs HvxVR:$Vd32),
   35056 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35057 "$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
   35058 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   35059 let Inst{7-5} = 0b110;
   35060 let Inst{13-13} = 0b0;
   35061 let Inst{31-21} = 0b00011111011;
   35062 let hasNewValue = 1;
   35063 let opNewValue = 0;
   35064 let DecoderNamespace = "EXT_mmvec";
   35065 }
   35066 def V6_vroundhb_alt : HInst<
   35067 (outs HvxVR:$Vd32),
   35068 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35069 "$Vd32 = vroundhb($Vu32,$Vv32):sat",
   35070 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35071 let hasNewValue = 1;
   35072 let opNewValue = 0;
   35073 let isPseudo = 1;
   35074 let isCodeGenOnly = 1;
   35075 let DecoderNamespace = "EXT_mmvec";
   35076 }
   35077 def V6_vroundhub : HInst<
   35078 (outs HvxVR:$Vd32),
   35079 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35080 "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
   35081 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   35082 let Inst{7-5} = 0b111;
   35083 let Inst{13-13} = 0b0;
   35084 let Inst{31-21} = 0b00011111011;
   35085 let hasNewValue = 1;
   35086 let opNewValue = 0;
   35087 let DecoderNamespace = "EXT_mmvec";
   35088 }
   35089 def V6_vroundhub_alt : HInst<
   35090 (outs HvxVR:$Vd32),
   35091 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35092 "$Vd32 = vroundhub($Vu32,$Vv32):sat",
   35093 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35094 let hasNewValue = 1;
   35095 let opNewValue = 0;
   35096 let isPseudo = 1;
   35097 let isCodeGenOnly = 1;
   35098 let DecoderNamespace = "EXT_mmvec";
   35099 }
   35100 def V6_vrounduhub : HInst<
   35101 (outs HvxVR:$Vd32),
   35102 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35103 "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
   35104 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
   35105 let Inst{7-5} = 0b011;
   35106 let Inst{13-13} = 0b0;
   35107 let Inst{31-21} = 0b00011111111;
   35108 let hasNewValue = 1;
   35109 let opNewValue = 0;
   35110 let DecoderNamespace = "EXT_mmvec";
   35111 }
   35112 def V6_vrounduhub_alt : HInst<
   35113 (outs HvxVR:$Vd32),
   35114 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35115 "$Vd32 = vrounduhub($Vu32,$Vv32):sat",
   35116 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   35117 let hasNewValue = 1;
   35118 let opNewValue = 0;
   35119 let isPseudo = 1;
   35120 let isCodeGenOnly = 1;
   35121 let DecoderNamespace = "EXT_mmvec";
   35122 }
   35123 def V6_vrounduwuh : HInst<
   35124 (outs HvxVR:$Vd32),
   35125 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35126 "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
   35127 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
   35128 let Inst{7-5} = 0b100;
   35129 let Inst{13-13} = 0b0;
   35130 let Inst{31-21} = 0b00011111111;
   35131 let hasNewValue = 1;
   35132 let opNewValue = 0;
   35133 let DecoderNamespace = "EXT_mmvec";
   35134 }
   35135 def V6_vrounduwuh_alt : HInst<
   35136 (outs HvxVR:$Vd32),
   35137 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35138 "$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
   35139 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   35140 let hasNewValue = 1;
   35141 let opNewValue = 0;
   35142 let isPseudo = 1;
   35143 let isCodeGenOnly = 1;
   35144 let DecoderNamespace = "EXT_mmvec";
   35145 }
   35146 def V6_vroundwh : HInst<
   35147 (outs HvxVR:$Vd32),
   35148 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35149 "$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
   35150 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   35151 let Inst{7-5} = 0b100;
   35152 let Inst{13-13} = 0b0;
   35153 let Inst{31-21} = 0b00011111011;
   35154 let hasNewValue = 1;
   35155 let opNewValue = 0;
   35156 let DecoderNamespace = "EXT_mmvec";
   35157 }
   35158 def V6_vroundwh_alt : HInst<
   35159 (outs HvxVR:$Vd32),
   35160 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35161 "$Vd32 = vroundwh($Vu32,$Vv32):sat",
   35162 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35163 let hasNewValue = 1;
   35164 let opNewValue = 0;
   35165 let isPseudo = 1;
   35166 let isCodeGenOnly = 1;
   35167 let DecoderNamespace = "EXT_mmvec";
   35168 }
   35169 def V6_vroundwuh : HInst<
   35170 (outs HvxVR:$Vd32),
   35171 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35172 "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
   35173 tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
   35174 let Inst{7-5} = 0b101;
   35175 let Inst{13-13} = 0b0;
   35176 let Inst{31-21} = 0b00011111011;
   35177 let hasNewValue = 1;
   35178 let opNewValue = 0;
   35179 let DecoderNamespace = "EXT_mmvec";
   35180 }
   35181 def V6_vroundwuh_alt : HInst<
   35182 (outs HvxVR:$Vd32),
   35183 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35184 "$Vd32 = vroundwuh($Vu32,$Vv32):sat",
   35185 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35186 let hasNewValue = 1;
   35187 let opNewValue = 0;
   35188 let isPseudo = 1;
   35189 let isCodeGenOnly = 1;
   35190 let DecoderNamespace = "EXT_mmvec";
   35191 }
   35192 def V6_vrsadubi : HInst<
   35193 (outs HvxWR:$Vdd32),
   35194 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   35195 "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
   35196 tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
   35197 let Inst{7-6} = 0b11;
   35198 let Inst{13-13} = 0b0;
   35199 let Inst{31-21} = 0b00011001010;
   35200 let hasNewValue = 1;
   35201 let opNewValue = 0;
   35202 let DecoderNamespace = "EXT_mmvec";
   35203 }
   35204 def V6_vrsadubi_acc : HInst<
   35205 (outs HvxWR:$Vxx32),
   35206 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   35207 "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
   35208 tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
   35209 let Inst{7-6} = 0b11;
   35210 let Inst{13-13} = 0b1;
   35211 let Inst{31-21} = 0b00011001010;
   35212 let hasNewValue = 1;
   35213 let opNewValue = 0;
   35214 let isAccumulator = 1;
   35215 let DecoderNamespace = "EXT_mmvec";
   35216 let Constraints = "$Vxx32 = $Vxx32in";
   35217 }
   35218 def V6_vrsadubi_acc_alt : HInst<
   35219 (outs HvxWR:$Vxx32),
   35220 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   35221 "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
   35222 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35223 let hasNewValue = 1;
   35224 let opNewValue = 0;
   35225 let isAccumulator = 1;
   35226 let isPseudo = 1;
   35227 let isCodeGenOnly = 1;
   35228 let DecoderNamespace = "EXT_mmvec";
   35229 let Constraints = "$Vxx32 = $Vxx32in";
   35230 }
   35231 def V6_vrsadubi_alt : HInst<
   35232 (outs HvxWR:$Vdd32),
   35233 (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
   35234 "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
   35235 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35236 let hasNewValue = 1;
   35237 let opNewValue = 0;
   35238 let isPseudo = 1;
   35239 let isCodeGenOnly = 1;
   35240 let DecoderNamespace = "EXT_mmvec";
   35241 }
   35242 def V6_vsathub : HInst<
   35243 (outs HvxVR:$Vd32),
   35244 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35245 "$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
   35246 tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
   35247 let Inst{7-5} = 0b010;
   35248 let Inst{13-13} = 0b0;
   35249 let Inst{31-21} = 0b00011111011;
   35250 let hasNewValue = 1;
   35251 let opNewValue = 0;
   35252 let DecoderNamespace = "EXT_mmvec";
   35253 }
   35254 def V6_vsathub_alt : HInst<
   35255 (outs HvxVR:$Vd32),
   35256 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35257 "$Vd32 = vsathub($Vu32,$Vv32)",
   35258 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35259 let hasNewValue = 1;
   35260 let opNewValue = 0;
   35261 let isPseudo = 1;
   35262 let isCodeGenOnly = 1;
   35263 let DecoderNamespace = "EXT_mmvec";
   35264 }
   35265 def V6_vsatuwuh : HInst<
   35266 (outs HvxVR:$Vd32),
   35267 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35268 "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
   35269 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   35270 let Inst{7-5} = 0b110;
   35271 let Inst{13-13} = 0b0;
   35272 let Inst{31-21} = 0b00011111001;
   35273 let hasNewValue = 1;
   35274 let opNewValue = 0;
   35275 let DecoderNamespace = "EXT_mmvec";
   35276 }
   35277 def V6_vsatuwuh_alt : HInst<
   35278 (outs HvxVR:$Vd32),
   35279 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35280 "$Vd32 = vsatuwuh($Vu32,$Vv32)",
   35281 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   35282 let hasNewValue = 1;
   35283 let opNewValue = 0;
   35284 let isPseudo = 1;
   35285 let isCodeGenOnly = 1;
   35286 let DecoderNamespace = "EXT_mmvec";
   35287 }
   35288 def V6_vsatwh : HInst<
   35289 (outs HvxVR:$Vd32),
   35290 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35291 "$Vd32.h = vsat($Vu32.w,$Vv32.w)",
   35292 tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
   35293 let Inst{7-5} = 0b011;
   35294 let Inst{13-13} = 0b0;
   35295 let Inst{31-21} = 0b00011111011;
   35296 let hasNewValue = 1;
   35297 let opNewValue = 0;
   35298 let DecoderNamespace = "EXT_mmvec";
   35299 }
   35300 def V6_vsatwh_alt : HInst<
   35301 (outs HvxVR:$Vd32),
   35302 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35303 "$Vd32 = vsatwh($Vu32,$Vv32)",
   35304 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35305 let hasNewValue = 1;
   35306 let opNewValue = 0;
   35307 let isPseudo = 1;
   35308 let isCodeGenOnly = 1;
   35309 let DecoderNamespace = "EXT_mmvec";
   35310 }
   35311 def V6_vsb : HInst<
   35312 (outs HvxWR:$Vdd32),
   35313 (ins HvxVR:$Vu32),
   35314 "$Vdd32.h = vsxt($Vu32.b)",
   35315 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
   35316 let Inst{7-5} = 0b011;
   35317 let Inst{13-13} = 0b0;
   35318 let Inst{31-16} = 0b0001111000000010;
   35319 let hasNewValue = 1;
   35320 let opNewValue = 0;
   35321 let DecoderNamespace = "EXT_mmvec";
   35322 }
   35323 def V6_vsb_alt : HInst<
   35324 (outs HvxWR:$Vdd32),
   35325 (ins HvxVR:$Vu32),
   35326 "$Vdd32 = vsxtb($Vu32)",
   35327 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35328 let hasNewValue = 1;
   35329 let opNewValue = 0;
   35330 let isPseudo = 1;
   35331 let isCodeGenOnly = 1;
   35332 let DecoderNamespace = "EXT_mmvec";
   35333 }
   35334 def V6_vscattermh : HInst<
   35335 (outs),
   35336 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35337 "vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
   35338 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
   35339 let Inst{7-5} = 0b001;
   35340 let Inst{31-21} = 0b00101111001;
   35341 let accessSize = HalfWordAccess;
   35342 let mayStore = 1;
   35343 let DecoderNamespace = "EXT_mmvec";
   35344 }
   35345 def V6_vscattermh_add : HInst<
   35346 (outs),
   35347 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35348 "vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
   35349 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
   35350 let Inst{7-5} = 0b101;
   35351 let Inst{31-21} = 0b00101111001;
   35352 let accessSize = HalfWordAccess;
   35353 let isAccumulator = 1;
   35354 let mayStore = 1;
   35355 let DecoderNamespace = "EXT_mmvec";
   35356 }
   35357 def V6_vscattermh_add_alt : HInst<
   35358 (outs),
   35359 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35360 "vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
   35361 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35362 let isAccumulator = 1;
   35363 let isPseudo = 1;
   35364 let isCodeGenOnly = 1;
   35365 let DecoderNamespace = "EXT_mmvec";
   35366 }
   35367 def V6_vscattermh_alt : HInst<
   35368 (outs),
   35369 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35370 "vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
   35371 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35372 let isPseudo = 1;
   35373 let isCodeGenOnly = 1;
   35374 let DecoderNamespace = "EXT_mmvec";
   35375 }
   35376 def V6_vscattermhq : HInst<
   35377 (outs),
   35378 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35379 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
   35380 tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
   35381 let Inst{7-7} = 0b1;
   35382 let Inst{31-21} = 0b00101111100;
   35383 let accessSize = HalfWordAccess;
   35384 let mayStore = 1;
   35385 let DecoderNamespace = "EXT_mmvec";
   35386 }
   35387 def V6_vscattermhq_alt : HInst<
   35388 (outs),
   35389 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35390 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
   35391 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35392 let isPseudo = 1;
   35393 let isCodeGenOnly = 1;
   35394 let DecoderNamespace = "EXT_mmvec";
   35395 }
   35396 def V6_vscattermhw : HInst<
   35397 (outs),
   35398 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35399 "vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
   35400 tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
   35401 let Inst{7-5} = 0b010;
   35402 let Inst{31-21} = 0b00101111001;
   35403 let accessSize = HalfWordAccess;
   35404 let mayStore = 1;
   35405 let DecoderNamespace = "EXT_mmvec";
   35406 }
   35407 def V6_vscattermhw_add : HInst<
   35408 (outs),
   35409 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35410 "vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
   35411 tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
   35412 let Inst{7-5} = 0b110;
   35413 let Inst{31-21} = 0b00101111001;
   35414 let accessSize = HalfWordAccess;
   35415 let isAccumulator = 1;
   35416 let mayStore = 1;
   35417 let DecoderNamespace = "EXT_mmvec";
   35418 }
   35419 def V6_vscattermhwq : HInst<
   35420 (outs),
   35421 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35422 "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
   35423 tc_94f43c04, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
   35424 let Inst{7-7} = 0b0;
   35425 let Inst{31-21} = 0b00101111101;
   35426 let accessSize = HalfWordAccess;
   35427 let mayStore = 1;
   35428 let DecoderNamespace = "EXT_mmvec";
   35429 }
   35430 def V6_vscattermw : HInst<
   35431 (outs),
   35432 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35433 "vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
   35434 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
   35435 let Inst{7-5} = 0b000;
   35436 let Inst{31-21} = 0b00101111001;
   35437 let accessSize = WordAccess;
   35438 let mayStore = 1;
   35439 let DecoderNamespace = "EXT_mmvec";
   35440 }
   35441 def V6_vscattermw_add : HInst<
   35442 (outs),
   35443 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35444 "vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
   35445 tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
   35446 let Inst{7-5} = 0b100;
   35447 let Inst{31-21} = 0b00101111001;
   35448 let accessSize = WordAccess;
   35449 let isAccumulator = 1;
   35450 let mayStore = 1;
   35451 let DecoderNamespace = "EXT_mmvec";
   35452 }
   35453 def V6_vscattermw_add_alt : HInst<
   35454 (outs),
   35455 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35456 "vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
   35457 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35458 let isAccumulator = 1;
   35459 let isPseudo = 1;
   35460 let isCodeGenOnly = 1;
   35461 let DecoderNamespace = "EXT_mmvec";
   35462 }
   35463 def V6_vscattermw_alt : HInst<
   35464 (outs),
   35465 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35466 "vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
   35467 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35468 let isPseudo = 1;
   35469 let isCodeGenOnly = 1;
   35470 let DecoderNamespace = "EXT_mmvec";
   35471 }
   35472 def V6_vscattermwh_add_alt : HInst<
   35473 (outs),
   35474 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35475 "vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
   35476 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35477 let isAccumulator = 1;
   35478 let isPseudo = 1;
   35479 let isCodeGenOnly = 1;
   35480 let DecoderNamespace = "EXT_mmvec";
   35481 }
   35482 def V6_vscattermwh_alt : HInst<
   35483 (outs),
   35484 (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35485 "vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
   35486 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35487 let isPseudo = 1;
   35488 let isCodeGenOnly = 1;
   35489 let DecoderNamespace = "EXT_mmvec";
   35490 }
   35491 def V6_vscattermwhq_alt : HInst<
   35492 (outs),
   35493 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
   35494 "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
   35495 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35496 let isPseudo = 1;
   35497 let isCodeGenOnly = 1;
   35498 let DecoderNamespace = "EXT_mmvec";
   35499 }
   35500 def V6_vscattermwq : HInst<
   35501 (outs),
   35502 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35503 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
   35504 tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
   35505 let Inst{7-7} = 0b0;
   35506 let Inst{31-21} = 0b00101111100;
   35507 let accessSize = WordAccess;
   35508 let mayStore = 1;
   35509 let DecoderNamespace = "EXT_mmvec";
   35510 }
   35511 def V6_vscattermwq_alt : HInst<
   35512 (outs),
   35513 (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
   35514 "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
   35515 PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
   35516 let isPseudo = 1;
   35517 let isCodeGenOnly = 1;
   35518 let DecoderNamespace = "EXT_mmvec";
   35519 }
   35520 def V6_vsh : HInst<
   35521 (outs HvxWR:$Vdd32),
   35522 (ins HvxVR:$Vu32),
   35523 "$Vdd32.w = vsxt($Vu32.h)",
   35524 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
   35525 let Inst{7-5} = 0b100;
   35526 let Inst{13-13} = 0b0;
   35527 let Inst{31-16} = 0b0001111000000010;
   35528 let hasNewValue = 1;
   35529 let opNewValue = 0;
   35530 let DecoderNamespace = "EXT_mmvec";
   35531 }
   35532 def V6_vsh_alt : HInst<
   35533 (outs HvxWR:$Vdd32),
   35534 (ins HvxVR:$Vu32),
   35535 "$Vdd32 = vsxth($Vu32)",
   35536 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35537 let hasNewValue = 1;
   35538 let opNewValue = 0;
   35539 let isPseudo = 1;
   35540 let isCodeGenOnly = 1;
   35541 let DecoderNamespace = "EXT_mmvec";
   35542 }
   35543 def V6_vshufeh : HInst<
   35544 (outs HvxVR:$Vd32),
   35545 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35546 "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
   35547 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35548 let Inst{7-5} = 0b011;
   35549 let Inst{13-13} = 0b0;
   35550 let Inst{31-21} = 0b00011111010;
   35551 let hasNewValue = 1;
   35552 let opNewValue = 0;
   35553 let DecoderNamespace = "EXT_mmvec";
   35554 }
   35555 def V6_vshufeh_alt : HInst<
   35556 (outs HvxVR:$Vd32),
   35557 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35558 "$Vd32 = vshuffeh($Vu32,$Vv32)",
   35559 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35560 let hasNewValue = 1;
   35561 let opNewValue = 0;
   35562 let isPseudo = 1;
   35563 let isCodeGenOnly = 1;
   35564 let DecoderNamespace = "EXT_mmvec";
   35565 }
   35566 def V6_vshuff : HInst<
   35567 (outs HvxVR:$Vy32, HvxVR:$Vx32),
   35568 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
   35569 "vshuff($Vy32,$Vx32,$Rt32)",
   35570 tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
   35571 let Inst{7-5} = 0b001;
   35572 let Inst{13-13} = 0b1;
   35573 let Inst{31-21} = 0b00011001111;
   35574 let hasNewValue = 1;
   35575 let opNewValue = 0;
   35576 let hasNewValue2 = 1;
   35577 let opNewValue2 = 1;
   35578 let DecoderNamespace = "EXT_mmvec";
   35579 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
   35580 }
   35581 def V6_vshuffb : HInst<
   35582 (outs HvxVR:$Vd32),
   35583 (ins HvxVR:$Vu32),
   35584 "$Vd32.b = vshuff($Vu32.b)",
   35585 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
   35586 let Inst{7-5} = 0b000;
   35587 let Inst{13-13} = 0b0;
   35588 let Inst{31-16} = 0b0001111000000010;
   35589 let hasNewValue = 1;
   35590 let opNewValue = 0;
   35591 let DecoderNamespace = "EXT_mmvec";
   35592 }
   35593 def V6_vshuffb_alt : HInst<
   35594 (outs HvxVR:$Vd32),
   35595 (ins HvxVR:$Vu32),
   35596 "$Vd32 = vshuffb($Vu32)",
   35597 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35598 let hasNewValue = 1;
   35599 let opNewValue = 0;
   35600 let isPseudo = 1;
   35601 let isCodeGenOnly = 1;
   35602 let DecoderNamespace = "EXT_mmvec";
   35603 }
   35604 def V6_vshuffeb : HInst<
   35605 (outs HvxVR:$Vd32),
   35606 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35607 "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
   35608 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35609 let Inst{7-5} = 0b001;
   35610 let Inst{13-13} = 0b0;
   35611 let Inst{31-21} = 0b00011111010;
   35612 let hasNewValue = 1;
   35613 let opNewValue = 0;
   35614 let DecoderNamespace = "EXT_mmvec";
   35615 }
   35616 def V6_vshuffeb_alt : HInst<
   35617 (outs HvxVR:$Vd32),
   35618 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35619 "$Vd32 = vshuffeb($Vu32,$Vv32)",
   35620 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35621 let hasNewValue = 1;
   35622 let opNewValue = 0;
   35623 let isPseudo = 1;
   35624 let isCodeGenOnly = 1;
   35625 let DecoderNamespace = "EXT_mmvec";
   35626 }
   35627 def V6_vshuffh : HInst<
   35628 (outs HvxVR:$Vd32),
   35629 (ins HvxVR:$Vu32),
   35630 "$Vd32.h = vshuff($Vu32.h)",
   35631 tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
   35632 let Inst{7-5} = 0b111;
   35633 let Inst{13-13} = 0b0;
   35634 let Inst{31-16} = 0b0001111000000001;
   35635 let hasNewValue = 1;
   35636 let opNewValue = 0;
   35637 let DecoderNamespace = "EXT_mmvec";
   35638 }
   35639 def V6_vshuffh_alt : HInst<
   35640 (outs HvxVR:$Vd32),
   35641 (ins HvxVR:$Vu32),
   35642 "$Vd32 = vshuffh($Vu32)",
   35643 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35644 let hasNewValue = 1;
   35645 let opNewValue = 0;
   35646 let isPseudo = 1;
   35647 let isCodeGenOnly = 1;
   35648 let DecoderNamespace = "EXT_mmvec";
   35649 }
   35650 def V6_vshuffob : HInst<
   35651 (outs HvxVR:$Vd32),
   35652 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35653 "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
   35654 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35655 let Inst{7-5} = 0b010;
   35656 let Inst{13-13} = 0b0;
   35657 let Inst{31-21} = 0b00011111010;
   35658 let hasNewValue = 1;
   35659 let opNewValue = 0;
   35660 let DecoderNamespace = "EXT_mmvec";
   35661 }
   35662 def V6_vshuffob_alt : HInst<
   35663 (outs HvxVR:$Vd32),
   35664 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35665 "$Vd32 = vshuffob($Vu32,$Vv32)",
   35666 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35667 let hasNewValue = 1;
   35668 let opNewValue = 0;
   35669 let isPseudo = 1;
   35670 let isCodeGenOnly = 1;
   35671 let DecoderNamespace = "EXT_mmvec";
   35672 }
   35673 def V6_vshuffvdd : HInst<
   35674 (outs HvxWR:$Vdd32),
   35675 (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
   35676 "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
   35677 tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
   35678 let Inst{7-5} = 0b011;
   35679 let Inst{13-13} = 0b1;
   35680 let Inst{31-24} = 0b00011011;
   35681 let hasNewValue = 1;
   35682 let opNewValue = 0;
   35683 let DecoderNamespace = "EXT_mmvec";
   35684 }
   35685 def V6_vshufoeb : HInst<
   35686 (outs HvxWR:$Vdd32),
   35687 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35688 "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
   35689 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   35690 let Inst{7-5} = 0b110;
   35691 let Inst{13-13} = 0b0;
   35692 let Inst{31-21} = 0b00011111010;
   35693 let hasNewValue = 1;
   35694 let opNewValue = 0;
   35695 let DecoderNamespace = "EXT_mmvec";
   35696 }
   35697 def V6_vshufoeb_alt : HInst<
   35698 (outs HvxWR:$Vdd32),
   35699 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35700 "$Vdd32 = vshuffoeb($Vu32,$Vv32)",
   35701 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35702 let hasNewValue = 1;
   35703 let opNewValue = 0;
   35704 let isPseudo = 1;
   35705 let isCodeGenOnly = 1;
   35706 let DecoderNamespace = "EXT_mmvec";
   35707 }
   35708 def V6_vshufoeh : HInst<
   35709 (outs HvxWR:$Vdd32),
   35710 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35711 "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
   35712 tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   35713 let Inst{7-5} = 0b101;
   35714 let Inst{13-13} = 0b0;
   35715 let Inst{31-21} = 0b00011111010;
   35716 let hasNewValue = 1;
   35717 let opNewValue = 0;
   35718 let DecoderNamespace = "EXT_mmvec";
   35719 }
   35720 def V6_vshufoeh_alt : HInst<
   35721 (outs HvxWR:$Vdd32),
   35722 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35723 "$Vdd32 = vshuffoeh($Vu32,$Vv32)",
   35724 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35725 let hasNewValue = 1;
   35726 let opNewValue = 0;
   35727 let isPseudo = 1;
   35728 let isCodeGenOnly = 1;
   35729 let DecoderNamespace = "EXT_mmvec";
   35730 }
   35731 def V6_vshufoh : HInst<
   35732 (outs HvxVR:$Vd32),
   35733 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35734 "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
   35735 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35736 let Inst{7-5} = 0b100;
   35737 let Inst{13-13} = 0b0;
   35738 let Inst{31-21} = 0b00011111010;
   35739 let hasNewValue = 1;
   35740 let opNewValue = 0;
   35741 let DecoderNamespace = "EXT_mmvec";
   35742 }
   35743 def V6_vshufoh_alt : HInst<
   35744 (outs HvxVR:$Vd32),
   35745 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35746 "$Vd32 = vshuffoh($Vu32,$Vv32)",
   35747 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35748 let hasNewValue = 1;
   35749 let opNewValue = 0;
   35750 let isPseudo = 1;
   35751 let isCodeGenOnly = 1;
   35752 let DecoderNamespace = "EXT_mmvec";
   35753 }
   35754 def V6_vsubb : HInst<
   35755 (outs HvxVR:$Vd32),
   35756 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35757 "$Vd32.b = vsub($Vu32.b,$Vv32.b)",
   35758 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35759 let Inst{7-5} = 0b101;
   35760 let Inst{13-13} = 0b0;
   35761 let Inst{31-21} = 0b00011100010;
   35762 let hasNewValue = 1;
   35763 let opNewValue = 0;
   35764 let DecoderNamespace = "EXT_mmvec";
   35765 }
   35766 def V6_vsubb_alt : HInst<
   35767 (outs HvxVR:$Vd32),
   35768 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35769 "$Vd32 = vsubb($Vu32,$Vv32)",
   35770 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35771 let hasNewValue = 1;
   35772 let opNewValue = 0;
   35773 let isPseudo = 1;
   35774 let isCodeGenOnly = 1;
   35775 let DecoderNamespace = "EXT_mmvec";
   35776 }
   35777 def V6_vsubb_dv : HInst<
   35778 (outs HvxWR:$Vdd32),
   35779 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35780 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
   35781 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   35782 let Inst{7-5} = 0b011;
   35783 let Inst{13-13} = 0b0;
   35784 let Inst{31-21} = 0b00011100100;
   35785 let hasNewValue = 1;
   35786 let opNewValue = 0;
   35787 let DecoderNamespace = "EXT_mmvec";
   35788 }
   35789 def V6_vsubb_dv_alt : HInst<
   35790 (outs HvxWR:$Vdd32),
   35791 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35792 "$Vdd32 = vsubb($Vuu32,$Vvv32)",
   35793 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35794 let hasNewValue = 1;
   35795 let opNewValue = 0;
   35796 let isPseudo = 1;
   35797 let isCodeGenOnly = 1;
   35798 let DecoderNamespace = "EXT_mmvec";
   35799 }
   35800 def V6_vsubbnq : HInst<
   35801 (outs HvxVR:$Vx32),
   35802 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35803 "if (!$Qv4) $Vx32.b -= $Vu32.b",
   35804 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   35805 let Inst{7-5} = 0b001;
   35806 let Inst{13-13} = 0b1;
   35807 let Inst{21-16} = 0b000010;
   35808 let Inst{31-24} = 0b00011110;
   35809 let hasNewValue = 1;
   35810 let opNewValue = 0;
   35811 let DecoderNamespace = "EXT_mmvec";
   35812 let Constraints = "$Vx32 = $Vx32in";
   35813 }
   35814 def V6_vsubbnq_alt : HInst<
   35815 (outs HvxVR:$Vx32),
   35816 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35817 "if (!$Qv4.b) $Vx32.b -= $Vu32.b",
   35818 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35819 let hasNewValue = 1;
   35820 let opNewValue = 0;
   35821 let isPseudo = 1;
   35822 let isCodeGenOnly = 1;
   35823 let DecoderNamespace = "EXT_mmvec";
   35824 let Constraints = "$Vx32 = $Vx32in";
   35825 }
   35826 def V6_vsubbq : HInst<
   35827 (outs HvxVR:$Vx32),
   35828 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35829 "if ($Qv4) $Vx32.b -= $Vu32.b",
   35830 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   35831 let Inst{7-5} = 0b110;
   35832 let Inst{13-13} = 0b1;
   35833 let Inst{21-16} = 0b000001;
   35834 let Inst{31-24} = 0b00011110;
   35835 let hasNewValue = 1;
   35836 let opNewValue = 0;
   35837 let DecoderNamespace = "EXT_mmvec";
   35838 let Constraints = "$Vx32 = $Vx32in";
   35839 }
   35840 def V6_vsubbq_alt : HInst<
   35841 (outs HvxVR:$Vx32),
   35842 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35843 "if ($Qv4.b) $Vx32.b -= $Vu32.b",
   35844 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35845 let hasNewValue = 1;
   35846 let opNewValue = 0;
   35847 let isPseudo = 1;
   35848 let isCodeGenOnly = 1;
   35849 let DecoderNamespace = "EXT_mmvec";
   35850 let Constraints = "$Vx32 = $Vx32in";
   35851 }
   35852 def V6_vsubbsat : HInst<
   35853 (outs HvxVR:$Vd32),
   35854 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35855 "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
   35856 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   35857 let Inst{7-5} = 0b010;
   35858 let Inst{13-13} = 0b0;
   35859 let Inst{31-21} = 0b00011111001;
   35860 let hasNewValue = 1;
   35861 let opNewValue = 0;
   35862 let DecoderNamespace = "EXT_mmvec";
   35863 }
   35864 def V6_vsubbsat_alt : HInst<
   35865 (outs HvxVR:$Vd32),
   35866 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35867 "$Vd32 = vsubb($Vu32,$Vv32):sat",
   35868 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   35869 let hasNewValue = 1;
   35870 let opNewValue = 0;
   35871 let isPseudo = 1;
   35872 let isCodeGenOnly = 1;
   35873 let DecoderNamespace = "EXT_mmvec";
   35874 }
   35875 def V6_vsubbsat_dv : HInst<
   35876 (outs HvxWR:$Vdd32),
   35877 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35878 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
   35879 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
   35880 let Inst{7-5} = 0b001;
   35881 let Inst{13-13} = 0b0;
   35882 let Inst{31-21} = 0b00011110101;
   35883 let hasNewValue = 1;
   35884 let opNewValue = 0;
   35885 let DecoderNamespace = "EXT_mmvec";
   35886 }
   35887 def V6_vsubbsat_dv_alt : HInst<
   35888 (outs HvxWR:$Vdd32),
   35889 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35890 "$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
   35891 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   35892 let hasNewValue = 1;
   35893 let opNewValue = 0;
   35894 let isPseudo = 1;
   35895 let isCodeGenOnly = 1;
   35896 let DecoderNamespace = "EXT_mmvec";
   35897 }
   35898 def V6_vsubcarry : HInst<
   35899 (outs HvxVR:$Vd32, HvxQR:$Qx4),
   35900 (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
   35901 "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
   35902 tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
   35903 let Inst{7-7} = 0b1;
   35904 let Inst{13-13} = 0b1;
   35905 let Inst{31-21} = 0b00011100101;
   35906 let hasNewValue = 1;
   35907 let opNewValue = 0;
   35908 let DecoderNamespace = "EXT_mmvec";
   35909 let Constraints = "$Qx4 = $Qx4in";
   35910 }
   35911 def V6_vsubh : HInst<
   35912 (outs HvxVR:$Vd32),
   35913 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35914 "$Vd32.h = vsub($Vu32.h,$Vv32.h)",
   35915 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   35916 let Inst{7-5} = 0b110;
   35917 let Inst{13-13} = 0b0;
   35918 let Inst{31-21} = 0b00011100010;
   35919 let hasNewValue = 1;
   35920 let opNewValue = 0;
   35921 let DecoderNamespace = "EXT_mmvec";
   35922 }
   35923 def V6_vsubh_alt : HInst<
   35924 (outs HvxVR:$Vd32),
   35925 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   35926 "$Vd32 = vsubh($Vu32,$Vv32)",
   35927 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35928 let hasNewValue = 1;
   35929 let opNewValue = 0;
   35930 let isPseudo = 1;
   35931 let isCodeGenOnly = 1;
   35932 let DecoderNamespace = "EXT_mmvec";
   35933 }
   35934 def V6_vsubh_dv : HInst<
   35935 (outs HvxWR:$Vdd32),
   35936 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35937 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
   35938 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   35939 let Inst{7-5} = 0b100;
   35940 let Inst{13-13} = 0b0;
   35941 let Inst{31-21} = 0b00011100100;
   35942 let hasNewValue = 1;
   35943 let opNewValue = 0;
   35944 let DecoderNamespace = "EXT_mmvec";
   35945 }
   35946 def V6_vsubh_dv_alt : HInst<
   35947 (outs HvxWR:$Vdd32),
   35948 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   35949 "$Vdd32 = vsubh($Vuu32,$Vvv32)",
   35950 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35951 let hasNewValue = 1;
   35952 let opNewValue = 0;
   35953 let isPseudo = 1;
   35954 let isCodeGenOnly = 1;
   35955 let DecoderNamespace = "EXT_mmvec";
   35956 }
   35957 def V6_vsubhnq : HInst<
   35958 (outs HvxVR:$Vx32),
   35959 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35960 "if (!$Qv4) $Vx32.h -= $Vu32.h",
   35961 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   35962 let Inst{7-5} = 0b010;
   35963 let Inst{13-13} = 0b1;
   35964 let Inst{21-16} = 0b000010;
   35965 let Inst{31-24} = 0b00011110;
   35966 let hasNewValue = 1;
   35967 let opNewValue = 0;
   35968 let DecoderNamespace = "EXT_mmvec";
   35969 let Constraints = "$Vx32 = $Vx32in";
   35970 }
   35971 def V6_vsubhnq_alt : HInst<
   35972 (outs HvxVR:$Vx32),
   35973 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35974 "if (!$Qv4.h) $Vx32.h -= $Vu32.h",
   35975 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   35976 let hasNewValue = 1;
   35977 let opNewValue = 0;
   35978 let isPseudo = 1;
   35979 let isCodeGenOnly = 1;
   35980 let DecoderNamespace = "EXT_mmvec";
   35981 let Constraints = "$Vx32 = $Vx32in";
   35982 }
   35983 def V6_vsubhq : HInst<
   35984 (outs HvxVR:$Vx32),
   35985 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   35986 "if ($Qv4) $Vx32.h -= $Vu32.h",
   35987 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   35988 let Inst{7-5} = 0b111;
   35989 let Inst{13-13} = 0b1;
   35990 let Inst{21-16} = 0b000001;
   35991 let Inst{31-24} = 0b00011110;
   35992 let hasNewValue = 1;
   35993 let opNewValue = 0;
   35994 let DecoderNamespace = "EXT_mmvec";
   35995 let Constraints = "$Vx32 = $Vx32in";
   35996 }
   35997 def V6_vsubhq_alt : HInst<
   35998 (outs HvxVR:$Vx32),
   35999 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   36000 "if ($Qv4.h) $Vx32.h -= $Vu32.h",
   36001 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36002 let hasNewValue = 1;
   36003 let opNewValue = 0;
   36004 let isPseudo = 1;
   36005 let isCodeGenOnly = 1;
   36006 let DecoderNamespace = "EXT_mmvec";
   36007 let Constraints = "$Vx32 = $Vx32in";
   36008 }
   36009 def V6_vsubhsat : HInst<
   36010 (outs HvxVR:$Vd32),
   36011 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36012 "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
   36013 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36014 let Inst{7-5} = 0b010;
   36015 let Inst{13-13} = 0b0;
   36016 let Inst{31-21} = 0b00011100011;
   36017 let hasNewValue = 1;
   36018 let opNewValue = 0;
   36019 let DecoderNamespace = "EXT_mmvec";
   36020 }
   36021 def V6_vsubhsat_alt : HInst<
   36022 (outs HvxVR:$Vd32),
   36023 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36024 "$Vd32 = vsubh($Vu32,$Vv32):sat",
   36025 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36026 let hasNewValue = 1;
   36027 let opNewValue = 0;
   36028 let isPseudo = 1;
   36029 let isCodeGenOnly = 1;
   36030 let DecoderNamespace = "EXT_mmvec";
   36031 }
   36032 def V6_vsubhsat_dv : HInst<
   36033 (outs HvxWR:$Vdd32),
   36034 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36035 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
   36036 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   36037 let Inst{7-5} = 0b000;
   36038 let Inst{13-13} = 0b0;
   36039 let Inst{31-21} = 0b00011100101;
   36040 let hasNewValue = 1;
   36041 let opNewValue = 0;
   36042 let DecoderNamespace = "EXT_mmvec";
   36043 }
   36044 def V6_vsubhsat_dv_alt : HInst<
   36045 (outs HvxWR:$Vdd32),
   36046 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36047 "$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
   36048 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36049 let hasNewValue = 1;
   36050 let opNewValue = 0;
   36051 let isPseudo = 1;
   36052 let isCodeGenOnly = 1;
   36053 let DecoderNamespace = "EXT_mmvec";
   36054 }
   36055 def V6_vsubhw : HInst<
   36056 (outs HvxWR:$Vdd32),
   36057 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36058 "$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
   36059 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   36060 let Inst{7-5} = 0b111;
   36061 let Inst{13-13} = 0b0;
   36062 let Inst{31-21} = 0b00011100101;
   36063 let hasNewValue = 1;
   36064 let opNewValue = 0;
   36065 let DecoderNamespace = "EXT_mmvec";
   36066 }
   36067 def V6_vsubhw_alt : HInst<
   36068 (outs HvxWR:$Vdd32),
   36069 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36070 "$Vdd32 = vsubh($Vu32,$Vv32)",
   36071 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36072 let hasNewValue = 1;
   36073 let opNewValue = 0;
   36074 let isPseudo = 1;
   36075 let isCodeGenOnly = 1;
   36076 let DecoderNamespace = "EXT_mmvec";
   36077 }
   36078 def V6_vsububh : HInst<
   36079 (outs HvxWR:$Vdd32),
   36080 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36081 "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
   36082 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   36083 let Inst{7-5} = 0b101;
   36084 let Inst{13-13} = 0b0;
   36085 let Inst{31-21} = 0b00011100101;
   36086 let hasNewValue = 1;
   36087 let opNewValue = 0;
   36088 let DecoderNamespace = "EXT_mmvec";
   36089 }
   36090 def V6_vsububh_alt : HInst<
   36091 (outs HvxWR:$Vdd32),
   36092 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36093 "$Vdd32 = vsubub($Vu32,$Vv32)",
   36094 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36095 let hasNewValue = 1;
   36096 let opNewValue = 0;
   36097 let isPseudo = 1;
   36098 let isCodeGenOnly = 1;
   36099 let DecoderNamespace = "EXT_mmvec";
   36100 }
   36101 def V6_vsububsat : HInst<
   36102 (outs HvxVR:$Vd32),
   36103 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36104 "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
   36105 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36106 let Inst{7-5} = 0b000;
   36107 let Inst{13-13} = 0b0;
   36108 let Inst{31-21} = 0b00011100011;
   36109 let hasNewValue = 1;
   36110 let opNewValue = 0;
   36111 let DecoderNamespace = "EXT_mmvec";
   36112 }
   36113 def V6_vsububsat_alt : HInst<
   36114 (outs HvxVR:$Vd32),
   36115 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36116 "$Vd32 = vsubub($Vu32,$Vv32):sat",
   36117 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36118 let hasNewValue = 1;
   36119 let opNewValue = 0;
   36120 let isPseudo = 1;
   36121 let isCodeGenOnly = 1;
   36122 let DecoderNamespace = "EXT_mmvec";
   36123 }
   36124 def V6_vsububsat_dv : HInst<
   36125 (outs HvxWR:$Vdd32),
   36126 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36127 "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
   36128 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   36129 let Inst{7-5} = 0b110;
   36130 let Inst{13-13} = 0b0;
   36131 let Inst{31-21} = 0b00011100100;
   36132 let hasNewValue = 1;
   36133 let opNewValue = 0;
   36134 let DecoderNamespace = "EXT_mmvec";
   36135 }
   36136 def V6_vsububsat_dv_alt : HInst<
   36137 (outs HvxWR:$Vdd32),
   36138 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36139 "$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
   36140 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36141 let hasNewValue = 1;
   36142 let opNewValue = 0;
   36143 let isPseudo = 1;
   36144 let isCodeGenOnly = 1;
   36145 let DecoderNamespace = "EXT_mmvec";
   36146 }
   36147 def V6_vsubububb_sat : HInst<
   36148 (outs HvxVR:$Vd32),
   36149 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36150 "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
   36151 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   36152 let Inst{7-5} = 0b101;
   36153 let Inst{13-13} = 0b0;
   36154 let Inst{31-21} = 0b00011110101;
   36155 let hasNewValue = 1;
   36156 let opNewValue = 0;
   36157 let DecoderNamespace = "EXT_mmvec";
   36158 }
   36159 def V6_vsubuhsat : HInst<
   36160 (outs HvxVR:$Vd32),
   36161 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36162 "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
   36163 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36164 let Inst{7-5} = 0b001;
   36165 let Inst{13-13} = 0b0;
   36166 let Inst{31-21} = 0b00011100011;
   36167 let hasNewValue = 1;
   36168 let opNewValue = 0;
   36169 let DecoderNamespace = "EXT_mmvec";
   36170 }
   36171 def V6_vsubuhsat_alt : HInst<
   36172 (outs HvxVR:$Vd32),
   36173 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36174 "$Vd32 = vsubuh($Vu32,$Vv32):sat",
   36175 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36176 let hasNewValue = 1;
   36177 let opNewValue = 0;
   36178 let isPseudo = 1;
   36179 let isCodeGenOnly = 1;
   36180 let DecoderNamespace = "EXT_mmvec";
   36181 }
   36182 def V6_vsubuhsat_dv : HInst<
   36183 (outs HvxWR:$Vdd32),
   36184 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36185 "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
   36186 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   36187 let Inst{7-5} = 0b111;
   36188 let Inst{13-13} = 0b0;
   36189 let Inst{31-21} = 0b00011100100;
   36190 let hasNewValue = 1;
   36191 let opNewValue = 0;
   36192 let DecoderNamespace = "EXT_mmvec";
   36193 }
   36194 def V6_vsubuhsat_dv_alt : HInst<
   36195 (outs HvxWR:$Vdd32),
   36196 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36197 "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
   36198 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36199 let hasNewValue = 1;
   36200 let opNewValue = 0;
   36201 let isPseudo = 1;
   36202 let isCodeGenOnly = 1;
   36203 let DecoderNamespace = "EXT_mmvec";
   36204 }
   36205 def V6_vsubuhw : HInst<
   36206 (outs HvxWR:$Vdd32),
   36207 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36208 "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
   36209 tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
   36210 let Inst{7-5} = 0b110;
   36211 let Inst{13-13} = 0b0;
   36212 let Inst{31-21} = 0b00011100101;
   36213 let hasNewValue = 1;
   36214 let opNewValue = 0;
   36215 let DecoderNamespace = "EXT_mmvec";
   36216 }
   36217 def V6_vsubuhw_alt : HInst<
   36218 (outs HvxWR:$Vdd32),
   36219 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36220 "$Vdd32 = vsubuh($Vu32,$Vv32)",
   36221 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36222 let hasNewValue = 1;
   36223 let opNewValue = 0;
   36224 let isPseudo = 1;
   36225 let isCodeGenOnly = 1;
   36226 let DecoderNamespace = "EXT_mmvec";
   36227 }
   36228 def V6_vsubuwsat : HInst<
   36229 (outs HvxVR:$Vd32),
   36230 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36231 "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
   36232 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
   36233 let Inst{7-5} = 0b100;
   36234 let Inst{13-13} = 0b0;
   36235 let Inst{31-21} = 0b00011111110;
   36236 let hasNewValue = 1;
   36237 let opNewValue = 0;
   36238 let DecoderNamespace = "EXT_mmvec";
   36239 }
   36240 def V6_vsubuwsat_alt : HInst<
   36241 (outs HvxVR:$Vd32),
   36242 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36243 "$Vd32 = vsubuw($Vu32,$Vv32):sat",
   36244 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   36245 let hasNewValue = 1;
   36246 let opNewValue = 0;
   36247 let isPseudo = 1;
   36248 let isCodeGenOnly = 1;
   36249 let DecoderNamespace = "EXT_mmvec";
   36250 }
   36251 def V6_vsubuwsat_dv : HInst<
   36252 (outs HvxWR:$Vdd32),
   36253 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36254 "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
   36255 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
   36256 let Inst{7-5} = 0b011;
   36257 let Inst{13-13} = 0b0;
   36258 let Inst{31-21} = 0b00011110101;
   36259 let hasNewValue = 1;
   36260 let opNewValue = 0;
   36261 let DecoderNamespace = "EXT_mmvec";
   36262 }
   36263 def V6_vsubuwsat_dv_alt : HInst<
   36264 (outs HvxWR:$Vdd32),
   36265 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36266 "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
   36267 PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
   36268 let hasNewValue = 1;
   36269 let opNewValue = 0;
   36270 let isPseudo = 1;
   36271 let isCodeGenOnly = 1;
   36272 let DecoderNamespace = "EXT_mmvec";
   36273 }
   36274 def V6_vsubw : HInst<
   36275 (outs HvxVR:$Vd32),
   36276 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36277 "$Vd32.w = vsub($Vu32.w,$Vv32.w)",
   36278 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36279 let Inst{7-5} = 0b111;
   36280 let Inst{13-13} = 0b0;
   36281 let Inst{31-21} = 0b00011100010;
   36282 let hasNewValue = 1;
   36283 let opNewValue = 0;
   36284 let DecoderNamespace = "EXT_mmvec";
   36285 }
   36286 def V6_vsubw_alt : HInst<
   36287 (outs HvxVR:$Vd32),
   36288 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36289 "$Vd32 = vsubw($Vu32,$Vv32)",
   36290 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36291 let hasNewValue = 1;
   36292 let opNewValue = 0;
   36293 let isPseudo = 1;
   36294 let isCodeGenOnly = 1;
   36295 let DecoderNamespace = "EXT_mmvec";
   36296 }
   36297 def V6_vsubw_dv : HInst<
   36298 (outs HvxWR:$Vdd32),
   36299 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36300 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
   36301 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   36302 let Inst{7-5} = 0b101;
   36303 let Inst{13-13} = 0b0;
   36304 let Inst{31-21} = 0b00011100100;
   36305 let hasNewValue = 1;
   36306 let opNewValue = 0;
   36307 let DecoderNamespace = "EXT_mmvec";
   36308 }
   36309 def V6_vsubw_dv_alt : HInst<
   36310 (outs HvxWR:$Vdd32),
   36311 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36312 "$Vdd32 = vsubw($Vuu32,$Vvv32)",
   36313 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36314 let hasNewValue = 1;
   36315 let opNewValue = 0;
   36316 let isPseudo = 1;
   36317 let isCodeGenOnly = 1;
   36318 let DecoderNamespace = "EXT_mmvec";
   36319 }
   36320 def V6_vsubwnq : HInst<
   36321 (outs HvxVR:$Vx32),
   36322 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   36323 "if (!$Qv4) $Vx32.w -= $Vu32.w",
   36324 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   36325 let Inst{7-5} = 0b011;
   36326 let Inst{13-13} = 0b1;
   36327 let Inst{21-16} = 0b000010;
   36328 let Inst{31-24} = 0b00011110;
   36329 let hasNewValue = 1;
   36330 let opNewValue = 0;
   36331 let DecoderNamespace = "EXT_mmvec";
   36332 let Constraints = "$Vx32 = $Vx32in";
   36333 }
   36334 def V6_vsubwnq_alt : HInst<
   36335 (outs HvxVR:$Vx32),
   36336 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   36337 "if (!$Qv4.w) $Vx32.w -= $Vu32.w",
   36338 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36339 let hasNewValue = 1;
   36340 let opNewValue = 0;
   36341 let isPseudo = 1;
   36342 let isCodeGenOnly = 1;
   36343 let DecoderNamespace = "EXT_mmvec";
   36344 let Constraints = "$Vx32 = $Vx32in";
   36345 }
   36346 def V6_vsubwq : HInst<
   36347 (outs HvxVR:$Vx32),
   36348 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   36349 "if ($Qv4) $Vx32.w -= $Vu32.w",
   36350 tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
   36351 let Inst{7-5} = 0b000;
   36352 let Inst{13-13} = 0b1;
   36353 let Inst{21-16} = 0b000010;
   36354 let Inst{31-24} = 0b00011110;
   36355 let hasNewValue = 1;
   36356 let opNewValue = 0;
   36357 let DecoderNamespace = "EXT_mmvec";
   36358 let Constraints = "$Vx32 = $Vx32in";
   36359 }
   36360 def V6_vsubwq_alt : HInst<
   36361 (outs HvxVR:$Vx32),
   36362 (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
   36363 "if ($Qv4.w) $Vx32.w -= $Vu32.w",
   36364 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36365 let hasNewValue = 1;
   36366 let opNewValue = 0;
   36367 let isPseudo = 1;
   36368 let isCodeGenOnly = 1;
   36369 let DecoderNamespace = "EXT_mmvec";
   36370 let Constraints = "$Vx32 = $Vx32in";
   36371 }
   36372 def V6_vsubwsat : HInst<
   36373 (outs HvxVR:$Vd32),
   36374 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36375 "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
   36376 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36377 let Inst{7-5} = 0b011;
   36378 let Inst{13-13} = 0b0;
   36379 let Inst{31-21} = 0b00011100011;
   36380 let hasNewValue = 1;
   36381 let opNewValue = 0;
   36382 let DecoderNamespace = "EXT_mmvec";
   36383 }
   36384 def V6_vsubwsat_alt : HInst<
   36385 (outs HvxVR:$Vd32),
   36386 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36387 "$Vd32 = vsubw($Vu32,$Vv32):sat",
   36388 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36389 let hasNewValue = 1;
   36390 let opNewValue = 0;
   36391 let isPseudo = 1;
   36392 let isCodeGenOnly = 1;
   36393 let DecoderNamespace = "EXT_mmvec";
   36394 }
   36395 def V6_vsubwsat_dv : HInst<
   36396 (outs HvxWR:$Vdd32),
   36397 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36398 "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
   36399 tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
   36400 let Inst{7-5} = 0b001;
   36401 let Inst{13-13} = 0b0;
   36402 let Inst{31-21} = 0b00011100101;
   36403 let hasNewValue = 1;
   36404 let opNewValue = 0;
   36405 let DecoderNamespace = "EXT_mmvec";
   36406 }
   36407 def V6_vsubwsat_dv_alt : HInst<
   36408 (outs HvxWR:$Vdd32),
   36409 (ins HvxWR:$Vuu32, HvxWR:$Vvv32),
   36410 "$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
   36411 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36412 let hasNewValue = 1;
   36413 let opNewValue = 0;
   36414 let isPseudo = 1;
   36415 let isCodeGenOnly = 1;
   36416 let DecoderNamespace = "EXT_mmvec";
   36417 }
   36418 def V6_vswap : HInst<
   36419 (outs HvxWR:$Vdd32),
   36420 (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
   36421 "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
   36422 tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
   36423 let Inst{7-7} = 0b0;
   36424 let Inst{13-13} = 0b1;
   36425 let Inst{31-21} = 0b00011110101;
   36426 let hasNewValue = 1;
   36427 let opNewValue = 0;
   36428 let DecoderNamespace = "EXT_mmvec";
   36429 }
   36430 def V6_vtmpyb : HInst<
   36431 (outs HvxWR:$Vdd32),
   36432 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36433 "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
   36434 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   36435 let Inst{7-5} = 0b000;
   36436 let Inst{13-13} = 0b0;
   36437 let Inst{31-21} = 0b00011001000;
   36438 let hasNewValue = 1;
   36439 let opNewValue = 0;
   36440 let DecoderNamespace = "EXT_mmvec";
   36441 }
   36442 def V6_vtmpyb_acc : HInst<
   36443 (outs HvxWR:$Vxx32),
   36444 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36445 "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
   36446 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   36447 let Inst{7-5} = 0b000;
   36448 let Inst{13-13} = 0b1;
   36449 let Inst{31-21} = 0b00011001000;
   36450 let hasNewValue = 1;
   36451 let opNewValue = 0;
   36452 let isAccumulator = 1;
   36453 let DecoderNamespace = "EXT_mmvec";
   36454 let Constraints = "$Vxx32 = $Vxx32in";
   36455 }
   36456 def V6_vtmpyb_acc_alt : HInst<
   36457 (outs HvxWR:$Vxx32),
   36458 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36459 "$Vxx32 += vtmpyb($Vuu32,$Rt32)",
   36460 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36461 let hasNewValue = 1;
   36462 let opNewValue = 0;
   36463 let isAccumulator = 1;
   36464 let isPseudo = 1;
   36465 let isCodeGenOnly = 1;
   36466 let DecoderNamespace = "EXT_mmvec";
   36467 let Constraints = "$Vxx32 = $Vxx32in";
   36468 }
   36469 def V6_vtmpyb_alt : HInst<
   36470 (outs HvxWR:$Vdd32),
   36471 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36472 "$Vdd32 = vtmpyb($Vuu32,$Rt32)",
   36473 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36474 let hasNewValue = 1;
   36475 let opNewValue = 0;
   36476 let isPseudo = 1;
   36477 let isCodeGenOnly = 1;
   36478 let DecoderNamespace = "EXT_mmvec";
   36479 }
   36480 def V6_vtmpybus : HInst<
   36481 (outs HvxWR:$Vdd32),
   36482 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36483 "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
   36484 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   36485 let Inst{7-5} = 0b001;
   36486 let Inst{13-13} = 0b0;
   36487 let Inst{31-21} = 0b00011001000;
   36488 let hasNewValue = 1;
   36489 let opNewValue = 0;
   36490 let DecoderNamespace = "EXT_mmvec";
   36491 }
   36492 def V6_vtmpybus_acc : HInst<
   36493 (outs HvxWR:$Vxx32),
   36494 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36495 "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
   36496 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   36497 let Inst{7-5} = 0b001;
   36498 let Inst{13-13} = 0b1;
   36499 let Inst{31-21} = 0b00011001000;
   36500 let hasNewValue = 1;
   36501 let opNewValue = 0;
   36502 let isAccumulator = 1;
   36503 let DecoderNamespace = "EXT_mmvec";
   36504 let Constraints = "$Vxx32 = $Vxx32in";
   36505 }
   36506 def V6_vtmpybus_acc_alt : HInst<
   36507 (outs HvxWR:$Vxx32),
   36508 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36509 "$Vxx32 += vtmpybus($Vuu32,$Rt32)",
   36510 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36511 let hasNewValue = 1;
   36512 let opNewValue = 0;
   36513 let isAccumulator = 1;
   36514 let isPseudo = 1;
   36515 let isCodeGenOnly = 1;
   36516 let DecoderNamespace = "EXT_mmvec";
   36517 let Constraints = "$Vxx32 = $Vxx32in";
   36518 }
   36519 def V6_vtmpybus_alt : HInst<
   36520 (outs HvxWR:$Vdd32),
   36521 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36522 "$Vdd32 = vtmpybus($Vuu32,$Rt32)",
   36523 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36524 let hasNewValue = 1;
   36525 let opNewValue = 0;
   36526 let isPseudo = 1;
   36527 let isCodeGenOnly = 1;
   36528 let DecoderNamespace = "EXT_mmvec";
   36529 }
   36530 def V6_vtmpyhb : HInst<
   36531 (outs HvxWR:$Vdd32),
   36532 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36533 "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
   36534 tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
   36535 let Inst{7-5} = 0b100;
   36536 let Inst{13-13} = 0b0;
   36537 let Inst{31-21} = 0b00011001101;
   36538 let hasNewValue = 1;
   36539 let opNewValue = 0;
   36540 let DecoderNamespace = "EXT_mmvec";
   36541 }
   36542 def V6_vtmpyhb_acc : HInst<
   36543 (outs HvxWR:$Vxx32),
   36544 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36545 "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
   36546 tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
   36547 let Inst{7-5} = 0b010;
   36548 let Inst{13-13} = 0b1;
   36549 let Inst{31-21} = 0b00011001000;
   36550 let hasNewValue = 1;
   36551 let opNewValue = 0;
   36552 let isAccumulator = 1;
   36553 let DecoderNamespace = "EXT_mmvec";
   36554 let Constraints = "$Vxx32 = $Vxx32in";
   36555 }
   36556 def V6_vtmpyhb_acc_alt : HInst<
   36557 (outs HvxWR:$Vxx32),
   36558 (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
   36559 "$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
   36560 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36561 let hasNewValue = 1;
   36562 let opNewValue = 0;
   36563 let isAccumulator = 1;
   36564 let isPseudo = 1;
   36565 let isCodeGenOnly = 1;
   36566 let DecoderNamespace = "EXT_mmvec";
   36567 let Constraints = "$Vxx32 = $Vxx32in";
   36568 }
   36569 def V6_vtmpyhb_alt : HInst<
   36570 (outs HvxWR:$Vdd32),
   36571 (ins HvxWR:$Vuu32, IntRegs:$Rt32),
   36572 "$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
   36573 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36574 let hasNewValue = 1;
   36575 let opNewValue = 0;
   36576 let isPseudo = 1;
   36577 let isCodeGenOnly = 1;
   36578 let DecoderNamespace = "EXT_mmvec";
   36579 }
   36580 def V6_vtran2x2_map : HInst<
   36581 (outs HvxVR:$Vy32, HvxVR:$Vx32),
   36582 (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
   36583 "vtrans2x2($Vy32,$Vx32,$Rt32)",
   36584 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36585 let hasNewValue = 1;
   36586 let opNewValue = 0;
   36587 let hasNewValue2 = 1;
   36588 let opNewValue2 = 1;
   36589 let isPseudo = 1;
   36590 let isCodeGenOnly = 1;
   36591 let DecoderNamespace = "EXT_mmvec";
   36592 let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
   36593 }
   36594 def V6_vunpackb : HInst<
   36595 (outs HvxWR:$Vdd32),
   36596 (ins HvxVR:$Vu32),
   36597 "$Vdd32.h = vunpack($Vu32.b)",
   36598 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
   36599 let Inst{7-5} = 0b010;
   36600 let Inst{13-13} = 0b0;
   36601 let Inst{31-16} = 0b0001111000000001;
   36602 let hasNewValue = 1;
   36603 let opNewValue = 0;
   36604 let DecoderNamespace = "EXT_mmvec";
   36605 }
   36606 def V6_vunpackb_alt : HInst<
   36607 (outs HvxWR:$Vdd32),
   36608 (ins HvxVR:$Vu32),
   36609 "$Vdd32 = vunpackb($Vu32)",
   36610 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36611 let hasNewValue = 1;
   36612 let opNewValue = 0;
   36613 let isPseudo = 1;
   36614 let isCodeGenOnly = 1;
   36615 let DecoderNamespace = "EXT_mmvec";
   36616 }
   36617 def V6_vunpackh : HInst<
   36618 (outs HvxWR:$Vdd32),
   36619 (ins HvxVR:$Vu32),
   36620 "$Vdd32.w = vunpack($Vu32.h)",
   36621 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
   36622 let Inst{7-5} = 0b011;
   36623 let Inst{13-13} = 0b0;
   36624 let Inst{31-16} = 0b0001111000000001;
   36625 let hasNewValue = 1;
   36626 let opNewValue = 0;
   36627 let DecoderNamespace = "EXT_mmvec";
   36628 }
   36629 def V6_vunpackh_alt : HInst<
   36630 (outs HvxWR:$Vdd32),
   36631 (ins HvxVR:$Vu32),
   36632 "$Vdd32 = vunpackh($Vu32)",
   36633 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36634 let hasNewValue = 1;
   36635 let opNewValue = 0;
   36636 let isPseudo = 1;
   36637 let isCodeGenOnly = 1;
   36638 let DecoderNamespace = "EXT_mmvec";
   36639 }
   36640 def V6_vunpackob : HInst<
   36641 (outs HvxWR:$Vxx32),
   36642 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
   36643 "$Vxx32.h |= vunpacko($Vu32.b)",
   36644 tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
   36645 let Inst{7-5} = 0b000;
   36646 let Inst{13-13} = 0b1;
   36647 let Inst{31-16} = 0b0001111000000000;
   36648 let hasNewValue = 1;
   36649 let opNewValue = 0;
   36650 let isAccumulator = 1;
   36651 let DecoderNamespace = "EXT_mmvec";
   36652 let Constraints = "$Vxx32 = $Vxx32in";
   36653 }
   36654 def V6_vunpackob_alt : HInst<
   36655 (outs HvxWR:$Vxx32),
   36656 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
   36657 "$Vxx32 |= vunpackob($Vu32)",
   36658 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36659 let hasNewValue = 1;
   36660 let opNewValue = 0;
   36661 let isAccumulator = 1;
   36662 let isPseudo = 1;
   36663 let DecoderNamespace = "EXT_mmvec";
   36664 let Constraints = "$Vxx32 = $Vxx32in";
   36665 }
   36666 def V6_vunpackoh : HInst<
   36667 (outs HvxWR:$Vxx32),
   36668 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
   36669 "$Vxx32.w |= vunpacko($Vu32.h)",
   36670 tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
   36671 let Inst{7-5} = 0b001;
   36672 let Inst{13-13} = 0b1;
   36673 let Inst{31-16} = 0b0001111000000000;
   36674 let hasNewValue = 1;
   36675 let opNewValue = 0;
   36676 let isAccumulator = 1;
   36677 let DecoderNamespace = "EXT_mmvec";
   36678 let Constraints = "$Vxx32 = $Vxx32in";
   36679 }
   36680 def V6_vunpackoh_alt : HInst<
   36681 (outs HvxWR:$Vxx32),
   36682 (ins HvxWR:$Vxx32in, HvxVR:$Vu32),
   36683 "$Vxx32 |= vunpackoh($Vu32)",
   36684 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36685 let hasNewValue = 1;
   36686 let opNewValue = 0;
   36687 let isAccumulator = 1;
   36688 let isPseudo = 1;
   36689 let isCodeGenOnly = 1;
   36690 let DecoderNamespace = "EXT_mmvec";
   36691 let Constraints = "$Vxx32 = $Vxx32in";
   36692 }
   36693 def V6_vunpackub : HInst<
   36694 (outs HvxWR:$Vdd32),
   36695 (ins HvxVR:$Vu32),
   36696 "$Vdd32.uh = vunpack($Vu32.ub)",
   36697 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
   36698 let Inst{7-5} = 0b000;
   36699 let Inst{13-13} = 0b0;
   36700 let Inst{31-16} = 0b0001111000000001;
   36701 let hasNewValue = 1;
   36702 let opNewValue = 0;
   36703 let DecoderNamespace = "EXT_mmvec";
   36704 }
   36705 def V6_vunpackub_alt : HInst<
   36706 (outs HvxWR:$Vdd32),
   36707 (ins HvxVR:$Vu32),
   36708 "$Vdd32 = vunpackub($Vu32)",
   36709 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36710 let hasNewValue = 1;
   36711 let opNewValue = 0;
   36712 let isPseudo = 1;
   36713 let isCodeGenOnly = 1;
   36714 let DecoderNamespace = "EXT_mmvec";
   36715 }
   36716 def V6_vunpackuh : HInst<
   36717 (outs HvxWR:$Vdd32),
   36718 (ins HvxVR:$Vu32),
   36719 "$Vdd32.uw = vunpack($Vu32.uh)",
   36720 tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
   36721 let Inst{7-5} = 0b001;
   36722 let Inst{13-13} = 0b0;
   36723 let Inst{31-16} = 0b0001111000000001;
   36724 let hasNewValue = 1;
   36725 let opNewValue = 0;
   36726 let DecoderNamespace = "EXT_mmvec";
   36727 }
   36728 def V6_vunpackuh_alt : HInst<
   36729 (outs HvxWR:$Vdd32),
   36730 (ins HvxVR:$Vu32),
   36731 "$Vdd32 = vunpackuh($Vu32)",
   36732 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36733 let hasNewValue = 1;
   36734 let opNewValue = 0;
   36735 let isPseudo = 1;
   36736 let isCodeGenOnly = 1;
   36737 let DecoderNamespace = "EXT_mmvec";
   36738 }
   36739 def V6_vwhist128 : HInst<
   36740 (outs),
   36741 (ins),
   36742 "vwhist128",
   36743 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
   36744 let Inst{13-0} = 0b10010010000000;
   36745 let Inst{31-16} = 0b0001111000000000;
   36746 let DecoderNamespace = "EXT_mmvec";
   36747 }
   36748 def V6_vwhist128m : HInst<
   36749 (outs),
   36750 (ins u1_0Imm:$Ii),
   36751 "vwhist128(#$Ii)",
   36752 tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
   36753 let Inst{7-0} = 0b10000000;
   36754 let Inst{13-9} = 0b10011;
   36755 let Inst{31-16} = 0b0001111000000000;
   36756 let DecoderNamespace = "EXT_mmvec";
   36757 }
   36758 def V6_vwhist128q : HInst<
   36759 (outs),
   36760 (ins HvxQR:$Qv4),
   36761 "vwhist128($Qv4)",
   36762 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
   36763 let Inst{13-0} = 0b10010010000000;
   36764 let Inst{21-16} = 0b000010;
   36765 let Inst{31-24} = 0b00011110;
   36766 let DecoderNamespace = "EXT_mmvec";
   36767 }
   36768 def V6_vwhist128qm : HInst<
   36769 (outs),
   36770 (ins HvxQR:$Qv4, u1_0Imm:$Ii),
   36771 "vwhist128($Qv4,#$Ii)",
   36772 tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
   36773 let Inst{7-0} = 0b10000000;
   36774 let Inst{13-9} = 0b10011;
   36775 let Inst{21-16} = 0b000010;
   36776 let Inst{31-24} = 0b00011110;
   36777 let DecoderNamespace = "EXT_mmvec";
   36778 }
   36779 def V6_vwhist256 : HInst<
   36780 (outs),
   36781 (ins),
   36782 "vwhist256",
   36783 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
   36784 let Inst{13-0} = 0b10001010000000;
   36785 let Inst{31-16} = 0b0001111000000000;
   36786 let DecoderNamespace = "EXT_mmvec";
   36787 }
   36788 def V6_vwhist256_sat : HInst<
   36789 (outs),
   36790 (ins),
   36791 "vwhist256:sat",
   36792 tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
   36793 let Inst{13-0} = 0b10001110000000;
   36794 let Inst{31-16} = 0b0001111000000000;
   36795 let DecoderNamespace = "EXT_mmvec";
   36796 }
   36797 def V6_vwhist256q : HInst<
   36798 (outs),
   36799 (ins HvxQR:$Qv4),
   36800 "vwhist256($Qv4)",
   36801 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
   36802 let Inst{13-0} = 0b10001010000000;
   36803 let Inst{21-16} = 0b000010;
   36804 let Inst{31-24} = 0b00011110;
   36805 let DecoderNamespace = "EXT_mmvec";
   36806 }
   36807 def V6_vwhist256q_sat : HInst<
   36808 (outs),
   36809 (ins HvxQR:$Qv4),
   36810 "vwhist256($Qv4):sat",
   36811 tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
   36812 let Inst{13-0} = 0b10001110000000;
   36813 let Inst{21-16} = 0b000010;
   36814 let Inst{31-24} = 0b00011110;
   36815 let DecoderNamespace = "EXT_mmvec";
   36816 }
   36817 def V6_vxor : HInst<
   36818 (outs HvxVR:$Vd32),
   36819 (ins HvxVR:$Vu32, HvxVR:$Vv32),
   36820 "$Vd32 = vxor($Vu32,$Vv32)",
   36821 tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
   36822 let Inst{7-5} = 0b111;
   36823 let Inst{13-13} = 0b0;
   36824 let Inst{31-21} = 0b00011100001;
   36825 let hasNewValue = 1;
   36826 let opNewValue = 0;
   36827 let DecoderNamespace = "EXT_mmvec";
   36828 }
   36829 def V6_vzb : HInst<
   36830 (outs HvxWR:$Vdd32),
   36831 (ins HvxVR:$Vu32),
   36832 "$Vdd32.uh = vzxt($Vu32.ub)",
   36833 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
   36834 let Inst{7-5} = 0b001;
   36835 let Inst{13-13} = 0b0;
   36836 let Inst{31-16} = 0b0001111000000010;
   36837 let hasNewValue = 1;
   36838 let opNewValue = 0;
   36839 let DecoderNamespace = "EXT_mmvec";
   36840 }
   36841 def V6_vzb_alt : HInst<
   36842 (outs HvxWR:$Vdd32),
   36843 (ins HvxVR:$Vu32),
   36844 "$Vdd32 = vzxtb($Vu32)",
   36845 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36846 let hasNewValue = 1;
   36847 let opNewValue = 0;
   36848 let isPseudo = 1;
   36849 let isCodeGenOnly = 1;
   36850 let DecoderNamespace = "EXT_mmvec";
   36851 }
   36852 def V6_vzh : HInst<
   36853 (outs HvxWR:$Vdd32),
   36854 (ins HvxVR:$Vu32),
   36855 "$Vdd32.uw = vzxt($Vu32.uh)",
   36856 tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
   36857 let Inst{7-5} = 0b010;
   36858 let Inst{13-13} = 0b0;
   36859 let Inst{31-16} = 0b0001111000000010;
   36860 let hasNewValue = 1;
   36861 let opNewValue = 0;
   36862 let DecoderNamespace = "EXT_mmvec";
   36863 }
   36864 def V6_vzh_alt : HInst<
   36865 (outs HvxWR:$Vdd32),
   36866 (ins HvxVR:$Vu32),
   36867 "$Vdd32 = vzxth($Vu32)",
   36868 PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
   36869 let hasNewValue = 1;
   36870 let opNewValue = 0;
   36871 let isPseudo = 1;
   36872 let isCodeGenOnly = 1;
   36873 let DecoderNamespace = "EXT_mmvec";
   36874 }
   36875 def Y2_barrier : HInst<
   36876 (outs),
   36877 (ins),
   36878 "barrier",
   36879 tc_367f7f3d, TypeST>, Enc_e3b0c4 {
   36880 let Inst{13-0} = 0b00000000000000;
   36881 let Inst{31-16} = 0b1010100000000000;
   36882 let isSoloAX = 1;
   36883 let hasSideEffects = 1;
   36884 }
   36885 def Y2_break : HInst<
   36886 (outs),
   36887 (ins),
   36888 "brkpt",
   36889 tc_4ca572d4, TypeCR>, Enc_e3b0c4 {
   36890 let Inst{13-0} = 0b00000000000000;
   36891 let Inst{31-16} = 0b0110110000100000;
   36892 let isSolo = 1;
   36893 }
   36894 def Y2_dccleana : HInst<
   36895 (outs),
   36896 (ins IntRegs:$Rs32),
   36897 "dccleana($Rs32)",
   36898 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
   36899 let Inst{13-0} = 0b00000000000000;
   36900 let Inst{31-21} = 0b10100000000;
   36901 let isRestrictSlot1AOK = 1;
   36902 let hasSideEffects = 1;
   36903 }
   36904 def Y2_dccleaninva : HInst<
   36905 (outs),
   36906 (ins IntRegs:$Rs32),
   36907 "dccleaninva($Rs32)",
   36908 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
   36909 let Inst{13-0} = 0b00000000000000;
   36910 let Inst{31-21} = 0b10100000010;
   36911 let isRestrictSlot1AOK = 1;
   36912 let hasSideEffects = 1;
   36913 }
   36914 def Y2_dcfetch : HInst<
   36915 (outs),
   36916 (ins IntRegs:$Rs32),
   36917 "dcfetch($Rs32)",
   36918 tc_3da80ba5, TypeMAPPING> {
   36919 let hasSideEffects = 1;
   36920 let isPseudo = 1;
   36921 let isCodeGenOnly = 1;
   36922 }
   36923 def Y2_dcfetchbo : HInst<
   36924 (outs),
   36925 (ins IntRegs:$Rs32, u11_3Imm:$Ii),
   36926 "dcfetch($Rs32+#$Ii)",
   36927 tc_4d9914c9, TypeLD>, Enc_2d829e {
   36928 let Inst{13-11} = 0b000;
   36929 let Inst{31-21} = 0b10010100000;
   36930 let addrMode = BaseImmOffset;
   36931 let isRestrictNoSlot1Store = 1;
   36932 let hasSideEffects = 1;
   36933 }
   36934 def Y2_dcinva : HInst<
   36935 (outs),
   36936 (ins IntRegs:$Rs32),
   36937 "dcinva($Rs32)",
   36938 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
   36939 let Inst{13-0} = 0b00000000000000;
   36940 let Inst{31-21} = 0b10100000001;
   36941 let isRestrictSlot1AOK = 1;
   36942 let hasSideEffects = 1;
   36943 }
   36944 def Y2_dczeroa : HInst<
   36945 (outs),
   36946 (ins IntRegs:$Rs32),
   36947 "dczeroa($Rs32)",
   36948 tc_00e7c26e, TypeST>, Enc_ecbcc8 {
   36949 let Inst{13-0} = 0b00000000000000;
   36950 let Inst{31-21} = 0b10100000110;
   36951 let isRestrictSlot1AOK = 1;
   36952 let mayStore = 1;
   36953 let hasSideEffects = 1;
   36954 }
   36955 def Y2_icinva : HInst<
   36956 (outs),
   36957 (ins IntRegs:$Rs32),
   36958 "icinva($Rs32)",
   36959 tc_999d32db, TypeJ>, Enc_ecbcc8 {
   36960 let Inst{13-0} = 0b00000000000000;
   36961 let Inst{31-21} = 0b01010110110;
   36962 let isSolo = 1;
   36963 }
   36964 def Y2_isync : HInst<
   36965 (outs),
   36966 (ins),
   36967 "isync",
   36968 tc_b13761ae, TypeJ>, Enc_e3b0c4 {
   36969 let Inst{13-0} = 0b00000000000010;
   36970 let Inst{31-16} = 0b0101011111000000;
   36971 let isSolo = 1;
   36972 }
   36973 def Y2_syncht : HInst<
   36974 (outs),
   36975 (ins),
   36976 "syncht",
   36977 tc_367f7f3d, TypeST>, Enc_e3b0c4 {
   36978 let Inst{13-0} = 0b00000000000000;
   36979 let Inst{31-16} = 0b1010100001000000;
   36980 let isSolo = 1;
   36981 }
   36982 def Y4_l2fetch : HInst<
   36983 (outs),
   36984 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   36985 "l2fetch($Rs32,$Rt32)",
   36986 tc_daa058fa, TypeST>, Enc_ca3887 {
   36987 let Inst{7-0} = 0b00000000;
   36988 let Inst{13-13} = 0b0;
   36989 let Inst{31-21} = 0b10100110000;
   36990 let isSoloAX = 1;
   36991 let mayStore = 1;
   36992 let hasSideEffects = 1;
   36993 }
   36994 def Y4_trace : HInst<
   36995 (outs),
   36996 (ins IntRegs:$Rs32),
   36997 "trace($Rs32)",
   36998 tc_c82dc1ff, TypeCR>, Enc_ecbcc8 {
   36999 let Inst{13-0} = 0b00000000000000;
   37000 let Inst{31-21} = 0b01100010010;
   37001 let isSoloAX = 1;
   37002 }
   37003 def Y5_l2fetch : HInst<
   37004 (outs),
   37005 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
   37006 "l2fetch($Rs32,$Rtt32)",
   37007 tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5]> {
   37008 let Inst{7-0} = 0b00000000;
   37009 let Inst{13-13} = 0b0;
   37010 let Inst{31-21} = 0b10100110100;
   37011 let isSoloAX = 1;
   37012 let mayStore = 1;
   37013 let hasSideEffects = 1;
   37014 }
   37015 def dep_A2_addsat : HInst<
   37016 (outs IntRegs:$Rd32),
   37017 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   37018 "$Rd32 = add($Rs32,$Rt32):sat:deprecated",
   37019 tc_b44c6e2a, TypeALU64>, Enc_5ab2be {
   37020 let Inst{7-5} = 0b000;
   37021 let Inst{13-13} = 0b0;
   37022 let Inst{31-21} = 0b11010101100;
   37023 let hasNewValue = 1;
   37024 let opNewValue = 0;
   37025 let prefersSlot3 = 1;
   37026 let Defs = [USR_OVF];
   37027 }
   37028 def dep_A2_subsat : HInst<
   37029 (outs IntRegs:$Rd32),
   37030 (ins IntRegs:$Rt32, IntRegs:$Rs32),
   37031 "$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
   37032 tc_b44c6e2a, TypeALU64>, Enc_bd6011 {
   37033 let Inst{7-5} = 0b100;
   37034 let Inst{13-13} = 0b0;
   37035 let Inst{31-21} = 0b11010101100;
   37036 let hasNewValue = 1;
   37037 let opNewValue = 0;
   37038 let prefersSlot3 = 1;
   37039 let Defs = [USR_OVF];
   37040 }
   37041 def dep_S2_packhl : HInst<
   37042 (outs DoubleRegs:$Rdd32),
   37043 (ins IntRegs:$Rs32, IntRegs:$Rt32),
   37044 "$Rdd32 = packhl($Rs32,$Rt32):deprecated",
   37045 tc_540fdfbc, TypeALU64>, Enc_be32a5 {
   37046 let Inst{7-5} = 0b000;
   37047 let Inst{13-13} = 0b0;
   37048 let Inst{31-21} = 0b11010100000;
   37049 }
   37050