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      1 //==- HexagonInstrFormatsV4.td - Hexagon Instruction Formats --*- tablegen -==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the Hexagon V4 instruction classes in TableGen format.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 //                      Duplex Instruction Class Declaration
     15 //===----------------------------------------------------------------------===//
     16 
     17 class OpcodeDuplex {
     18   field bits<32> Inst = ?; // Default to an invalid insn.
     19   bits<4> IClass = 0; // ICLASS
     20   bits<13> ISubHi = 0; // Low sub-insn
     21   bits<13> ISubLo = 0; // High sub-insn
     22 
     23   let Inst{31-29} = IClass{3-1};
     24   let Inst{13}    = IClass{0};
     25   let Inst{15-14} = 0;
     26   let Inst{28-16} = ISubHi;
     27   let Inst{12-0}  = ISubLo;
     28 }
     29 
     30 class InstDuplex<bits<4> iClass, list<dag> pattern = [],
     31                  string cstr = "">
     32   : Instruction, OpcodeDuplex {
     33   let Namespace = "Hexagon";
     34   IType Type = TypeDUPLEX;  // uses slot 0,1
     35   let isCodeGenOnly = 1;
     36   let hasSideEffects = 0;
     37   dag OutOperandList = (outs);
     38   dag InOperandList = (ins);
     39   let IClass = iClass;
     40   let Constraints = cstr;
     41   let Itinerary = DUPLEX;
     42   let Size = 4;
     43 
     44   // SoftFail is a field the disassembler can use to provide a way for
     45   // instructions to not match without killing the whole decode process. It is
     46   // mainly used for ARM, but Tablegen expects this field to exist or it fails
     47   // to build the decode table.
     48   field bits<32> SoftFail = 0;
     49 
     50   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
     51 
     52   let TSFlags{5-0} = Type.Value;
     53 
     54   // Predicated instructions.
     55   bits<1> isPredicated = 0;
     56   let TSFlags{6} = isPredicated;
     57   bits<1> isPredicatedFalse = 0;
     58   let TSFlags{7} = isPredicatedFalse;
     59   bits<1> isPredicatedNew = 0;
     60   let TSFlags{8} = isPredicatedNew;
     61 
     62   // New-value insn helper fields.
     63   bits<1> isNewValue = 0;
     64   let TSFlags{9} = isNewValue; // New-value consumer insn.
     65   bits<1> hasNewValue = 0;
     66   let TSFlags{10} = hasNewValue; // New-value producer insn.
     67   bits<3> opNewValue = 0;
     68   let TSFlags{13-11} = opNewValue; // New-value produced operand.
     69   bits<1> isNVStorable = 0;
     70   let TSFlags{14} = isNVStorable; // Store that can become new-value store.
     71   bits<1> isNVStore = 0;
     72   let TSFlags{15} = isNVStore; // New-value store insn.
     73 
     74   // Immediate extender helper fields.
     75   bits<1> isExtendable = 0;
     76   let TSFlags{16} = isExtendable; // Insn may be extended.
     77   bits<1> isExtended = 0;
     78   let TSFlags{17} = isExtended; // Insn must be extended.
     79   bits<3> opExtendable = 0;
     80   let TSFlags{20-18} = opExtendable; // Which operand may be extended.
     81   bits<1> isExtentSigned = 0;
     82   let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
     83   bits<5> opExtentBits = 0;
     84   let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
     85   bits<2> opExtentAlign = 0;
     86   let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
     87 }
     88