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      1 //===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     11   def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
     12            (MI HvxVR:$src1, IntRegs:$src2)>;
     13   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
     14            (MI HvxVR:$src1, IntRegs:$src2)>;
     15 }
     16 
     17 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     18   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
     19            (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
     20   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
     21                                             IntRegsLow8:$src3),
     22            (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
     23 }
     24 
     25 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     26   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
     27            (MI HvxVR:$src1, HvxVR:$src2)>;
     28   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
     29            (MI HvxVR:$src1, HvxVR:$src2)>;
     30 }
     31 
     32 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     33   def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
     34            (MI HvxWR:$src1, HvxWR:$src2)>;
     35   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
     36            (MI HvxWR:$src1, HvxWR:$src2)>;
     37 }
     38 
     39 multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     40   def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
     41            (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
     42   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
     43                                             HvxVR:$src3),
     44            (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
     45 }
     46 
     47 multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     48   def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
     49            (MI HvxWR:$src1, IntRegs:$src2)>;
     50   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
     51            (MI HvxWR:$src1, IntRegs:$src2)>;
     52 }
     53 
     54 multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     55   def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
     56            (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
     57   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
     58                                             IntRegs:$src3),
     59            (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
     60 }
     61 
     62 multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     63   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
     64            (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
     65   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
     66                                             IntRegs:$src3),
     67            (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
     68 }
     69 
     70 multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     71   def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
     72            (MI HvxQR:$src1, IntRegs:$src2)>;
     73   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
     74            (MI HvxQR:$src1, IntRegs:$src2)>;
     75 }
     76 
     77 multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     78   def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
     79            (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
     80   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
     81                                             IntRegs:$src3),
     82            (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
     83 }
     84 
     85 multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     86   def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
     87            (MI HvxQR:$src1, HvxVR:$src2)>;
     88   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
     89            (MI HvxQR:$src1, HvxVR:$src2)>;
     90 }
     91 
     92 multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
     93   def: Pat<(IntID IntRegs:$src1),
     94            (MI IntRegs:$src1)>;
     95   def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
     96            (MI IntRegs:$src1)>;
     97 }
     98 
     99 multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
    100   def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
    101            (MI HvxQR:$src1, HvxQR:$src2)>;
    102   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
    103            (MI HvxQR:$src1, HvxQR:$src2)>;
    104 }
    105 
    106 multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
    107   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
    108            (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
    109   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
    110                                             imm:$src3),
    111            (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
    112 }
    113 
    114 multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
    115   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
    116            (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
    117   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
    118                                             HvxVR:$src3, imm:$src4),
    119            (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
    120 }
    121 
    122 multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
    123   def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
    124            (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
    125   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
    126                                             HvxVR:$src3, imm:$src4),
    127            (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
    128 }
    129 
    130 def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
    131 def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>;
    132 def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>;
    133 def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>;
    134 def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>;
    135 
    136 defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>;
    137 defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>;
    138 defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>;
    139 defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>;
    140 defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>;
    141 defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>;
    142 defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>;
    143 defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>;
    144 defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>;
    145 defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>;
    146 defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>;
    147 defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>;
    148 defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>;
    149 defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>;
    150 defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>;
    151 defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>;
    152 defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>;
    153 defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>;
    154 defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>;
    155 defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>;
    156 defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>;
    157 defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>;
    158 defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>;
    159 defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>;
    160 defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>;
    161 defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>;
    162 defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>;
    163 defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>;
    164 defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>;
    165 defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>;
    166 defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>;
    167 defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>;
    168 defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>;
    169 defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>;
    170 defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>;
    171 defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>;
    172 defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>;
    173 defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>;
    174 defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>;
    175 defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>;
    176 defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>;
    177 defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>;
    178 defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>;
    179 defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>;
    180 defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>;
    181