1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 def LD_tc_ld_SLOT01 : InstrItinClass; 11 def ST_tc_st_SLOT01 : InstrItinClass; 12 13 class HexagonV4PseudoItin { 14 list<InstrItinData> V4PseudoItin_list = [ 15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 16 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 17 InstrStage<1, [SLOT2, SLOT3]>]>, 18 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>, 19 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]> 20 ]; 21 } 22 23 def HexagonV4ItinList : DepScalarItinV4, HexagonV4PseudoItin { 24 list<InstrItinData> V4Itin_list = [ 25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>, 26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]> 27 ]; 28 list<InstrItinData> ItinList = 29 !listconcat(V4Itin_list, DepScalarItinV4_list, V4PseudoItin_list); 30 } 31 32 def HexagonItinerariesV4 : 33 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], 34 [Hex_FWD], HexagonV4ItinList.ItinList>; 35 36 def HexagonModelV4 : SchedMachineModel { 37 // Max issue per cycle == bundle width. 38 let IssueWidth = 4; 39 let Itineraries = HexagonItinerariesV4; 40 let LoadLatency = 1; 41 let CompleteModel = 0; 42 } 43 44 //===----------------------------------------------------------------------===// 45 // Hexagon V4 Resource Definitions - 46 //===----------------------------------------------------------------------===// 47
