1 //=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 11 class HexagonV55PseudoItin { 12 list<InstrItinData> V55PseudoItin_list = [ 13 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], 14 [1, 1, 1]>, 15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 16 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, 17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>, 18 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> 19 ]; 20 } 21 22 def HexagonV55ItinList : DepScalarItinV55, 23 HexagonV55PseudoItin { 24 list<InstrItinData> V55Itin_list = [ 25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>, 26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], 27 [1, 1, 1]> 28 ]; 29 list<InstrItinData> ItinList = 30 !listconcat(V55Itin_list, DepScalarItinV55_list, 31 V55PseudoItin_list); 32 } 33 34 def HexagonItinerariesV55 : 35 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], 36 [Hex_FWD], HexagonV55ItinList.ItinList>; 37 38 def HexagonModelV55 : SchedMachineModel { 39 // Max issue per cycle == bundle width. 40 let IssueWidth = 4; 41 let Itineraries = HexagonItinerariesV55; 42 let LoadLatency = 1; 43 let CompleteModel = 0; 44 } 45 46 //===----------------------------------------------------------------------===// 47 // Hexagon V55 Resource Definitions - 48 //===----------------------------------------------------------------------===// 49
