1 //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // ScalarItin contains some old itineraries still used by a 11 // handful of instructions. Hopefully, we will be able to get rid of them soon. 12 13 def HexagonV62ItinList : DepScalarItinV62, ScalarItin, 14 DepHVXItinV62, HVXItin, PseudoItin { 15 list<InstrItinData> ItinList = 16 !listconcat(DepScalarItinV62_list, ScalarItin_list, 17 DepHVXItinV62_list, HVXItin_list, PseudoItin_list); 18 } 19 20 def HexagonItinerariesV62 : 21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 22 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 23 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 24 CVI_ALL_NOMEM], 25 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>; 26 27 def HexagonModelV62 : SchedMachineModel { 28 // Max issue per cycle == bundle width. 29 let IssueWidth = 4; 30 let Itineraries = HexagonItinerariesV62; 31 let LoadLatency = 1; 32 let CompleteModel = 0; 33 } 34 35 //===----------------------------------------------------------------------===// 36 // Hexagon V62 Resource Definitions - 37 //===----------------------------------------------------------------------===// 38
