1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes microMIPS32r6 instruction formats. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class MMR6Arch<string opstr> { 15 string Arch = "micromipsr6"; 16 string BaseOpcode = opstr; 17 string DecoderNamespace = "MicroMipsR6"; 18 } 19 20 //===----------------------------------------------------------------------===// 21 // 22 // Disambiguators 23 // 24 //===----------------------------------------------------------------------===// 25 // 26 // Some encodings are ambiguous except by comparing field values. 27 28 class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> { 29 string DecoderNamespace = "MicroMipsR6_Ambiguous"; 30 } 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Encoding Formats 35 // 36 //===----------------------------------------------------------------------===// 37 38 class BC16_FM_MM16R6 { 39 bits<10> offset; 40 41 bits<16> Inst; 42 43 let Inst{15-10} = 0x33; 44 let Inst{9-0} = offset; 45 } 46 47 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> { 48 bits<3> rs; 49 bits<7> offset; 50 51 bits<16> Inst; 52 53 let Inst{15-10} = op; 54 let Inst{9-7} = rs; 55 let Inst{6-0} = offset; 56 } 57 58 class POOL16C_JALRC_FM_MM16R6<bits<5> op> { 59 bits<5> rs; 60 61 bits<16> Inst; 62 63 let Inst{15-10} = 0x11; 64 let Inst{9-5} = rs; 65 let Inst{4-0} = op; 66 } 67 68 class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 69 bits<5> rt; 70 bits<5> rs; 71 bits<16> offset; 72 73 bits<32> Inst; 74 75 let Inst{31-26} = 0b011101; 76 let Inst{25-21} = rt; 77 let Inst{20-16} = rs; 78 let Inst{15-0} = offset; 79 } 80 81 class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 82 bits<5> rt; 83 bits<5> rs; 84 bits<16> offset; 85 86 bits<32> Inst; 87 88 let Inst{31-26} = 0b011111; 89 let Inst{25-21} = rt; 90 let Inst{20-16} = rs; 91 let Inst{15-0} = offset; 92 } 93 94 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> { 95 bits<5> imm; 96 97 bits<16> Inst; 98 99 let Inst{15-10} = 0x11; 100 let Inst{9-5} = imm; 101 let Inst{4-0} = op; 102 } 103 104 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> { 105 bits<2> rt; 106 bits<4> addr; 107 108 bits<16> Inst; 109 110 let Inst{15-10} = 0x11; 111 let Inst{9-8} = rt; 112 let Inst{7-4} = addr; 113 let Inst{3-0} = funct; 114 } 115 116 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst { 117 bits<5> rd; 118 bits<5> rt; 119 120 bits<32> Inst; 121 122 let Inst{31-26} = 0b000000; 123 let Inst{25-21} = rt; 124 let Inst{20-16} = rd; 125 let Inst{15-12} = 0b0000; 126 let Inst{11-6} = funct; 127 let Inst{5-0} = 0b111100; 128 } 129 130 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst { 131 bits<21> addr; 132 bits<5> hint; 133 134 bits<32> Inst; 135 136 let Inst{31-26} = opgroup; 137 let Inst{25-21} = hint; 138 let Inst{20-16} = addr{20-16}; 139 let Inst{15-12} = funct; 140 let Inst{11-0} = addr{11-0}; 141 } 142 143 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> { 144 bits<5> rd; 145 bits<5> rt; 146 bits<5> rs; 147 148 bits<32> Inst; 149 150 let Inst{31-26} = 0; 151 let Inst{25-21} = rt; 152 let Inst{20-16} = rs; 153 let Inst{15-11} = rd; 154 let Inst{10} = 0; 155 let Inst{9-0} = funct; 156 } 157 158 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 159 bits<5> rt; 160 bits<5> rs; 161 bits<16> imm16; 162 163 bits<32> Inst; 164 165 let Inst{31-26} = op; 166 let Inst{25-21} = rt; 167 let Inst{20-16} = rs; 168 let Inst{15-0} = imm16; 169 } 170 171 class LB32_FM_MMR6 : MipsR6Inst { 172 bits<21> addr; 173 bits<5> rt; 174 bits<5> base = addr{20-16}; 175 bits<16> offset = addr{15-0}; 176 177 bits<32> Inst; 178 179 let Inst{31-26} = 0b000111; 180 let Inst{25-21} = rt; 181 let Inst{20-16} = base; 182 let Inst{15-0} = offset; 183 } 184 185 class LBU32_FM_MMR6 : MipsR6Inst { 186 bits<21> addr; 187 bits<5> rt; 188 bits<5> base = addr{20-16}; 189 bits<16> offset = addr{15-0}; 190 191 bits<32> Inst; 192 193 let Inst{31-26} = 0b000101; 194 let Inst{25-21} = rt; 195 let Inst{20-16} = base; 196 let Inst{15-0} = offset; 197 } 198 199 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst { 200 bits<5> rt; 201 bits<19> imm; 202 203 bits<32> Inst; 204 205 let Inst{31-26} = 0b011110; 206 let Inst{25-21} = rt; 207 let Inst{20-19} = funct; 208 let Inst{18-0} = imm; 209 } 210 211 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst { 212 bits<5> rt; 213 bits<16> imm; 214 215 bits<32> Inst; 216 217 let Inst{31-26} = 0b011110; 218 let Inst{25-21} = rt; 219 let Inst{20-16} = funct; 220 let Inst{15-0} = imm; 221 } 222 223 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst { 224 bits<5> rd; 225 bits<5> rs; 226 bits<5> rt; 227 228 bits<32> Inst; 229 230 let Inst{31-26} = 0b000000; 231 let Inst{25-21} = rt; 232 let Inst{20-16} = rs; 233 let Inst{15-11} = rd; 234 let Inst{10} = 0; 235 let Inst{9-0} = funct; 236 } 237 238 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 239 bits<32> Inst; 240 241 let Inst{31-26} = 0; 242 let Inst{25-21} = 0; 243 let Inst{20-16} = 0; 244 let Inst{15-11} = op; 245 let Inst{10-6} = 0; 246 let Inst{5-0} = 0; 247 } 248 249 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> { 250 bits<5> rt; 251 bits<5> rd; 252 bits<32> Inst; 253 254 let Inst{31-26} = 0; 255 let Inst{25-21} = rt; 256 let Inst{20-16} = rd; 257 let Inst{15-6} = funct; 258 let Inst{5-0} = 0b111100; 259 } 260 261 class POOL32A_RDHWR_FM_MMR6 { 262 bits<5> rt; 263 bits<5> rs; 264 bits<3> sel; 265 bits<32> Inst; 266 267 let Inst{31-26} = 0; 268 let Inst{25-21} = rt; 269 let Inst{20-16} = rs; 270 let Inst{15-14} = 0; 271 let Inst{13-11} = sel; 272 let Inst{10} = 0; 273 let Inst{9-0} = 0b0111000000; 274 } 275 276 class POOL32A_SYNC_FM_MMR6 { 277 bits<5> stype; 278 279 bits<32> Inst; 280 281 let Inst{31-26} = 0; 282 let Inst{25-21} = 0; 283 let Inst{20-16} = stype; 284 let Inst{15-6} = 0b0110101101; 285 let Inst{5-0} = 0b111100; 286 } 287 288 class POOL32I_SYNCI_FM_MMR6 { 289 bits<21> addr; 290 bits<5> base = addr{20-16}; 291 bits<16> immediate = addr{15-0}; 292 293 bits<32> Inst; 294 295 let Inst{31-26} = 0b010000; 296 let Inst{25-21} = 0b01100; 297 let Inst{20-16} = base; 298 let Inst{15-0} = immediate; 299 } 300 301 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst { 302 bits<5> rs; 303 bits<5> rt; 304 305 bits<32> Inst; 306 307 let Inst{31-26} = 0b000000; 308 let Inst{25-21} = rt; 309 let Inst{20-16} = rs; 310 let Inst{15-6} = funct; 311 let Inst{5-0} = 0b111100; 312 } 313 314 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst { 315 bits<5> rs; 316 bits<5> rt; 317 318 bits<32> Inst; 319 320 let Inst{31-26} = 0b000000; 321 let Inst{25-21} = rs; 322 let Inst{20-16} = 0b00000; 323 let Inst{15-11} = rt; 324 let Inst{10-6} = 0b00001; 325 let Inst{5-0} = funct; 326 } 327 328 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst { 329 bits<5> rd; 330 bits<5> rs; 331 bits<5> rt; 332 bits<2> bp; 333 334 bits<32> Inst; 335 336 let Inst{31-26} = 0b000000; 337 let Inst{25-21} = rs; 338 let Inst{20-16} = rt; 339 let Inst{15-11} = rd; 340 let Inst{10-9} = bp; 341 let Inst{8-6} = 0b000; 342 let Inst{5-0} = funct; 343 } 344 345 class AUI_FM_MMR6 : MipsR6Inst { 346 bits<5> rs; 347 bits<5> rt; 348 bits<16> imm; 349 350 bits<32> Inst; 351 352 let Inst{31-26} = 0b000100; 353 let Inst{25-21} = rt; 354 let Inst{20-16} = rs; 355 let Inst{15-0} = imm; 356 } 357 358 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst { 359 bits<5> rd; 360 bits<5> rs; 361 bits<5> rt; 362 bits<2> imm2; 363 364 bits<32> Inst; 365 366 let Inst{31-26} = 0b000000; 367 let Inst{25-21} = rt; 368 let Inst{20-16} = rs; 369 let Inst{15-11} = rd; 370 let Inst{10-9} = imm2; 371 let Inst{8-6} = 0b000; 372 let Inst{5-0} = funct; 373 } 374 375 class SB32_SH32_STORE_FM_MMR6<bits<6> op> { 376 bits<5> rt; 377 bits<21> addr; 378 bits<5> base = addr{20-16}; 379 bits<16> offset = addr{15-0}; 380 381 bits<32> Inst; 382 383 let Inst{31-26} = op; 384 let Inst{25-21} = rt; 385 let Inst{20-16} = base; 386 let Inst{15-0} = offset; 387 } 388 389 class LOAD_WORD_FM_MMR6 { 390 bits<5> rt; 391 bits<21> addr; 392 bits<5> base = addr{20-16}; 393 bits<16> offset = addr{15-0}; 394 395 bits<32> Inst; 396 397 let Inst{31-26} = 0b111111; 398 let Inst{25-21} = rt; 399 let Inst{20-16} = base; 400 let Inst{15-0} = offset; 401 } 402 403 class LOAD_UPPER_IMM_FM_MMR6 { 404 bits<5> rt; 405 bits<16> imm16; 406 407 bits<32> Inst; 408 409 let Inst{31-26} = 0b000100; 410 let Inst{25-21} = rt; 411 let Inst{20-16} = 0; 412 let Inst{15-0} = imm16; 413 } 414 415 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 416 : MMR6Arch<instr_asm>, MipsR6Inst { 417 bits<5> rt; 418 bits<16> offset; 419 420 bits<32> Inst; 421 422 let Inst{31-26} = funct; 423 let Inst{25-21} = rt; 424 let Inst{20-16} = 0b00000; 425 let Inst{15-0} = offset; 426 } 427 428 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 429 : MMR6Arch<instr_asm>, MipsR6Inst { 430 bits<5> rt; 431 bits<16> offset; 432 433 bits<32> Inst; 434 435 let Inst{31-26} = funct; 436 let Inst{25-21} = rt; 437 let Inst{20-16} = rt; 438 let Inst{15-0} = offset; 439 } 440 441 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct> 442 : MipsR6Inst, MMR6Arch<instr_asm> { 443 bits<5> rt; 444 bits<5> rs; 445 446 bits<32> Inst; 447 448 let Inst{31-26} = 0; 449 let Inst{25-21} = rt; 450 let Inst{20-16} = rs; 451 let Inst{15-6} = funct; 452 let Inst{5-0} = 0b111100; 453 } 454 455 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct> 456 : MMR6Arch<instr_asm>, MipsR6Inst { 457 bits<5> rt; 458 bits<5> rs; 459 bits<5> size; 460 bits<5> pos; 461 462 bits<32> Inst; 463 464 let Inst{31-26} = 0; 465 let Inst{25-21} = rt; 466 let Inst{20-16} = rs; 467 let Inst{15-11} = size; 468 let Inst{10-6} = pos; 469 let Inst{5-0} = funct; 470 } 471 472 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct> 473 : MMR6Arch<instr_asm> { 474 bits<32> Inst; 475 476 let Inst{31-26} = 0x00; 477 let Inst{25-16} = 0x00; 478 let Inst{15-6} = funct; 479 let Inst{5-0} = 0x3c; 480 } 481 482 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> { 483 bits<32> Inst; 484 485 let Inst{31-26} = 0x00; 486 let Inst{25-17} = 0x00; 487 let Inst{16-16} = 0x01; 488 let Inst{15-6} = 0x3cd; 489 let Inst{5-0} = 0x3c; 490 } 491 492 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> { 493 bits<10> code_1; 494 bits<10> code_2; 495 bits<32> Inst; 496 let Inst{31-26} = 0x0; 497 let Inst{25-16} = code_1; 498 let Inst{15-6} = code_2; 499 let Inst{5-0} = 0x07; 500 } 501 502 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 503 bits<32> Inst; 504 505 let Inst{31-26} = 0x0; 506 let Inst{25-21} = 0x0; 507 let Inst{20-16} = 0x0; 508 let Inst{15-11} = op; 509 let Inst{10-6} = 0x0; 510 let Inst{5-0} = 0x0; 511 } 512 513 class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct> 514 : MMR6Arch<instr_asm> { 515 bits<32> Inst; 516 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt 517 518 let Inst{31-26} = 0x00; 519 let Inst{25-21} = 0x00; 520 let Inst{20-16} = rt; 521 let Inst{15-6} = funct; 522 let Inst{5-0} = 0x3c; 523 } 524 525 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> { 526 bits<5> rd; 527 bits<5> rt; 528 bits<5> shamt; 529 530 bits<32> Inst; 531 532 let Inst{31-26} = 0; 533 let Inst{25-21} = rd; 534 let Inst{20-16} = rt; 535 let Inst{15-11} = shamt; 536 let Inst{10} = rotate; 537 let Inst{9-0} = funct; 538 } 539 540 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 541 bits<5> rt; 542 bits<21> addr; 543 544 bits<32> Inst; 545 546 let Inst{31-26} = op; 547 let Inst{25-21} = rt; 548 let Inst{20-16} = addr{20-16}; 549 let Inst{15-0} = addr{15-0}; 550 } 551 552 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct> 553 : MMR6Arch<instr_asm>, MipsR6Inst { 554 bits<5> ft; 555 bits<5> fs; 556 bits<5> fd; 557 558 bits<32> Inst; 559 560 let Inst{31-26} = 0b010101; 561 let Inst{25-21} = ft; 562 let Inst{20-16} = fs; 563 let Inst{15-11} = fd; 564 let Inst{10} = 0; 565 let Inst{9-8} = fmt; 566 let Inst{7-0} = funct; 567 } 568 569 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 570 : MMR6Arch<instr_asm>, MipsR6Inst { 571 bits<5> ft; 572 bits<5> fs; 573 bits<5> fd; 574 575 bits<32> Inst; 576 577 let Inst{31-26} = 0b010101; 578 let Inst{25-21} = ft; 579 let Inst{20-16} = fs; 580 let Inst{15-11} = fd; 581 let Inst{10-9} = fmt; 582 let Inst{8-0} = funct; 583 } 584 585 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 586 : MMR6Arch<instr_asm>, MipsR6Inst { 587 bits<5> ft; 588 bits<5> fs; 589 590 bits<32> Inst; 591 592 let Inst{31-26} = 0b010101; 593 let Inst{25-21} = ft; 594 let Inst{20-16} = fs; 595 let Inst{15} = 0; 596 let Inst{14-13} = fmt; 597 let Inst{12-6} = funct; 598 let Inst{5-0} = 0b111011; 599 } 600 601 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct> 602 : MMR6Arch<instr_asm>, MipsR6Inst { 603 bits<5> ft; 604 bits<5> fs; 605 bits<5> fd; 606 607 bits<32> Inst; 608 609 let Inst{31-26} = 0b010101; 610 let Inst{25-21} = ft; 611 let Inst{20-16} = fs; 612 let Inst{15-11} = fd; 613 let Inst{10-9} = fmt; 614 let Inst{8-0} = funct; 615 } 616 617 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond> 618 : MMR6Arch<instr_asm>, MipsR6Inst { 619 bits<5> ft; 620 bits<5> fs; 621 bits<5> fd; 622 623 bits<32> Inst; 624 625 let Inst{31-26} = 0b010101; 626 let Inst{25-21} = ft; 627 let Inst{20-16} = fs; 628 let Inst{15-11} = fd; 629 let Inst{10-6} = Cond.Value; 630 let Inst{5-0} = format; 631 } 632 633 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct> 634 : MMR6Arch<instr_asm>, MipsR6Inst { 635 bits<5> ft; 636 bits<5> fs; 637 638 bits<32> Inst; 639 let Inst{31-26} = 0b010101; 640 let Inst{25-21} = ft; 641 let Inst{20-16} = fs; 642 let Inst{15} = 0; 643 let Inst{14} = fmt; 644 let Inst{13-6} = funct; 645 let Inst{5-0} = 0b111011; 646 } 647 648 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct> 649 : MMR6Arch<instr_asm>, MipsR6Inst { 650 bits<5> ft; 651 bits<5> fs; 652 653 bits<32> Inst; 654 let Inst{31-26} = 0b010101; 655 let Inst{25-21} = ft; 656 let Inst{20-16} = fs; 657 let Inst{15} = 0; 658 let Inst{14-13} = fmt; 659 let Inst{12-6} = funct; 660 let Inst{5-0} = 0b111011; 661 } 662 663 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 664 : MMR6Arch<instr_asm>, MipsR6Inst { 665 bits<5> ft; 666 bits<5> fs; 667 668 bits<32> Inst; 669 670 let Inst{31-26} = 0b010101; 671 let Inst{25-21} = ft; 672 let Inst{20-16} = fs; 673 let Inst{15} = 0; 674 let Inst{14-13} = fmt; 675 let Inst{12-6} = funct; 676 let Inst{5-0} = 0b111011; 677 } 678 679 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 680 : MMR6Arch<instr_asm>, MipsR6Inst { 681 bits<5> ft; 682 bits<5> fs; 683 684 bits<32> Inst; 685 686 let Inst{31-26} = 0b010101; 687 let Inst{25-21} = ft; 688 let Inst{20-16} = fs; 689 let Inst{15} = 0; 690 let Inst{14} = fmt; 691 let Inst{13-6} = funct; 692 let Inst{5-0} = 0b111011; 693 } 694 695 class POOL16A_ADDU16_FM_MMR6 { 696 bits<3> rs; 697 bits<3> rt; 698 bits<3> rd; 699 700 bits<16> Inst; 701 702 let Inst{15-10} = 0b000001; 703 let Inst{9-7} = rs; 704 let Inst{6-4} = rt; 705 let Inst{3-1} = rd; 706 let Inst{0} = 0; 707 } 708 709 class POOL16C_AND16_FM_MMR6 { 710 bits<3> rt; 711 bits<3> rs; 712 713 bits<16> Inst; 714 715 let Inst{15-10} = 0b010001; 716 let Inst{9-7} = rt; 717 let Inst{6-4} = rs; 718 let Inst{3-0} = 0b0001; 719 } 720 721 class POOL16C_NOT16_FM_MMR6 { 722 bits<3> rt; 723 bits<3> rs; 724 725 bits<16> Inst; 726 727 let Inst{15-10} = 0x11; 728 let Inst{9-7} = rt; 729 let Inst{6-4} = rs; 730 let Inst{3-0} = 0b0000; 731 } 732 733 class POOL16C_MOVEP16_FM_MMR6 { 734 bits<3> dst_regs; 735 bits<3> rt; 736 bits<3> rs; 737 738 bits<16> Inst; 739 740 let Inst{15-10} = 0b010001; 741 let Inst{9-7} = dst_regs; 742 let Inst{6-4} = rt; 743 let Inst{3} = rs{2}; 744 let Inst{2} = 0b1; 745 let Inst{1-0} = rs{1-0}; 746 } 747 748 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> { 749 bits<3> rt; 750 bits<3> rs; 751 752 bits<16> Inst; 753 754 let Inst{15-10} = 0b010001; 755 let Inst{9-7} = rt; 756 let Inst{6-4} = rs; 757 let Inst{3-0} = op; 758 } 759 760 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> { 761 bits<4> code_; 762 bits<16> Inst; 763 764 let Inst{15-10} = 0b010001; 765 let Inst{9-6} = code_; 766 let Inst{5-0} = op; 767 } 768 769 class POOL16A_SUBU16_FM_MMR6 { 770 bits<3> rs; 771 bits<3> rt; 772 bits<3> rd; 773 774 bits<16> Inst; 775 776 let Inst{15-10} = 0b000001; 777 let Inst{9-7} = rs; 778 let Inst{6-4} = rt; 779 let Inst{3-1} = rd; 780 let Inst{0} = 0b1; 781 } 782 783 class POOL32A_WRPGPR_WSBH_FM_MMR6<string instr_asm, bits<10> funct> 784 : MMR6Arch<instr_asm>, MipsR6Inst { 785 bits<5> rt; 786 bits<5> rs; 787 788 bits<32> Inst; 789 790 let Inst{31-26} = 0x00; 791 let Inst{25-21} = rt; 792 let Inst{20-16} = rs; 793 let Inst{15-6} = funct; 794 let Inst{5-0} = 0x3c; 795 } 796 797 class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 798 : MMR6Arch<instr_asm>, MipsR6Inst { 799 bits<5> ft; 800 bits<5> fs; 801 802 bits<32> Inst; 803 804 let Inst{31-26} = 0b010101; 805 let Inst{25-21} = ft; 806 let Inst{20-16} = fs; 807 let Inst{15} = 0; 808 let Inst{14} = fmt; 809 let Inst{13-6} = funct; 810 let Inst{5-0} = 0b111011; 811 } 812 813 class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> 814 : MMR6Arch<instr_asm>, MipsR6Inst { 815 bits<5> fs; 816 bits<5> fd; 817 818 bits<32> Inst; 819 820 let Inst{31-26} = 0b010101; 821 let Inst{25-21} = fs; 822 let Inst{20-16} = fd; 823 let Inst{15-11} = 0; 824 let Inst{10-9} = fmt; 825 let Inst{8-0} = 0b000100000; 826 } 827 828 class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 829 : MMR6Arch<instr_asm>, MipsR6Inst { 830 bits<5> ft; 831 bits<5> fs; 832 bits<5> fd; 833 834 bits<32> Inst; 835 836 let Inst{31-26} = 0b010101; 837 let Inst{25-21} = ft; 838 let Inst{20-16} = fs; 839 let Inst{15-11} = fd; 840 let Inst{10-9} = fmt; 841 let Inst{8-0} = funct; 842 } 843 844 class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 845 : MMR6Arch<instr_asm>, MipsR6Inst { 846 bits<5> fs; 847 bits<5> fd; 848 849 bits<32> Inst; 850 851 let Inst{31-26} = 0b010101; 852 let Inst{25-21} = fs; 853 let Inst{20-16} = fd; 854 let Inst{15-11} = 0b00000; 855 let Inst{10-9} = fmt; 856 let Inst{8-0} = funct; 857 } 858 859 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct> 860 : MMR6Arch<instr_asm>, MipsR6Inst { 861 bits<32> Inst; 862 863 let Inst{31-26} = 0x0; 864 let Inst{25-16} = 0x0; 865 let Inst{15-6} = funct; 866 let Inst{5-0} = 0b111100; 867 } 868 869 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode> 870 : MMR6Arch<instr_asm>, MipsR6Inst { 871 bits<5> rt; 872 bits<5> rs; 873 bits<3> sel; 874 875 bits<32> Inst; 876 877 let Inst{31-26} = 0b000000; 878 let Inst{25-21} = rt; 879 let Inst{20-16} = rs; 880 let Inst{15-14} = 0; 881 let Inst{13-11} = sel; 882 let Inst{10-6} = funct; 883 let Inst{5-0} = opcode; 884 } 885 886 class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv> 887 : MMR6Arch<instr_asm>, MipsR6Inst { 888 bits<5> rs; 889 bits<2> type; 890 891 bits<32> Inst; 892 893 let Inst{31-26} = 0x0; 894 let Inst{25-21} = 0x0; 895 let Inst{20-16} = rs; 896 let Inst{15-13} = 0b011; 897 let Inst{12-11} = ginv; 898 let Inst{10-9} = type; 899 let Inst{8-6} = 0b101; 900 let Inst{5-0} = 0b111100; 901 } 902 903 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct> 904 : MMR6Arch<instr_asm> { 905 bits<5> rt; 906 bits<5> fs; 907 908 bits<32> Inst; 909 910 let Inst{31-26} = 0b010101; 911 let Inst{25-21} = rt; 912 let Inst{20-16} = fs; 913 let Inst{15-14} = 0; 914 let Inst{13-6} = funct; 915 let Inst{5-0} = 0b111011; 916 } 917 918 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct> 919 : MMR6Arch<instr_asm>, MipsR6Inst { 920 bits<5> rt; 921 bits<5> impl; 922 923 bits<32> Inst; 924 925 let Inst{31-26} = 0b000000; 926 let Inst{25-21} = rt; 927 let Inst{20-16} = impl; 928 let Inst{15-6} = funct; 929 let Inst{5-0} = 0b111100; 930 } 931 932 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct> 933 : MipsR6Inst, MMR6Arch<opstr> { 934 bits<5> rt; 935 bits<5> rs; 936 bits<16> offset; 937 938 bits<32> Inst; 939 940 let Inst{31-26} = funct; 941 let Inst{25-21} = rt; 942 let Inst{20-16} = rs; 943 let Inst{15-0} = offset; 944 } 945 946 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct> 947 : MMR6Arch<instr_asm>, MipsR6Inst { 948 bits<5> rs; 949 950 bits<32> Inst; 951 952 let Inst{31-26} = 0b000000; 953 let Inst{25-21} = 0b00000; 954 let Inst{20-16} = rs; 955 let Inst{15-6} = funct; 956 let Inst{5-0} = 0b111100; 957 } 958 959 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst { 960 bits<5> rs; 961 bits<21> offset; 962 963 bits<32> Inst; 964 965 let Inst{31-26} = funct; 966 let Inst{25-21} = rs; 967 let Inst{20-0} = offset; 968 } 969 970 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct> 971 : MMR6Arch<instr_asm> { 972 bits<5> rt; 973 bits<16> offset; 974 975 bits<32> Inst; 976 977 let Inst{31-26} = 0b010000; 978 let Inst{25-21} = funct; 979 let Inst{20-16} = rt; 980 let Inst{15-0} = offset; 981 } 982 983 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct> 984 : MMR6Arch<instr_asm> { 985 bits<5> ft; 986 bits<21> addr; 987 bits<5> base = addr{20-16}; 988 bits<16> offset = addr{15-0}; 989 990 bits<32> Inst; 991 992 let Inst{31-26} = funct; 993 let Inst{25-21} = ft; 994 let Inst{20-16} = base; 995 let Inst{15-0} = offset; 996 } 997 998 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct> 999 : MMR6Arch<instr_asm>, MipsR6Inst { 1000 bits<5> rt; 1001 bits<21> addr; 1002 bits<5> base = addr{20-16}; 1003 bits<11> offset = addr{10-0}; 1004 1005 bits<32> Inst; 1006 1007 let Inst{31-26} = 0b001000; 1008 let Inst{25-21} = rt; 1009 let Inst{20-16} = base; 1010 let Inst{15-12} = funct; 1011 let Inst{11} = 0; 1012 let Inst{10-0} = offset; 1013 } 1014 1015 class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc, 1016 bits<3> minorFunc> 1017 : MMR6Arch<instr_asm>, MipsR6Inst { 1018 bits<5> rt; 1019 bits<21> addr; 1020 bits<5> base = addr{20-16}; 1021 bits<9> offset = addr{8-0}; 1022 1023 bits<32> Inst; 1024 1025 let Inst{31-26} = 0b011000; 1026 let Inst{25-21} = rt; 1027 let Inst{20-16} = base; 1028 let Inst{15-12} = majorFunc; 1029 let Inst{11-9} = minorFunc; 1030 let Inst{8-0} = offset; 1031 } 1032
