1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This is the top level entry point for the Mips target. 10 //===----------------------------------------------------------------------===// 11 12 //===----------------------------------------------------------------------===// 13 // Target-independent interfaces 14 //===----------------------------------------------------------------------===// 15 16 include "llvm/Target/Target.td" 17 18 // The overall idea of the PredicateControl class is to chop the Predicates list 19 // into subsets that are usually overridden independently. This allows 20 // subclasses to partially override the predicates of their superclasses without 21 // having to re-add all the existing predicates. 22 class PredicateControl { 23 // Predicates for the encoding scheme in use such as HasStdEnc 24 list<Predicate> EncodingPredicates = []; 25 // Predicates for the GPR size such as IsGP64bit 26 list<Predicate> GPRPredicates = []; 27 // Predicates for the PTR size such as IsPTR64bit 28 list<Predicate> PTRPredicates = []; 29 // Predicates for the FGR size and layout such as IsFP64bit 30 list<Predicate> FGRPredicates = []; 31 // Predicates for the instruction group membership such as ISA's. 32 list<Predicate> InsnPredicates = []; 33 // Predicate for the ASE that an instruction belongs to. 34 list<Predicate> ASEPredicate = []; 35 // Predicate for marking the instruction as usable in hard-float mode only. 36 list<Predicate> HardFloatPredicate = []; 37 // Predicates for anything else 38 list<Predicate> AdditionalPredicates = []; 39 list<Predicate> Predicates = !listconcat(EncodingPredicates, 40 GPRPredicates, 41 PTRPredicates, 42 FGRPredicates, 43 InsnPredicates, 44 HardFloatPredicate, 45 ASEPredicate, 46 AdditionalPredicates); 47 } 48 49 // Like Requires<> but for the AdditionalPredicates list 50 class AdditionalRequires<list<Predicate> preds> { 51 list<Predicate> AdditionalPredicates = preds; 52 } 53 54 //===----------------------------------------------------------------------===// 55 // Register File, Calling Conv, Instruction Descriptions 56 //===----------------------------------------------------------------------===// 57 58 include "MipsRegisterInfo.td" 59 include "MipsSchedule.td" 60 include "MipsInstrInfo.td" 61 include "MipsCallingConv.td" 62 include "MipsRegisterBanks.td" 63 64 // Avoid forward declaration issues. 65 include "MipsScheduleP5600.td" 66 include "MipsScheduleGeneric.td" 67 68 def MipsInstrInfo : InstrInfo; 69 70 //===----------------------------------------------------------------------===// 71 // Mips Subtarget features // 72 //===----------------------------------------------------------------------===// 73 74 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", 75 "Disable SVR4-style position-independent code">; 76 def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true", 77 "Pointers are 64-bit wide">; 78 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 79 "General Purpose Registers are 64-bit wide">; 80 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 81 "Support 64-bit FP registers">; 82 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true", 83 "Support for FPXX">; 84 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true", 85 "IEEE 754-2008 NaN encoding">; 86 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 87 "true", "Only supports single precision float">; 88 def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true", 89 "Does not support floating point instructions">; 90 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", 91 "Disable odd numbered single-precision " 92 "registers">; 93 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 94 "true", "Enable vector FPU instructions">; 95 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", 96 "Mips I ISA Support [highly experimental]">; 97 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", 98 "Mips II ISA Support [highly experimental]", 99 [FeatureMips1]>; 100 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true", 101 "Subset of MIPS-III that is also in MIPS32 " 102 "[highly experimental]">; 103 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true", 104 "Subset of MIPS-III that is also in MIPS32r2 " 105 "[highly experimental]">; 106 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3", 107 "MIPS III ISA Support [highly experimental]", 108 [FeatureMips2, FeatureMips3_32, 109 FeatureMips3_32r2, FeatureGP64Bit, 110 FeatureFP64Bit]>; 111 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true", 112 "Subset of MIPS-IV that is also in MIPS32 " 113 "[highly experimental]">; 114 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true", 115 "Subset of MIPS-IV that is also in MIPS32r2 " 116 "[highly experimental]">; 117 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", 118 "Mips4", "MIPS IV ISA Support", 119 [FeatureMips3, FeatureMips4_32, 120 FeatureMips4_32r2]>; 121 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true", 122 "Subset of MIPS-V that is also in MIPS32r2 " 123 "[highly experimental]">; 124 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5", 125 "MIPS V ISA Support [highly experimental]", 126 [FeatureMips4, FeatureMips5_32r2]>; 127 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 128 "Mips32 ISA Support", 129 [FeatureMips2, FeatureMips3_32, 130 FeatureMips4_32]>; 131 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 132 "Mips32r2", "Mips32r2 ISA Support", 133 [FeatureMips3_32r2, FeatureMips4_32r2, 134 FeatureMips5_32r2, FeatureMips32]>; 135 def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion", 136 "Mips32r3", "Mips32r3 ISA Support", 137 [FeatureMips32r2]>; 138 def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion", 139 "Mips32r5", "Mips32r5 ISA Support", 140 [FeatureMips32r3]>; 141 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", 142 "Mips32r6", 143 "Mips32r6 ISA Support [experimental]", 144 [FeatureMips32r5, FeatureFP64Bit, 145 FeatureNaN2008]>; 146 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 147 "Mips64", "Mips64 ISA Support", 148 [FeatureMips5, FeatureMips32]>; 149 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 150 "Mips64r2", "Mips64r2 ISA Support", 151 [FeatureMips64, FeatureMips32r2]>; 152 def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion", 153 "Mips64r3", "Mips64r3 ISA Support", 154 [FeatureMips64r2, FeatureMips32r3]>; 155 def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion", 156 "Mips64r5", "Mips64r5 ISA Support", 157 [FeatureMips64r3, FeatureMips32r5]>; 158 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion", 159 "Mips64r6", 160 "Mips64r6 ISA Support [experimental]", 161 [FeatureMips32r6, FeatureMips64r5, 162 FeatureNaN2008]>; 163 def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true", 164 "Symbols are 32 bit on Mips64">; 165 166 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 167 "Mips16 mode">; 168 169 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 170 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 171 "Mips DSP-R2 ASE", [FeatureDSP]>; 172 def FeatureDSPR3 173 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE", 174 [ FeatureDSP, FeatureDSPR2 ]>; 175 176 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 177 178 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; 179 180 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">; 181 182 def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true", 183 "Mips Virtualization ASE">; 184 185 def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true", 186 "Mips Global Invalidate ASE">; 187 188 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 189 "microMips mode">; 190 191 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips", 192 "true", "Octeon cnMIPS Support", 193 [FeatureMips64r2]>; 194 195 def FeatureUseTCCInDIV : SubtargetFeature< 196 "use-tcc-in-div", 197 "UseTCCInDIV", "false", 198 "Force the assembler to use trapping">; 199 200 def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true", 201 "Disable 4-operand madd.fmt and related instructions">; 202 203 def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">; 204 205 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true", 206 "Disable use of the jal instruction">; 207 208 def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", 209 "UseIndirectJumpsHazard", 210 "true", "Use indirect jump" 211 " guards to prevent certain speculation based attacks">; 212 //===----------------------------------------------------------------------===// 213 // Mips processors supported. 214 //===----------------------------------------------------------------------===// 215 216 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", 217 "MipsSubtarget::CPU::P5600", 218 "The P5600 Processor", [FeatureMips32r5]>; 219 220 class Proc<string Name, list<SubtargetFeature> Features> 221 : ProcessorModel<Name, MipsGenericModel, Features>; 222 223 def : Proc<"mips1", [FeatureMips1]>; 224 def : Proc<"mips2", [FeatureMips2]>; 225 def : Proc<"mips32", [FeatureMips32]>; 226 def : Proc<"mips32r2", [FeatureMips32r2]>; 227 def : Proc<"mips32r3", [FeatureMips32r3]>; 228 def : Proc<"mips32r5", [FeatureMips32r5]>; 229 def : Proc<"mips32r6", [FeatureMips32r6]>; 230 231 def : Proc<"mips3", [FeatureMips3]>; 232 def : Proc<"mips4", [FeatureMips4]>; 233 def : Proc<"mips5", [FeatureMips5]>; 234 def : Proc<"mips64", [FeatureMips64]>; 235 def : Proc<"mips64r2", [FeatureMips64r2]>; 236 def : Proc<"mips64r3", [FeatureMips64r3]>; 237 def : Proc<"mips64r5", [FeatureMips64r5]>; 238 def : Proc<"mips64r6", [FeatureMips64r6]>; 239 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>; 240 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>; 241 242 def MipsAsmParser : AsmParser { 243 let ShouldEmitMatchRegisterName = 0; 244 } 245 246 def MipsAsmParserVariant : AsmParserVariant { 247 int Variant = 0; 248 249 // Recognize hard coded registers. 250 string RegisterPrefix = "$"; 251 } 252 253 def Mips : Target { 254 let InstructionSet = MipsInstrInfo; 255 let AssemblyParsers = [MipsAsmParser]; 256 let AssemblyParserVariants = [MipsAsmParserVariant]; 257 let AllowRegisterRenaming = 1; 258 } 259
