1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips32r6 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 include "Mips32r6InstrFormats.td" 15 16 //===----------------------------------------------------------------------===// 17 // 18 // Mips profiles and nodes 19 // 20 //===----------------------------------------------------------------------===// 21 22 def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>, 23 SDTCisSameAs<0,2>, 24 SDTCisSameAs<2,3>]>; 25 26 def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>; 27 28 //===----------------------------------------------------------------------===// 29 // 30 // Mips Operands 31 // 32 //===----------------------------------------------------------------------===// 33 34 // Notes about removals/changes from MIPS32r6: 35 // Reencoded: jr -> jalr 36 // Reencoded: jr.hb -> jalr.hb 37 38 def brtarget21 : Operand<OtherVT> { 39 let EncoderMethod = "getBranchTarget21OpValue"; 40 let OperandType = "OPERAND_PCREL"; 41 let DecoderMethod = "DecodeBranchTarget21"; 42 let ParserMatchClass = MipsJumpTargetAsmOperand; 43 } 44 45 def brtarget26 : Operand<OtherVT> { 46 let EncoderMethod = "getBranchTarget26OpValue"; 47 let OperandType = "OPERAND_PCREL"; 48 let DecoderMethod = "DecodeBranchTarget26"; 49 let ParserMatchClass = MipsJumpTargetAsmOperand; 50 } 51 52 def jmpoffset16 : Operand<OtherVT> { 53 let EncoderMethod = "getJumpOffset16OpValue"; 54 let ParserMatchClass = MipsJumpTargetAsmOperand; 55 } 56 57 def calloffset16 : Operand<iPTR> { 58 let EncoderMethod = "getJumpOffset16OpValue"; 59 let ParserMatchClass = MipsJumpTargetAsmOperand; 60 } 61 62 //===----------------------------------------------------------------------===// 63 // 64 // Instruction Encodings 65 // 66 //===----------------------------------------------------------------------===// 67 68 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; 69 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; 70 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; 71 class AUI_ENC : AUI_FM; 72 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; 73 74 class BAL_ENC : BAL_FM; 75 class BALC_ENC : BRANCH_OFF26_FM<0b111010>; 76 class BC_ENC : BRANCH_OFF26_FM<0b110010>; 77 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 78 DecodeDisambiguates<"AddiGroupBranch">; 79 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>, 80 DecodeDisambiguatedBy<"DaddiGroupBranch">; 81 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 82 DecodeDisambiguates<"DaddiGroupBranch">; 83 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>, 84 DecodeDisambiguatedBy<"DaddiGroupBranch">; 85 86 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>, 87 DecodeDisambiguates<"BgtzlGroupBranch">; 88 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>, 89 DecodeDisambiguatedBy<"BlezlGroupBranch">; 90 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>, 91 DecodeDisambiguatedBy<"BlezGroupBranch">; 92 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>, 93 DecodeDisambiguates<"BlezlGroupBranch">; 94 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>, 95 DecodeDisambiguatedBy<"BgtzGroupBranch">; 96 97 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>, 98 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 99 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>, 100 DecodeDisambiguatedBy<"BgtzGroupBranch">; 101 102 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>, 103 DecodeDisambiguatedBy<"BlezlGroupBranch">; 104 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>, 105 DecodeDisambiguates<"BgtzGroupBranch">; 106 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>, 107 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 108 109 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; 110 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>, 111 DecodeDisambiguates<"BlezGroupBranch">; 112 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; 113 114 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>; 115 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; 116 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; 117 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; 118 119 class DVP_ENC : COP0_EVP_DVP_FM<0b1>; 120 class EVP_ENC : COP0_EVP_DVP_FM<0b0>; 121 122 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; 123 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; 124 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>; 125 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; 126 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>, 127 DecodeDisambiguatedBy<"BlezGroupBranch">; 128 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 129 DecodeDisambiguatedBy<"DaddiGroupBranch">; 130 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 131 DecodeDisambiguatedBy<"AddiGroupBranch">; 132 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; 133 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; 134 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; 135 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; 136 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; 137 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; 138 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; 139 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; 140 141 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>; 142 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>; 143 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>; 144 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; 145 146 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; 147 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; 148 149 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>; 150 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; 151 152 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>; 153 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 154 155 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; 156 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; 157 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; 158 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; 159 160 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; 161 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; 162 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; 163 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; 164 165 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; 166 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; 167 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; 168 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; 169 170 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; 171 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; 172 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; 173 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; 174 175 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>; 176 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>; 177 178 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>; 179 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>; 180 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>; 181 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>; 182 183 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>; 184 185 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; 186 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; 187 188 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>; 189 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>; 190 191 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM; 192 193 class CRC32B_ENC : SPECIAL3_2R_SZ_CRC<0,0>; 194 class CRC32H_ENC : SPECIAL3_2R_SZ_CRC<1,0>; 195 class CRC32W_ENC : SPECIAL3_2R_SZ_CRC<2,0>; 196 class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>; 197 class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>; 198 class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>; 199 200 class GINVI_ENC : SPECIAL3_GINV<0>; 201 class GINVT_ENC : SPECIAL3_GINV<2>; 202 203 //===----------------------------------------------------------------------===// 204 // 205 // Instruction Multiclasses 206 // 207 //===----------------------------------------------------------------------===// 208 209 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, 210 RegisterOperand FGROpnd, 211 InstrItinClass Itin, 212 SDPatternOperator Op = null_frag> { 213 dag OutOperandList = (outs FGRCCOpnd:$fd); 214 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 215 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); 216 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; 217 bit isCTI = 1; 218 InstrItinClass Itinerary = Itin; 219 } 220 221 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, 222 RegisterOperand FGROpnd, InstrItinClass Itin>{ 223 let AdditionalPredicates = [NotInMicroMips] in { 224 def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>, 225 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, 226 MipsR6Arch<!strconcat("cmp.af.", Typestr)>, 227 ISA_MIPS32R6, HARDFLOAT; 228 def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, 229 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, 230 MipsR6Arch<!strconcat("cmp.un.", Typestr)>, 231 ISA_MIPS32R6, HARDFLOAT; 232 def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, 233 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, 234 setoeq>, 235 MipsR6Arch<!strconcat("cmp.eq.", Typestr)>, 236 ISA_MIPS32R6, HARDFLOAT; 237 def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 238 FIELD_CMP_COND_UEQ>, 239 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, 240 setueq>, 241 MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>, 242 ISA_MIPS32R6, HARDFLOAT; 243 def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, 244 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, 245 setolt>, 246 MipsR6Arch<!strconcat("cmp.lt.", Typestr)>, 247 ISA_MIPS32R6, HARDFLOAT; 248 def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 249 FIELD_CMP_COND_ULT>, 250 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, 251 setult>, 252 MipsR6Arch<!strconcat("cmp.ult.", Typestr)>, 253 ISA_MIPS32R6, HARDFLOAT; 254 def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, 255 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, 256 setole>, 257 MipsR6Arch<!strconcat("cmp.le.", Typestr)>, 258 ISA_MIPS32R6, HARDFLOAT; 259 def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 260 FIELD_CMP_COND_ULE>, 261 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, 262 setule>, 263 MipsR6Arch<!strconcat("cmp.ule.", Typestr)>, 264 ISA_MIPS32R6, HARDFLOAT; 265 def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 266 FIELD_CMP_COND_SAF>, 267 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, 268 MipsR6Arch<!strconcat("cmp.saf.", Typestr)>, 269 ISA_MIPS32R6, HARDFLOAT; 270 def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 271 FIELD_CMP_COND_SUN>, 272 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, 273 MipsR6Arch<!strconcat("cmp.sun.", Typestr)>, 274 ISA_MIPS32R6, HARDFLOAT; 275 def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 276 FIELD_CMP_COND_SEQ>, 277 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, 278 MipsR6Arch<!strconcat("cmp.seq.", Typestr)>, 279 ISA_MIPS32R6, HARDFLOAT; 280 def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 281 FIELD_CMP_COND_SUEQ>, 282 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, 283 MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>, 284 ISA_MIPS32R6, HARDFLOAT; 285 def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 286 FIELD_CMP_COND_SLT>, 287 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, 288 MipsR6Arch<!strconcat("cmp.slt.", Typestr)>, 289 ISA_MIPS32R6, HARDFLOAT; 290 def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 291 FIELD_CMP_COND_SULT>, 292 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, 293 MipsR6Arch<!strconcat("cmp.sult.", Typestr)>, 294 ISA_MIPS32R6, HARDFLOAT; 295 def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 296 FIELD_CMP_COND_SLE>, 297 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, 298 MipsR6Arch<!strconcat("cmp.sle.", Typestr)>, 299 ISA_MIPS32R6, HARDFLOAT; 300 def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 301 FIELD_CMP_COND_SULE>, 302 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, 303 MipsR6Arch<!strconcat("cmp.sule.", Typestr)>, 304 ISA_MIPS32R6, HARDFLOAT; 305 } 306 } 307 308 //===----------------------------------------------------------------------===// 309 // 310 // Instruction Descriptions 311 // 312 //===----------------------------------------------------------------------===// 313 314 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 315 Operand ImmOpnd, InstrItinClass itin> 316 : MipsR6Arch<instr_asm> { 317 dag OutOperandList = (outs GPROpnd:$rs); 318 dag InOperandList = (ins ImmOpnd:$imm); 319 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 320 list<dag> Pattern = []; 321 InstrItinClass Itinerary = itin; 322 } 323 324 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2, 325 II_ADDIUPC>; 326 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>; 327 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>; 328 329 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 330 Operand ImmOpnd, InstrItinClass itin> 331 : MipsR6Arch<instr_asm> { 332 dag OutOperandList = (outs GPROpnd:$rd); 333 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 334 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 335 list<dag> Pattern = []; 336 InstrItinClass Itinerary = itin; 337 } 338 339 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>; 340 341 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 342 InstrItinClass itin = NoItinerary> 343 : MipsR6Arch<instr_asm> { 344 dag OutOperandList = (outs GPROpnd:$rs); 345 dag InOperandList = (ins simm16:$imm); 346 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 347 list<dag> Pattern = []; 348 InstrItinClass Itinerary = itin; 349 } 350 351 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>; 352 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>; 353 354 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 355 InstrItinClass itin = NoItinerary> 356 : MipsR6Arch<instr_asm> { 357 dag OutOperandList = (outs GPROpnd:$rt); 358 dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); 359 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); 360 list<dag> Pattern = []; 361 InstrItinClass Itinerary = itin; 362 } 363 364 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>; 365 366 class BRANCH_DESC_BASE { 367 bit isBranch = 1; 368 bit isTerminator = 1; 369 bit hasDelaySlot = 0; 370 bit isCTI = 1; 371 } 372 373 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE, 374 MipsR6Arch<instr_asm> { 375 dag InOperandList = (ins opnd:$offset); 376 dag OutOperandList = (outs); 377 string AsmString = !strconcat(instr_asm, "\t$offset"); 378 bit isBarrier = 1; 379 InstrItinClass Itinerary = II_BC; 380 bit isCTI = 1; 381 } 382 383 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 384 RegisterOperand GPROpnd> : BRANCH_DESC_BASE, 385 MipsR6Arch<instr_asm> { 386 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 387 dag OutOperandList = (outs); 388 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 389 list<Register> Defs = [AT]; 390 InstrItinClass Itinerary = II_BCCC; 391 bit hasForbiddenSlot = 1; 392 bit isCTI = 1; 393 } 394 395 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 396 RegisterOperand GPROpnd> 397 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> { 398 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 399 dag OutOperandList = (outs); 400 string AsmString = !strconcat(instr_asm, "\t$rs, $offset"); 401 list<Register> Defs = [AT]; 402 InstrItinClass Itinerary = II_BCCZC; 403 bit hasForbiddenSlot = 1; 404 bit isCTI = 1; 405 } 406 407 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 408 RegisterOperand GPROpnd> 409 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> { 410 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 411 dag OutOperandList = (outs); 412 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 413 list<Register> Defs = [AT]; 414 InstrItinClass Itinerary = II_BCCZC; 415 bit hasForbiddenSlot = 1; 416 bit isCTI = 1; 417 } 418 419 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> { 420 bit isCall = 1; 421 bit hasDelaySlot = 1; 422 list<Register> Defs = [RA]; 423 bit isCTI = 1; 424 } 425 426 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> { 427 bit isCall = 1; 428 list<Register> Defs = [RA]; 429 InstrItinClass Itinerary = II_BALC; 430 bit isCTI = 1; 431 } 432 433 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>; 434 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>; 435 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>; 436 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>; 437 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>; 438 439 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>; 440 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>; 441 442 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>; 443 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>; 444 445 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>; 446 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>; 447 448 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>; 449 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>; 450 451 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 452 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset); 453 dag OutOperandList = (outs); 454 string AsmString = instr_asm; 455 bit hasDelaySlot = 1; 456 InstrItinClass Itinerary = II_BC1CCZ; 457 } 458 459 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">; 460 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">; 461 462 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 463 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset); 464 dag OutOperandList = (outs); 465 string AsmString = instr_asm; 466 bit hasDelaySlot = 1; 467 bit isCTI = 1; 468 InstrItinClass Itinerary = II_BC2CCZ; 469 } 470 471 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; 472 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">; 473 474 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; 475 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; 476 477 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 478 RegisterOperand GPROpnd, 479 InstrItinClass itin = NoItinerary> 480 : MipsR6Arch<opstr> { 481 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 482 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 483 list<dag> Pattern = []; 484 bit hasDelaySlot = 0; 485 InstrItinClass Itinerary = itin; 486 bit isCTI = 1; 487 bit isBranch = 1; 488 bit isIndirectBranch = 1; 489 } 490 491 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 492 GPR32Opnd, II_JIALC> { 493 bit isCall = 1; 494 list<Register> Defs = [RA]; 495 } 496 497 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, 498 GPR32Opnd, II_JIALC> { 499 bit isBarrier = 1; 500 bit isTerminator = 1; 501 list<Register> Defs = [AT]; 502 } 503 504 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 505 bit isBranch = 1; 506 bit isIndirectBranch = 1; 507 bit hasDelaySlot = 1; 508 bit isTerminator=1; 509 bit isBarrier=1; 510 bit isCTI = 1; 511 InstrItinClass Itinerary = II_JR_HB; 512 } 513 514 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 515 InstrItinClass itin> 516 : MipsR6Arch<instr_asm> { 517 dag OutOperandList = (outs GPROpnd:$rd); 518 dag InOperandList = (ins GPROpnd:$rt); 519 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 520 list<dag> Pattern = []; 521 InstrItinClass Itinerary = itin; 522 } 523 524 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>; 525 526 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 527 InstrItinClass itin, 528 SDPatternOperator Op=null_frag> 529 : MipsR6Arch<instr_asm> { 530 dag OutOperandList = (outs GPROpnd:$rd); 531 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 532 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 533 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 534 InstrItinClass Itinerary = itin; 535 // This instruction doesn't trap division by zero itself. We must insert 536 // teq instructions as well. 537 bit usesCustomInserter = 1; 538 } 539 540 class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin> 541 : MipsR6Arch<instr_asm> { 542 dag OutOperandList = (outs GPR32Opnd:$rt); 543 dag InOperandList = (ins); 544 string AsmString = !strconcat(instr_asm, "\t$rt"); 545 list<dag> Pattern = []; 546 InstrItinClass Itinerary = Itin; 547 bit hasUnModeledSideEffects = 1; 548 } 549 550 class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>; 551 class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>; 552 553 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>; 554 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>; 555 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>; 556 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>; 557 558 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { 559 list<Register> Defs = [RA]; 560 } 561 562 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { 563 list<Register> Defs = [RA]; 564 } 565 566 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { 567 list<Register> Defs = [RA]; 568 } 569 570 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { 571 list<Register> Defs = [RA]; 572 } 573 574 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { 575 list<Register> Defs = [RA]; 576 } 577 578 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { 579 list<Register> Defs = [RA]; 580 } 581 582 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 583 InstrItinClass itin, 584 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> { 585 dag OutOperandList = (outs GPROpnd:$rd); 586 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 587 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 588 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 589 InstrItinClass Itinerary = itin; 590 } 591 592 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>; 593 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>; 594 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>; 595 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>; 596 597 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 598 InstrItinClass itin> { 599 dag OutOperandList = (outs FGROpnd:$fd); 600 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 601 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 602 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in, 603 FGROpnd:$ft, 604 FGROpnd:$fs))]; 605 string Constraints = "$fd_in = $fd"; 606 InstrItinClass Itinerary = itin; 607 } 608 609 class COP1_SEL_D_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 610 InstrItinClass itin> { 611 dag OutOperandList = (outs FGROpnd:$fd); 612 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 613 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 614 list<dag> Pattern = [(set FGROpnd:$fd, (MipsFSelect FGROpnd:$fd_in, 615 FGROpnd:$ft, 616 FGROpnd:$fs))]; 617 string Constraints = "$fd_in = $fd"; 618 InstrItinClass Itinerary = itin; 619 } 620 621 class SEL_D_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>, 622 MipsR6Arch<"sel.d">; 623 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>, 624 MipsR6Arch<"sel.s">; 625 626 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 627 : MipsR6Arch<instr_asm> { 628 dag OutOperandList = (outs GPROpnd:$rd); 629 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 630 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 631 list<dag> Pattern = []; 632 InstrItinClass Itinerary = II_SELCCZ; 633 } 634 635 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>; 636 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>; 637 638 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 639 InstrItinClass itin = NoItinerary> { 640 dag OutOperandList = (outs FGROpnd:$fd); 641 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 642 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 643 list<dag> Pattern = []; 644 string Constraints = "$fd_in = $fd"; 645 InstrItinClass Itinerary = itin; 646 } 647 648 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>; 649 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>; 650 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>; 651 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>; 652 653 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 654 InstrItinClass itin> { 655 dag OutOperandList = (outs FGROpnd:$fd); 656 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 657 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 658 list<dag> Pattern = []; 659 InstrItinClass Itinerary = itin; 660 } 661 662 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>; 663 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>; 664 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>; 665 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>; 666 667 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>; 668 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>; 669 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>; 670 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>; 671 672 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 673 InstrItinClass itin> { 674 dag OutOperandList = (outs FGROpnd:$fd); 675 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 676 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 677 list<dag> Pattern = []; 678 InstrItinClass Itinerary = itin; 679 } 680 681 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>, 682 MipsR6Arch<"seleqz.s">; 683 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>, 684 MipsR6Arch<"seleqz.d">; 685 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>, 686 MipsR6Arch<"selnez.s">; 687 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>, 688 MipsR6Arch<"selnez.d">; 689 690 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 691 InstrItinClass itin> { 692 dag OutOperandList = (outs FGROpnd:$fd); 693 dag InOperandList = (ins FGROpnd:$fs); 694 string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); 695 list<dag> Pattern = []; 696 InstrItinClass Itinerary = itin; 697 } 698 699 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>; 700 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>; 701 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>; 702 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>; 703 704 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, 705 RegisterOperand GPROpnd, InstrItinClass itin> 706 : MipsR6Arch<instr_asm> { 707 dag OutOperandList = (outs); 708 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 709 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 710 list<dag> Pattern = []; 711 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 712 InstrItinClass Itinerary = itin; 713 } 714 715 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>; 716 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>; 717 718 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd, 719 InstrItinClass itin> { 720 dag OutOperandList = (outs COPOpnd:$rt); 721 dag InOperandList = (ins mem_simm11:$addr); 722 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 723 list<dag> Pattern = []; 724 bit mayLoad = 1; 725 string DecoderMethod = "DecodeFMemCop2R6"; 726 InstrItinClass Itinerary = itin; 727 } 728 729 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>; 730 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>; 731 732 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd, 733 InstrItinClass itin> { 734 dag OutOperandList = (outs); 735 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr); 736 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 737 list<dag> Pattern = []; 738 bit mayStore = 1; 739 string DecoderMethod = "DecodeFMemCop2R6"; 740 InstrItinClass Itinerary = itin; 741 } 742 743 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>; 744 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>; 745 746 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 747 Operand ImmOpnd, InstrItinClass itin> 748 : MipsR6Arch<instr_asm> { 749 dag OutOperandList = (outs GPROpnd:$rd); 750 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); 751 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2"); 752 list<dag> Pattern = []; 753 InstrItinClass Itinerary = itin; 754 } 755 756 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>; 757 758 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 759 Operand MemOpnd, InstrItinClass itin> 760 : MipsR6Arch<instr_asm> { 761 dag OutOperandList = (outs GPROpnd:$rt); 762 dag InOperandList = (ins MemOpnd:$addr); 763 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 764 list<dag> Pattern = []; 765 bit mayLoad = 1; 766 InstrItinClass Itinerary = itin; 767 } 768 769 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>; 770 771 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 772 InstrItinClass itin> { 773 dag OutOperandList = (outs GPROpnd:$dst); 774 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 775 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 776 list<dag> Pattern = []; 777 bit mayStore = 1; 778 string Constraints = "$rt = $dst"; 779 InstrItinClass Itinerary = itin; 780 } 781 782 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; 783 784 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 785 InstrItinClass itin> 786 : MipsR6Arch<instr_asm> { 787 dag OutOperandList = (outs GPROpnd:$rd); 788 dag InOperandList = (ins GPROpnd:$rs); 789 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 790 InstrItinClass Itinerary = itin; 791 } 792 793 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 794 InstrItinClass itin> : 795 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> { 796 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))]; 797 } 798 799 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 800 InstrItinClass itin> : 801 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> { 802 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; 803 } 804 805 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>; 806 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>; 807 808 class SDBBP_R6_DESC { 809 dag OutOperandList = (outs); 810 dag InOperandList = (ins uimm20:$code_); 811 string AsmString = "sdbbp\t$code_"; 812 list<dag> Pattern = []; 813 bit isCTI = 1; 814 InstrItinClass Itinerary = II_SDBBP; 815 } 816 817 class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 818 InstrItinClass itin> : MipsR6Arch<instr_asm> { 819 dag OutOperandList = (outs GPROpnd:$rd); 820 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 821 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 822 list<dag> Pattern = []; 823 InstrItinClass Itinerary = itin; 824 } 825 826 class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>; 827 class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>; 828 class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>; 829 class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>; 830 class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>; 831 class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>; 832 833 class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 834 InstrItinClass itin> : MipsR6Arch<instr_asm> { 835 dag OutOperandList = (outs); 836 dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_); 837 string AsmString = !strconcat(instr_asm, "\t$rs, $type_"); 838 list<dag> Pattern = []; 839 InstrItinClass Itinerary = itin; 840 bit hasSideEffects = 1; 841 } 842 843 class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> { 844 dag InOperandList = (ins GPR32Opnd:$rs); 845 string AsmString = "ginvi\t$rs"; 846 } 847 class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>; 848 849 //===----------------------------------------------------------------------===// 850 // 851 // Instruction Definitions 852 // 853 //===----------------------------------------------------------------------===// 854 855 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; 856 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; 857 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; 858 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6; 859 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; 860 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; 861 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; 862 let AdditionalPredicates = [NotInMicroMips] in { 863 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; 864 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; 865 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; 866 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; 867 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; 868 def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; 869 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; 870 def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; 871 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; 872 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; 873 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; 874 def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; 875 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; 876 def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; 877 } 878 def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; 879 let AdditionalPredicates = [NotInMicroMips] in { 880 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; 881 def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; 882 def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; 883 def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; 884 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; 885 def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; 886 def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; 887 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; 888 def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; 889 def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; 890 def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; 891 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; 892 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT; 893 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT; 894 } 895 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; 896 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; 897 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>; 898 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>; 899 let AdditionalPredicates = [NotInMicroMips] in { 900 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; 901 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; 902 } 903 904 def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6; 905 def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6; 906 907 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; 908 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; 909 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; 910 let AdditionalPredicates = [NotInMicroMips] in { 911 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; 912 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6; 913 } 914 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; 915 let AdditionalPredicates = [NotInMicroMips] in { 916 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; 917 } 918 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; 919 let AdditionalPredicates = [NotInMicroMips] in { 920 def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; 921 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 922 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 923 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 924 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 925 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT; 926 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT; 927 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 928 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 929 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT; 930 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT; 931 932 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6; 933 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6; 934 935 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 936 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 937 938 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; 939 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; 940 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; 941 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; 942 } 943 def NAL; // BAL with rd=0 944 let AdditionalPredicates = [NotInMicroMips] in { 945 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; 946 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; 947 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; 948 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6; 949 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; 950 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; 951 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; 952 def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, 953 HARDFLOAT; 954 def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, 955 HARDFLOAT; 956 def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, 957 HARDFLOAT; 958 def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, 959 HARDFLOAT; 960 def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; 961 def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; 962 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; 963 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; 964 } 965 966 let AdditionalPredicates = [NotInMicroMips] in { 967 def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC; 968 def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC; 969 def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC; 970 def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC; 971 def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC; 972 def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC; 973 } 974 975 let AdditionalPredicates = [NotInMicroMips] in { 976 def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV; 977 def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV; 978 } 979 980 //===----------------------------------------------------------------------===// 981 // 982 // Instruction Aliases 983 // 984 //===----------------------------------------------------------------------===// 985 986 def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6; 987 def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6; 988 989 let AdditionalPredicates = [NotInMicroMips] in { 990 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; 991 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32; 992 } 993 994 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; 995 996 let AdditionalPredicates = [NotInMicroMips] in { 997 def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; 998 } 999 1000 def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, 1001 GPR32Opnd:$rt)>, ISA_MIPS32R6; 1002 def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, 1003 GPR32Opnd:$rt)>, ISA_MIPS32R6; 1004 1005 def : MipsInstAlias<"lapc $rd, $imm", 1006 (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6; 1007 1008 //===----------------------------------------------------------------------===// 1009 // 1010 // Patterns and Pseudo Instructions 1011 // 1012 //===----------------------------------------------------------------------===// 1013 1014 // comparisons supported via another comparison 1015 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> { 1016 def : MipsPat<(setone VT:$lhs, VT:$rhs), 1017 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1018 def : MipsPat<(seto VT:$lhs, VT:$rhs), 1019 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1020 def : MipsPat<(setune VT:$lhs, VT:$rhs), 1021 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1022 def : MipsPat<(seteq VT:$lhs, VT:$rhs), 1023 (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>; 1024 def : MipsPat<(setgt VT:$lhs, VT:$rhs), 1025 (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>; 1026 def : MipsPat<(setge VT:$lhs, VT:$rhs), 1027 (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>; 1028 def : MipsPat<(setlt VT:$lhs, VT:$rhs), 1029 (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>; 1030 def : MipsPat<(setle VT:$lhs, VT:$rhs), 1031 (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>; 1032 def : MipsPat<(setne VT:$lhs, VT:$rhs), 1033 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1034 } 1035 1036 let AdditionalPredicates = [NotInMicroMips] in { 1037 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6; 1038 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6; 1039 } 1040 1041 // i32 selects 1042 multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp, 1043 Instruction SLTiOp, Instruction SLTiuOp, 1044 Instruction SELEQZOp, Instruction SELNEZOp, 1045 SDPatternOperator imm_type, ValueType Opg> { 1046 // reg, immz 1047 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f), 1048 (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>; 1049 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f), 1050 (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>; 1051 1052 // reg, immZExt16[_64] 1053 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 1054 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 1055 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 1056 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 1057 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 1058 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 1059 1060 // reg, immSExt16Plus1 1061 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 1062 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))), 1063 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>; 1064 def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 1065 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))), 1066 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>; 1067 1068 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz), 1069 (SELEQZOp RC:$t, RC:$cond)>; 1070 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz), 1071 (SELNEZOp RC:$t, RC:$cond)>; 1072 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f), 1073 (SELNEZOp RC:$f, RC:$cond)>; 1074 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f), 1075 (SELEQZOp RC:$f, RC:$cond)>; 1076 } 1077 1078 let AdditionalPredicates = [NotInMicroMips] in { 1079 defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ, 1080 immZExt16, i32>, ISA_MIPS32R6; 1081 1082 def : MipsPat<(select i32:$cond, i32:$t, i32:$f), 1083 (OR (SELNEZ i32:$t, i32:$cond), 1084 (SELEQZ i32:$f, i32:$cond))>, 1085 ISA_MIPS32R6; 1086 def : MipsPat<(select i32:$cond, i32:$t, immz), 1087 (SELNEZ i32:$t, i32:$cond)>, 1088 ISA_MIPS32R6; 1089 def : MipsPat<(select i32:$cond, immz, i32:$f), 1090 (SELEQZ i32:$f, i32:$cond)>, 1091 ISA_MIPS32R6; 1092 } 1093 1094 // Pseudo instructions 1095 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 1096 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { 1097 class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> : 1098 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, 1099 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>; 1100 } 1101 1102 class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT, 1103 RegisterOperand RO> : 1104 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], 1105 II_IndirectBranchPseudo>, 1106 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> { 1107 let isTerminator=1; 1108 let isBarrier=1; 1109 let hasDelaySlot = 1; 1110 let isBranch = 1; 1111 let isIndirectBranch = 1; 1112 bit isCTI = 1; 1113 } 1114 1115 1116 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 1117 NoIndirectJumpGuards] in { 1118 def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6; 1119 def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO, 1120 GPR32Opnd>, 1121 ISA_MIPS32R6; 1122 } 1123 1124 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 1125 UseIndirectJumpsHazard] in { 1126 def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6; 1127 def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6, 1128 GPR32Opnd>, 1129 ISA_MIPS32R6; 1130 } 1131 1132
