1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips64 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Mips Operand, Complex Patterns and Transformations Definitions. 16 //===----------------------------------------------------------------------===// 17 18 // shamt must fit in 6 bits. 19 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 20 21 // Node immediate fits as 10-bit sign extended on target immediate. 22 // e.g. seqi, snei 23 def immSExt10_64 : PatLeaf<(i64 imm), 24 [{ return isInt<10>(N->getSExtValue()); }]>; 25 26 def immZExt16_64 : PatLeaf<(i64 imm), 27 [{ return isUInt<16>(N->getZExtValue()); }]>; 28 29 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 30 31 // Transformation function: get log2 of low 32 bits of immediate 32 def Log2LO : SDNodeXForm<imm, [{ 33 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 34 }]>; 35 36 // Transformation function: get log2 of high 32 bits of immediate 37 def Log2HI : SDNodeXForm<imm, [{ 38 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 39 }]>; 40 41 // Predicate: True if immediate is a power of 2 and fits 32 bits 42 def PowerOf2LO : PatLeaf<(imm), [{ 43 if (N->getValueType(0) == MVT::i64) { 44 uint64_t Imm = N->getZExtValue(); 45 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 46 } 47 else 48 return false; 49 }]>; 50 51 // Predicate: True if immediate is a power of 2 and exceeds 32 bits 52 def PowerOf2HI : PatLeaf<(imm), [{ 53 if (N->getValueType(0) == MVT::i64) { 54 uint64_t Imm = N->getZExtValue(); 55 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 56 } 57 else 58 return false; 59 }]>; 60 61 def PowerOf2LO_i32 : PatLeaf<(imm), [{ 62 if (N->getValueType(0) == MVT::i32) { 63 uint64_t Imm = N->getZExtValue(); 64 return isPowerOf2_32(Imm) && isUInt<32>(Imm); 65 } 66 else 67 return false; 68 }]>; 69 70 def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); 72 }]>; 73 74 //===----------------------------------------------------------------------===// 75 // Instructions specific format 76 //===----------------------------------------------------------------------===// 77 let usesCustomInserter = 1 in { 78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 86 } 87 88 def ATOMIC_LOAD_ADD_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 89 def ATOMIC_LOAD_SUB_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 90 def ATOMIC_LOAD_AND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 91 def ATOMIC_LOAD_OR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 92 def ATOMIC_LOAD_XOR_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 93 def ATOMIC_LOAD_NAND_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 94 95 def ATOMIC_SWAP_I64_POSTRA : Atomic2OpsPostRA<GPR64>; 96 97 def ATOMIC_CMP_SWAP_I64_POSTRA : AtomicCmpSwapPostRA<GPR64>; 98 99 /// Pseudo instructions for loading and storing accumulator registers. 100 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 101 def LOAD_ACC128 : Load<"", ACC128>; 102 def STORE_ACC128 : Store<"", ACC128>; 103 } 104 105 //===----------------------------------------------------------------------===// 106 // Instruction definition 107 //===----------------------------------------------------------------------===// 108 let DecoderNamespace = "Mips64" in { 109 /// Arithmetic Instructions (ALU Immediate) 110 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, 111 ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; 112 let AdditionalPredicates = [NotInMicroMips] in { 113 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 114 immSExt16, add>, 115 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 116 } 117 118 let isCodeGenOnly = 1 in { 119 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 120 SLTI_FM<0xa>, GPR_64; 121 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 122 SLTI_FM<0xb>, GPR_64; 123 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 124 ADDI_FM<0xc>, GPR_64; 125 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 126 ADDI_FM<0xd>, GPR_64; 127 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 128 ADDI_FM<0xe>, GPR_64; 129 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64; 130 } 131 132 /// Arithmetic Instructions (3-Operand, R-Type) 133 let AdditionalPredicates = [NotInMicroMips] in { 134 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, 135 ISA_MIPS3; 136 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 137 ADD_FM<0, 0x2d>, ISA_MIPS3; 138 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, 139 ADD_FM<0, 0x2f>, ISA_MIPS3; 140 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 141 ISA_MIPS3; 142 } 143 144 let isCodeGenOnly = 1 in { 145 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64; 146 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64; 147 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>, 148 GPR_64; 149 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>, 150 GPR_64; 151 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>, 152 GPR_64; 153 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>, GPR_64; 154 } 155 156 /// Shift Instructions 157 let AdditionalPredicates = [NotInMicroMips] in { 158 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, 159 immZExt6>, 160 SRA_FM<0x38, 0>, ISA_MIPS3; 161 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, 162 immZExt6>, 163 SRA_FM<0x3a, 0>, ISA_MIPS3; 164 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, 165 immZExt6>, 166 SRA_FM<0x3b, 0>, ISA_MIPS3; 167 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 168 SRLV_FM<0x14, 0>, ISA_MIPS3; 169 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 170 SRLV_FM<0x17, 0>, ISA_MIPS3; 171 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 172 SRLV_FM<0x16, 0>, ISA_MIPS3; 173 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 174 SRA_FM<0x3c, 0>, ISA_MIPS3; 175 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 176 SRA_FM<0x3e, 0>, ISA_MIPS3; 177 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 178 SRA_FM<0x3f, 0>, ISA_MIPS3; 179 180 // Rotate Instructions 181 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 182 immZExt6>, 183 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 184 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 185 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 186 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 187 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 188 } 189 190 /// Load and Store Instructions 191 /// aligned 192 let isCodeGenOnly = 1 in { 193 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>, GPR_64; 194 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>, GPR_64; 195 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>, GPR_64; 196 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>, GPR_64; 197 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>, GPR_64; 198 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>, GPR_64; 199 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>, 200 GPR_64; 201 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>, 202 GPR_64; 203 } 204 205 let AdditionalPredicates = [NotInMicroMips] in { 206 def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, 207 LW_FM<0x27>, ISA_MIPS3; 208 def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load, II_LD>, 209 LW_FM<0x37>, ISA_MIPS3; 210 def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store, II_SD>, 211 LW_FM<0x3f>, ISA_MIPS3; 212 } 213 214 215 216 /// load/store left/right 217 let isCodeGenOnly = 1 in { 218 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>, 219 GPR_64; 220 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>, 221 GPR_64; 222 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>, 223 GPR_64; 224 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>, 225 GPR_64; 226 } 227 228 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 229 ISA_MIPS3_NOT_32R6_64R6; 230 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 231 ISA_MIPS3_NOT_32R6_64R6; 232 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 233 ISA_MIPS3_NOT_32R6_64R6; 234 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 235 ISA_MIPS3_NOT_32R6_64R6; 236 237 /// Load-linked, Store-conditional 238 let AdditionalPredicates = [NotInMicroMips] in { 239 def LLD : LLBase<"lld", GPR64Opnd, mem_simmptr>, LW_FM<0x34>, 240 ISA_MIPS3_NOT_32R6_64R6; 241 } 242 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 243 244 let AdditionalPredicates = [NotInMicroMips], 245 DecoderNamespace = "Mips32_64_PTR64" in { 246 def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, 247 ISA_MIPS2_NOT_32R6_64R6; 248 def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, 249 ISA_MIPS2_NOT_32R6_64R6; 250 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64; 251 } 252 253 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 254 255 /// Jump and Branch Instructions 256 let isCodeGenOnly = 1 in { 257 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>, 258 GPR_64; 259 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>, 260 GPR_64; 261 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>, 262 GPR_64; 263 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>, 264 GPR_64; 265 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>, 266 GPR_64; 267 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>, 268 GPR_64; 269 let AdditionalPredicates = [NoIndirectJumpGuards] in 270 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 271 } 272 let AdditionalPredicates = [NotInMicroMips], 273 DecoderNamespace = "Mips64" in { 274 def JR_HB64 : JR_HB_DESC<GPR64Opnd>, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; 275 def JALR_HB64 : JALR_HB_DESC<GPR64Opnd>, JALR_HB_ENC, ISA_MIPS32R2; 276 } 277 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; 278 279 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 280 NoIndirectJumpGuards] in { 281 def TAILCALLREG64 : TailCallReg<JR64, GPR64Opnd>, ISA_MIPS3_NOT_32R6_64R6, 282 PTR_64; 283 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<JR64, GPR64Opnd>, 284 ISA_MIPS3_NOT_32R6_64R6; 285 } 286 287 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 288 UseIndirectJumpsHazard] in { 289 def TAILCALLREGHB64 : TailCallReg<JR_HB64, GPR64Opnd>, 290 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; 291 def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase<JR_HB64, 292 GPR64Opnd>, 293 ISA_MIPS32R2_NOT_32R6_64R6; 294 } 295 296 /// Multiply and Divide Instructions. 297 let AdditionalPredicates = [NotInMicroMips] in { 298 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 299 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 300 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 301 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 302 } 303 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 304 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 305 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 306 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 307 let AdditionalPredicates = [NotInMicroMips] in { 308 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 309 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 310 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 311 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 312 } 313 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 314 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 315 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 316 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 317 318 let isCodeGenOnly = 1 in { 319 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 320 ISA_MIPS3_NOT_32R6_64R6; 321 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 322 ISA_MIPS3_NOT_32R6_64R6; 323 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 324 ISA_MIPS3_NOT_32R6_64R6; 325 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 326 ISA_MIPS3_NOT_32R6_64R6; 327 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 328 ISA_MIPS3_NOT_32R6_64R6; 329 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 330 ISA_MIPS3_NOT_32R6_64R6; 331 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 332 333 /// Sign Ext In Register Instructions. 334 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 335 ISA_MIPS32R2; 336 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 337 ISA_MIPS32R2; 338 } 339 340 /// Count Leading 341 let AdditionalPredicates = [NotInMicroMips] in { 342 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>, 343 ISA_MIPS64_NOT_64R6; 344 def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>, 345 ISA_MIPS64_NOT_64R6; 346 347 /// Double Word Swap Bytes/HalfWords 348 def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, 349 ISA_MIPS64R2; 350 def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>, 351 ISA_MIPS64R2; 352 353 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>, 354 GPR_64; 355 } 356 357 let isCodeGenOnly = 1 in 358 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM, GPR_64; 359 360 let AdditionalPredicates = [NotInMicroMips] in { 361 // The 'pos + size' constraints for code generation are enforced by the 362 // code that lowers into MipsISD::Ext. 363 // For assembly parsing, we alias dextu and dextm to dext, and match by 364 // operand were possible then check the 'pos + size' in MipsAsmParser. 365 // We override the generated decoder to enforce that dext always comes out 366 // for dextm and dextu like binutils. 367 let DecoderMethod = "DecodeDEXT" in { 368 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, 369 uimm5_plus1_report_uimm6, immZExt5, immZExt5Plus1, 370 MipsExt>, EXT_FM<3>, ISA_MIPS64R2; 371 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, 372 immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2; 373 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 374 immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, 375 ISA_MIPS64R2; 376 } 377 // The 'pos + size' constraints for code generation are enforced by the 378 // code that lowers into MipsISD::Ins. 379 // For assembly parsing, we alias dinsu and dinsm to dins, and match by 380 // operand were possible then check the 'pos + size' in MipsAsmParser. 381 // We override the generated decoder to enforce that dins always comes out 382 // for dinsm and dinsu like binutils. 383 let DecoderMethod = "DecodeDINS" in { 384 def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, 385 immZExt5, immZExt5Plus1>, EXT_FM<7>, 386 ISA_MIPS64R2; 387 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, 388 immZExt5Plus32, immZExt5Plus1>, 389 EXT_FM<6>, ISA_MIPS64R2; 390 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64, 391 immZExt5, immZExtRange2To64>, 392 EXT_FM<5>, ISA_MIPS64R2; 393 } 394 } 395 396 let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in { 397 def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt), 398 (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, 399 uimm5_plus1:$size), 400 "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">, 401 EXT_FM<3>, ISA_MIPS64R2; 402 } 403 404 let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 405 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 406 "dsll\t$rd, $rt, 32", [], II_DSLL>, GPR_64; 407 let isMoveReg = 1 in { 408 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 409 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 410 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 411 "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64; 412 } 413 } 414 415 // We need the following pseudo instruction to avoid offset calculation for 416 // long branches. See the comment in file MipsLongBranch.cpp for detailed 417 // explanation. 418 419 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 420 // where %PART may be %hi or %lo, depending on the relocation kind 421 // that $tgt is annotated with. 422 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst), 423 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>, GPR_64; 424 425 // Cavium Octeon cnMIPS instructions 426 let DecoderNamespace = "CnMips", 427 // FIXME: The lack of HasStdEnc is probably a bug 428 EncodingPredicates = []<Predicate> in { 429 430 class Count1s<string opstr, RegisterOperand RO>: 431 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 432 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 433 let TwoOperandAliasConstraint = "$rd = $rs"; 434 } 435 436 class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO, 437 PatFrag PosImm, SDPatternOperator Op = null_frag>: 438 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1), 439 !strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"), 440 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))], 441 itin, FrmR, opstr> { 442 let TwoOperandAliasConstraint = "$rt = $rs"; 443 } 444 445 class SetCC64_R<string opstr, PatFrag cond_op> : 446 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 447 !strconcat(opstr, "\t$rd, $rs, $rt"), 448 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 449 GPR64Opnd:$rt)))], 450 II_SEQ_SNE, FrmR, opstr> { 451 let TwoOperandAliasConstraint = "$rd = $rs"; 452 } 453 454 class SetCC64_I<string opstr, PatFrag cond_op>: 455 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 456 !strconcat(opstr, "\t$rt, $rs, $imm10"), 457 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 458 immSExt10_64:$imm10)))], 459 II_SEQI_SNEI, FrmI, opstr> { 460 let TwoOperandAliasConstraint = "$rt = $rs"; 461 } 462 463 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 464 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 465 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 466 !strconcat(opstr, "\t$rs, $p, $offset"), 467 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 468 bb:$offset)], II_BBIT, FrmI, opstr> { 469 let isBranch = 1; 470 let isTerminator = 1; 471 let hasDelaySlot = 1; 472 let Defs = [AT]; 473 } 474 475 class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> : 476 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 477 !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>; 478 479 // Unsigned Byte Add 480 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 481 ADD_FM<0x1c, 0x28>, ASE_CNMIPS { 482 let Pattern = [(set GPR64Opnd:$rd, 483 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; 484 } 485 486 // Branch on Bit Clear /+32 487 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 488 uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; 489 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 490 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; 491 492 // Branch on Bit Set /+32 493 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 494 uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; 495 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 496 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 497 498 // Multiply Doubleword to GPR 499 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 500 ADD_FM<0x1c, 0x03>, ASE_CNMIPS { 501 let Defs = [HI0, LO0, P0, P1, P2]; 502 } 503 504 let AdditionalPredicates = [NotInMicroMips] in { 505 // Extract a signed bit field /+32 506 def EXTS : ExtsCins<"exts", II_EXT, GPR64Opnd, immZExt5>, EXTS_FM<0x3a>, 507 ASE_MIPS64_CNMIPS; 508 def EXTS32: ExtsCins<"exts32", II_EXT, GPR64Opnd, immZExt5Plus32>, 509 EXTS_FM<0x3b>, ASE_MIPS64_CNMIPS; 510 511 // Clear and insert a bit field /+32 512 def CINS : ExtsCins<"cins", II_INS, GPR64Opnd, immZExt5, MipsCIns>, 513 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 514 def CINS32: ExtsCins<"cins32", II_INS, GPR64Opnd, immZExt5Plus32, MipsCIns>, 515 EXTS_FM<0x33>, ASE_MIPS64_CNMIPS; 516 let isCodeGenOnly = 1 in { 517 def CINS_i32 : ExtsCins<"cins", II_INS, GPR32Opnd, immZExt5, MipsCIns>, 518 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 519 def CINS64_32 :InstSE<(outs GPR64Opnd:$rt), 520 (ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 521 "cins\t$rt, $rs, $pos, $lenm1", [], II_INS, FrmR, 522 "cins">, 523 EXTS_FM<0x32>, ASE_MIPS64_CNMIPS; 524 } 525 } 526 527 // Move to multiplier/product register 528 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, 529 ASE_CNMIPS; 530 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, 531 ASE_CNMIPS; 532 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, 533 ASE_CNMIPS; 534 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; 535 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; 536 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; 537 538 // Count Ones in a Word/Doubleword 539 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; 540 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; 541 542 // Set on equal/not equal 543 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; 544 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; 545 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; 546 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; 547 548 // 192-bit x 64-bit Unsigned Multiply and Add 549 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, 550 ASE_CNMIPS { 551 let Defs = [P0, P1, P2]; 552 } 553 554 // 64-bit Unsigned Multiply and Add Move 555 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, 556 ASE_CNMIPS { 557 let Defs = [MPL0, P0, P1, P2]; 558 } 559 560 // 64-bit Unsigned Multiply and Add 561 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, 562 ASE_CNMIPS { 563 let Defs = [MPL1, MPL2, P0, P1, P2]; 564 } 565 566 // Move between CPU and coprocessor registers 567 def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>, 568 ASE_CNMIPS; 569 def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, 570 ASE_CNMIPS; 571 } 572 573 } 574 575 /// Move between CPU and coprocessor registers 576 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 577 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, 578 MFC3OP_FM<0x10, 1, 0>, ISA_MIPS3; 579 def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, 580 MFC3OP_FM<0x10, 5, 0>, ISA_MIPS3; 581 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, 582 MFC3OP_FM<0x12, 1, 0>, ISA_MIPS3; 583 def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, 584 MFC3OP_FM<0x12, 5, 0>, ISA_MIPS3; 585 } 586 587 /// Move between CPU and guest coprocessor registers (Virtualization ASE) 588 let DecoderNamespace = "Mips64" in { 589 def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>, 590 MFC3OP_FM<0x10, 3, 1>, ISA_MIPS64R5, ASE_VIRT; 591 def DMTGC0 : MTC3OP<"dmtgc0", COP0Opnd, GPR64Opnd, II_DMTGC0>, 592 MFC3OP_FM<0x10, 3, 3>, ISA_MIPS64R5, ASE_VIRT; 593 } 594 595 let AdditionalPredicates = [UseIndirectJumpsHazard] in 596 def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, RA_64>; 597 598 //===----------------------------------------------------------------------===// 599 // Arbitrary patterns that map to one or more instructions 600 //===----------------------------------------------------------------------===// 601 602 // Materialize i64 constants. 603 defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64; 604 605 def : MipsPat<(i64 immZExt32Low16Zero:$imm), 606 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64; 607 608 def : MipsPat<(i64 immZExt32:$imm), 609 (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), 610 (LO16 imm:$imm))>, ISA_MIPS3, GPR_64; 611 612 // extended loads 613 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 614 GPR_64; 615 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, 616 GPR_64; 617 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>, ISA_MIPS3, 618 GPR_64; 619 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>, ISA_MIPS3, 620 GPR_64; 621 622 // hi/lo relocs 623 let AdditionalPredicates = [NotInMicroMips] in 624 defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, ISA_MIPS3, GPR_64, 625 SYM_32; 626 627 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>, ISA_MIPS3, 628 GPR_64; 629 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>, 630 ISA_MIPS3, GPR_64; 631 632 def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>, 633 ISA_MIPS3, GPR_64; 634 635 // highest/higher/hi/lo relocs 636 let AdditionalPredicates = [NotInMicroMips] in { 637 def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)), 638 (JAL texternalsym:$dst)>, ISA_MIPS3, GPR_64, SYM_64; 639 def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), 640 (LUi64 tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 641 def : MipsPat<(MipsHighest (i64 tblockaddress:$in)), 642 (LUi64 tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 643 def : MipsPat<(MipsHighest (i64 tjumptable:$in)), 644 (LUi64 tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 645 def : MipsPat<(MipsHighest (i64 tconstpool:$in)), 646 (LUi64 tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 647 def : MipsPat<(MipsHighest (i64 texternalsym:$in)), 648 (LUi64 texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 649 650 def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), 651 (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; 652 def : MipsPat<(MipsHigher (i64 tblockaddress:$in)), 653 (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; 654 def : MipsPat<(MipsHigher (i64 tjumptable:$in)), 655 (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; 656 def : MipsPat<(MipsHigher (i64 tconstpool:$in)), 657 (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; 658 def : MipsPat<(MipsHigher (i64 texternalsym:$in)), 659 (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; 660 661 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), 662 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 663 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))), 664 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 665 SYM_64; 666 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))), 667 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 668 def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))), 669 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 670 671 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), 672 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 673 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))), 674 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 675 SYM_64; 676 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))), 677 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 678 def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))), 679 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 680 681 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), 682 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 683 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))), 684 (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, 685 SYM_64; 686 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))), 687 (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 688 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))), 689 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; 690 def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))), 691 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, 692 SYM_64; 693 } 694 695 // gp_rel relocs 696 def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), 697 (DADDiu GPR64:$gp, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64; 698 def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)), 699 (DADDiu GPR64:$gp, tconstpool:$in)>, ISA_MIPS3, ABI_N64; 700 701 def : WrapperPat<tglobaladdr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 702 def : WrapperPat<tconstpool, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 703 def : WrapperPat<texternalsym, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 704 def : WrapperPat<tblockaddress, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 705 def : WrapperPat<tjumptable, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 706 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; 707 708 709 defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 710 ZERO_64>, ISA_MIPS3, GPR_64; 711 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 712 (BLEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 713 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 714 (BGEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; 715 716 // setcc patterns 717 let AdditionalPredicates = [NotInMicroMips] in { 718 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>, ISA_MIPS3, GPR_64; 719 defm : SetlePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 720 defm : SetgtPats<GPR64, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 721 defm : SetgePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; 722 defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>, ISA_MIPS3, GPR_64; 723 } 724 // truncate 725 def : MipsPat<(trunc (assertsext GPR64:$src)), 726 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 727 // The forward compatibility strategy employed by MIPS requires us to treat 728 // values as being sign extended to an infinite number of bits. This allows 729 // existing software to run without modification on any future MIPS 730 // implementation (e.g. 128-bit, or 1024-bit). Being compatible with this 731 // strategy requires that truncation acts as a sign-extension for values being 732 // fed into instructions operating on 32-bit values. Such instructions have 733 // undefined results if this is not true. 734 // For our case, this means that we can't issue an extract_subreg for nodes 735 // such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the 736 // lower subreg would not be replicated into the upper half. 737 def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), 738 (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; 739 def : MipsPat<(i32 (trunc GPR64:$src)), 740 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, ISA_MIPS3, GPR_64; 741 742 // variable shift instructions patterns 743 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 744 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 745 ISA_MIPS3, GPR_64; 746 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 747 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 748 ISA_MIPS3, GPR_64; 749 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 750 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 751 ISA_MIPS3, GPR_64; 752 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 753 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, 754 ISA_MIPS3, GPR_64; 755 756 // 32-to-64-bit extension 757 def : MipsPat<(i64 (anyext GPR32:$src)), 758 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>, 759 ISA_MIPS3, GPR_64; 760 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>, 761 ISA_MIPS3, GPR_64; 762 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3, 763 GPR_64; 764 765 let AdditionalPredicates = [NotInMicroMips] in { 766 def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>, 767 ISA_MIPS64R2, GPR_64; 768 def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))), 769 (CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>, 770 ISA_MIPS64R2, GPR_64, ASE_MIPS64_CNMIPS; 771 } 772 773 // Sign extend in register 774 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 775 (SLL64_64 GPR64:$src)>, ISA_MIPS3, GPR_64; 776 777 // bswap MipsPattern 778 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2; 779 780 // Carry pattern 781 let AdditionalPredicates = [NotInMicroMips] in { 782 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 783 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64; 784 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 785 (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 786 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 787 (DADDiu GPR64:$lhs, imm:$imm)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; 788 } 789 790 // Octeon bbit0/bbit1 MipsPattern 791 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 792 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 793 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 794 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 795 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 796 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 797 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 798 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, 799 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 800 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 801 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, 802 ISA_MIPS64R2, ASE_MIPS64_CNMIPS; 803 def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 804 (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 805 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 806 ASE_MIPS64_CNMIPS; 807 def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), 808 (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), 809 (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, 810 ASE_MIPS64_CNMIPS; 811 812 // Atomic load patterns. 813 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>, ISA_MIPS3, GPR_64; 814 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>, ISA_MIPS3, GPR_64; 815 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>, ISA_MIPS3, GPR_64; 816 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>, ISA_MIPS3, GPR_64; 817 818 // Atomic store patterns. 819 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>, 820 ISA_MIPS3, GPR_64; 821 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>, 822 ISA_MIPS3, GPR_64; 823 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>, 824 ISA_MIPS3, GPR_64; 825 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>, 826 ISA_MIPS3, GPR_64; 827 828 // Patterns used for matching away redundant sign extensions. 829 // MIPS32 arithmetic instructions sign extend their result implicitly. 830 def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))), 831 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 832 (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>; 833 def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))), 834 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 835 (ADDu GPR32:$src, GPR32:$src2), sub_32)>; 836 def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))), 837 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 838 (SUBu GPR32:$src, GPR32:$src2), sub_32)>; 839 def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), 840 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 841 (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS3_NOT_32R6_64R6; 842 def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), 843 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 844 (PseudoMFHI ACC64:$src), sub_32)>; 845 def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))), 846 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 847 (PseudoMFLO ACC64:$src), sub_32)>; 848 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))), 849 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 850 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>; 851 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))), 852 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 853 (SLLV GPR32:$src, GPR32:$src2), sub_32)>; 854 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))), 855 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 856 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>; 857 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))), 858 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 859 (SRLV GPR32:$src, GPR32:$src2), sub_32)>; 860 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))), 861 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 862 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>; 863 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))), 864 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 865 (SRAV GPR32:$src, GPR32:$src2), sub_32)>; 866 867 //===----------------------------------------------------------------------===// 868 // Instruction aliases 869 //===----------------------------------------------------------------------===// 870 let AdditionalPredicates = [NotInMicroMips] in { 871 def : MipsInstAlias<"move $dst, $src", 872 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 873 GPR_64; 874 def : MipsInstAlias<"move $dst, $src", 875 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 876 GPR_64; 877 def : MipsInstAlias<"dadd $rs, $rt, $imm", 878 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 879 0>, ISA_MIPS3_NOT_32R6_64R6; 880 def : MipsInstAlias<"dadd $rs, $imm", 881 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 882 0>, ISA_MIPS3_NOT_32R6_64R6; 883 def : MipsInstAlias<"daddu $rs, $rt, $imm", 884 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 885 0>, ISA_MIPS3; 886 def : MipsInstAlias<"daddu $rs, $imm", 887 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 888 0>, ISA_MIPS3; 889 890 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi64, GPR64Opnd, imm64>, 891 ISA_MIPS3, GPR_64; 892 893 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi64, GPR64Opnd, imm64>, 894 ISA_MIPS3, GPR_64; 895 896 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>, 897 ISA_MIPS3, GPR_64; 898 } 899 let AdditionalPredicates = [NotInMicroMips] in { 900 def : MipsInstAlias<"dneg $rt, $rs", 901 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 902 ISA_MIPS3; 903 def : MipsInstAlias<"dneg $rt", 904 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 905 ISA_MIPS3; 906 def : MipsInstAlias<"dnegu $rt, $rs", 907 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 908 ISA_MIPS3; 909 def : MipsInstAlias<"dnegu $rt", 910 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 911 ISA_MIPS3; 912 } 913 def : MipsInstAlias<"dsubi $rs, $rt, $imm", 914 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 915 InvertedImOperand64:$imm), 916 0>, ISA_MIPS3_NOT_32R6_64R6; 917 def : MipsInstAlias<"dsubi $rs, $imm", 918 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 919 InvertedImOperand64:$imm), 920 0>, ISA_MIPS3_NOT_32R6_64R6; 921 def : MipsInstAlias<"dsub $rs, $rt, $imm", 922 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 923 InvertedImOperand64:$imm), 924 0>, ISA_MIPS3_NOT_32R6_64R6; 925 def : MipsInstAlias<"dsub $rs, $imm", 926 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 927 InvertedImOperand64:$imm), 928 0>, ISA_MIPS3_NOT_32R6_64R6; 929 let AdditionalPredicates = [NotInMicroMips] in { 930 def : MipsInstAlias<"dsubu $rt, $rs, $imm", 931 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 932 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 933 def : MipsInstAlias<"dsubu $rs, $imm", 934 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 935 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 936 } 937 def : MipsInstAlias<"dsra $rd, $rt, $rs", 938 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 939 ISA_MIPS3; 940 let AdditionalPredicates = [NotInMicroMips] in { 941 def : MipsInstAlias<"dsll $rd, $rt, $rs", 942 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 943 ISA_MIPS3; 944 def : MipsInstAlias<"dsrl $rd, $rt, $rs", 945 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 946 ISA_MIPS3; 947 def : MipsInstAlias<"dsrl $rd, $rt", 948 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 949 ISA_MIPS3; 950 def : MipsInstAlias<"dsll $rd, $rt", 951 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>, 952 ISA_MIPS3; 953 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 954 (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 955 uimm_range_2_64:$size), 0>, ISA_MIPS64R2; 956 def : MipsInstAlias<"dins $rt, $rs, $pos, $size", 957 (DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 958 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 959 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 960 (DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos, 961 uimm5_plus33:$size), 0>, ISA_MIPS64R2; 962 def : MipsInstAlias<"dext $rt, $rs, $pos, $size", 963 (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, 964 uimm5_plus1:$size), 0>, ISA_MIPS64R2; 965 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>, 966 ISA_MIPS64; 967 // Two operand (implicit 0 selector) versions: 968 def : MipsInstAlias<"dmtc0 $rt, $rd", 969 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 970 def : MipsInstAlias<"dmfc0 $rt, $rd", 971 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 972 def : MipsInstAlias<"dmfgc0 $rt, $rd", 973 (DMFGC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>, 974 ISA_MIPS64R5, ASE_VIRT; 975 def : MipsInstAlias<"dmtgc0 $rt, $rd", 976 (DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>, 977 ISA_MIPS64R5, ASE_VIRT; 978 } 979 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 980 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 981 982 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; 983 def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; 984 def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; 985 def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; 986 987 // cnMIPS Aliases. 988 989 // bbit* with $p 32-63 converted to bbit*32 with $p 0-31 990 def : MipsInstAlias<"bbit0 $rs, $p, $offset", 991 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 992 brtarget:$offset), 0>, 993 ASE_CNMIPS; 994 def : MipsInstAlias<"bbit1 $rs, $p, $offset", 995 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 996 brtarget:$offset), 0>, 997 ASE_CNMIPS; 998 999 // exts with $pos 32-63 in converted to exts32 with $pos 0-31 1000 def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 1001 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1002 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1003 ASE_MIPS64_CNMIPS; 1004 def : MipsInstAlias<"exts $rt, $pos, $lenm1", 1005 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1006 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1007 ASE_MIPS64_CNMIPS; 1008 1009 // cins with $pos 32-63 in converted to cins32 with $pos 0-31 1010 def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 1011 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 1012 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1013 ASE_MIPS64_CNMIPS; 1014 def : MipsInstAlias<"cins $rt, $pos, $lenm1", 1015 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 1016 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 1017 ASE_MIPS64_CNMIPS; 1018 1019 //===----------------------------------------------------------------------===// 1020 // Assembler Pseudo Instructions 1021 //===----------------------------------------------------------------------===// 1022 1023 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 1024 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 1025 !strconcat(instr_asm, "\t$rt, $imm64")> ; 1026 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 1027 1028 def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 1029 "dla\t$rt, $addr">; 1030 def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 1031 "dla\t$rt, $imm64">; 1032 1033 def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1034 simm32_relaxed:$imm), 1035 "dmul\t$rs, $rt, $imm">, 1036 ISA_MIPS3_NOT_32R6_64R6; 1037 def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1038 GPR64Opnd:$rd), 1039 "dmulo\t$rs, $rt, $rd">, 1040 ISA_MIPS3_NOT_32R6_64R6; 1041 def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1042 GPR64Opnd:$rd), 1043 "dmulou\t$rs, $rt, $rd">, 1044 ISA_MIPS3_NOT_32R6_64R6; 1045 1046 def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt, 1047 GPR64Opnd:$rd), 1048 "dmul\t$rs, $rt, $rd"> { 1049 let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips]; 1050 } 1051 1052 let AdditionalPredicates = [NotInMicroMips] in { 1053 def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1054 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1055 "ddiv\t$rd, $rs, $rt">, 1056 ISA_MIPS3_NOT_32R6_64R6; 1057 def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1058 (ins GPR64Opnd:$rs, imm64:$imm), 1059 "ddiv\t$rd, $rs, $imm">, 1060 ISA_MIPS3_NOT_32R6_64R6; 1061 def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1062 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1063 "ddivu\t$rd, $rs, $rt">, 1064 ISA_MIPS3_NOT_32R6_64R6; 1065 def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1066 (ins GPR64Opnd:$rs, imm64:$imm), 1067 "ddivu\t$rd, $rs, $imm">, 1068 ISA_MIPS3_NOT_32R6_64R6; 1069 1070 // GAS expands 'div' and 'ddiv' differently when the destination 1071 // register is $zero and the instruction is in the two operand 1072 // form. 'ddiv' gets expanded, while 'div' is not expanded. 1073 1074 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs, 1075 GPR64Opnd:$rs, 1076 GPR64Opnd:$rt), 0>, 1077 ISA_MIPS3_NOT_32R6_64R6; 1078 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd, 1079 GPR64Opnd:$rd, 1080 imm64:$imm), 0>, 1081 ISA_MIPS3_NOT_32R6_64R6; 1082 1083 // GAS expands 'divu' and 'ddivu' differently when the destination 1084 // register is $zero and the instruction is in the two operand 1085 // form. 'ddivu' gets expanded, while 'divu' is not expanded. 1086 1087 def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt, 1088 GPR64Opnd:$rt, 1089 GPR64Opnd:$rs), 0>, 1090 ISA_MIPS3_NOT_32R6_64R6; 1091 def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd, 1092 GPR64Opnd:$rd, 1093 imm64:$imm), 0>, 1094 ISA_MIPS3_NOT_32R6_64R6; 1095 def DSRemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1096 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1097 "drem\t$rd, $rs, $rt">, 1098 ISA_MIPS3_NOT_32R6_64R6; 1099 def DSRemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1100 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1101 "drem\t$rd, $rs, $imm">, 1102 ISA_MIPS3_NOT_32R6_64R6; 1103 def DURemMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1104 (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 1105 "dremu\t$rd, $rs, $rt">, 1106 ISA_MIPS3_NOT_32R6_64R6; 1107 def DURemIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), 1108 (ins GPR64Opnd:$rs, simm32_relaxed:$imm), 1109 "dremu\t$rd, $rs, $imm">, 1110 ISA_MIPS3_NOT_32R6_64R6; 1111 def : MipsInstAlias<"drem $rt, $rs", (DSRemMacro GPR64Opnd:$rt, 1112 GPR64Opnd:$rt, 1113 GPR64Opnd:$rs), 0>, 1114 ISA_MIPS3_NOT_32R6_64R6; 1115 def : MipsInstAlias<"drem $rd, $imm", (DSRemIMacro GPR64Opnd:$rd, 1116 GPR64Opnd:$rd, 1117 simm32_relaxed:$imm), 0>, 1118 ISA_MIPS3_NOT_32R6_64R6; 1119 def : MipsInstAlias<"dremu $rt, $rs", (DURemMacro GPR64Opnd:$rt, 1120 GPR64Opnd:$rt, 1121 GPR64Opnd:$rs), 0>, 1122 ISA_MIPS3_NOT_32R6_64R6; 1123 def : MipsInstAlias<"dremu $rd, $imm", (DURemIMacro GPR64Opnd:$rd, 1124 GPR64Opnd:$rd, 1125 simm32_relaxed:$imm), 0>, 1126 ISA_MIPS3_NOT_32R6_64R6; 1127 } 1128 1129 def NORImm64 : NORIMM_DESC_BASE<GPR64Opnd, imm64>, GPR_64; 1130 def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1131 imm64:$imm)>, GPR_64; 1132 def SLTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1133 (ins GPR64Opnd:$rt, imm64:$imm), 1134 "slt\t$rs, $rt, $imm">, GPR_64; 1135 def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1136 imm64:$imm)>, GPR_64; 1137 def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), 1138 (ins GPR64Opnd:$rt, imm64:$imm), 1139 "sltu\t$rs, $rt, $imm">, GPR_64; 1140 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, 1141 imm64:$imm)>, GPR_64; 1142 1143 def : MipsInstAlias<"rdhwr $rt, $rs", 1144 (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; 1145
